WO2014208450A1 - Electric power converter - Google Patents

Electric power converter Download PDF

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Publication number
WO2014208450A1
WO2014208450A1 PCT/JP2014/066312 JP2014066312W WO2014208450A1 WO 2014208450 A1 WO2014208450 A1 WO 2014208450A1 JP 2014066312 W JP2014066312 W JP 2014066312W WO 2014208450 A1 WO2014208450 A1 WO 2014208450A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor element
main electrode
power conversion
conversion device
main
Prior art date
Application number
PCT/JP2014/066312
Other languages
French (fr)
Japanese (ja)
Inventor
卓 下村
林　哲也
大 津川
崇 広田
健太 江森
啓一郎 沼倉
Original Assignee
日産自動車株式会社
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Publication date
Application filed by 日産自動車株式会社 filed Critical 日産自動車株式会社
Priority to JP2015524014A priority Critical patent/JP6056971B2/en
Publication of WO2014208450A1 publication Critical patent/WO2014208450A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the present invention relates to a power conversion device used for an inverter or the like that operates a plurality of switching elements, and more particularly to a technique for preventing the generation of surge voltage.
  • the inverter device for converting direct current power to alternating current power turns on and off the switching element, so that a surge voltage is generated. Therefore, it is necessary to reduce the generation of surge voltage, and for example, a technique disclosed in Patent Document 1 has been proposed.
  • Patent Document 1 in order to reduce inductance when the power supply side is viewed from the switching element, additional wiring is provided on the positive (high potential side) bus bar and the negative (low potential side) bus bar connected to the power supply. It is described.
  • a power conversion device includes a first semiconductor element constituting an upper arm, a second semiconductor element constituting a lower arm, and a positive conductive member that supplies a positive potential to the upper arm.
  • a negative-side conductive member that supplies a negative potential to the lower arm, and an output-side conductive member that outputs a potential at a connection point between the upper arm and the lower arm.
  • the positive-side conductive member is a main surface of the semiconductor element.
  • the negative side conductive member has a negative side flat plate-shaped portion arranged so as to be substantially parallel to the main surface.
  • the output-side conductive member has an output-side flat plate-shaped portion that is disposed so as to be substantially parallel to the main surface of the semiconductor element.
  • the plus-side flat plate-shaped portion is arranged so as to overlap the entire main surface of the first semiconductor element, or the negative-side flat plate-shaped portion is the second semiconductor element.
  • the plus-side flat plate-shaped portion and the minus-side flat plate-shaped portion are arranged so that at least one of the arrangement is made to overlap with the entire main surface of the plate. May be.
  • one end side of the first semiconductor element and one end side of the second semiconductor element are connected, the plus side conductive member is connected to the other end side of the first semiconductor element, and the minus side conductive member is
  • the second semiconductor element may be connected to the other end side.
  • the power conversion device may be characterized in that the plus side flat plate portion, the minus side flat plate portion, and the output side flat plate portion are sealed with resin.
  • the power converter according to the present invention further includes a capacitor that connects between the plus side conductive member and the minus side conductive member, in addition to the plus side flat plate shape portion, the minus side flat plate shape portion, and the output side flat plate shape portion,
  • the capacitor may be sealed with resin.
  • the power converter according to the present invention further includes a support substrate that supports the first semiconductor element and the second semiconductor element on a surface opposite to the main surface, and includes a plus-side conductive member, a minus-side conductive member, and an output side.
  • Each of the conductive members has a fixing surface for directly fixing to the support substrate, and further, the first semiconductor element is installed on the fixing surface of the plus-side conductive member, and the second semiconductor element is an output-side conductive member
  • the fixing surface may be provided, and at least a part of the support substrate, the fixing surface, and the first semiconductor element and the second semiconductor element may be sealed with resin.
  • the power conversion device is characterized in that the third main electrode is disposed so as to straddle between the plurality of arms in parallel with at least the first main electrode or the second main electrode. May be.
  • the power converter according to the present invention may be characterized in that the third main electrode is arranged so as to overlap one or more semiconductor elements in the vertical direction.
  • the semiconductor module further includes a first main terminal portion and a second main terminal portion connected to the outside, and the first main terminal portion and the second main terminal portion are respectively the first main terminal portion.
  • the first main terminal portion is disposed on the front surface of the semiconductor module, and the second main terminal portion is disposed on the rear surface of the semiconductor module.
  • the second main terminal portion is electrically connected to the electrode and the second main electrode. It may be.
  • the power conversion device may be characterized in that the third main electrode has a portion that is in surface contact with the resin surface of the semiconductor module.
  • the power converter according to the present invention is characterized in that the semiconductor module has at least one arm sealed with resin, and the third main electrode is resin-sealed in the semiconductor module. There may be.
  • the power conversion device may be characterized in that the cooling surface of the semiconductor module is metal-bonded to the cooler via an insulating material.
  • FIG. 1 is a perspective view showing the configuration of the power converter according to the first embodiment of the present invention.
  • FIG. 2 is a circuit diagram of a three-phase inverter circuit configured using the power conversion device according to the embodiment of the present invention.
  • FIG. 3 is a perspective view showing the configuration of the power conversion device according to the second embodiment of the present invention.
  • Fig.4 (a) is a perspective view which shows the structure of the power converter device which concerns on 3rd Embodiment of this invention
  • FIG.4 (b) is sectional drawing in the A line of Fig.4 (a).
  • FIG.5 (a) is a perspective view which shows the structure of the power converter device which concerns on 4th Embodiment of this invention
  • FIG.5 (b) is sectional drawing in the B line
  • FIG. 6A is a perspective view showing a configuration of a power conversion device according to the fifth embodiment of the present invention
  • FIG. 6B is a cross-sectional view taken along line C in FIG. Fig.7 (a) is a perspective view which shows the structure of the power converter device which concerns on 6th Embodiment of this invention
  • FIG.7 (b) is sectional drawing in the D line of Fig.7 (a).
  • FIG. 11 is sectional drawing of the power converter device which concerns on the modification 1 of 7th Embodiment of this invention.
  • FIG. 12 is sectional drawing of the power converter device which concerns on the modification 2 of 7th Embodiment of this invention.
  • FIG. 13 is a perspective view of a power converter according to the eighth embodiment of the present invention.
  • FIG. 14A, FIG. 14B, and FIG. 14C are diagrams showing the configuration of the power conversion device according to the eighth embodiment of the present invention, and
  • FIG. FIG. 14B is a schematic diagram showing a current path during operation of the power conversion device.
  • FIG.14 (c) is a perspective view which shows the internal structure of the semiconductor module used for the power converter device which concerns on 8th Embodiment of this invention.
  • FIG. 15 (a) and 15 (b) are diagrams showing the configuration of the power conversion device according to the ninth embodiment of the present invention.
  • FIG. 15 (a) is a perspective view of the power conversion device
  • FIG. b) is a cross-sectional view of the power converter shown in FIG.
  • the power conversion apparatus 101 includes three bus bars 4, 7, 10, a support substrate 3, a first semiconductor element 5, and a second semiconductor element 8. Then, a bus bar portion 1 composed of flat plate-shaped portions 4a, 7a, 10a of each bus bar, a power module comprising a support substrate 3, a first semiconductor element 5, a second semiconductor element 8, and conductive portions 4b, 7b, 10b of each bus bar. Part 2 is roughly divided into two parts.
  • the power module unit 2 includes an insulating support substrate 3. On the support substrate 3, a conductive portion 4 b (fixed surface) of a bus bar 4 (plus side conductive member) and a bus bar 10 (minus side conductive member). ) Conductive portion 10b (fixed surface) and bus bar 7 (output-side conductive member) conductive portion 7b (fixed surface).
  • the bus bar 4 has a positive pole, and supplies a positive potential at point P in FIG. 2 to a first semiconductor element 5 described later.
  • the bus bar 10 has a negative pole, and supplies a negative potential at the point N (or called the N side) in FIG. 2 to a second semiconductor element 8 to be described later.
  • the bus bar 7 serves as a power output unit, and can supply a potential corresponding to the point S in FIG. 2 to a load connected to the power converter.
  • the positive potential and the negative potential are supplied to the power converter by the DC power supply VB connected via the bus bar 4 and the bus bar 10 of the power converter.
  • the present embodiment has a circuit configuration in which the voltage of the DC power source is directly switched to the output by the switching element.
  • Both the first semiconductor element 5 and the second semiconductor element 8 can perform both switching operation and reflux operation.
  • the first semiconductor element 5 forms an upper arm of one phase of the inverter device shown in FIG. 2
  • the second semiconductor element 8 forms a lower arm of one phase of the inverter device.
  • the connection point of an upper arm and a lower arm is S point shown in FIG.
  • the first semiconductor element 5 and the second semiconductor element 8 are connected to the controller MU. Switching operations of the first semiconductor element 5 and the second semiconductor element 8 are controlled by a signal from the controller MU.
  • the bus bars 7, 4, and 10 shown in FIG. 1 are each bent in a “U” shape in a side view, and the surface of the bus bar 7 that faces the support substrate 3 is a flat plate-shaped portion 7 a (output-side flat plate-shaped portion).
  • the surface of the bus bar 4 facing the support substrate 3 is a flat plate-shaped portion 4a (plus-side flat plate-shaped portion), and the surface of the bus bar 10 facing the support substrate 3 is flat-plate-shaped portion 10a (minus-side flat plate). Shape part).
  • the bus-bar part 1 is comprised by three flat shape part 4a, 7a, 10a.
  • bus bars 7, 4, and 10 are described as being formed by bending one flat plate member into a “U” shape when viewed from the side. Absent.
  • the bus bars 4, 7, 10 may be manufactured in a “U” shape in a side view by combining a plurality of flat plate-like members.
  • the flat plate-shaped portion 7a (output-side flat plate-shaped portion) is the first semiconductor element 5 and the second semiconductor element. 8 is arranged substantially parallel to the main surface. Further, the three flat plate shaped portions 4a, 7a, and 10a are also arranged substantially parallel to each other.
  • the first semiconductor element 5 and the flat plate-shaped portions 4 a, 7 a, and 10 a are arranged so as to overlap each other, and the flat plate-shaped portions 4 a, 7 a, and 10 a are more than the first semiconductor element 5.
  • the size of the capacitive coupling tends to be proportional to the area of the overlapping portion between the opposing surfaces, and tends to increase in inverse proportion to the distance between the opposing surfaces.
  • the main surface of the first semiconductor element 5 and the main surface of the second semiconductor element 8 and the three flat plate-shaped portions 4a, 7a, and 10a are arranged substantially parallel to each other, and the main surface of the first semiconductor element 5 and the first 2 Since the entire main surface of the semiconductor element 8 is arranged so as to overlap the flat plate-shaped portions 4a, 7a, 10a, the flat plate-shaped portions 4a, 7a, 10a of each bus bar, the first semiconductor element 5, and the second The capacitive coupling of the semiconductor element 8 increases.
  • the flat plate-shaped portions 4a, 7a and 10a of the bus bar are arranged so as to overlap with each other and the flat plate-shaped portion 7a for output is provided at the end, the current path of the bus bar 10 and the current path of the bus bar 4 are close to each other. Therefore, the capacitive coupling increases when the distance between the current path of the bus bar 10 and the current path of the bus bar 4 is small. Further, since the distance between the current path of the bus bar 10 and the current path of the bus bar 4 is small and the current path of the bus bar 10 and the current path of the bus bar 4 are close to each other, the current generated in each of the bus bars 4 and 10 and the mutual magnetic property are It becomes easy to obtain the action.
  • the flat plate-shaped portion 4a is arranged by arranging the flat plate-shaped portions 4a, 7a, 10a of the respective bus bars 4, 7, 10 in a range wider than the portion overlapping the entirety of the first semiconductor element 5 and the second semiconductor element 8. , 7a, 10a and the conductive portions 4b, 7b, 10b of the respective bus bars 4, 7, 10 are increased.
  • each bus bar 4, 7 and 10 is a shape in which the opposing areas are widened. Further, the bus bars 4, 7 and 10 are close to each other as long as they are not electrically connected to each other. The distance between 10a and the first semiconductor element 5 and the second semiconductor element 8 is preferably short.
  • illustration is abbreviate
  • the main component, structure, shape, number, and electrical characteristics can be arbitrarily selected.
  • each semiconductor element is installed so as to be either electrically in parallel or in series, or both. It is possible. Also in this case, it is desirable to arrange the flat plate-like portions 4a, 7a, 10a so as to overlap with respect to the main surfaces of all the semiconductor elements.
  • the main component and shape can be selected arbitrarily.
  • the conductive portions 4b, 7b and 10b and the connecting lines 6 and 9 have a large facing area between the flat plate shaped portions 4a, 7a and 10a and a short distance between the facing surfaces. As a result, both capacitive couplings increase and an inductance reduction effect is further obtained.
  • the withstand voltage of the members constituting the inverter for driving the motor is determined in consideration of the surge voltage generated inside the inverter.
  • the surge voltage can be suppressed by reducing the inductance of the current path.
  • not only the inductance of the bus bar alone but also the inductance of the entire inverter including the power module is reduced. Therefore, the withstand voltage of each member when configuring the inverter can be reduced, and the cost can be reduced.
  • FIG. 1 shows only one phase of the inverter device shown in FIG. 2, and in order to construct a three-phase inverter, the power converter device 101 shown in FIG. Just do it.
  • the power conversion device 102 according to the second embodiment includes three bus bars 4, 7, 10, two support substrates 23 a, 23 b, a first semiconductor element 5, and a second semiconductor element 8.
  • bus bar part 21 which consists of flat shape part 4a, 7a, 10a of each bus bar, support substrate 23a, the 1st semiconductor element 5, power module part 22a which consists of conductive parts 4b, 7b1 of each bus bar, support board 23b,
  • the power module portion 22b is composed of the second semiconductor element 8 and the conductive portions 7b2 and 10b of the bus bars.
  • the power module portions 22a and 22b include insulating support substrates 23a and 23b.
  • the conductive portion 4b of the bus bar 4 serving as a positive pole (corresponding to the point P in FIG. 2) and the power
  • the conductive portion 7b1 of the bus bar 7 serving as an output portion (corresponding to the point S in FIG. 2) is provided.
  • the conductive portion 10b of the bus bar 10 that becomes the negative pole (corresponding to the N point in FIG. 2) and the conductive portion of the bus bar 7 that becomes the power output portion (corresponding to the S point in FIG. 2). 7b2 is provided.
  • the conductive portion 4b of the bus bar 4 is provided with the first semiconductor element 5 (Q1, D1 shown in FIG. 2), and the conductive portion 7b2 of the bus bar 7 is provided with the second semiconductor element 8 (Q2, Q2, shown in FIG. 2). D2) is provided. That is, the first semiconductor element 5 is indirectly supported via the bus bar 4 by the support substrate 23a. The second semiconductor element 8 is indirectly supported through the bus bar 7 by the support substrate 23b. In addition, not only indirectly but it is good also as a structure supported directly on the insulating support substrates 23a and 23b.
  • the first semiconductor element 5 and the flat plate-shaped portions 4 a, 7 a, and 10 a are disposed so as to overlap each other, and the flat plate-shaped portions 4 a, 7 a, and 10 a are wider than the first semiconductor element 5. It is arranged over. That is, when viewed in plan, the entire first semiconductor element 5 is disposed so as to be covered by the flat plate-shaped portions 4a, 7a, and 10a, and the flat plate-shaped portions 4a, 7a, and 10a are disposed in a wider area. Has been.
  • the second semiconductor element 8 and the flat plate-shaped portions 4 a, 7 a, and 10 a are disposed so as to overlap each other, and the flat plate-shaped portions 4 a, 7 a, and 10 a are wider than the first semiconductor element 5. It is arranged over.
  • the main surface of the first semiconductor element 5 and the main surface of the second semiconductor element 8 and the three flat plate-shaped portions 4a, 7a, and 10a are respectively It arrange
  • the capacitive coupling between the flat plate shaped portions 4a, 7a, 10a of each bus bar and the first semiconductor element 5 and the second semiconductor element 8 is increased as in the first embodiment described above.
  • the flat plate-shaped portions 4a, 7a and 10a of the bus bar are arranged so as to overlap with each other and the flat plate-shaped portion 7a for output is provided at the end, the current path of the bus bar 10 and the current path of the bus bar 4 are close to each other. Therefore, it becomes easier to obtain the interaction between the current generated in each bus bar 10 and 4 and magnetism.
  • the flat plate-shaped portion 4a is arranged by arranging the flat plate-shaped portions 4a, 7a, 10a of the respective bus bars 4, 7, 10 in a range wider than the portion overlapping the entirety of the first semiconductor element 5 and the second semiconductor element 8. , 7a, 10a and the conductive portions 4b, 7b1, 7b2, 10b of the bus bars 4, 7, 10 are increased in capacitive coupling. Due to these factors, it is possible to reduce the inductance of the entire power conversion device 102 including the bus bar portion 21 and the power module portions 22a and 22b. As a result, it is possible to suppress the occurrence of a surge voltage caused by the inductance.
  • each bus bar 4, 7 and 10 is a shape in which the opposing areas are widened. Further, the bus bars 4, 7 and 10 are close to each other as long as they are not electrically connected to each other. The distance between 10a and the first semiconductor element 5 and the second semiconductor element 8 is preferably short.
  • the main component, structure, shape, number, and electrical characteristics can be arbitrarily selected.
  • each element should be installed so as to be either in parallel or in series or both. Is possible.
  • the main component and shape can be selected arbitrarily.
  • the conductive portions 4b, 7b1, 7b2, 10b and the connecting lines 6, 9 have a large facing area between the flat plate-shaped portions 4a, 7a, 10a and a short distance between the facing surfaces. As a result, both capacitive couplings increase and the inductance can be further reduced.
  • the power conversion device 103 according to the third embodiment is different from the power conversion device 101 (see FIG. 1) shown in the first embodiment in that a sealing agent 24 is provided on the bus bar portion 1 side. To do.
  • a sealing agent 24 is provided on the bus bar portion 1 side.
  • the power conversion device 103 includes three plate-shaped portions 4a (plus-side plate-shaped portions), a plate-shaped portion 7a (output-side plate-shaped portions), and a plate-shaped portion 10a (minus-side plate-shaped portions).
  • the bus bar portion 1 is sealed with a sealant 24.
  • FIG. 4B shows a cross-sectional view taken along line A shown in FIG. As shown in FIG. 4B, the bus bar portion 1 including the three flat plate-shaped portions 4a, 7a, and 10a is sealed with two types of resins 24a and 24b.
  • FIG. 4B shows a state where the periphery of the bus bar portion 1 and the power module portion 2 is sealed with a resin 24a.
  • the size of the capacitive coupling tends to be proportional to the area of the overlapping portion between the opposing surfaces, and tends to increase in inverse proportion to the distance between the opposing surfaces.
  • the dielectric constant between the opposing surfaces increases by filling the resin between the opposing surfaces, the magnitude of the capacitive coupling tends to increase.
  • the capacitive coupling between the regions between the flat plate-shaped portions 4a, 7a and 10a and the first semiconductor element 5 and the second semiconductor element 8 can be enhanced. Moreover, since the dielectric constant of the space between the region between the flat plate-shaped portions 4a, 7a, and 10a and the first semiconductor element 5 and the second semiconductor element 8 is set high by the resin 24b, the interaction between the current paths is increased. Can be increased. And the inductance which arises between the bus bar part 1 and the power module part 2 by these two effects can be reduced further.
  • the bus bar portion 1 and the power module portion 2 are magnetically formed by the resin 24a. Shielded. That is, the magnetic field generated in the bus bar unit 1 and the power module unit 2 is prevented from leaking outside the region surrounded by the resin 24a, and as a result, the interaction of the current paths can be enhanced.
  • the power converter device 104 which concerns on 4th Embodiment is the point which provided the sealing agent 25 in the power module part 2 side compared with the power converter device 101 (refer FIG. 1) shown in 1st Embodiment. Is different.
  • the same parts as those of the power conversion device 101 shown in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
  • the power conversion device 104 seals the support substrate 3 and the conductive portions 4b, 7b, and 10b mounted on the support substrate 3 with a sealant 25.
  • FIG. 5B shows a cross-sectional view taken along line B shown in FIG.
  • the power module unit 2 including the support substrate 3 and the conductive portions 4b, 7b, and 10b mounted on the support substrate 3 is sealed with two types of resins 25a and 25b. Yes.
  • each conductive portion 4b, 7b, 10b is sealed with a resin 25b having a high dielectric constant, and the region serving as the surrounding portion is sealed with a resin 25a having a high magnetic permeability.
  • the power converter device 105 which concerns on 5th Embodiment is the point which provided the sealing agent 26 so that the whole apparatus might be covered compared with the power converter device 101 (refer FIG. 1) shown in 1st Embodiment. Is different.
  • the same parts as those of the power conversion device 101 shown in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
  • the power conversion device 105 seals the bus bar portion 1 composed of three flat plate-shaped portions 4a, 7a, and 10a and the power module portion 2 composed of the support substrate 3 and the respective conductive portions 4b, 7b, and 10b. Seal with a stopper 26.
  • FIG. 6B shows a cross-sectional view taken along line C shown in FIG. As shown in FIG. 6B, the bus bar portion 1 and the power module portion 2 are sealed with two types of resins 26a and 26b.
  • Fig.7 (a) is a perspective view which shows the structure of the power converter device 106 which concerns on 6th Embodiment of this invention.
  • This power conversion device 106 constitutes one phase of a three-phase inverter device, as in the first embodiment described above.
  • the power converter 106 has a capacitor 29 (C1 shown in FIG. 2) on the upper side of the bus bar unit 1 as compared with the power converter 101 (see FIG. 1) shown in the first embodiment.
  • a sealant 27 is provided so as to cover the entire region including the bus bar portion 1 and the capacitor 29.
  • the bus bar portion 1 including the three flat plate shape portions 4a (plus side flat plate shape portion), the flat plate shape portion 7a (output side flat plate shape portion), and the flat plate shape portion 10a (minus side flat plate shape portion)
  • the bus bar 4 Capacitor 29 that connects between positive side conductive member
  • bus bar 10 negative side conductive member
  • FIG. 7B shows a cross-sectional view taken along line D shown in FIG.
  • the three flat plate shaped portions 4a, 7a, 10a and the capacitor 29 are sealed with two kinds of resins 27a, 27b.
  • the region between the capacitor 29 and each flat plate-shaped portion 4a, 7a, 10a is sealed with a resin 27b having a high dielectric constant, and the region surrounding the capacitor 29 is sealed with a resin 27a having a high magnetic permeability.
  • This power conversion device 201 constitutes one phase of a three-phase inverter circuit, similarly to the power conversion devices described in the first to sixth embodiments.
  • FIG. 8A, FIG. 8B, and FIG. 8C are diagrams showing the configuration of the power conversion device 201 according to the seventh embodiment of the present invention.
  • 8A is a perspective view of the power converter 201
  • FIG. 8B is a plan view of the power converter 201.
  • FIG.8 (c) is the schematic which shows the current pathway in the power converter device 201 at the time of operation
  • the power conversion device 201 includes a semiconductor module 208L (first semiconductor module) that constitutes an upper arm, a semiconductor module 208R (second semiconductor module) that constitutes a lower arm, and a third main electrode 209 (output-side conductive member). Is done.
  • the third main electrode 209 electrically connects the semiconductor modules 208L and 208R in series. As a result of this connection, the third main electrode 209 and the semiconductor modules 208L and 208R form upper and lower arm circuits.
  • the third main electrode 209 outputs a potential at a connection point between the upper arm and the lower arm in the upper and lower arm circuits.
  • the semiconductor modules 208L and 208R constituting the power conversion device 201 have the same structure as the semiconductor module 208 shown in FIGS. 9A, 9B, and 9C.
  • the semiconductor modules 208L and 208R will be described as having the same structure.
  • the semiconductor modules 208L and 208R may be referred to as the semiconductor module 208.
  • FIG. 9A, FIG. 9B, and FIG. 9C are diagrams showing the semiconductor module 208 that constitutes the power conversion apparatus 201.
  • FIG. FIG. 9A shows a perspective view of the semiconductor module 208, and shows how power terminals 207 a and 207 b (first terminal portion and second terminal portion, respectively), which will be described later, are exposed to the outside of the semiconductor module 208.
  • FIG. 9B shows a perspective view of the internal structure of the semiconductor module 208.
  • FIG. 9C is a diagram showing a plan view of the internal structure of the semiconductor module 208.
  • the semiconductor module 208 is electrically connected to the semiconductor element 210, the first main electrode 203 and the second main electrode 202 electrically connected to the semiconductor element 210, and the first main electrode 203 and the second main electrode 202, respectively.
  • Power terminals 207a and 207b As shown in FIG. 9B, the semiconductor element 210 is disposed on the first main electrode 203, and the semiconductor element 210 and the first main electrode 203 are electrically connected via a bonding material 206 on the lower surface of the semiconductor element 210. It is connected. Further, the second main electrode 202 is disposed on the semiconductor element 210, and the semiconductor element 210 and the second main electrode 202 are electrically connected via a bonding material 206 on the upper surface of the semiconductor element 210.
  • a signal terminal connected to the semiconductor element 210 for transmitting a signal for controlling the semiconductor element 210 is omitted.
  • signal terminals for controlling the semiconductor element 210 are exposed on the surface of the semiconductor module 208.
  • the signal terminal is connected to the controller MU as shown in FIG.
  • an element for forming one arm of the three-phase inverter circuit in the semiconductor module 208 is indicated by one semiconductor element 210.
  • FIG. The semiconductor element 210 can perform both a switching operation and a reflux operation. The switching operation of the semiconductor element 210 is controlled by a signal from the controller MU transmitted through a signal terminal (not shown).
  • the third main electrode 209 constitutes a power terminal 207b of the semiconductor module 208L constituting the upper arm and a lower arm on the front side of the power conversion device 201.
  • the power terminal 207a of the semiconductor module 208R to be connected is connected.
  • the third main electrode 209 is connected and fixed to the power terminal 207b of the semiconductor module 208L and the power terminal 207a of the semiconductor module 208R by means such as screwing.
  • the third main electrode 209 has a portion that is placed on the resin surface on the upper surface of the semiconductor modules 208L and 208R, and is arranged so as to cover a part or the whole of the upper surface of the semiconductor modules 208L and 208R. .
  • the semiconductor modules 208L and 208R are disposed so as to straddle both upper surfaces.
  • the upper and lower arm circuits configured as described above are supplied with a potential from a power supply external to the power converter 201 by the bus bars 207P and 207N.
  • the bus bar 207P can be connected and fixed to the power terminal 207a of the semiconductor module 208L by means such as screwing.
  • the power terminal 207b of the semiconductor module 208R can be connected to the bus bar 207N by means of screwing or the like. It can be fixed.
  • a positive potential at point P in FIG. 2 is supplied to the power terminal 207a of the semiconductor module 208L through the bus bar 207P.
  • a negative potential at point N in FIG. 2 is supplied to the power terminal 207b of the semiconductor module 208R through the bus bar 207N.
  • FIG. 10 shows a cross-sectional view of the power conversion device 201 shown in FIG.
  • This cross-sectional view shows a cross section in a plane passing through the semiconductor element 210 of the semiconductor modules 208L and 208R and perpendicular to the lower surfaces of the semiconductor modules 208L and 208R.
  • the third main electrode 209 is disposed so as to contact the upper surfaces of the semiconductor modules 208L and 208R and cover the upper surfaces of the semiconductor modules 208L and 208R. That is, the third main electrode 209 is disposed so as to overlap with the semiconductor element 210 in the semiconductor modules 208L and 208R in the vertical direction.
  • the third main electrode 209 is close to the second main electrode 202 with a region insulated by the sealant 205 interposed therebetween.
  • FIG. 10 shows a state where the power conversion device 201 is disposed on the cooler RG.
  • the power conversion device 201 is in contact with the cooler RG on the lower surfaces of the semiconductor modules 208L and 208R. That is, the lower surfaces of the semiconductor modules 208L and 208R serve as cooling surfaces for the power conversion device 201 and the semiconductor modules 208L and 208R.
  • the cooler RG exhausts heat generated inside the power conversion device 201 when the power conversion device 201 operates, in particular, heat generated in the semiconductor element 210 to the outside of the power conversion device 201.
  • the third main electrode 209 has a structure close to the second main electrode 202 with the sealant 205 interposed therebetween, the heat generated in the semiconductor element 210 is generated by the second main electrode 202. , And the third main electrode 209 via the sealant 205.
  • the cooler RG has a structure close to the first main electrode 203 with the sealant 205 interposed therebetween, the heat generated in the semiconductor element 210 causes the first main electrode 203 and the sealant 205 to flow. To the cooler RG.
  • the first main electrode 203 and the second main electrode 202 are preferably made of a metal material that is relatively inexpensive and has good thermal conductivity, such as copper or aluminum.
  • the semiconductor element 210 in the semiconductor module 208L and the semiconductor element 210 in the semiconductor module 208R are the first semiconductor element 5 and the first semiconductor element 208, respectively. 2 corresponds to the semiconductor element 8.
  • the third main electrode 209 corresponds to a part of the bus bar 7 which is an output side conductive member.
  • the first main electrode 203 in the semiconductor module 208L corresponds to a part of the bus bar 4 that is a plus-side conductive member.
  • the second main electrode 202 in the semiconductor module 208 ⁇ / b> L corresponds to the connection line 6 and a part of the bus bar 7.
  • the first main electrode 203 in the semiconductor module 208 ⁇ / b> R corresponds to a part of the bus bar 7.
  • the second main electrode 202 in the semiconductor module 208R corresponds to the connection line 9 and a part of the bus bar 10 that is the negative side conductive member.
  • FIG. 8C shows a current path when current flows from the P side to the N side of the upper and lower arm circuits.
  • the P side and N side of the upper and lower arm circuits correspond to the points P and N in FIG. 2, respectively.
  • a point P1 indicates a joint portion between the power terminal 207a of the semiconductor module 208L and the bus bar 207P.
  • a point P9 indicates a joint portion between the power terminal 207b of the semiconductor module 208R and the bus bar 207N.
  • a point P4 indicates a joint portion between the power terminal 207b of the semiconductor module 208L and the third main electrode 209.
  • a point P6 indicates a joint portion between the power terminal 207a of the semiconductor module 208R and the third main electrode 209.
  • Points P2 and P7 indicate joint portions of the first main electrode 203 and the semiconductor element 210 in the semiconductor modules 208L and 208R, respectively.
  • Points P3 and P8 indicate joint portions of the second main electrode 202 and the semiconductor element 210 in the semiconductor modules 208L and 208R, respectively.
  • a point P5 indicates a position near the middle between the points P4 and P6 in the third main electrode 209.
  • the current introduced from the bus bar 207P to the power conversion device 201 is the point P1, P2, P3, P4, P5.
  • the first current path flows counterclockwise in turn, and then the second current path flows counterclockwise in the order of points P5, P6, P7, P8, and P9.
  • the first current circuit includes the third main electrode 209 and the semiconductor module 208L. More specifically, the first current circuit includes the third main electrode 209, the power terminal 207a of the semiconductor module 208L, the first main electrode 203, the semiconductor element 210, the second main electrode 202, and the power terminal 202b.
  • the second current circuit is composed of the third main electrode 209 and the semiconductor module 208R. More specifically, the second current circuit includes the third main electrode 209, the power terminal 207a of the semiconductor module 208R, the first main electrode 203, the semiconductor element 210, the second main electrode 202, and the power terminal 202b.
  • a first magnetic field in a direction from the lower surface to the upper surface of the power conversion device 201 is generated in a region surrounded by the first current path.
  • a second magnetic field from the lower surface to the upper surface of the power conversion device 201 is generated in a region surrounded by the second current path.
  • the first magnetic field is directed from the upper surface to the lower surface of the power conversion device 201 outside the region surrounded by the first current path.
  • the second magnetic field is directed from the upper surface to the lower surface of the power converter 201 outside the region surrounded by the second current path. For this reason, the first magnetic field and the second magnetic field face in opposite directions, so that they weaken each other.
  • the semiconductor modules 208L and 208R are arranged adjacent to each other, and the first magnetic field and the second magnetic field that are generated when a current flows through the semiconductor modules 208L and 208R are mutually weakened. This corresponds to suppressing the radiation of the magnetic field from the power converter 201 by increasing the interaction between the semiconductor modules 208L and 208R. By increasing the interaction between the semiconductor modules 208L and 208R and increasing the effect of canceling out magnetic fields, the overall inductance of the power conversion device 201 can be reduced.
  • the third main electrode 209 is disposed on the semiconductor modules 208L and 208R so as to straddle both the semiconductor modules 208L and 208R and covers the upper and lower arm circuits, the semiconductor modules 208L and 208R are disposed.
  • the leakage of the first magnetic field and the second magnetic field radiated from the outside is suppressed. Therefore, the magnetic field strengths of the first magnetic field and the second magnetic field in the power conversion device 201 are improved, so that the effect of canceling each other between the first magnetic field and the second magnetic field is enhanced. As a result, the inductance of the entire power conversion device 201 can be reduced.
  • the third main electrode 209 is disposed on the semiconductor modules 208L and 208R, so that the third main electrode 209, the first main electrode 203, and the second main electrode 202 are close to each other.
  • the mutual inductance increases between at least one of the first main electrode 203 or the second main electrode 202 and the third main electrode 209, the overall inductance of the power converter 201 can be reduced. it can.
  • the power terminal 207a of the semiconductor module 208L and the power terminal 207b of the semiconductor module 208R are adjacent, the P side and N side of the upper and lower arm circuits are adjacent. For this reason, the PNs can be connected to an external circuit while being adjacent to each other. For example, if the bus bars 207P and 207N are overlapped with each other and connected to a capacitor, motor, battery, or the like at the circuit destination, the inductance to the connection destination can be reduced.
  • the inductance of the entire power conversion device 201 can be reduced, the surge voltage can be effectively reduced. Furthermore, the switching frequency can be increased by suppressing the surge voltage.
  • the third main electrode 209 and the cooler RG are close to the first main electrode 203 and the second main electrode 202, and the distance between the cooler RG and the first main electrode 203, the third main electrode 209, The distance between the second main electrodes 202 is shortened. Therefore, the heat generated in the power conversion device 201, particularly the heat generated in the semiconductor element 210 is transmitted to the first main electrode 203 and the second main electrode 202, and then transmitted to the third main electrode 209 and the cooler RG. The distance required for heat conduction is shortened. Since the heat generated inside the power conversion device 201 is finally transferred to the third main electrode 209 and the cooler RG to be exhausted from the power conversion device 201, the thermal resistance of the power conversion device 201 can be reduced. it can.
  • the third main electrode 209 is disposed close to the second main electrode 202, heat transfer is easy between the semiconductor modules 208L and 208R and the third main electrode 209. Therefore, heat can be transferred to the semiconductor modules 208L and 208R of the arm on the non-operating side of the upper and lower arm circuits. That is, the thermal resistance can be reduced also by the inverter operation.
  • the inductance reduction and the thermal resistance reduction of the entire power conversion device 201 can be realized at the same time, a separate heat countermeasure is required when the power conversion device 201 is increased in frequency. Therefore, the heat generated in the semiconductor module 208 can be easily released to the outside. Therefore, the power converter 201 can be reduced in size. That is, a small power conversion device 201 capable of high-frequency operation can be obtained.
  • the semiconductor module 208 is resin-sealed by molding, insulation can be maintained in parallel with the plane of the first main electrode 203 or the second main electrode 202 with high accuracy, so that the third main electrode 209 is made of semiconductor.
  • a high degree of parallelism can be maintained when used either inside or outside the module 208. Therefore, the mutual inductance between the semiconductor modules 208L and 208R can be made to work more effectively. As a result, the overall inductance of the power converter 201 can be reduced.
  • the resin is sealed, the heat distortion applied to the semiconductor element 210 mounted inside the resin and the solder material used for mounting can be reduced, so that the reliability is improved.
  • the warpage of the semiconductor module 208 can be suppressed, the degree of parallelism with respect to the warpage can be increased.
  • the thickness of the resin between the first main electrode 203, the second main electrode 202, and the third main electrode 209 is as thin as possible while ensuring the necessary insulation distance, and the effect of mutual inductance is higher.
  • the effect of reducing the inductance is increased.
  • the insulation distance can be minimized and the inductance can be further reduced.
  • the third main electrode 209 is externally attached to the semiconductor module 208, the third main electrode 209 and the second main electrode 202 are reliably insulated from each other while the third main electrode 209 and the second main electrode 202 are simultaneously insulated.
  • the distance between the main electrode 209 and the second main electrode 202 can be shortened.
  • the sealing agent 205 existing between the surface of the semiconductor module 208 and the second main electrode is used when molding the exterior of the semiconductor module 208.
  • the layer can be thinly formed and then the third main electrode 209 can be externally attached. Therefore, the distance between the third main electrode 209 and the second main electrode 202 can be shortened at the same time while reliably insulating the third main electrode 209 and the second main electrode 202.
  • the effect of the mutual inductance between the third main electrode 209 and the second main electrode 202 can be enhanced. it can. As a result, the effect of reducing the inductance of the entire power conversion device 201 is increased.
  • FIG. 11 has shown sectional drawing of the power converter device 301 which concerns on the modification 1 of 7th Embodiment.
  • This power conversion device 301 constitutes one phase of a three-phase inverter device, as in the first to seventh embodiments described above.
  • the power conversion device 301 according to the modification 1 is different from the power conversion device 201 (see FIG. 10) in that the upper arm and the lower arm are packaged in one semiconductor module 208W1.
  • the same parts as those of the power conversion device 301 shown in the seventh embodiment are denoted by the same reference numerals, and description thereof will be omitted.
  • the semiconductor module 208W1 has two semiconductor elements 210, two first main electrodes 203, and two second main electrodes 202, and power terminals 207a and 207b. There are also two each.
  • the semiconductor module 208W1 has the structure of two semiconductor modules 208, and a single semiconductor module 208W1 can constitute an upper and lower arm circuit.
  • the semiconductor module 208W1 is a component corresponding to the two arms of the three-phase inverter and is called a 2-in-1 power semiconductor module.
  • one semiconductor module 208W1 can constitute one phase of a three-phase inverter circuit.
  • the connection method between the power terminals 207a and 207b is the same as that of the power converter 201.
  • the third main electrode 209 is disposed so as to be in contact with the upper surface of the semiconductor module 208W1 and to cover the upper surface of the semiconductor module 208W1, so that the third main electrode 209 is insulated by the sealing agent 205.
  • the two main main electrodes 202 located in the semiconductor module 208W1 are close to each other across the region to be processed. Therefore, since the mutual inductance increases between at least one of the first main electrode 203 or the second main electrode 202 and the third main electrode 209, the inductance of the entire power conversion device 301 can be reduced.
  • the third main electrode 209 and the cooler RG are close to the first main electrode 203 and the second main electrode 202, and the distance between the third main electrode 209 and the first main electrode 203, The distance between the cooler RG and the second main electrode 202 is shortened. Therefore, similarly to the power converter 201, the heat generated inside the power converter 301 is transmitted to the third main electrode 209 and the cooler RG, and is easily exhausted from the power converter 301. Therefore, the thermal resistance of the power converter 301 can be reduced.
  • FIG. 12 shows a cross-sectional view of a power conversion device 401 according to Modification 2 of the seventh embodiment.
  • the cross section of the power converter device 401 is shown at a position corresponding to the cross sectional view shown in FIG. 10 when the power converter device 201 is described.
  • This power conversion device 401 constitutes one phase of a three-phase inverter device as in the first to seventh embodiments described above.
  • the power conversion device 401 according to the modification 2 is different from the power conversion device 301 (see FIG. 10) in that the third main electrode 209 is packaged in the semiconductor module 208W2.
  • the same parts as those of the power conversion device 301 shown in the seventh embodiment are denoted by the same reference numerals, and description thereof will be omitted.
  • the sealing agent 205 is reliably filled between the third main electrode 209 and the second main electrode 202. Therefore, it is necessary to devise measures such as increasing the distance between the third main electrode 209 and the second main electrode 202 with the sealant 205 as compared with the case where the third main electrode 209 is externally attached to the semiconductor module 208. .
  • the external work of the third main electrode 209 is unnecessary, so that versatility and mass productivity can be improved while being small.
  • the semiconductor module Within 208W2 Even in a situation where thermal stress and mechanical stress generated between the part constituting the upper arm and the part constituting the lower arm are generated, and warpage that cannot be suppressed by the sealant 205 may occur, the semiconductor module Within 208W2, the third main electrode 209 provided so as to cover the upper and lower arm circuits is supported, and the warpage of the semiconductor module 208W2 due to thermal stress and mechanical stress can be reduced. As a result, the semiconductor module 208W2 can be reliably kept in contact with the surface of the cooler.
  • This power conversion device 501 configures one phase of the three-phase inverter circuit, similarly to the power conversion devices described in the first to seventh embodiments and the first and second modifications of the seventh embodiment. To do.
  • FIG. 13 is a perspective view of the power conversion device 501 according to the eighth embodiment.
  • FIG. 14A, FIG. 14B, and FIG. 14C are diagrams showing the configuration of the power converter 501.
  • FIG. 14A is a plan view of the power converter 501.
  • FIG. ) Is a schematic diagram showing a current path during operation of the power conversion device 501.
  • FIG. 14C is a perspective view showing the internal structure of the semiconductor modules 208AL and 208AR (semiconductor module 208A) used in the power conversion device 501.
  • the semiconductor modules 208AL and 208AR constituting the power conversion device 501 will be described as having the same structure.
  • the semiconductor modules 208AL and 208AR may be referred to as the semiconductor module 208A.
  • the power terminals 207a and 207b are respectively disposed on the opposing surfaces of the semiconductor module 208A with the semiconductor element 210 interposed therebetween.
  • the power terminal 207a is disposed on the front surface of the semiconductor module 208A
  • the power terminal 207b is disposed on the rear surface of the semiconductor module 208A. Therefore, in the semiconductor module 208A, the power terminal 207a, the semiconductor element 210, and the power terminal 207b are arranged in substantially the same straight line in this order.
  • the power terminal 207a of the semiconductor module 208AL constituting the upper arm and the power terminal 207b of the semiconductor module 208AR constituting the lower arm are arranged adjacent to each other.
  • the power terminal 207b of the semiconductor module 208AL constituting the upper arm and the power terminal 207a of the semiconductor module 208AR constituting the lower arm are arranged adjacent to each other.
  • the power terminal 207b of the semiconductor module 208AL constituting the upper arm and the power terminal 207a of the semiconductor module 208AR constituting the lower arm are electrically connected by the third main electrode 209A, and the semiconductor module 208AL and the semiconductor module 208AR are They are connected in series so as to form upper and lower arm circuits.
  • one of the two semiconductor modules 208A is rotated 180 degrees and arranged to form semiconductor modules 208AL and 208AR. Therefore, as in the current path shown in FIG. 14B, the flow of current flowing from the P side to the N side of the upper and lower arm circuits proceeds in the order of points P1, P2, P3, and P4, and then turns back at point P5. , Following the flowing path in the order of points P6, P7, P8, and P9. Since the current flows in such a manner as shown in FIG. 14B, by shortening the length of the side from the point P4 to the point P6 in the current path in FIG. 14B, the current path (from the point P1 to the point on the semiconductor module 208AL side).
  • the mutual inductance between the side up to P4) and the current path on the semiconductor module 208AR side (side from the point P6 to the point P9) can be increased.
  • the effect of reducing the inductance of the entire power conversion device 501 is increased.
  • the width of the semiconductor module 208A can be reduced. Further, as compared with the case where the power terminals 207a and 207b are arranged on the same side surface (front surface) as in the semiconductor module 208 shown in the seventh embodiment, between the power terminals 207a and 207b of the semiconductor module 208A. Since the insulation distance can be easily shortened, the width between the semiconductor modules 208A when the semiconductor modules 208A are arranged can be narrowed. With these features, the power conversion device 501 can be downsized.
  • This power conversion device 601 constitutes one phase of a three-phase inverter circuit, similarly to the power conversion devices described in the first to eighth embodiments.
  • the power conversion device 601 shown in FIG. 15 includes two third main electrodes 209B and 209B separately on the third main electrode 209A of the power conversion device 501 described in the eighth embodiment via an insulator 235.
  • the state where 209C is arranged is shown. Since other configurations are the same as those of the power conversion device 501 of the eighth embodiment, description thereof is omitted.
  • terminals for connection with external circuits included in the third main electrodes 209A, 209B, and 209C are omitted.
  • the third main electrode 209C is electrically connected to the power terminal 207a of the semiconductor module 208AL by a connecting fitting 221.
  • the third main electrode 209B is electrically connected to the power terminal 207b of the semiconductor module 208AR by a connecting fitting 222. Therefore, the third main electrode 209C is connected to the P side of the upper and lower arm circuit, and the third main electrode 209B is connected to the N side of the upper and lower arm circuit.
  • the effect of current folding back is provided.
  • a mutual inductance effect can be generated between the third main electrode 209C and the semiconductor module 208AL.
  • the third main electrode 209B connected to the N side is provided to oppose the current direction of the power terminal 207b (N side) of the semiconductor module 208AR, the third main electrode 209B is similarly provided. It is possible to generate a mutual inductance effect between the semiconductor module 208AR and the semiconductor module 208AR.
  • the upper and lower arrangement of the plurality of third main electrodes 209A, 209B, and 209C can be freely changed depending on the configuration with the semiconductor modules 208AL and 208AR, and an optimum arrangement can be selected so as to obtain a predetermined effect.
  • the third main electrodes 209A, 209B, and 209C are connected to a capacitor, a motor, a battery, or the like at a circuit destination while the third main electrodes 209A, 209B, and 209C are overlapped, inductance to the connection destination can be reduced.
  • each of the semiconductor elements 5, 8, and 210 has been described as a single element part. However, if the switching operation and the reflux operation are performed, it is not necessarily formed as a single element part, and each of the semiconductor elements 5, 8, 210 is formed by combining a plurality of element parts. It does not matter.
  • a MOSFET can perform a switching operation and a recirculation operation with a PN diode built in the MOSFET, so that the semiconductor elements 5, 8, and 210 can be configured by using one MOSFET as an element component.
  • an FWD diode
  • the semiconductor elements 5, 8, 210 may be made of Si, SiC, or the like.
  • an inverter having a circuit configuration in which the voltage of a DC power supply is directly connected to an output by a switching element and connected that is, a voltage type inverter has been described as an example.
  • the same effect can be obtained even when applied to an inverter having a circuit configuration in which a constant current is supplied from a DC power source via an inductor and a terminal into which the current flows is switched by switching, that is, a current type inverter.
  • a current type inverter by increasing the capacitive coupling between the bus bar constituting the inverter and the semiconductor element, the inductance of the entire inverter can be reduced, and the generation of a surge voltage caused by the inductance can be suppressed. .
  • the third main electrodes 209 and 209A output the potential at the connection point between the upper arm and the lower arm of the upper and lower arm circuits.
  • the third main electrodes 209 and 209A may alternatively output the P-side potential or the N-side potential of the upper and lower arm circuits.
  • the third main electrodes 209 and 209A are provided close to the second main electrode 202 in the semiconductor modules 208, 208W1, 208W2 and 208A and are arranged so as to cover the upper and lower arm circuits. This has the same effect as the seventh to ninth embodiments.
  • the semiconductor modules 208L and 208R or the semiconductor modules 208AL and 208AR have been described as having the same structure (semiconductor modules 208 and 208A), but the upper and lower arms constituting the phases of the three-phase inverter circuit
  • the structure is not necessarily the same as long as the structure is such that the magnetism generated by the current flowing through the semiconductor module 208L and the magnetism generated by the current flowing through the semiconductor module 208R cancel each other.
  • the power terminals 207a and 207b are provided as separate members from the first main electrode 203 and the second main electrode 202, respectively, and are electrically connected to the first main electrode 203 and the second main electrode 202 through the bonding material 206, respectively. Described as connected. However, it is not limited to such a structure, and the power terminal 207a and the first main electrode 203 may be integrally formed. Similarly, the power terminal 207b and the second main electrode 202 may be integrally formed.
  • connection / fixation method between the power terminals 207a, 207b and the third main electrode 209 and the connection / fixation method between the power terminals 207a, 207b and the bus bars 207P, 207N have been described as being screwed. Moreover, it is realizable also by the method of welding or joining with joining materials, such as solder. As long as the bus bars 207P and 207N are respectively connected and fixed to the power terminals 207a and 207b, they are not limited to these methods.
  • the semiconductor element 210 has been described as being directly connected to the first main electrode 203 and the second main electrode 202 by the bonding material 206, the semiconductor element 210 is connected between the semiconductor element 210 and the first main electrode 203 or between the semiconductor element 210 and the second main electrode 203.
  • the semiconductor element 210 may be connected between the two main electrodes 202 with a conductive substance made of copper or copper molybdenum interposed therebetween.
  • the insulating material examples include an insulating sheet made of resin and an insulating substrate made of ceramic.
  • a method of joining to the cooler RG there are a method of direct joining such as solder or wax material or indirect joining such as grease.
  • the cooler RG may be air-cooled or water-cooled.
  • Modification 1 and Modification 2 described in the seventh embodiment of the present invention can be applied to the other eighth and ninth embodiments. That is, instead of the semiconductor modules 208 and 208A corresponding to one arm, the semiconductor modules 208W1 and 208W2 in which two arm circuits are packaged in one can be used. It is also possible to use a semiconductor module in which two or more arm circuits are packaged.
  • the ninth embodiment of the present invention can also be applied to the other seventh embodiment, its modifications 1 and 2, and the eighth embodiment. That is, in addition to the third main electrode 209 for outputting the potential at the connection point of the upper arm and the lower arm, the third main electrode electrically connected to the P side and the N side of the upper and lower arm circuits, respectively. It may be provided.
  • the plus-side flat plate-shaped portion, the minus-side flat plate-shaped portion, and the output-side flat plate-shaped portion are arranged so that the main surfaces of the first semiconductor element and the second semiconductor element are substantially parallel.
  • the capacitive coupling between the members and the capacitive coupling between the conductive member and the semiconductor element can be increased, and the inductance existing in the entire power conversion device can be reduced.

Abstract

A plate-shaped part (4a) of a bus bar (4) that serves as a positive-side conductive member, a plate-shaped part (10a) of a bus bar (10) that serves as a negative-side conductive member and a plate-shaped part (7a) of a bus bar (7) that serves as an output-side conductive member are arranged so as to be generally parallel to the main surfaces of a first semiconductor element (5) and a second semiconductor element (8). Consequently, the capacitive coupling between respective regions among the plate-shaped parts (4a, 7a, 10a) and the first semiconductor element (5) and the second semiconductor element (8) can be increased, thereby reducing the inductance of the device as a whole.

Description

電力変換装置Power converter
　本発明は、複数のスイッチング素子を作動させるインバータ等に用いられる電力変換装置に係り、特にサージ電圧の発生を防止する技術に関する。 The present invention relates to a power conversion device used for an inverter or the like that operates a plurality of switching elements, and more particularly to a technique for preventing the generation of surge voltage.
　直流電力を交流電力に変換するためのインバータ装置は、スイッチング素子をオン、オフ操作するので、サージ電圧が発生する。従って、サージ電圧の発生を低減させる必要があり、例えば特許文献１に開示された技術が提案されている。 The inverter device for converting direct current power to alternating current power turns on and off the switching element, so that a surge voltage is generated. Therefore, it is necessary to reduce the generation of surge voltage, and for example, a technique disclosed in Patent Document 1 has been proposed.
　特許文献１には、スイッチング素子から電源側を見たときのインダクタンスを小さくするために、電源に接続される正極（高電位側）のバスバと負極（低電位側）のバスバに追加配線を設けることが記載されている。 In Patent Document 1, in order to reduce inductance when the power supply side is viewed from the switching element, additional wiring is provided on the positive (high potential side) bus bar and the negative (low potential side) bus bar connected to the power supply. It is described.
特開２００２－１４１４５２号公報JP 2002-141452 A
　しかしながら、上述した特許文献１に開示された例では、スイッチング素子の出力側（出力バスバ）については記載が無く、インバータ内のインダクタンスを低減することができない。従って、サージ電圧を効果的に低減することができない。 However, in the example disclosed in Patent Document 1 described above, the output side (output bus bar) of the switching element is not described, and the inductance in the inverter cannot be reduced. Therefore, the surge voltage cannot be reduced effectively.
　本発明は、このような課題を解決するためになされたものであり、その目的とするところは、装置全体のインダクタンスを低減することが可能な電力変換装置を提供することにある。 The present invention has been made to solve such a problem, and an object thereof is to provide a power conversion device capable of reducing the inductance of the entire device.
　上記目的を達成するため、本願発明に係る電力変換装置は、上アームを構成する第１半導体素子と、下アームを構成する第２半導体素子と、上アームにプラス電位を供給するプラス側導電部材と、下アームにマイナス電位を供給するマイナス側導電部材と、上アームと下アームとの接続点の電位を出力する出力側導電部材と、を備え、プラス側導電部材は、半導体素子の主面に対して略平行となるように配置されるプラス側平板形状部を有し、マイナス側導電部材は、主面に対して略平行となるように配置されるマイナス側平板形状部を有し、出力側導電部材は、半導体素子の主面に対して略平行となるように配置される出力側平板形状部を有する。 In order to achieve the above object, a power conversion device according to the present invention includes a first semiconductor element constituting an upper arm, a second semiconductor element constituting a lower arm, and a positive conductive member that supplies a positive potential to the upper arm. A negative-side conductive member that supplies a negative potential to the lower arm, and an output-side conductive member that outputs a potential at a connection point between the upper arm and the lower arm. The positive-side conductive member is a main surface of the semiconductor element. The negative side conductive member has a negative side flat plate-shaped portion arranged so as to be substantially parallel to the main surface. The output-side conductive member has an output-side flat plate-shaped portion that is disposed so as to be substantially parallel to the main surface of the semiconductor element.
　本願発明に係る電力変換装置は、プラス側平板形状部が、第１半導体素子の主面の全体に対して重複するように配置されること、もしくは、マイナス側平板形状部が、第２半導体素子の主面の全体に対して重複するように配置されること、の少なくとも１つが成立するようにプラス側平板形状部とマイナス側平板形状部とが配置されていることを特徴とするものであってもよい。 In the power conversion device according to the present invention, the plus-side flat plate-shaped portion is arranged so as to overlap the entire main surface of the first semiconductor element, or the negative-side flat plate-shaped portion is the second semiconductor element. The plus-side flat plate-shaped portion and the minus-side flat plate-shaped portion are arranged so that at least one of the arrangement is made to overlap with the entire main surface of the plate. May be.
　本願発明に係る電力変換装置は、第１半導体素子の一端側と第２半導体素子の一端側が接続され、プラス側導電部材は、第１半導体素子の他端側と接続され、マイナス側導電部材は、第２半導体素子の他端側に接続されることを特徴とするものであってもよい。 In the power conversion device according to the present invention, one end side of the first semiconductor element and one end side of the second semiconductor element are connected, the plus side conductive member is connected to the other end side of the first semiconductor element, and the minus side conductive member is The second semiconductor element may be connected to the other end side.
　本願発明に係る電力変換装置は、出力側導電部材が、第１半導体素子、及び第２半導体素子の、少なくとも一方の主面全体に対して重複するように配置されるものであってもよい。 The power conversion device according to the present invention may be arranged such that the output-side conductive member overlaps at least one main surface of the first semiconductor element and the second semiconductor element.
　本願発明に係る電力変換装置は、プラス側平板形状部、マイナス側平板形状部、及び出力側平板形状部を、樹脂にて封止することを特徴とするものであってもよい。 The power conversion device according to the present invention may be characterized in that the plus side flat plate portion, the minus side flat plate portion, and the output side flat plate portion are sealed with resin.
　本願発明に係る電力変換装置は、プラス側導電部材とマイナス側導電部材との間を接続するコンデンサを更に備え、プラス側平板形状部、マイナス側平板形状部、及び出力側平板形状部に加え、コンデンサを樹脂にて封止することを特徴とするものであってもよい。 The power converter according to the present invention further includes a capacitor that connects between the plus side conductive member and the minus side conductive member, in addition to the plus side flat plate shape portion, the minus side flat plate shape portion, and the output side flat plate shape portion, The capacitor may be sealed with resin.
　本願発明に係る電力変換装置は、第１半導体素子と第２半導体素子とを主面とが反対側の面で支持する支持基板を更に備え、プラス側導電部材、マイナス側導電部材、及び出力側導電部材が、それぞれ支持基板に直接的に固定するための固定面を有し、更に、第１半導体素子が、プラス側導電部材の固定面に設置され、第２半導体素子は、出力側導電部材の固定面に設置され、支持基板の少なくとも一部と、固定面、及び第１半導体素子、第２半導体素子を樹脂にて封止することを特徴とするものであってもよい。 The power converter according to the present invention further includes a support substrate that supports the first semiconductor element and the second semiconductor element on a surface opposite to the main surface, and includes a plus-side conductive member, a minus-side conductive member, and an output side. Each of the conductive members has a fixing surface for directly fixing to the support substrate, and further, the first semiconductor element is installed on the fixing surface of the plus-side conductive member, and the second semiconductor element is an output-side conductive member The fixing surface may be provided, and at least a part of the support substrate, the fixing surface, and the first semiconductor element and the second semiconductor element may be sealed with resin.
　本願発明に係る電力変換装置は、アームが、半導体素子と、半導体素子に主面で接続される第１主電極と、半導体素子に主面とは反対側の面で接続される第２主電極と、を有する半導体モジュールからなり、各アーム内で、第１主電極には、第２主電極よりも高電位の電位が印加され、複数の半導体モジュールが、上下アーム回路を形成するように直列に接続されており、プラス側導電部材、マイナス側導電部材、出力側導電部材のいずれかの一部を構成する第３主電極が、少なくとも第１主電極または第２主電極に平行する部位が垂直方向に重なる部分を有するように、半導体モジュールの冷却面と反対側に配置されること特徴とするものであってもよい。 In the power conversion device according to the present invention, the arm has a semiconductor element, a first main electrode connected to the semiconductor element on a main surface, and a second main electrode connected to the semiconductor element on a surface opposite to the main surface. In each arm, a potential higher than that of the second main electrode is applied to the first main electrode in each arm, and a plurality of semiconductor modules are connected in series so as to form upper and lower arm circuits. A third main electrode constituting a part of any of the positive side conductive member, the negative side conductive member, and the output side conductive member is at least a portion parallel to the first main electrode or the second main electrode. The semiconductor module may be arranged on the side opposite to the cooling surface of the semiconductor module so as to have a portion overlapping in the vertical direction.
　本願発明に係る電力変換装置は、第３主電極が、複数のアームの間を、少なくとも第１主電極または第２主電極に平行してまたがるように配置されることを特徴とするものであってもよい。 The power conversion device according to the present invention is characterized in that the third main electrode is disposed so as to straddle between the plurality of arms in parallel with at least the first main electrode or the second main electrode. May be.
　本願発明に係る電力変換装置は、第３主電極が、１つないし複数の半導体素子と垂直方向に重なるように配置されることを特徴とするものであってもよい。 The power converter according to the present invention may be characterized in that the third main electrode is arranged so as to overlap one or more semiconductor elements in the vertical direction.
　本願発明に係る電力変換装置は、半導体モジュールが、外部と接続する第１主端子部および第２主端子部を更に有し、第１主端子部および第２主端子部が、それぞれ第１主電極および第２主電極と電気的に接続され、共に半導体モジュールの前面に配置されていることを特徴とするものであってもよい。 In the power conversion device according to the present invention, the semiconductor module further includes a first main terminal portion and a second main terminal portion connected to the outside, and the first main terminal portion and the second main terminal portion are respectively the first main terminal portion. The electrode and the second main electrode may be electrically connected and both may be disposed on the front surface of the semiconductor module.
　本願発明に係る電力変換装置は、半導体モジュールが、外部と接続する第１主端子部および第２主端子部を更に有し、第１主端子部および第２主端子部が、それぞれ第１主電極および第２主電極と電気的に接続され、第１主端子部が、半導体モジュールの前面に配置され、第２主端子部は、半導体モジュールの後面に配置されていることを特徴とするものであってもよい。 In the power conversion device according to the present invention, the semiconductor module further includes a first main terminal portion and a second main terminal portion connected to the outside, and the first main terminal portion and the second main terminal portion are respectively the first main terminal portion. The first main terminal portion is disposed on the front surface of the semiconductor module, and the second main terminal portion is disposed on the rear surface of the semiconductor module. The second main terminal portion is electrically connected to the electrode and the second main electrode. It may be.
　本願発明に係る電力変換装置は、半導体モジュールが、金型成形で樹脂封止されることを特徴とするものであってもよい。 The power converter according to the present invention may be characterized in that the semiconductor module is resin-sealed by molding.
　本願発明に係る電力変換装置は、第３主電極が、半導体モジュールの樹脂表面に面接地している部位を有することを特徴とするものであってもよい。 The power conversion device according to the present invention may be characterized in that the third main electrode has a portion that is in surface contact with the resin surface of the semiconductor module.
　本願発明に係る電力変換装置は、半導体モジュールが、樹脂封止された少なくとも１つ以上のアームを有し、第３主電極が、半導体モジュール内に樹脂封止されることを特徴とするものであってもよい。 The power converter according to the present invention is characterized in that the semiconductor module has at least one arm sealed with resin, and the third main electrode is resin-sealed in the semiconductor module. There may be.
　本願発明に係る電力変換装置は、半導体モジュールの冷却面が、絶縁材を介して冷却器に金属接合されることを特徴とするものであってもよい。 The power conversion device according to the present invention may be characterized in that the cooling surface of the semiconductor module is metal-bonded to the cooler via an insulating material.
　本願発明に係る電力変換装置は、複数の第３主電極が、プラス側導電部材の一部を構成する、少なくとも１つの第３主電極と、マイナス側導電部材の一部を構成する、少なくとも１つの第３主電極と、出力側平板形状部の一部を構成する、少なくとも１つの第３主電極と、から構成され、複数の第３主電極が、第１主電極または第２主電極の上に平行して重なる部分を有するように配置されることを特徴とするものであってもよい。 In the power conversion device according to the present invention, the plurality of third main electrodes constitute at least one third main electrode that constitutes a part of the plus side conductive member and at least 1 that constitutes a part of the minus side conductive member. One third main electrode and at least one third main electrode constituting a part of the output side plate-shaped portion, and the plurality of third main electrodes are formed of the first main electrode or the second main electrode. It may be characterized by being arranged so as to have a portion overlapping in parallel.
図１は、本発明の第１実施形態に係る電力変換装置の構成を示す斜視図である。FIG. 1 is a perspective view showing the configuration of the power converter according to the first embodiment of the present invention. 図２は、本発明の実施形態に係る電力変換装置を用いて構成される３相インバータ回路の回路図である。FIG. 2 is a circuit diagram of a three-phase inverter circuit configured using the power conversion device according to the embodiment of the present invention. 図３は、本発明の第２実施形態に係る電力変換装置の構成を示す斜視図である。FIG. 3 is a perspective view showing the configuration of the power conversion device according to the second embodiment of the present invention. 図４（ａ）は、本発明の第３実施形態に係る電力変換装置の構成を示す斜視図であり、図４（ｂ）は図４（ａ）のＡ線での断面図である。Fig.4 (a) is a perspective view which shows the structure of the power converter device which concerns on 3rd Embodiment of this invention, FIG.4 (b) is sectional drawing in the A line of Fig.4 (a). 図５（ａ）は、本発明の第４実施形態に係る電力変換装置の構成を示す斜視図であり、図５（ｂ）は図５（ａ）のＢ線での断面図である。Fig.5 (a) is a perspective view which shows the structure of the power converter device which concerns on 4th Embodiment of this invention, FIG.5 (b) is sectional drawing in the B line | wire of Fig.5 (a). 図６（ａ）は、本発明の第５実施形態に係る電力変換装置の構成を示す斜視図であり、図６（ｂ）は図６（ａ）のＣ線での断面図である。FIG. 6A is a perspective view showing a configuration of a power conversion device according to the fifth embodiment of the present invention, and FIG. 6B is a cross-sectional view taken along line C in FIG. 図７（ａ）は、本発明の第６実施形態に係る電力変換装置の構成を示す斜視図であり、図７（ｂ）は図７（ａ）のＤ線での断面図である。Fig.7 (a) is a perspective view which shows the structure of the power converter device which concerns on 6th Embodiment of this invention, FIG.7 (b) is sectional drawing in the D line of Fig.7 (a). 図８（ａ）、図８（ｂ）、図８（ｃ）は、本発明の第７実施形態に係る電力変換装置の構成を示す図であり、図８（ａ）は、電力変換装置の斜視図、図８（ｂ）は、電力変換装置の平面図、図８（ｃ）は、電力変換装置の動作時における電流経路を示す概略図である。FIG. 8A, FIG. 8B, and FIG. 8C are diagrams showing the configuration of the power conversion device according to the seventh embodiment of the present invention, and FIG. FIG. 8B is a plan view of the power conversion device, and FIG. 8C is a schematic diagram illustrating a current path during operation of the power conversion device. 図９（ａ）、図９（ｂ）、図９（ｃ）は、本発明の第７実施形態に係る電力変換装置に使用される半導体モジュールを示す図であり、図９（ａ）は、半導体モジュールの斜視図、図９（ｂ）は、半導体モジュールの内部構造の斜視図、図９（ｃ）は、半導体モジュールの内部構造の平面図を示す図である。9 (a), 9 (b), and 9 (c) are diagrams showing a semiconductor module used in the power conversion device according to the seventh embodiment of the present invention, and FIG. FIG. 9B is a perspective view of the internal structure of the semiconductor module, and FIG. 9C is a plan view of the internal structure of the semiconductor module. 図１０は、図８（ａ）に示す本発明の第７実施形態に係る電力変換装置のＸ線での断面図である。FIG. 10 is a cross-sectional view of the power converter according to the seventh embodiment of the present invention shown in FIG. 図１１は、本発明の第７実施形態の変形例１に係る電力変換装置の断面図である。FIG. 11: is sectional drawing of the power converter device which concerns on the modification 1 of 7th Embodiment of this invention. 図１２は、本発明の第７実施形態の変形例２に係る電力変換装置の断面図である。FIG. 12: is sectional drawing of the power converter device which concerns on the modification 2 of 7th Embodiment of this invention. 図１３は、本発明の第８実施形態に係る電力変換装置の斜視図である。FIG. 13 is a perspective view of a power converter according to the eighth embodiment of the present invention. 図１４（ａ）、図１４（ｂ）、図１４（ｃ）は、本発明の第８実施形態に係る電力変換装置の構成を示す図であり、図１４（ａ）は、電力変換装置の平面図、図１４（ｂ）は、電力変換装置の動作時における電流経路を示す概略図である。また、図１４（ｃ）は、本発明の第８実施形態に係る電力変換装置に使用される半導体モジュールの内部構造を示す斜視図である。FIG. 14A, FIG. 14B, and FIG. 14C are diagrams showing the configuration of the power conversion device according to the eighth embodiment of the present invention, and FIG. FIG. 14B is a schematic diagram showing a current path during operation of the power conversion device. Moreover, FIG.14 (c) is a perspective view which shows the internal structure of the semiconductor module used for the power converter device which concerns on 8th Embodiment of this invention. 図１５（ａ）、図１５（ｂ）は、本発明の第９実施形態に係る電力変換装置の構成を示す図であり、図１５（ａ）は、電力変換装置の斜視図、図１５（ｂ）は、図１５（ａ）に示す電力変換装置の断面図である。15 (a) and 15 (b) are diagrams showing the configuration of the power conversion device according to the ninth embodiment of the present invention. FIG. 15 (a) is a perspective view of the power conversion device, and FIG. b) is a cross-sectional view of the power converter shown in FIG.
　以下、本発明の実施形態を図面に基づいて説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
［第１実施形態の説明］
　図１は、本発明の第１実施形態に係る電力変換装置１０１の構成を示す斜視図である。この電力変換装置１０１は、例えば、３相のインバータ装置の１つの相を構成するものである。図２は、３相インバータ回路の回路図であり、Ｕ相、Ｖ相、Ｗ相の３相からなるスイッチング素子を備えている。図２に示す回路図では、Ｕ相は素子Ｑ１，Ｄ１，Ｑ２，Ｄ２によって構成され、Ｖ相は素子Ｑ３，Ｄ３，Ｑ４，Ｄ４によって構成され、Ｗ相は素子Ｑ５，Ｄ５，Ｑ６，Ｄ６によって構成される場合が表現されている。素子Ｑ１～Ｑ６はスイッチング動作が可能であり、素子Ｄ１～Ｄ６は還流動作が可能である。 [Description of First Embodiment]
FIG. 1 is a perspective view showing a configuration of a power conversion device 101 according to the first embodiment of the present invention. For example, the power conversion device 101 constitutes one phase of a three-phase inverter device. FIG. 2 is a circuit diagram of a three-phase inverter circuit, which includes a switching element composed of three phases of U phase, V phase, and W phase. In the circuit diagram shown in FIG. 2, the U phase is composed of elements Q1, D1, Q2, and D2, the V phase is composed of elements Q3, D3, Q4, and D4, and the W phase is composed of elements Q5, D5, Q6, and D6. The case where it is composed is expressed. The elements Q1 to Q6 can perform a switching operation, and the elements D1 to D6 can perform a reflux operation.
　そして、図１に示す電力変換装置１０１は、１つの相（例えば、Ｕ相）のスイッチング素子を搭載するパワーモジュールの配置構成を示している。 And the power converter device 101 shown in FIG. 1 has shown the arrangement configuration of the power module which mounts the switching element of one phase (for example, U phase).
　以下、図１を参照して、第１実施形態に係る電力変換装置１０１について説明する。図１に示すように、第１実施形態に係る電力変換装置１０１は、３つのバスバ４，７，１０と、支持基板３、及び第１半導体素子５、第２半導体素子８を備えている。そして、各バスバの平板形状部４ａ，７ａ，１０ａからなるバスバ部１と、支持基板３、第１半導体素子５、第２半導体素子８、各バスバの導電部４ｂ，７ｂ，１０ｂからなるパワーモジュール部２に大別して構成されている。 Hereinafter, the power conversion apparatus 101 according to the first embodiment will be described with reference to FIG. As shown in FIG. 1, the power conversion device 101 according to the first embodiment includes three bus bars 4, 7, 10, a support substrate 3, a first semiconductor element 5, and a second semiconductor element 8. Then, a bus bar portion 1 composed of flat plate-shaped portions 4a, 7a, 10a of each bus bar, a power module comprising a support substrate 3, a first semiconductor element 5, a second semiconductor element 8, and conductive portions 4b, 7b, 10b of each bus bar. Part 2 is roughly divided into two parts.
　パワーモジュール部２は、絶縁性の支持基板３を備えており、該支持基板３上には、バスバ４（プラス側導電部材）の導電部４ｂ（固定面）と、バスバ１０（マイナス側導電部材）の導電部１０ｂ（固定面）と、バスバ７（出力側導電部材）の導電部７ｂ（固定面）が設けられている。バスバ４はプラス極となっており、図２のＰ点でのプラス電位を、後述する第１半導体素子５に供給している。バスバ１０はマイナス極となっており、図２のＮ点（もしくはＮ側と呼ぶ）でのマイナス電位を、後述する第２半導体素子８に供給している。バスバ７は電力の出力部となっており、図２のＳ点に対応する電位を、電力変換装置に接続された負荷に対して供給できるようになっている。 The power module unit 2 includes an insulating support substrate 3. On the support substrate 3, a conductive portion 4 b (fixed surface) of a bus bar 4 (plus side conductive member) and a bus bar 10 (minus side conductive member). ) Conductive portion 10b (fixed surface) and bus bar 7 (output-side conductive member) conductive portion 7b (fixed surface). The bus bar 4 has a positive pole, and supplies a positive potential at point P in FIG. 2 to a first semiconductor element 5 described later. The bus bar 10 has a negative pole, and supplies a negative potential at the point N (or called the N side) in FIG. 2 to a second semiconductor element 8 to be described later. The bus bar 7 serves as a power output unit, and can supply a potential corresponding to the point S in FIG. 2 to a load connected to the power converter.
　電力変換装置のバスバ４およびバスバ１０を介して接続された直流の電源ＶＢによって、プラス電位およびマイナス電位は、電力変換装置に供給されている。図２に示すように、本実施形態では、直流の電源の電圧をスイッチング素子によってそのまま出力にスイッチングして繋げる回路構成となっている。 The positive potential and the negative potential are supplied to the power converter by the DC power supply VB connected via the bus bar 4 and the bus bar 10 of the power converter. As shown in FIG. 2, the present embodiment has a circuit configuration in which the voltage of the DC power source is directly switched to the output by the switching element.
　そして、バスバ４の導電部４ｂには、図２に示すＱ１，Ｄ１に対応する、平板形状の第１半導体素子５が設けられ、バスバ７の導電部７ｂには、図２に示すＱ２，Ｄ２に対応する、平板形状の第２半導体素子８が設けられている。即ち、第１半導体素子５は、支持基板３によりバスバ４を介して間接的に支持されている。また、第２半導体素子８は、支持基板３によりバスバ７を介して間接的に支持されている。なお、間接的に限らず、絶縁性の支持基板３上に直接的に支持される構成としても良い。 The conductive portion 4b of the bus bar 4 is provided with a flat plate-shaped first semiconductor element 5 corresponding to Q1 and D1 shown in FIG. 2, and the conductive portion 7b of the bus bar 7 has Q2, D2 shown in FIG. A flat plate-like second semiconductor element 8 corresponding to the above is provided. That is, the first semiconductor element 5 is indirectly supported by the support substrate 3 via the bus bar 4. The second semiconductor element 8 is indirectly supported by the support substrate 3 via the bus bar 7. In addition, not only indirectly but it is good also as a structure supported directly on the insulating support substrate 3. FIG.
　第１半導体素子５、第２半導体素子８は共に、スイッチング動作、還流動作の両方の動作が可能である。ここで第１半導体素子５は、図２に示すインバータ装置の１つの相の上アームを形成しており、第２半導体素子８は、インバータ装置の１つの相の下アームを形成している。そして、上アームと下アームの接続点が、図２に示すＳ点である。 Both the first semiconductor element 5 and the second semiconductor element 8 can perform both switching operation and reflux operation. Here, the first semiconductor element 5 forms an upper arm of one phase of the inverter device shown in FIG. 2, and the second semiconductor element 8 forms a lower arm of one phase of the inverter device. And the connection point of an upper arm and a lower arm is S point shown in FIG.
　図２に示すように、第１半導体素子５および第２半導体素子８は、コントローラＭＵに接続されている。コントローラＭＵからの信号によって、第１半導体素子５、および第２半導体素子８のスイッチング動作が制御される。 As shown in FIG. 2, the first semiconductor element 5 and the second semiconductor element 8 are connected to the controller MU. Switching operations of the first semiconductor element 5 and the second semiconductor element 8 are controlled by a signal from the controller MU.
　図１に示すバスバ７，４，１０は、それぞれ側面視「Ｕ」字形状に折り曲げられており、バスバ７の、支持基板３と対向する面が平板形状部７ａ（出力側平板形状部）とされ、バスバ４の、支持基板３と対向する面が平板形状部４ａ（プラス側平板形状部）とされ、更に、バスバ１０の、支持基板３と対向する面が平板形状部１０ａ（マイナス側平板形状部）とされている。そして、３つの平板形状部４ａ，７ａ，１０ａにより、バスバ部１が構成されている。 The bus bars 7, 4, and 10 shown in FIG. 1 are each bent in a “U” shape in a side view, and the surface of the bus bar 7 that faces the support substrate 3 is a flat plate-shaped portion 7 a (output-side flat plate-shaped portion). The surface of the bus bar 4 facing the support substrate 3 is a flat plate-shaped portion 4a (plus-side flat plate-shaped portion), and the surface of the bus bar 10 facing the support substrate 3 is flat-plate-shaped portion 10a (minus-side flat plate). Shape part). And the bus-bar part 1 is comprised by three flat shape part 4a, 7a, 10a.
　なお、上記の記載ではバスバ７，４，１０は平板状の１枚の部材を折り曲げ加工して、側面視「Ｕ」字形状とする旨説明しているが、必ずしも折り曲げ加工で製造する必要はない。例えば、複数枚の平板状の部材を組み合わせることで、バスバ４，７，１０が側面視「Ｕ」字形状になるように製造しても良い。 In the above description, the bus bars 7, 4, and 10 are described as being formed by bending one flat plate member into a “U” shape when viewed from the side. Absent. For example, the bus bars 4, 7, 10 may be manufactured in a “U” shape in a side view by combining a plurality of flat plate-like members.
　従って、図１、図２に示すように、電力変換装置１０１において、第１半導体素子５は上アームを形成し、第２半導体素子８は下アームを形成している。図１に示すように、上アームにプラス電位を供給するプラス側導電部材であるバスバ４のうち、平板形状部４ａ（プラス側平板形状部）は、第１半導体素子５及び第２半導体素子８の主面（支持基板３側の面とは反対側となる面）と略平行に配置される。また、下アームにマイナス電位を供給するマイナス側導電部材であるバスバ１０のうち、平板形状部１０ａ（マイナス側平板形状部）は、第１半導体素子５及び第２半導体素子８の主面と略平行に配置される。更に、上アームと下アームとの接続点の電位を出力する出力側導電部材であるバスバ７のうち、平板形状部７ａ（出力側平板形状部）は、第１半導体素子５及び第２半導体素子８の主面と略平行に配置される。また、３つの平板形状部４ａ，７ａ，１０ａについてもそれぞれが互いに略平行に配置されることになる。 Therefore, as shown in FIGS. 1 and 2, in the power conversion device 101, the first semiconductor element 5 forms an upper arm and the second semiconductor element 8 forms a lower arm. As shown in FIG. 1, in the bus bar 4 that is a plus-side conductive member that supplies a plus potential to the upper arm, the flat plate-shaped portion 4 a (plus-side flat plate-shaped portion) includes the first semiconductor element 5 and the second semiconductor element 8. The main surface (the surface opposite to the surface on the support substrate 3 side) is arranged substantially in parallel. Further, in the bus bar 10 that is a negative conductive member that supplies a negative potential to the lower arm, the flat plate-shaped portion 10 a (negative flat plate-shaped portion) is substantially the main surface of the first semiconductor element 5 and the second semiconductor element 8. Arranged in parallel. Further, in the bus bar 7 that is an output side conductive member that outputs a potential at a connection point between the upper arm and the lower arm, the flat plate-shaped portion 7a (output-side flat plate-shaped portion) is the first semiconductor element 5 and the second semiconductor element. 8 is arranged substantially parallel to the main surface. Further, the three flat plate shaped portions 4a, 7a, and 10a are also arranged substantially parallel to each other.
　この際、第１半導体素子５と各平板形状部４ａ，７ａ，１０ａは、重複するように配置されており、更に、各平板形状部４ａ，７ａ，１０ａの方が、第１半導体素子５よりも広い範囲に亘って配置されている。即ち、平面視したときに、第１半導体素子５全体が各平板形状部４ａ，７ａ，１０ａに覆われるように配置され、且つ、各平板形状部４ａ，７ａ，１０ａの方が広い面積で配置されている。同様に、第２半導体素子８と各平板形状部４ａ，７ａ，１０ａとが重複するように配置され、更に、各平板形状部４ａ，７ａ，１０ａの方が、第２半導体素子８よりも広い範囲に亘って配置されている。 At this time, the first semiconductor element 5 and the flat plate-shaped portions 4 a, 7 a, and 10 a are arranged so as to overlap each other, and the flat plate-shaped portions 4 a, 7 a, and 10 a are more than the first semiconductor element 5. Are also arranged over a wide range. That is, when viewed in plan, the entire first semiconductor element 5 is disposed so as to be covered by the flat plate-shaped portions 4a, 7a, and 10a, and the flat plate-shaped portions 4a, 7a, and 10a are disposed in a wider area. Has been. Similarly, the second semiconductor element 8 and each flat plate-shaped portion 4a, 7a, 10a are arranged so as to overlap each other, and each flat plate-shaped portion 4a, 7a, 10a is wider than the second semiconductor element 8. It is arranged over a range.
　また、第１半導体素子５と導電部７ｂを接続するように、接続線６が設けられ、第２半導体素子８と導電部１０ｂを接続するように、接続線９が設けられている。即ち、第１半導体素子５の一端側と第２半導体素子８の一端側が接続線６により接続され、バスバ４（プラス側導電部材）は、第１半導体素子５の他端側と接続され、バスバ１０（マイナス側導電部材）は、第２半導体素子８の他端側に接続されている。 Further, a connection line 6 is provided so as to connect the first semiconductor element 5 and the conductive part 7b, and a connection line 9 is provided so as to connect the second semiconductor element 8 and the conductive part 10b. That is, one end side of the first semiconductor element 5 and one end side of the second semiconductor element 8 are connected by the connection line 6, and the bus bar 4 (plus side conductive member) is connected to the other end side of the first semiconductor element 5, and the bus bar 10 (minus side conductive member) is connected to the other end side of the second semiconductor element 8.
　次に、上述のように構成された第１実施形態に係る電力変換装置１０１の作用について説明する。上述したように、第１実施形態に係る電力変換装置１０１は、第１半導体素子５の主面及び第２半導体素子８の主面と、３つの平板形状部４ａ，７ａ，１０ａとが、それぞれ略平行に配置される。 Next, the operation of the power conversion device 101 according to the first embodiment configured as described above will be described. As described above, in the power conversion device 101 according to the first embodiment, the main surface of the first semiconductor element 5, the main surface of the second semiconductor element 8, and the three flat plate-shaped portions 4a, 7a, and 10a are respectively It arrange | positions substantially parallel.
　容量結合の大きさは、対向する面同士の重なる部分の面積に比例する傾向にあり、また対向する面同士の間の距離に反比例して増大する傾向がある。 The size of the capacitive coupling tends to be proportional to the area of the overlapping portion between the opposing surfaces, and tends to increase in inverse proportion to the distance between the opposing surfaces.
　第１半導体素子５の主面及び第２半導体素子８の主面と、３つの平板形状部４ａ，７ａ，１０ａとが、それぞれ略平行に配置され、第１半導体素子５の主面、及び第２半導体素子８の主面の全体が、平板形状部４ａ，７ａ，１０ａと重なるように配置されているため、各バスバの平板形状部４ａ，７ａ，１０ａと第１半導体素子５、及び第２半導体素子８の容量結合が増大する。 The main surface of the first semiconductor element 5 and the main surface of the second semiconductor element 8 and the three flat plate-shaped portions 4a, 7a, and 10a are arranged substantially parallel to each other, and the main surface of the first semiconductor element 5 and the first 2 Since the entire main surface of the semiconductor element 8 is arranged so as to overlap the flat plate-shaped portions 4a, 7a, 10a, the flat plate-shaped portions 4a, 7a, 10a of each bus bar, the first semiconductor element 5, and the second The capacitive coupling of the semiconductor element 8 increases.
　また、バスバの平板形状部４ａ，７ａ，１０ａを重ねて配置し、且つ、出力用の平板形状部７ａを端部に設けているため、バスバ１０の電流経路とバスバ４の電流経路が近接するので、バスバ１０の電流経路とバスバ４の電流経路の間の距離が小さいことにより、容量結合が増大する。またバスバ１０の電流経路とバスバ４の電流経路の間の距離が小さく、バスバ１０の電流経路とバスバ４の電流経路が近接しているため、各バスバ４、１０に発生する電流と磁気の相互作用を得易くなる。 Further, since the flat plate-shaped portions 4a, 7a and 10a of the bus bar are arranged so as to overlap with each other and the flat plate-shaped portion 7a for output is provided at the end, the current path of the bus bar 10 and the current path of the bus bar 4 are close to each other. Therefore, the capacitive coupling increases when the distance between the current path of the bus bar 10 and the current path of the bus bar 4 is small. Further, since the distance between the current path of the bus bar 10 and the current path of the bus bar 4 is small and the current path of the bus bar 10 and the current path of the bus bar 4 are close to each other, the current generated in each of the bus bars 4 and 10 and the mutual magnetic property are It becomes easy to obtain the action.
　更に、第１半導体素子５及び第２半導体素子８の全体と重なる部分よりも広い範囲で、各バスバ４，７，１０の平板形状部４ａ，７ａ，１０ａを配置することにより、平板形状部４ａ，７ａ，１０ａと、各バスバ４，７，１０の導電部４ｂ，７ｂ，１０ｂとの間の容量結合が増加する構造となる。 Furthermore, the flat plate-shaped portion 4a is arranged by arranging the flat plate-shaped portions 4a, 7a, 10a of the respective bus bars 4, 7, 10 in a range wider than the portion overlapping the entirety of the first semiconductor element 5 and the second semiconductor element 8. , 7a, 10a and the conductive portions 4b, 7b, 10b of the respective bus bars 4, 7, 10 are increased.
　そして、第１実施形態に係る電力変換装置１０１では、上記した各要因により、バスバ部１及びパワーモジュール部２からなる電力変換装置１０１全体のインダクタンスを低減することが可能となる。その結果、インダクタンスに起因して生じるサージ電圧の発生を抑制することが可能となる。 And in the power converter device 101 which concerns on 1st Embodiment, it becomes possible to reduce the inductance of the power converter device 101 whole which consists of the bus bar part 1 and the power module part 2 by each above-mentioned factor. As a result, it is possible to suppress the generation of surge voltage caused by inductance.
　また、バスバ４の平板形状部４ａは、第１半導体素子５の主面（図１において、第１半導体素子５の上側の面）全体に重複するように配置されること、もしくは、バスバ１０の平板形状部１０ａは、第２半導体素子８の主面（図１において、第２半導体素子８の上側の面）全体に重複するように配置されること、の少なくとも１つが成立するように平板形状部４ａおよび平板形状部１０ａが配置されることにより、各バスバ４，７，１０に対する第１半導体素子５、及び第２半導体素子８の容量結合が増大させることができる。その結果、インダクタンスを低減させることができる。 Further, the flat plate-like portion 4a of the bus bar 4 is arranged so as to overlap the entire main surface of the first semiconductor element 5 (the upper surface of the first semiconductor element 5 in FIG. 1), or the bus bar 10 The flat plate-shaped portion 10a is formed in a flat plate shape so that at least one of the arrangement is provided so as to overlap the entire main surface of the second semiconductor element 8 (the upper surface of the second semiconductor element 8 in FIG. 1). By disposing the portion 4a and the flat plate-shaped portion 10a, the capacitive coupling of the first semiconductor element 5 and the second semiconductor element 8 to the bus bars 4, 7, 10 can be increased. As a result, the inductance can be reduced.
　更に、第１半導体素子５と第２半導体素子８が接続線６を介して直列に接続されているので、第１半導体素子５及び第２半導体素子８と各バスバ４，７，１０との容量結合をより一層増大させることができ、インダクタンスの低減に寄与する。 Further, since the first semiconductor element 5 and the second semiconductor element 8 are connected in series via the connection line 6, the capacitance of the first semiconductor element 5 and the second semiconductor element 8 and each bus bar 4, 7, 10. Coupling can be further increased, contributing to a reduction in inductance.
　また、バスバ７（出力側導電部材）の平板形状部７ａが、第１半導体素子５及び第２半導体素子８の主面全体に対して重複するように配置されているので、より一層、容量結合を増大させることができ、インダクタンスを低減することができる。 Further, since the flat plate-like portion 7a of the bus bar 7 (output-side conductive member) is arranged so as to overlap the entire main surface of the first semiconductor element 5 and the second semiconductor element 8, further capacitive coupling is achieved. Can be increased, and the inductance can be reduced.
　また、各バスバ４，７，１０の形状は、対向する面積が広くなる形状であることが望ましく、更に、互いが電気的に導通しない範囲で近接し、各バスバの平板形状部４ａ，７ａ，１０ａと、第１半導体素子５及び第２半導体素子８との距離が短いことが望ましい。なお、図示を省略するが、使用目的に合わせて第１半導体素子５及び第２半導体素子８、導電部４ｂ，７ｂ，１０ｂの変更が可能である。 Moreover, it is desirable that the shape of each bus bar 4, 7 and 10 is a shape in which the opposing areas are widened. Further, the bus bars 4, 7 and 10 are close to each other as long as they are not electrically connected to each other. The distance between 10a and the first semiconductor element 5 and the second semiconductor element 8 is preferably short. In addition, although illustration is abbreviate | omitted, the change of the 1st semiconductor element 5, the 2nd semiconductor element 8, and the electroconductive part 4b, 7b, 10b is possible according to a use purpose.
　また、第１半導体素子５及び第２半導体素子８については、その主成分、構造、形状、個数、電気的特性を任意に選択することができる。更に、１つの導電部（４ｂ，７ｂ，１０ｂ）に対して複数の半導体素子を搭載する場合には、各半導体素子を電気的に並列或いは直列のいずれか一方、或いは両方になるように設置することが可能である。この場合についても、全ての半導体素子の主面に対して、各平板形状部４ａ，７ａ，１０ａが重複するように配置することが望ましい。また、導電部４ｂ，７ｂ，１０ｂ、及び接続線６，９については、その主成分、形状を任意に選択することができる。 In addition, for the first semiconductor element 5 and the second semiconductor element 8, the main component, structure, shape, number, and electrical characteristics can be arbitrarily selected. Further, when a plurality of semiconductor elements are mounted on one conductive portion (4b, 7b, 10b), each semiconductor element is installed so as to be either electrically in parallel or in series, or both. It is possible. Also in this case, it is desirable to arrange the flat plate- like portions 4a, 7a, 10a so as to overlap with respect to the main surfaces of all the semiconductor elements. Moreover, about the electroconductive parts 4b, 7b, 10b, and the connection lines 6 and 9, the main component and shape can be selected arbitrarily.
　導電部４ｂ，７ｂ，１０ｂ、接続線６，９の形状は、各平板形状部４ａ，７ａ，１０ａとの間の対向面積が大きく、且つ、対向面間の距離が短いことが望ましい。このことにより、双方の容量結合が増加し、インダクタンス低減効果がさらに得られることになる。 It is desirable that the conductive portions 4b, 7b and 10b and the connecting lines 6 and 9 have a large facing area between the flat plate shaped portions 4a, 7a and 10a and a short distance between the facing surfaces. As a result, both capacitive couplings increase and an inductance reduction effect is further obtained.
　即ち、電動機駆動用のインバータを構成する部材の耐電圧は、インバータ内部で発生するサージ電圧を考慮して耐電圧を決定している。サージ電圧は、電流経路のインダクタンスを低減することにより抑えることができる。本実施形態では、バスバ単体のインダクタンスの低減のみならず、パワーモジュールを含んだインバータ全体でのインダクタンスを低減している。よって、インバータを構成する際の各部材の耐電圧を低下させることができ、コストダウンを図ることができる。 That is, the withstand voltage of the members constituting the inverter for driving the motor is determined in consideration of the surge voltage generated inside the inverter. The surge voltage can be suppressed by reducing the inductance of the current path. In this embodiment, not only the inductance of the bus bar alone but also the inductance of the entire inverter including the power module is reduced. Therefore, the withstand voltage of each member when configuring the inverter can be reduced, and the cost can be reduced.
　なお、図１に示す電力変換装置１０１は、図２に示すインバータ装置の１相のみを示しており、３相のインバータを構成するためには、図１に示す電力変換装置１０１を３系統併設すれば良い。 1 shows only one phase of the inverter device shown in FIG. 2, and in order to construct a three-phase inverter, the power converter device 101 shown in FIG. Just do it.
［第２実施形態の説明］
　次に、本発明の第２実施形態について説明する。図３は、本発明の第２実施形態に係る電力変換装置１０２の構成を示す斜視図である。この電力変換装置１０２は、前述した第１実施形態と同様に、３相のインバータ装置の１つの相を構成するものである。 [Description of Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 3 is a perspective view showing the configuration of the power converter 102 according to the second embodiment of the present invention. This power conversion device 102 constitutes one phase of a three-phase inverter device, as in the first embodiment described above.
　以下、図３を参照して、第２実施形態に係る電力変換装置１０２について説明する。図３に示すように、第２実施形態に係る電力変換装置１０２は、３つのバスバ４，７，１０と、２つの支持基板２３ａ，２３ｂ、及び第１半導体素子５、第２半導体素子８を備えている。そして、各バスバの平板形状部４ａ，７ａ，１０ａからなるバスバ部２１と、支持基板２３ａ、第１半導体素子５、各バスバの導電部４ｂ，７ｂ１からなるパワーモジュール部２２ａと、支持基板２３ｂ、第２半導体素子８、各バスバの導電部７ｂ２，１０ｂからなるパワーモジュール部２２ｂに大別して構成されている。 Hereinafter, the power converter 102 according to the second embodiment will be described with reference to FIG. As shown in FIG. 3, the power conversion device 102 according to the second embodiment includes three bus bars 4, 7, 10, two support substrates 23 a, 23 b, a first semiconductor element 5, and a second semiconductor element 8. I have. And bus bar part 21 which consists of flat shape part 4a, 7a, 10a of each bus bar, support substrate 23a, the 1st semiconductor element 5, power module part 22a which consists of conductive parts 4b, 7b1 of each bus bar, support board 23b, The power module portion 22b is composed of the second semiconductor element 8 and the conductive portions 7b2 and 10b of the bus bars.
　パワーモジュール部２２ａ，２２ｂは、絶縁性の支持基板２３ａ，２３ｂを備えており、支持基板２３ａ上には、プラス極（図２のＰ点に対応）となるバスバ４の導電部４ｂと、電力の出力部（図２のＳ点に対応）となるバスバ７の導電部７ｂ１が設けられている。一方、支持基板２３ｂ上には、マイナス極（図２のＮ点に対応）となるバスバ１０の導電部１０ｂと、電力の出力部（図２のＳ点に対応）となるバスバ７の導電部７ｂ２が設けられている。 The power module portions 22a and 22b include insulating support substrates 23a and 23b. On the support substrate 23a, the conductive portion 4b of the bus bar 4 serving as a positive pole (corresponding to the point P in FIG. 2) and the power The conductive portion 7b1 of the bus bar 7 serving as an output portion (corresponding to the point S in FIG. 2) is provided. On the other hand, on the support substrate 23b, the conductive portion 10b of the bus bar 10 that becomes the negative pole (corresponding to the N point in FIG. 2) and the conductive portion of the bus bar 7 that becomes the power output portion (corresponding to the S point in FIG. 2). 7b2 is provided.
　そして、バスバ４の導電部４ｂには、第１半導体素子５（図２に示すＱ１，Ｄ１）が設けられ、バスバ７の導電部７ｂ２には、第２半導体素子８（図２に示すＱ２，Ｄ２）が設けられている。即ち、第１半導体素子５は、支持基板２３ａによりバスバ４を介して間接的に支持されている。また、第２半導体素子８は、支持基板２３ｂによりバスバ７を介して間接的に支持されている。なお、間接的に限らず、絶縁性の支持基板２３ａ，２３ｂ上に直接的に支持される構成としても良い。 The conductive portion 4b of the bus bar 4 is provided with the first semiconductor element 5 (Q1, D1 shown in FIG. 2), and the conductive portion 7b2 of the bus bar 7 is provided with the second semiconductor element 8 (Q2, Q2, shown in FIG. 2). D2) is provided. That is, the first semiconductor element 5 is indirectly supported via the bus bar 4 by the support substrate 23a. The second semiconductor element 8 is indirectly supported through the bus bar 7 by the support substrate 23b. In addition, not only indirectly but it is good also as a structure supported directly on the insulating support substrates 23a and 23b.
　また、バスバ７，４，１０は、それぞれ側面視「Ｕ」字形状に折り曲げられており、バスバ７の支持基板２３ａ，２３ｂと対向する面が平板形状部７ａとされ、バスバ４の支持基板２３ａ，２３ｂと対向する面が平板形状部４ａとされ、更に、バスバ１０の支持基板２３ａ，２３ｂと対向する面が平板形状部１０ａとされている。そして、３つの平板形状部４ａ，７ａ，１０ａにより、バスバ部２１が構成されている。 The bus bars 7, 4, 10 are each bent in a “U” shape when viewed from the side, and the surface of the bus bar 7 that faces the support substrates 23 a, 23 b is a flat plate-shaped portion 7 a, and the support substrate 23 a of the bus bar 4. , 23b is a flat plate-shaped portion 4a, and the bus bar 10 is a flat plate-shaped portion 10a. And the bus-bar part 21 is comprised by three flat shape part 4a, 7a, 10a.
　従って、図３に示すように、プラス側導電部材であるバスバ４の平板形状部４ａは、第１半導体素子５及び第２半導体素子８の主面（支持基板３側の面とは反対側となる面）と略平行に配置される。また、マイナス側導電部材であるバスバ１０の平板形状部１０ａは、第１半導体素子５及び第２半導体素子８の主面と略平行に配置される。更に、出力側導電部材であるバスバ７の平板形状部７ａは、第１半導体素子５及び第２半導体素子８の主面と略平行に配置される。また、３つの平板形状部４ａ，７ａ，１０ａについてもそれぞれが互いに略平行に配置されることになる。 Therefore, as shown in FIG. 3, the flat plate-shaped portion 4 a of the bus bar 4 that is a plus-side conductive member is formed on the main surface of the first semiconductor element 5 and the second semiconductor element 8 (on the side opposite to the surface on the support substrate 3 side). To be substantially parallel to the surface. In addition, the flat plate-shaped portion 10 a of the bus bar 10 that is a negative side conductive member is disposed substantially parallel to the main surfaces of the first semiconductor element 5 and the second semiconductor element 8. Further, the flat plate-like portion 7 a of the bus bar 7, which is an output side conductive member, is disposed substantially parallel to the main surfaces of the first semiconductor element 5 and the second semiconductor element 8. Further, the three flat plate shaped portions 4a, 7a, and 10a are also arranged substantially parallel to each other.
　この際、第１半導体素子５と各平板形状部４ａ，７ａ，１０ａは、重複配置されており、更に、各平板形状部４ａ，７ａ，１０ａの方が、第１半導体素子５よりも広い範囲に亘って配置されている。即ち、平面視したときに、第１半導体素子５全体が各平板形状部４ａ，７ａ，１０ａに覆われるように配置され、且つ、各平板形状部４ａ，７ａ，１０ａの方が広い面積で配置されている。同様に、第２半導体素子８と各平板形状部４ａ，７ａ，１０ａとが重複して配置され、更に、各平板形状部４ａ，７ａ，１０ａの方が、第１半導体素子５よりも広い範囲に亘って配置されている。 At this time, the first semiconductor element 5 and the flat plate-shaped portions 4 a, 7 a, and 10 a are disposed so as to overlap each other, and the flat plate-shaped portions 4 a, 7 a, and 10 a are wider than the first semiconductor element 5. It is arranged over. That is, when viewed in plan, the entire first semiconductor element 5 is disposed so as to be covered by the flat plate-shaped portions 4a, 7a, and 10a, and the flat plate-shaped portions 4a, 7a, and 10a are disposed in a wider area. Has been. Similarly, the second semiconductor element 8 and the flat plate-shaped portions 4 a, 7 a, and 10 a are disposed so as to overlap each other, and the flat plate-shaped portions 4 a, 7 a, and 10 a are wider than the first semiconductor element 5. It is arranged over.
　また、第１半導体素子５と導電部７ｂ１を接続するように、接続線６が設けられ、第２半導体素子８と導電部１０ｂを接続するように、接続線９が設けられている。 Also, a connection line 6 is provided so as to connect the first semiconductor element 5 and the conductive part 7b1, and a connection line 9 is provided so as to connect the second semiconductor element 8 and the conductive part 10b.
　次に、上述のように構成された第２実施形態に係る電力変換装置の作用について説明する。上述したように、第２実施形態に係る電力変換装置１０２は、第１半導体素子５の主面及び第２半導体素子８の主面と、３つの平板形状部４ａ，７ａ，１０ａとが、それぞれ略平行に配置される。 Next, the operation of the power conversion device according to the second embodiment configured as described above will be described. As described above, in the power conversion device 102 according to the second embodiment, the main surface of the first semiconductor element 5 and the main surface of the second semiconductor element 8 and the three flat plate-shaped portions 4a, 7a, and 10a are respectively It arrange | positions substantially parallel.
　このように配置することにより、前述した第１実施形態と同様に、各バスバの平板形状部４ａ，７ａ，１０ａと、第１半導体素子５、及び第２半導体素子８との容量結合が増大する。また、バスバの平板形状部４ａ，７ａ，１０ａを重ねて配置し、且つ、出力用の平板形状部７ａを端部に設けているため、バスバ１０の電流経路とバスバ４の電流経路が近接することになるので、各バスバ１０，４に発生する電流と磁気の相互作用を得易くなる。 By arranging in this way, the capacitive coupling between the flat plate shaped portions 4a, 7a, 10a of each bus bar and the first semiconductor element 5 and the second semiconductor element 8 is increased as in the first embodiment described above. . Further, since the flat plate-shaped portions 4a, 7a and 10a of the bus bar are arranged so as to overlap with each other and the flat plate-shaped portion 7a for output is provided at the end, the current path of the bus bar 10 and the current path of the bus bar 4 are close to each other. Therefore, it becomes easier to obtain the interaction between the current generated in each bus bar 10 and 4 and magnetism.
　更に、第１半導体素子５及び第２半導体素子８の全体と重なる部分よりも広い範囲で、各バスバ４，７，１０の平板形状部４ａ，７ａ，１０ａを配置することにより、平板形状部４ａ，７ａ，１０ａと、各バスバ４，７，１０の導電部４ｂ，７ｂ１，７ｂ２，１０ｂとの間の容量結合が増加する構造となる。そして、これらの要因により、バスバ部２１及びパワーモジュール部２２ａ，２２ｂからなる電力変換装置１０２全体のインダクタンスを低減することが可能となる。その結果、インダクタンスに起因して生じるサージ電圧の発生を抑制することができる。 Furthermore, the flat plate-shaped portion 4a is arranged by arranging the flat plate-shaped portions 4a, 7a, 10a of the respective bus bars 4, 7, 10 in a range wider than the portion overlapping the entirety of the first semiconductor element 5 and the second semiconductor element 8. , 7a, 10a and the conductive portions 4b, 7b1, 7b2, 10b of the bus bars 4, 7, 10 are increased in capacitive coupling. Due to these factors, it is possible to reduce the inductance of the entire power conversion device 102 including the bus bar portion 21 and the power module portions 22a and 22b. As a result, it is possible to suppress the occurrence of a surge voltage caused by the inductance.
　また、各バスバ４，７，１０の形状は、対向する面積が広くなる形状であることが望ましく、更に、互いが電気的に導通しない範囲で近接し、各バスバの平板形状部４ａ，７ａ，１０ａと、第１半導体素子５及び第２半導体素子８との距離が短いことが望ましい。 Moreover, it is desirable that the shape of each bus bar 4, 7 and 10 is a shape in which the opposing areas are widened. Further, the bus bars 4, 7 and 10 are close to each other as long as they are not electrically connected to each other. The distance between 10a and the first semiconductor element 5 and the second semiconductor element 8 is preferably short.
　なお、図示を省略するが、使用目的に合わせて第１半導体素子５及び第２半導体素子８、導電部４ｂ，７ｂ，１０ｂの変更が可能である。 In addition, although illustration is abbreviate | omitted, the change of the 1st semiconductor element 5, the 2nd semiconductor element 8, and the electroconductive part 4b, 7b, 10b is possible according to a use purpose.
　また、第１半導体素子５及び第２半導体素子８については、その主成分、構造、形状、個数、電気的特性を任意に選択することができる。更に、１つの導電部（４ｂ，７ｂ１，７ｂ２，１０ｂ）に対して複数の素子を搭載する場合には、各素子を電気的に並列或いは直列のいずれか一方または両方になるように設置することが可能である。この場合についても、全ての素子の主面に対して、各平板形状部４ａ，７ａ，１０ａが重複するように配置することが望ましい。また、導電部４ｂ，７ｂ１，７ｂ２，１０ｂ、及び接続線６，９については、その主成分、形状を任意に選択することができる。 In addition, for the first semiconductor element 5 and the second semiconductor element 8, the main component, structure, shape, number, and electrical characteristics can be arbitrarily selected. Further, when a plurality of elements are mounted on one conductive part (4b, 7b1, 7b2, 10b), each element should be installed so as to be either in parallel or in series or both. Is possible. Also in this case, it is desirable to arrange the flat plate-shaped portions 4a, 7a, and 10a so as to overlap with respect to the main surfaces of all the elements. Moreover, about the electroconductive parts 4b, 7b1, 7b2, and 10b and the connection lines 6 and 9, the main component and shape can be selected arbitrarily.
　導電部４ｂ，７ｂ１，７ｂ２，１０ｂ、接続線６，９の形状は、各平板形状部４ａ，７ａ，１０ａとの間の対向面積が大きく、且つ、対向面間の距離が短いことが望ましい。このことにより、双方の容量結合が増加し、インダクタンスをより一層低減することが可能となる。 It is desirable that the conductive portions 4b, 7b1, 7b2, 10b and the connecting lines 6, 9 have a large facing area between the flat plate-shaped portions 4a, 7a, 10a and a short distance between the facing surfaces. As a result, both capacitive couplings increase and the inductance can be further reduced.
［第３実施形態の説明］
　次に、本発明の第３実施形態について説明する。図４（ａ）は、本発明の第３実施形態に係る電力変換装置１０３の構成を示す斜視図である。この電力変換装置１０３は、前述した第１実施形態と同様に、３相のインバータ装置の１つの相を構成するものである。 [Description of Third Embodiment]
Next, a third embodiment of the present invention will be described. Fig.4 (a) is a perspective view which shows the structure of the power converter device 103 which concerns on 3rd Embodiment of this invention. This power conversion device 103 constitutes one phase of a three-phase inverter device as in the first embodiment described above.
　また、第３実施形態に係る電力変換装置１０３は、第１実施形態で示した電力変換装置１０１（図１参照）と対比して、バスバ部１側に封止剤２４を設けた点で相違する。以下、相違点についてのみ説明し、第１実施形態で示した電力変換装置１０１と同一部分は同一の符号を付して説明を省略する。 Further, the power conversion device 103 according to the third embodiment is different from the power conversion device 101 (see FIG. 1) shown in the first embodiment in that a sealing agent 24 is provided on the bus bar portion 1 side. To do. Hereinafter, only differences will be described, and the same parts as those of the power conversion device 101 shown in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
　第３実施形態に係る電力変換装置１０３は、３つの平板形状部４ａ（プラス側平板形状部）、平板形状部７ａ（出力側平板形状部）、平板形状部１０ａ（マイナス側平板形状部）からなるバスバ部１を封止剤２４で封止する。図４（ｂ）は、図４（ａ）に示すＡ線での断面図を示している。図４（ｂ）に示すように、３つの平板形状部４ａ，７ａ，１０ａからなるバスバ部１は、２種類の樹脂２４ａ，２４ｂにより封止されている。 The power conversion device 103 according to the third embodiment includes three plate-shaped portions 4a (plus-side plate-shaped portions), a plate-shaped portion 7a (output-side plate-shaped portions), and a plate-shaped portion 10a (minus-side plate-shaped portions). The bus bar portion 1 is sealed with a sealant 24. FIG. 4B shows a cross-sectional view taken along line A shown in FIG. As shown in FIG. 4B, the bus bar portion 1 including the three flat plate-shaped portions 4a, 7a, and 10a is sealed with two types of resins 24a and 24b.
　即ち、各平板形状部４ａ，７ａ，１０ａ間の領域は、誘電率の高い樹脂２４ｂ（樹脂２４ａよりも相対的に誘電率の高い樹脂）により封止し、その周囲部となる領域は、透磁率の高い樹脂２４ａ（樹脂２４ｂよりも相対的に透磁率の高い樹脂）により封止する。図４（ｂ）では、バスバ部１とパワーモジュール部２の周囲が樹脂２４ａにより封止されている状態が示されている。 That is, the region between the flat plate-shaped portions 4a, 7a and 10a is sealed with a resin 24b having a high dielectric constant (a resin having a dielectric constant relatively higher than that of the resin 24a), and the region serving as the peripheral portion thereof is transparent. Sealing is performed with a resin 24a having a high magnetic permeability (a resin having a relatively higher magnetic permeability than that of the resin 24b). FIG. 4B shows a state where the periphery of the bus bar portion 1 and the power module portion 2 is sealed with a resin 24a.
　容量結合の大きさは、対向する面同士の重なる部分の面積に比例する傾向にあり、また対向する面同士の間の距離に反比例して増大する傾向がある。また、対向する面の間に樹脂などが充填されることにより、対向する面の間の誘電率が高くなるほど、容量結合の大きさは大きくなる傾向にある。 The size of the capacitive coupling tends to be proportional to the area of the overlapping portion between the opposing surfaces, and tends to increase in inverse proportion to the distance between the opposing surfaces. In addition, as the dielectric constant between the opposing surfaces increases by filling the resin between the opposing surfaces, the magnitude of the capacitive coupling tends to increase.
　そのため、このような構成とすることにより、各平板形状部４ａ，７ａ，１０ａ間の領域と第１半導体素子５及び第２半導体素子８との間の容量結合を高めることができる。また、樹脂２４ｂにより各平板形状部４ａ，７ａ，１０ａ間の領域と第１半導体素子５及び第２半導体素子８との間の空間の誘電率が高く設定されるため、電流経路の相互作用を高めることができる。そして、この２つの効果でバスバ部１とパワーモジュール部２との間に生じるインダクタンスをより一層低減することができる。 Therefore, by adopting such a configuration, the capacitive coupling between the regions between the flat plate-shaped portions 4a, 7a and 10a and the first semiconductor element 5 and the second semiconductor element 8 can be enhanced. Moreover, since the dielectric constant of the space between the region between the flat plate-shaped portions 4a, 7a, and 10a and the first semiconductor element 5 and the second semiconductor element 8 is set high by the resin 24b, the interaction between the current paths is increased. Can be increased. And the inductance which arises between the bus bar part 1 and the power module part 2 by these two effects can be reduced further.
　さらに、各平板形状部４ａ，７ａ，１０ａ間の領域と、その樹脂２４ｂの周囲部となる領域が、樹脂２４ａにより封止されているため、バスバ部１とパワーモジュール部２は樹脂２４ａによって磁気遮蔽される。すなわち、バスバ部１とパワーモジュール部２で発生した磁場が樹脂２４ａによって囲まれた領域の外部に漏れ出すことが抑制され、その結果、電流経路の相互作用を高めることができる。 Further, since the region between the flat plate-shaped portions 4a, 7a, 10a and the region around the resin 24b are sealed by the resin 24a, the bus bar portion 1 and the power module portion 2 are magnetically formed by the resin 24a. Shielded. That is, the magnetic field generated in the bus bar unit 1 and the power module unit 2 is prevented from leaking outside the region surrounded by the resin 24a, and as a result, the interaction of the current paths can be enhanced.
　なお、上述した第３実施形態では、２種類の樹脂２４ａ，２４ｂを用いる例について説明したが、２種類の樹脂のうちいずれか一方の、１種類のみの樹脂を用いる場合でもインダクタンスを低減する効果を得ることができる。 In the above-described third embodiment, an example using two types of resins 24a and 24b has been described. However, even when only one type of two types of resins is used, the effect of reducing inductance is achieved. Can be obtained.
［第４実施形態の説明］
　次に、本発明の第４実施形態について説明する。図５（ａ）は、本発明の第４実施形態に係る電力変換装置１０４の構成を示す斜視図である。この電力変換装置１０４は、前述した第１実施形態と同様に、３相のインバータ装置の１つの相を構成するものである。 [Description of Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 5A is a perspective view showing the configuration of the power conversion device 104 according to the fourth embodiment of the present invention. The power conversion device 104 constitutes one phase of a three-phase inverter device, as in the first embodiment described above.
　また、第４実施形態に係る電力変換装置１０４は、第１実施形態で示した電力変換装置１０１（図１参照）と対比して、パワーモジュール部２側に封止剤２５を設けた点で相違する。以下、相違点についてのみ説明し、第１実施形態で示した電力変換装置１０１と同一部分は同一の符号を付して説明を省略する。 Moreover, the power converter device 104 which concerns on 4th Embodiment is the point which provided the sealing agent 25 in the power module part 2 side compared with the power converter device 101 (refer FIG. 1) shown in 1st Embodiment. Is different. Hereinafter, only differences will be described, and the same parts as those of the power conversion device 101 shown in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
　第４実施形態に係る電力変換装置１０４は、支持基板３、及び該支持基板３に搭載される導電部４ｂ，７ｂ，１０ｂを封止剤２５で封止する。図５（ｂ）は、図５（ａ）に示すＢ線での断面図を示している。図５（ｂ）に示すように、支持基板３、及び該支持基板３に搭載される導電部４ｂ，７ｂ，１０ｂからなるパワーモジュール部２は、２種類の樹脂２５ａ，２５ｂにより封止されている。 The power conversion device 104 according to the fourth embodiment seals the support substrate 3 and the conductive portions 4b, 7b, and 10b mounted on the support substrate 3 with a sealant 25. FIG. 5B shows a cross-sectional view taken along line B shown in FIG. As shown in FIG. 5B, the power module unit 2 including the support substrate 3 and the conductive portions 4b, 7b, and 10b mounted on the support substrate 3 is sealed with two types of resins 25a and 25b. Yes.
　即ち、各導電部４ｂ，７ｂ，１０ｂの周囲領域は、誘電率の高い樹脂２５ｂにより封止し、その周囲部となる領域は、透磁率の高い樹脂２５ａにより封止する。 That is, the surrounding region of each conductive portion 4b, 7b, 10b is sealed with a resin 25b having a high dielectric constant, and the region serving as the surrounding portion is sealed with a resin 25a having a high magnetic permeability.
　そして、このような構成とすることにより、第１半導体素子５及び第２半導体素子８と、各平板形状部４ａ，７ａ，１０ａとの間の容量結合を高めることができる。また、樹脂２５ｂにより電流経路の相互作用を高めることができる。そして、この２つの効果でバスバ部１とパワーモジュール部２との間に生じるインダクタンスをより一層低減することができる。なお、上述した第４実施形態では、２種類の樹脂２５ａ，２５ｂを用いる例について説明したが、１種類の樹脂を用いる場合でもインダクタンスを低減する効果を得ることができる。 And by setting it as such a structure, the capacitive coupling between the 1st semiconductor element 5 and the 2nd semiconductor element 8, and each flat plate shape part 4a, 7a, 10a can be improved. Further, the interaction of the current path can be enhanced by the resin 25b. And the inductance which arises between the bus bar part 1 and the power module part 2 by these two effects can be reduced further. In the fourth embodiment described above, an example using two types of resins 25a and 25b has been described, but the effect of reducing inductance can be obtained even when one type of resin is used.
［第５実施形態の説明］
　次に、本発明の第５実施形態について説明する。図６（ａ）は、本発明の第５実施形態に係る電力変換装置１０５の構成を示す斜視図である。この電力変換装置１０５は、前述した第１実施形態と同様に、３相のインバータ装置の１つの相を構成するものである。 [Description of Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. Fig.6 (a) is a perspective view which shows the structure of the power converter device 105 which concerns on 5th Embodiment of this invention. The power conversion device 105 constitutes one phase of a three-phase inverter device, as in the first embodiment described above.
　また、第５実施形態に係る電力変換装置１０５は、第１実施形態で示した電力変換装置１０１（図１参照）と対比して、装置全体を覆うように封止剤２６を設けた点で相違する。以下、相違点についてのみ説明し、第１実施形態で示した電力変換装置１０１と同一部分は同一の符号を付して説明を省略する。 Moreover, the power converter device 105 which concerns on 5th Embodiment is the point which provided the sealing agent 26 so that the whole apparatus might be covered compared with the power converter device 101 (refer FIG. 1) shown in 1st Embodiment. Is different. Hereinafter, only differences will be described, and the same parts as those of the power conversion device 101 shown in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
　第５実施形態に係る電力変換装置１０５は、３つの平板形状部４ａ，７ａ，１０ａからなるバスバ部１、及び支持基板３，各導電部４ｂ，７ｂ，１０ｂからなるパワーモジュール部２を、封止剤２６で封止する。図６（ｂ）は、図６（ａ）に示すＣ線での断面図を示している。図６（ｂ）に示すように、バスバ部１及びパワーモジュール部２は、２種類の樹脂２６ａ，２６ｂにより封止されている。 The power conversion device 105 according to the fifth embodiment seals the bus bar portion 1 composed of three flat plate-shaped portions 4a, 7a, and 10a and the power module portion 2 composed of the support substrate 3 and the respective conductive portions 4b, 7b, and 10b. Seal with a stopper 26. FIG. 6B shows a cross-sectional view taken along line C shown in FIG. As shown in FIG. 6B, the bus bar portion 1 and the power module portion 2 are sealed with two types of resins 26a and 26b.
　即ち、各平板形状部４ａ，７ａ，１０ａと支持基板３との間の領域は、誘電率の高い樹脂２６ｂにより封止し、その周囲部となる領域は、透磁率の高い樹脂２６ａにより封止する。 That is, the region between each flat plate-shaped portion 4a, 7a, 10a and the support substrate 3 is sealed with a resin 26b with a high dielectric constant, and the region around it is sealed with a resin 26a with a high magnetic permeability. To do.
　そして、このような構成とすることにより、各平板形状部４ａ，７ａ，１０ａ間の領域と第１半導体素子５及び第２半導体素子８との間の容量結合を高めることができる。また、樹脂２６ｂにより電流経路の相互作用を高めることができる。そして、この２つの効果でバスバ部１とパワーモジュール部２との間に生じるインダクタンスをより一層低減することができる。なお、上述した第５実施形態では、２種類の樹脂２６ａ，２６ｂを用いる例について説明したが、１種類の樹脂を用いる場合でもインダクタンスを低減する効果を得ることができる。 And by setting it as such a structure, the capacitive coupling between the area | region between each flat shape part 4a, 7a, 10a and the 1st semiconductor element 5 and the 2nd semiconductor element 8 can be improved. Further, the interaction of the current path can be enhanced by the resin 26b. And the inductance which arises between the bus bar part 1 and the power module part 2 by these two effects can be reduced further. In the fifth embodiment described above, an example using two types of resins 26a and 26b has been described. However, even when one type of resin is used, an effect of reducing inductance can be obtained.
［第６実施形態の説明］
　次に、本発明の第６実施形態について説明する。図７（ａ）は、本発明の第６実施形態に係る電力変換装置１０６の構成を示す斜視図である。この電力変換装置１０６は、前述した第１実施形態と同様に、３相のインバータ装置の１つの相を構成するものである。 [Explanation of Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described. Fig.7 (a) is a perspective view which shows the structure of the power converter device 106 which concerns on 6th Embodiment of this invention. This power conversion device 106 constitutes one phase of a three-phase inverter device, as in the first embodiment described above.
　また、第６実施形態に係る電力変換装置１０６は、第１実施形態で示した電力変換装置１０１（図１参照）と対比して、バスバ部１の上側にコンデンサ２９（図２に示したＣ１に対応）を搭載し、更に、バスバ部１とコンデンサ２９を含む領域全体を覆うように封止剤２７を設けた点で相違する。以下、相違点についてのみ説明し、第１実施形態で示した電力変換装置１０１と同一部分は同一の符号を付して説明を省略する。 In addition, the power converter 106 according to the sixth embodiment has a capacitor 29 (C1 shown in FIG. 2) on the upper side of the bus bar unit 1 as compared with the power converter 101 (see FIG. 1) shown in the first embodiment. And a sealant 27 is provided so as to cover the entire region including the bus bar portion 1 and the capacitor 29. Hereinafter, only differences will be described, and the same parts as those of the power conversion device 101 shown in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
　第６実施形態に係る電力変換装置１０６は、平板形状部４ａの上側に円筒形状のコンデンサ２９が設けられている。また、バスバ４は、平板形状部４ａに対して直交するブラケット４ｃを有しており、バスバ１０は、平板形状部１０ａに対して直交するブラケット１０ｃを有している。そして、コンデンサ２９の２つの端子のうちの一方はブラケット４ｃに接続され、他方はブラケット１０ｃに接続されている。即ち、図２に示すインバータ回路に設けられるコンデンサＣ１の一端が電源ＶＢの一端に接続され、コンデンサＣ１の他端が電源ＶＢの他端に接続されることに対応している。 In the power conversion device 106 according to the sixth embodiment, a cylindrical capacitor 29 is provided on the upper side of the flat plate-shaped portion 4a. The bus bar 4 has a bracket 4c orthogonal to the flat plate-shaped portion 4a, and the bus bar 10 has a bracket 10c orthogonal to the flat plate-shaped portion 10a. One of the two terminals of the capacitor 29 is connected to the bracket 4c, and the other is connected to the bracket 10c. That is, one end of the capacitor C1 provided in the inverter circuit shown in FIG. 2 is connected to one end of the power source VB, and the other end of the capacitor C1 is connected to the other end of the power source VB.
　そして、３つの平板形状部４ａ（プラス側平板形状部）、平板形状部７ａ（出力側平板形状部）、平板形状部１０ａ（マイナス側平板形状部）からなるバスバ部１に加え、バスバ４（プラス側導電部材）とバスバ１０（マイナス側導電部材）との間を接続するコンデンサ２９を、封止剤２７で封止する。図７（ｂ）は、図７（ａ）に示すＤ線での断面図を示している。図７（ｂ）に示すように、３つの平板形状部４ａ，７ａ，１０ａ、及びコンデンサ２９は２種類の樹脂２７ａ，２７ｂにより封止されている。 In addition to the bus bar portion 1 including the three flat plate shape portions 4a (plus side flat plate shape portion), the flat plate shape portion 7a (output side flat plate shape portion), and the flat plate shape portion 10a (minus side flat plate shape portion), the bus bar 4 ( Capacitor 29 that connects between positive side conductive member) and bus bar 10 (negative side conductive member) is sealed with sealant 27. FIG. 7B shows a cross-sectional view taken along line D shown in FIG. As shown in FIG. 7B, the three flat plate shaped portions 4a, 7a, 10a and the capacitor 29 are sealed with two kinds of resins 27a, 27b.
　即ち、コンデンサ２９と、各平板形状部４ａ，７ａ，１０ａ間の領域は、誘電率の高い樹脂２７ｂにより封止し、その周囲部となる領域は、透磁率の高い樹脂２７ａにより封止する。 That is, the region between the capacitor 29 and each flat plate-shaped portion 4a, 7a, 10a is sealed with a resin 27b having a high dielectric constant, and the region surrounding the capacitor 29 is sealed with a resin 27a having a high magnetic permeability.
　そして、このような構成とすることにより、各平板形状部４ａ，７ａ，１０ａ間の領域と第１半導体素子５及び第２半導体素子８との間の容量結合を高めることができる。また、樹脂２４ｂにより電流経路の相互作用を高めることができる。そして、この２つの効果でバスバ部１とパワーモジュール部２との間に生じるインダクタンスをより一層低減することができる。なお、上述した第６実施形態では、２種類の樹脂２７ａ，２７ｂを用いる例について説明したが、１種類の樹脂を用いる場合でもインダクタンスを低減する効果を得ることができる。 And by setting it as such a structure, the capacitive coupling between the area | region between each flat shape part 4a, 7a, 10a and the 1st semiconductor element 5 and the 2nd semiconductor element 8 can be improved. Moreover, the interaction of the current path can be enhanced by the resin 24b. And the inductance which arises between the bus bar part 1 and the power module part 2 by these two effects can be reduced further. In the above-described sixth embodiment, an example in which two types of resins 27a and 27b are used has been described. However, an effect of reducing inductance can be obtained even when one type of resin is used.
［第７実施形態の説明］
　次に、本発明の第７実施形態について説明する。この電力変換装置２０１は、第１実施形態～第６実施形態で説明した電力変換装置と同様に、３相インバータ回路の１つの相を構成するものである。 [Description of Seventh Embodiment]
Next, a seventh embodiment of the present invention will be described. This power conversion device 201 constitutes one phase of a three-phase inverter circuit, similarly to the power conversion devices described in the first to sixth embodiments.
　［本実施形態の構造］
　まず初めに、電力変換装置２０１の構造、および電力変換装置２０１を構成する半導体モジュール２０８Ｌ，２０８Ｒの構造について説明する。図８（ａ）、図８（ｂ）、図８（ｃ）は、本発明の第７実施形態に係る電力変換装置２０１の構成を示す図である。特に、図８（ａ）は、電力変換装置２０１の斜視図、図８（ｂ）は、電力変換装置２０１の平面図を示している。図８（ｃ）は、図８（ａ）に示す電力変換装置２０１の動作時における、電力変換装置２０１内の電流経路を示す概略図である。 [Structure of this embodiment]
First, the structure of the power conversion device 201 and the structures of the semiconductor modules 208L and 208R constituting the power conversion device 201 will be described. FIG. 8A, FIG. 8B, and FIG. 8C are diagrams showing the configuration of the power conversion device 201 according to the seventh embodiment of the present invention. 8A is a perspective view of the power converter 201, and FIG. 8B is a plan view of the power converter 201. FIG.8 (c) is the schematic which shows the current pathway in the power converter device 201 at the time of operation | movement of the power converter device 201 shown to Fig.8 (a).
　電力変換装置２０１は、上アームを構成する半導体モジュール２０８Ｌ（第１半導体モジュール）、下アームを構成する半導体モジュール２０８Ｒ（第２半導体モジュール）、第３主電極２０９（出力側導電部材）とから構成される。第３主電極２０９は、半導体モジュール２０８Ｌ，２０８Ｒを、電気的に直列接続しており、この接続の結果、第３主電極２０９、半導体モジュール２０８Ｌ，２０８Ｒとは、上下アーム回路を形成する。第３主電極２０９は、上下アーム回路の、上アームと下アームとの接続点の電位を出力する。 The power conversion device 201 includes a semiconductor module 208L (first semiconductor module) that constitutes an upper arm, a semiconductor module 208R (second semiconductor module) that constitutes a lower arm, and a third main electrode 209 (output-side conductive member). Is done. The third main electrode 209 electrically connects the semiconductor modules 208L and 208R in series. As a result of this connection, the third main electrode 209 and the semiconductor modules 208L and 208R form upper and lower arm circuits. The third main electrode 209 outputs a potential at a connection point between the upper arm and the lower arm in the upper and lower arm circuits.
　電力変換装置２０１を構成する半導体モジュール２０８Ｌ，２０８Ｒは、図９（ａ）、図９（ｂ）、図９（ｃ）に示す半導体モジュール２０８と同等の構造を有している。以下では、半導体モジュール２０８Ｌ，２０８Ｒは同一の構造を有するものとして説明する。以降の説明において、半導体モジュール２０８Ｌ，２０８Ｒを半導体モジュール２０８として参照する場合がある。 The semiconductor modules 208L and 208R constituting the power conversion device 201 have the same structure as the semiconductor module 208 shown in FIGS. 9A, 9B, and 9C. Hereinafter, the semiconductor modules 208L and 208R will be described as having the same structure. In the following description, the semiconductor modules 208L and 208R may be referred to as the semiconductor module 208.
　図９（ａ）、図９（ｂ）、図９（ｃ）は、電力変換装置２０１を構成する半導体モジュール２０８を示す図である。図９（ａ）は、半導体モジュール２０８の斜視図を示しており、後述するパワー端子２０７ａ，２０７ｂ（それぞれ第１端子部、第２端子部）が半導体モジュール２０８の外部に露出している様子を示している。図９（ｂ）は、半導体モジュール２０８の内部構造の斜視図を示している。図９（ｃ）は、半導体モジュール２０８の内部構造の平面図を示す図である。 FIG. 9A, FIG. 9B, and FIG. 9C are diagrams showing the semiconductor module 208 that constitutes the power conversion apparatus 201. FIG. FIG. 9A shows a perspective view of the semiconductor module 208, and shows how power terminals 207 a and 207 b (first terminal portion and second terminal portion, respectively), which will be described later, are exposed to the outside of the semiconductor module 208. Show. FIG. 9B shows a perspective view of the internal structure of the semiconductor module 208. FIG. 9C is a diagram showing a plan view of the internal structure of the semiconductor module 208.
　半導体モジュール２０８は、３相インバータ回路の１つのアームに対応する部品であり、１ｉｎ１パワー半導体モジュールと呼ばれる。２つの１ｉｎ１パワー半導体モジュールを、上下アーム回路を形成するように直列に接続することにより、３相インバータ回路の１つの相を構成することができる。 The semiconductor module 208 is a component corresponding to one arm of the three-phase inverter circuit, and is called a 1 in 1 power semiconductor module. By connecting two 1 in 1 power semiconductor modules in series so as to form an upper and lower arm circuit, one phase of the three-phase inverter circuit can be configured.
　半導体モジュール２０８は、半導体素子２１０、半導体素子２１０に電気的に接続される第１主電極２０３および第２主電極２０２、そして、第１主電極２０３、第２主電極２０２とそれぞれ電気的に接続されるパワー端子２０７ａ，２０７ｂを有する。図９（ｂ）に示すように、半導体素子２１０は第１主電極２０３の上に配置され、半導体素子２１０の下面において半導体素子２１０と第１主電極２０３は接合材２０６を介して電気的に接続されている。さらに、第２主電極２０２は半導体素子２１０の上に配置され、半導体素子２１０の上面において半導体素子２１０と第２主電極２０２は接合材２０６を介して電気的に接続されている。 The semiconductor module 208 is electrically connected to the semiconductor element 210, the first main electrode 203 and the second main electrode 202 electrically connected to the semiconductor element 210, and the first main electrode 203 and the second main electrode 202, respectively. Power terminals 207a and 207b. As shown in FIG. 9B, the semiconductor element 210 is disposed on the first main electrode 203, and the semiconductor element 210 and the first main electrode 203 are electrically connected via a bonding material 206 on the lower surface of the semiconductor element 210. It is connected. Further, the second main electrode 202 is disposed on the semiconductor element 210, and the semiconductor element 210 and the second main electrode 202 are electrically connected via a bonding material 206 on the upper surface of the semiconductor element 210.
　図９（ｂ）に示すような内部構造を封止剤２０５によって封止することにより、図９（ａ）に示す直方体状の半導体モジュール２０８を形成する。より詳しく説明すると、半導体素子２１０、第１主電極２０３、第２主電極２０２、接合材２０６は、封止剤２０５によって封止されることにより、半導体素子２１０、第１主電極２０３、第２主電極２０２、接合材２０６は半導体モジュール２０８の外部から密閉され、絶縁された状態となる。一方、封止剤２０５はパワー端子２０７ａ，２０７ｂを部分的に封止する。封止剤２０５によって封止された状態において、パワー端子２０７ａ，２０７ｂのそれぞれの一部分が、半導体モジュール２０８の表面に露出している。 A rectangular parallelepiped semiconductor module 208 shown in FIG. 9A is formed by sealing the internal structure as shown in FIG. More specifically, the semiconductor element 210, the first main electrode 203, the second main electrode 202, and the bonding material 206 are sealed with a sealant 205, whereby the semiconductor element 210, the first main electrode 203, and the second The main electrode 202 and the bonding material 206 are sealed from the outside of the semiconductor module 208 and insulated. On the other hand, the sealant 205 partially seals the power terminals 207a and 207b. A part of each of the power terminals 207 a and 207 b is exposed on the surface of the semiconductor module 208 in a state of being sealed with the sealant 205.
　図９（ａ）、図９（ｂ）に示すように、パワー端子２０７ａ，２０７ｂは、共に半導体モジュール２０８の前面に露出するように配置され、半導体素子２１０は、パワー端子２０７ａ，２０７ｂの後方に配置されている。 As shown in FIGS. 9A and 9B, the power terminals 207a and 207b are both arranged so as to be exposed on the front surface of the semiconductor module 208, and the semiconductor element 210 is located behind the power terminals 207a and 207b. Has been placed.
　本実施形態では、半導体素子２１０を制御する信号を伝達するための、半導体素子２１０に接続される信号端子は省略している。実際には、パワー端子２０７ａ，２０７ｂ以外にも、半導体素子２１０を制御する信号端子が半導体モジュール２０８の表面に露出している。信号端子は、図２に示すようにコントローラＭＵに接続される。 In this embodiment, a signal terminal connected to the semiconductor element 210 for transmitting a signal for controlling the semiconductor element 210 is omitted. Actually, in addition to the power terminals 207 a and 207 b, signal terminals for controlling the semiconductor element 210 are exposed on the surface of the semiconductor module 208. The signal terminal is connected to the controller MU as shown in FIG.
　図９（ｂ）、図９（ｃ）では、半導体モジュール２０８内にある３相インバータ回路の１つのアームを構成するための素子を、１個の半導体素子２１０で示している。半導体素子２１０は、スイッチング動作、還流動作の両方の動作が可能である。図示しない信号端子を介して伝達されるコントローラＭＵからの信号によって、半導体素子２１０のスイッチング動作が制御される。 9B and 9C, an element for forming one arm of the three-phase inverter circuit in the semiconductor module 208 is indicated by one semiconductor element 210. FIG. The semiconductor element 210 can perform both a switching operation and a reflux operation. The switching operation of the semiconductor element 210 is controlled by a signal from the controller MU transmitted through a signal terminal (not shown).
　パワー端子２０７ａ，２０７ｂは、それぞれ第１主電極２０３、第２主電極２０２を介して半導体素子２１０に電気的に接続されているので、パワー端子２０７ａ，２０７ｂに半導体モジュール２０８の外部より供給された電圧は、第１主電極２０３、第２主電極２０２を介して半導体素子２１０に供給される。本実施形態では、第１主電極２０３、パワー端子２０７ａ（第１端子部）が半導体モジュール２０８の高電位入力端子となっており、一方、第２主電極２０２、パワー端子２０７ｂ（第２端子部）が半導体モジュール２０８の低電位入力端子となっている。すなわち、半導体モジュール２０８を３相インバータ回路の１つのアームとして動作させる際には、パワー端子２０７ｂよりも高電位の電圧がパワー端子２０７ａに対して供給される。 Since the power terminals 207a and 207b are electrically connected to the semiconductor element 210 via the first main electrode 203 and the second main electrode 202, respectively, the power terminals 207a and 207b are supplied from the outside of the semiconductor module 208 to the power terminals 207a and 207b. The voltage is supplied to the semiconductor element 210 through the first main electrode 203 and the second main electrode 202. In the present embodiment, the first main electrode 203 and the power terminal 207a (first terminal portion) are high potential input terminals of the semiconductor module 208, while the second main electrode 202 and the power terminal 207b (second terminal portion). ) Is a low potential input terminal of the semiconductor module 208. That is, when the semiconductor module 208 is operated as one arm of the three-phase inverter circuit, a voltage having a higher potential than the power terminal 207b is supplied to the power terminal 207a.
　図８（ａ）、図８（ｂ）に示すように、第３主電極２０９は、電力変換装置２０１の前面側において、上アームを構成する半導体モジュール２０８Ｌのパワー端子２０７ｂと、下アームを構成する半導体モジュール２０８Ｒのパワー端子２０７ａとを接続する。第３主電極２０９は、ねじ止めなどの手段により半導体モジュール２０８Ｌのパワー端子２０７ｂ、および半導体モジュール２０８Ｒのパワー端子２０７ａに接続され、固定される。第３主電極２０９は、半導体モジュール２０８Ｌ，２０８Ｒの上面の樹脂表面に対して面設置している部位を有し、半導体モジュール２０８Ｌ，２０８Ｒの上面の、一部あるいは全体を覆うように配置される。特に、半導体モジュール２０８Ｌ，２０８Ｒの両方の上面をまたがるように配置される。 As shown in FIGS. 8A and 8B, the third main electrode 209 constitutes a power terminal 207b of the semiconductor module 208L constituting the upper arm and a lower arm on the front side of the power conversion device 201. The power terminal 207a of the semiconductor module 208R to be connected is connected. The third main electrode 209 is connected and fixed to the power terminal 207b of the semiconductor module 208L and the power terminal 207a of the semiconductor module 208R by means such as screwing. The third main electrode 209 has a portion that is placed on the resin surface on the upper surface of the semiconductor modules 208L and 208R, and is arranged so as to cover a part or the whole of the upper surface of the semiconductor modules 208L and 208R. . In particular, the semiconductor modules 208L and 208R are disposed so as to straddle both upper surfaces.
　第３主電極２０９による接続の結果、半導体モジュール２０８Ｌのパワー端子２０７ｂと半導体モジュール２０８Ｒのパワー端子２０７ａは同じ電位となる。この電位は、図２のＳ点における電位に対応する。第３主電極２０９の、電力変換装置２０１の後面側には、外部回路を構成するバスバを固定することができる出力用端子が設けられている。電力変換装置２０１は、この出力用端子を介して、電力変換装置２０１に接続された負荷に対して出力用の電位を供給できる。すなわち、第３主電極２０９を介して、半導体モジュール２０８Ｌ，２０８Ｒが、上下アーム回路を形成するように電気的に直列接続される。 As a result of connection by the third main electrode 209, the power terminal 207b of the semiconductor module 208L and the power terminal 207a of the semiconductor module 208R have the same potential. This potential corresponds to the potential at point S in FIG. An output terminal capable of fixing a bus bar constituting an external circuit is provided on the rear surface side of the third main electrode 209 on the power conversion device 201. The power conversion device 201 can supply an output potential to the load connected to the power conversion device 201 via the output terminal. That is, the semiconductor modules 208L and 208R are electrically connected in series via the third main electrode 209 so as to form upper and lower arm circuits.
　上記のように構成された上下アーム回路には、バスバ２０７Ｐ，２０７Ｎによって、電力変換装置２０１の外部の電源からの電位が供給される。半導体モジュール２０８Ｌのパワー端子２０７ａには、ねじ止めなどの手段によりバスバ２０７Ｐを接続し固定できるようになっており、また、半導体モジュール２０８Ｒのパワー端子２０７ｂは、ねじ止めなどの手段によりバスバ２０７Ｎを接続し固定できるようになっている。バスバ２０７Ｐを通じて、半導体モジュール２０８Ｌのパワー端子２０７ａには、図２のＰ点でのプラス電位が供給される。そしてバスバ２０７Ｎを通じて、半導体モジュール２０８Ｒのパワー端子２０７ｂには、図２のＮ点でのマイナス電位が供給される。 The upper and lower arm circuits configured as described above are supplied with a potential from a power supply external to the power converter 201 by the bus bars 207P and 207N. The bus bar 207P can be connected and fixed to the power terminal 207a of the semiconductor module 208L by means such as screwing. The power terminal 207b of the semiconductor module 208R can be connected to the bus bar 207N by means of screwing or the like. It can be fixed. A positive potential at point P in FIG. 2 is supplied to the power terminal 207a of the semiconductor module 208L through the bus bar 207P. A negative potential at point N in FIG. 2 is supplied to the power terminal 207b of the semiconductor module 208R through the bus bar 207N.
　図１０は、図８（ａ）に示す電力変換装置２０１のＸ線での断面図を示している。この断面図は、半導体モジュール２０８Ｌ，２０８Ｒの半導体素子２１０を通る平面で、且つ、半導体モジュール２０８Ｌ，２０８Ｒの下面に垂直な面での断面を示している。第３主電極２０９は、半導体モジュール２０８Ｌ，２０８Ｒの上面に接して、半導体モジュール２０８Ｌ，２０８Ｒの上面を覆うように配置されている。すなわち第３主電極２０９は、半導体モジュール２０８Ｌ，２０８Ｒ内の半導体素子２１０と垂直方向に重なって配置されている。そして、第３主電極２０９は、封止剤２０５で絶縁される領域を挟んで、第２主電極２０２と近接している。 FIG. 10 shows a cross-sectional view of the power conversion device 201 shown in FIG. This cross-sectional view shows a cross section in a plane passing through the semiconductor element 210 of the semiconductor modules 208L and 208R and perpendicular to the lower surfaces of the semiconductor modules 208L and 208R. The third main electrode 209 is disposed so as to contact the upper surfaces of the semiconductor modules 208L and 208R and cover the upper surfaces of the semiconductor modules 208L and 208R. That is, the third main electrode 209 is disposed so as to overlap with the semiconductor element 210 in the semiconductor modules 208L and 208R in the vertical direction. The third main electrode 209 is close to the second main electrode 202 with a region insulated by the sealant 205 interposed therebetween.
　なお、図１０には、電力変換装置２０１は冷却器ＲＧの上に配置された状態が示されている。電力変換装置２０１は、半導体モジュール２０８Ｌ，２０８Ｒの下面で、冷却器ＲＧと接している。すなわち、半導体モジュール２０８Ｌ，２０８Ｒの下面が、電力変換装置２０１、半導体モジュール２０８Ｌ，２０８Ｒの冷却面となっている。冷却器ＲＧは、電力変換装置２０１が動作する際に電力変換装置２０１の内部で発生する熱、特に半導体素子２１０において発生する熱を、電力変換装置２０１の外部に排熱する。 FIG. 10 shows a state where the power conversion device 201 is disposed on the cooler RG. The power conversion device 201 is in contact with the cooler RG on the lower surfaces of the semiconductor modules 208L and 208R. That is, the lower surfaces of the semiconductor modules 208L and 208R serve as cooling surfaces for the power conversion device 201 and the semiconductor modules 208L and 208R. The cooler RG exhausts heat generated inside the power conversion device 201 when the power conversion device 201 operates, in particular, heat generated in the semiconductor element 210 to the outside of the power conversion device 201.
　図１０に示すように、第３主電極２０９は、封止剤２０５を挟んで第２主電極２０２と近接した構造となっているため、半導体素子２１０で発生した熱は、第２主電極２０２、および封止剤２０５を介して第３主電極２０９に伝わる。また、冷却器ＲＧは、封止剤２０５を挟んで第１主電極２０３と近接した構造となっているため、半導体素子２１０で発生した熱は、第１主電極２０３、および封止剤２０５を介して冷却器ＲＧに伝わる。 As shown in FIG. 10, since the third main electrode 209 has a structure close to the second main electrode 202 with the sealant 205 interposed therebetween, the heat generated in the semiconductor element 210 is generated by the second main electrode 202. , And the third main electrode 209 via the sealant 205. In addition, since the cooler RG has a structure close to the first main electrode 203 with the sealant 205 interposed therebetween, the heat generated in the semiconductor element 210 causes the first main electrode 203 and the sealant 205 to flow. To the cooler RG.
　なお、熱伝導性とコストを考慮すると、第１主電極２０３と第２主電極２０２は、銅やアルミなどの、比較的安価で熱伝導率が良い金属材料であることが好ましい。 In consideration of thermal conductivity and cost, the first main electrode 203 and the second main electrode 202 are preferably made of a metal material that is relatively inexpensive and has good thermal conductivity, such as copper or aluminum.
　比較のため、本実施形態の各部位を第１～第６実施形態と比較すると、半導体モジュール２０８Ｌ内の半導体素子２１０、および半導体モジュール２０８Ｒ内の半導体素子２１０が、それぞれ第１半導体素子５および第２半導体素子８に対応する。また、第３主電極２０９は出力側導電部材であるバスバ７の一部に対応する。半導体モジュール２０８Ｌ内の第１主電極２０３は、プラス側導電部材であるバスバ４の一部に対応する。半導体モジュール２０８Ｌ内の第２主電極２０２は、接続線６およびバスバ７の一部に対応する。半導体モジュール２０８Ｒ内の第１主電極２０３は、バスバ７の一部に対応する。半導体モジュール２０８Ｒ内の第２主電極２０２は、接続線９およびマイナス側導電部材であるバスバ１０の一部に対応する。 For comparison, when each part of the present embodiment is compared with the first to sixth embodiments, the semiconductor element 210 in the semiconductor module 208L and the semiconductor element 210 in the semiconductor module 208R are the first semiconductor element 5 and the first semiconductor element 208, respectively. 2 corresponds to the semiconductor element 8. The third main electrode 209 corresponds to a part of the bus bar 7 which is an output side conductive member. The first main electrode 203 in the semiconductor module 208L corresponds to a part of the bus bar 4 that is a plus-side conductive member. The second main electrode 202 in the semiconductor module 208 </ b> L corresponds to the connection line 6 and a part of the bus bar 7. The first main electrode 203 in the semiconductor module 208 </ b> R corresponds to a part of the bus bar 7. The second main electrode 202 in the semiconductor module 208R corresponds to the connection line 9 and a part of the bus bar 10 that is the negative side conductive member.
　［本実施形態での電流経路］
　次に、電力変換装置２０１の内部を流れる電流の経路について説明する。図８（ｃ）には、上下アーム回路のＰ側からＮ側へ電流が流れるときの電流経路を示している。上下アーム回路のＰ側、Ｎ側は、それぞれ図２のＰ点、Ｎ点に相当する。 [Current path in this embodiment]
Next, a path of current flowing through the power converter 201 will be described. FIG. 8C shows a current path when current flows from the P side to the N side of the upper and lower arm circuits. The P side and N side of the upper and lower arm circuits correspond to the points P and N in FIG. 2, respectively.
　点Ｐ１は、半導体モジュール２０８Ｌのパワー端子２０７ａと、バスバ２０７Ｐの接合部位を示している。
　点Ｐ９は、半導体モジュール２０８Ｒのパワー端子２０７ｂと、バスバ２０７Ｎの接合部位を示している。
　点Ｐ４は、半導体モジュール２０８Ｌのパワー端子２０７ｂと、第３主電極２０９の接合部位を示している。
　点Ｐ６は、半導体モジュール２０８Ｒのパワー端子２０７ａと、第３主電極２０９の接合部位を示している。
　点Ｐ２、Ｐ７は、それぞれ半導体モジュール２０８Ｌ，２０８Ｒ内における、第１主電極２０３と半導体素子２１０の接合部位を示している。
　点Ｐ３、Ｐ８は、それぞれ半導体モジュール２０８Ｌ，２０８Ｒ内における、第２主電極２０２と半導体素子２１０の接合部位を示している。
　点Ｐ５は、第３主電極２０９において、点Ｐ４と点Ｐ６の中間付近の位置を示している。 A point P1 indicates a joint portion between the power terminal 207a of the semiconductor module 208L and the bus bar 207P.
A point P9 indicates a joint portion between the power terminal 207b of the semiconductor module 208R and the bus bar 207N.
A point P4 indicates a joint portion between the power terminal 207b of the semiconductor module 208L and the third main electrode 209.
A point P6 indicates a joint portion between the power terminal 207a of the semiconductor module 208R and the third main electrode 209.
Points P2 and P7 indicate joint portions of the first main electrode 203 and the semiconductor element 210 in the semiconductor modules 208L and 208R, respectively.
Points P3 and P8 indicate joint portions of the second main electrode 202 and the semiconductor element 210 in the semiconductor modules 208L and 208R, respectively.
A point P5 indicates a position near the middle between the points P4 and P6 in the third main electrode 209.
　図８（ｃ）に示すように、上下アーム回路のＰ側からＮ側へ電流が流れるとき、バスバ２０７Ｐから電力変換装置２０１に導入された電流は、点Ｐ１、Ｐ２、Ｐ３、Ｐ４、Ｐ５の順に、反時計回りの第１電流経路を流れ、その後、点Ｐ５、Ｐ６、Ｐ７、Ｐ８、Ｐ９の順に、反時計回りの第２電流経路を流れる。 As shown in FIG. 8C, when a current flows from the P side to the N side of the upper and lower arm circuits, the current introduced from the bus bar 207P to the power conversion device 201 is the point P1, P2, P3, P4, P5. The first current path flows counterclockwise in turn, and then the second current path flows counterclockwise in the order of points P5, P6, P7, P8, and P9.
　第１電流回路は、第３主電極２０９と半導体モジュール２０８Ｌによって構成される。より詳しくは、第１電流回路は、第３主電極２０９と、半導体モジュール２０８Ｌのパワー端子２０７ａ、第１主電極２０３、半導体素子２１０、第２主電極２０２、パワー端子２０２ｂによって構成される。 The first current circuit includes the third main electrode 209 and the semiconductor module 208L. More specifically, the first current circuit includes the third main electrode 209, the power terminal 207a of the semiconductor module 208L, the first main electrode 203, the semiconductor element 210, the second main electrode 202, and the power terminal 202b.
　第２電流回路は、第３主電極２０９と半導体モジュール２０８Ｒによって構成される。より詳しくは、第２電流回路は、第３主電極２０９と、半導体モジュール２０８Ｒのパワー端子２０７ａ、第１主電極２０３、半導体素子２１０、第２主電極２０２、パワー端子２０２ｂによって構成される。 The second current circuit is composed of the third main electrode 209 and the semiconductor module 208R. More specifically, the second current circuit includes the third main electrode 209, the power terminal 207a of the semiconductor module 208R, the first main electrode 203, the semiconductor element 210, the second main electrode 202, and the power terminal 202b.
　第１電流経路を電流が流れることにより、第１電流経路で囲まれる領域内に、電力変換装置２０１の下面から上面に向かう方向の第１磁場が発生する。さらに、第２電流経路を電流が流れることにより、第２電流経路で囲まれる領域内に、電力変換装置２０１の下面から上面に向かう第２磁場が発生する。第１磁場は、第１電流経路で囲まれる領域の外部において、電力変換装置２０１の上面から下面に向かう方向となることに注意する。また第２磁場は、第２電流経路で囲まれる領域の外部において、電力変換装置２０１の上面から下面に向かう方向となることに注意する。そのため、第１磁場と第２磁場とは逆方向を向くため、互いに弱め合うことになる。 When a current flows through the first current path, a first magnetic field in a direction from the lower surface to the upper surface of the power conversion device 201 is generated in a region surrounded by the first current path. Furthermore, when a current flows through the second current path, a second magnetic field from the lower surface to the upper surface of the power conversion device 201 is generated in a region surrounded by the second current path. Note that the first magnetic field is directed from the upper surface to the lower surface of the power conversion device 201 outside the region surrounded by the first current path. Note that the second magnetic field is directed from the upper surface to the lower surface of the power converter 201 outside the region surrounded by the second current path. For this reason, the first magnetic field and the second magnetic field face in opposite directions, so that they weaken each other.
　［本実施形態による効果］
　上述した本実施形態の構造及び本実施形態における電流経路によりもたらされる効果を説明する。 [Effects of this embodiment]
The effect brought about by the structure of the present embodiment described above and the current path in the present embodiment will be described.
　本実施形態では、半導体モジュール２０８Ｌ，２０８Ｒが隣り合って配置されており、半導体モジュール２０８Ｌ，２０８Ｒに電流が流れる際に発生する、第１磁場と第２磁場は互いに弱め合うようになっている。これは半導体モジュール２０８Ｌ，２０８Ｒの相互作用を高めることで電力変換装置２０１からの磁場の放射を抑制することに相当する。半導体モジュール２０８Ｌ，２０８Ｒの相互作用を高め、磁界の打ち消し合いの効果が高まることによって、電力変換装置２０１の全体でのインダクタンスを低減させることができる。 In the present embodiment, the semiconductor modules 208L and 208R are arranged adjacent to each other, and the first magnetic field and the second magnetic field that are generated when a current flows through the semiconductor modules 208L and 208R are mutually weakened. This corresponds to suppressing the radiation of the magnetic field from the power converter 201 by increasing the interaction between the semiconductor modules 208L and 208R. By increasing the interaction between the semiconductor modules 208L and 208R and increasing the effect of canceling out magnetic fields, the overall inductance of the power conversion device 201 can be reduced.
　さらに、第３主電極２０９が、半導体モジュール２０８Ｌ，２０８Ｒの上に、半導体モジュール２０８Ｌ，２０８Ｒの両方にまたがるように配置され、上下アーム回路を覆うように配置されているため、半導体モジュール２０８Ｌ，２０８Ｒから放射される第１磁場および第２磁場が外部に漏れ出ることが抑制される。そのため、電力変換装置２０１内での第１磁場、第２磁場の磁界強度が向上するため、第１磁場、第２磁場の間での打ち消し合う効果が高められる。その結果、電力変換装置２０１の全体でのインダクタンスを低減させることができる。 Further, since the third main electrode 209 is disposed on the semiconductor modules 208L and 208R so as to straddle both the semiconductor modules 208L and 208R and covers the upper and lower arm circuits, the semiconductor modules 208L and 208R are disposed. The leakage of the first magnetic field and the second magnetic field radiated from the outside is suppressed. Therefore, the magnetic field strengths of the first magnetic field and the second magnetic field in the power conversion device 201 are improved, so that the effect of canceling each other between the first magnetic field and the second magnetic field is enhanced. As a result, the inductance of the entire power conversion device 201 can be reduced.
　また、第３主電極２０９が、半導体モジュール２０８Ｌ，２０８Ｒの上に配置されることにより、第３主電極２０９と、第１主電極２０３および第２主電極２０２とが近接する。この結果、第１主電極２０３または第２主電極２０２の少なくとも一方と、第３主電極２０９との間で、相互インダクタンスが大きくなるため、電力変換装置２０１の全体でのインダクタンスを低減させることができる。 Further, the third main electrode 209 is disposed on the semiconductor modules 208L and 208R, so that the third main electrode 209, the first main electrode 203, and the second main electrode 202 are close to each other. As a result, since the mutual inductance increases between at least one of the first main electrode 203 or the second main electrode 202 and the third main electrode 209, the overall inductance of the power converter 201 can be reduced. it can.
　また、半導体モジュール２０８Ｌのパワー端子２０７ａと、半導体モジュール２０８Ｒのパワー端子２０７ｂが隣接しているため、上下アーム回路のＰ側、Ｎ側が隣接している。そのためＰＮ間を隣接したまま外部回路に接続することができる。例えば、バスバ２０７Ｐ，２０７Ｎ同士を重ねたまま回路先のコンデンサやモーター、電池などへ接続させれば、接続先までのインダクタンスも低減させることができる。 Also, since the power terminal 207a of the semiconductor module 208L and the power terminal 207b of the semiconductor module 208R are adjacent, the P side and N side of the upper and lower arm circuits are adjacent. For this reason, the PNs can be connected to an external circuit while being adjacent to each other. For example, if the bus bars 207P and 207N are overlapped with each other and connected to a capacitor, motor, battery, or the like at the circuit destination, the inductance to the connection destination can be reduced.
　さらに、半導体モジュール２０８Ｌ，２０８Ｒ（２０８）では、パワー端子２０７ａ，２０７ｂが、共に半導体モジュールの前面に露出するように配置され、半導体素子２１０は、半導体モジュール２０８の内部で、パワー端子２０７ａ，２０７ｂの後方に配置されているため、半導体モジュール２０８内で、高電位側から低電位側へ（Ｐ側からＮ側へ）流れる電流が、半導体素子２１０を介して折り返すように流れる。そのため相互インダクタンスによるインダクタンスの低減とともに、半導体モジュール２０８と第３主電極２０９との相互インダクタンスによるインダクタンスが低減できる。さらに第３主電極２０９が、Ｐ側からＮ側に電流が流れるときに生じる磁界を強めることができるので、さらにインダクタンスを低減させる効果が大きくなる。 Further, in the semiconductor modules 208L and 208R (208), the power terminals 207a and 207b are both disposed so as to be exposed on the front surface of the semiconductor module, and the semiconductor element 210 is connected to the power terminals 207a and 207b inside the semiconductor module 208. Since the semiconductor module 208 is disposed behind, a current that flows from the high potential side to the low potential side (from the P side to the N side) flows through the semiconductor element 210 in the semiconductor module 208. Therefore, the inductance due to the mutual inductance between the semiconductor module 208 and the third main electrode 209 can be reduced along with the reduction of the inductance due to the mutual inductance. Furthermore, since the third main electrode 209 can strengthen the magnetic field generated when current flows from the P side to the N side, the effect of further reducing the inductance is further increased.
　上述のように、電力変換装置２０１の全体でのインダクタンスを低減できるため、サージ電圧を効果的に低減することができる。さらに、サージ電圧が抑制されることにより、スイッチング周波数を上げることが可能である。 As described above, since the inductance of the entire power conversion device 201 can be reduced, the surge voltage can be effectively reduced. Furthermore, the switching frequency can be increased by suppressing the surge voltage.
　さらに、第３主電極２０９および冷却器ＲＧが、第１主電極２０３および第２主電極２０２と近接しており、冷却器ＲＧと第１主電極２０３の間の距離、第３主電極２０９と第２主電極２０２の間の距離が短くなっている。そのため電力変換装置２０１の内部で生じた熱、特に半導体素子２１０で生じた熱が、第１主電極２０３および第２主電極２０２に伝わり、その後、第３主電極２０９および冷却器ＲＧに伝わるまでの、熱伝導に必要な距離が短くなっている。電力変換装置２０１の内部で生じた熱は、最終的に第３主電極２０９および冷却器ＲＧに伝わることにより電力変換装置２０１から排熱されるため、電力変換装置２０１の熱抵抗を低減することができる。 Further, the third main electrode 209 and the cooler RG are close to the first main electrode 203 and the second main electrode 202, and the distance between the cooler RG and the first main electrode 203, the third main electrode 209, The distance between the second main electrodes 202 is shortened. Therefore, the heat generated in the power conversion device 201, particularly the heat generated in the semiconductor element 210 is transmitted to the first main electrode 203 and the second main electrode 202, and then transmitted to the third main electrode 209 and the cooler RG. The distance required for heat conduction is shortened. Since the heat generated inside the power conversion device 201 is finally transferred to the third main electrode 209 and the cooler RG to be exhausted from the power conversion device 201, the thermal resistance of the power conversion device 201 can be reduced. it can.
　第３主電極２０９が第２主電極２０２と近接して配置されているため、半導体モジュール２０８Ｌ，２０８Ｒと第３主電極２０９との間で、熱の移動が容易になっている。そのため、上下アーム回路のうち、動作していない側のアームの半導体モジュール２０８Ｌ，２０８Ｒへ熱を移動させることもできる。すなわち、インバータ動作によっても熱抵抗を低減させることができる。 Since the third main electrode 209 is disposed close to the second main electrode 202, heat transfer is easy between the semiconductor modules 208L and 208R and the third main electrode 209. Therefore, heat can be transferred to the semiconductor modules 208L and 208R of the arm on the non-operating side of the upper and lower arm circuits. That is, the thermal resistance can be reduced also by the inverter operation.
　本実施形態では、電力変換装置２０１の全体でのインダクタンス低減と、熱抵抗の低減を同時に実現できるため、さらなる効果を得ることができる。 In this embodiment, since the inductance reduction of the whole power converter 201 and the reduction of thermal resistance can be realized at the same time, further effects can be obtained.
　一般的な３相インバータ回路においてスイッチング周波数を上げた場合、半導体モジュール内部での損失が増大する。そのため熱対策が必要となる場合があり、電力変換装置自体を小型化することが難しかった。 When the switching frequency is increased in a general three-phase inverter circuit, the loss inside the semiconductor module increases. Therefore, heat countermeasures may be required, and it is difficult to reduce the size of the power converter itself.
　一方、本実施形態では、電力変換装置２０１の全体でのインダクタンス低減と、熱抵抗の低減を同時に実現できるため、電力変換装置２０１の高周波化を行った際に、別途の熱対策を必要とすることなく、半導体モジュール２０８内で発生する熱を容易に外部に逃がすことができる。そのため電力変換装置２０１を小型化することができる。すなわち、高周波動作が可能な、小型の電力変換装置２０１を得ることができる。 On the other hand, in the present embodiment, since the inductance reduction and the thermal resistance reduction of the entire power conversion device 201 can be realized at the same time, a separate heat countermeasure is required when the power conversion device 201 is increased in frequency. Therefore, the heat generated in the semiconductor module 208 can be easily released to the outside. Therefore, the power converter 201 can be reduced in size. That is, a small power conversion device 201 capable of high-frequency operation can be obtained.
　半導体モジュール２０８を金型成形で樹脂封止すれば、第１主電極２０３または第２主電極２０２の平面に対して精度よく平行して絶縁を保てることができるので、第３主電極２０９を半導体モジュール２０８の内外いずれかに用いた際に高い平行度を保つことができる。そのため半導体モジュール２０８Ｌ，２０８Ｒの間の相互インダクタンスをより効果的に作用させることができる。このことにより、電力変換装置２０１の全体のインダクタンスを低減させることができる。 If the semiconductor module 208 is resin-sealed by molding, insulation can be maintained in parallel with the plane of the first main electrode 203 or the second main electrode 202 with high accuracy, so that the third main electrode 209 is made of semiconductor. A high degree of parallelism can be maintained when used either inside or outside the module 208. Therefore, the mutual inductance between the semiconductor modules 208L and 208R can be made to work more effectively. As a result, the overall inductance of the power converter 201 can be reduced.
　また、樹脂封止されていることで、樹脂内部に実装されている半導体素子２１０や実装に用いるはんだ材にかかる熱ひずみを軽減することができるので信頼性が向上する。また、半導体モジュール２０８の反りを抑えることができるので、反りに対する平行度も高くすることができる。 Also, since the resin is sealed, the heat distortion applied to the semiconductor element 210 mounted inside the resin and the solder material used for mounting can be reduced, so that the reliability is improved. In addition, since the warpage of the semiconductor module 208 can be suppressed, the degree of parallelism with respect to the warpage can be increased.
　第１主電極２０３と第２主電極２０２、第３主電極２０９との樹脂の肉厚は、必要な絶縁距離を確保しつつできるだけ薄い方が相互インダクタンスの効果が高く、電力変換装置２０１全体のインダクタンスを低減させる効果が大きくなる。本実施形態のように、第３主電極２０９を半導体モジュール２０８Ｌ，２０８Ｒの樹脂上表面に接地させることで、絶縁距離を最短にしてインダクタンスをより低減することができる。 The thickness of the resin between the first main electrode 203, the second main electrode 202, and the third main electrode 209 is as thin as possible while ensuring the necessary insulation distance, and the effect of mutual inductance is higher. The effect of reducing the inductance is increased. As in this embodiment, by grounding the third main electrode 209 to the resin upper surface of the semiconductor modules 208L and 208R, the insulation distance can be minimized and the inductance can be further reduced.
　さらに、本実施形態では、第３主電極２０９を半導体モジュール２０８に対して外付けする方式であるため、第３主電極２０９と第２主電極２０２の間を確実に絶縁しつつ、同時に第３主電極２０９と第２主電極２０２の間の距離を短くすることができる。 Further, in the present embodiment, since the third main electrode 209 is externally attached to the semiconductor module 208, the third main electrode 209 and the second main electrode 202 are reliably insulated from each other while the third main electrode 209 and the second main electrode 202 are simultaneously insulated. The distance between the main electrode 209 and the second main electrode 202 can be shortened.
　一般に、主電極を半導体モジュール内に含めて樹脂封止する場合には、樹脂が主電極間を回り込みづらく、絶縁が保てなかったりプロセスコストがかかったり主電極に穴をあけたりなどの形状工夫が求められることになる。そのため製造上、絶縁距離が確保できず、主電極間の距離を広げなければならないことがある。このような場合と比較して、第３主電極２０９を外付けする方式では、半導体モジュール２０８の外装を成形する時に半導体モジュール２０８の表面と第２主電極の間に存在する封止剤２０５による層を薄く成形し、その後、第３主電極２０９を外付けできる。よって、第３主電極２０９と第２主電極２０２の間を確実に絶縁しつつ、同時に第３主電極２０９と第２主電極２０２の間の距離を短くすることができる。 In general, when resin is sealed by including the main electrode in the semiconductor module, it is difficult for the resin to wrap around the main electrodes, insulation cannot be maintained, process costs are increased, holes are made in the main electrode, etc. Will be required. Therefore, in manufacturing, the insulation distance cannot be secured, and the distance between the main electrodes may have to be increased. Compared to such a case, in the method in which the third main electrode 209 is externally attached, the sealing agent 205 existing between the surface of the semiconductor module 208 and the second main electrode is used when molding the exterior of the semiconductor module 208. The layer can be thinly formed and then the third main electrode 209 can be externally attached. Therefore, the distance between the third main electrode 209 and the second main electrode 202 can be shortened at the same time while reliably insulating the third main electrode 209 and the second main electrode 202.
　本実施形態では、第３主電極２０９と第２主電極２０２の間の距離を短くすることができるため、第３主電極２０９と第２主電極２０２の間の相互インダクタンスの効果を高めることができる。その結果、電力変換装置２０１全体のインダクタンスを低減させる効果が大きくなる。 In the present embodiment, since the distance between the third main electrode 209 and the second main electrode 202 can be shortened, the effect of the mutual inductance between the third main electrode 209 and the second main electrode 202 can be enhanced. it can. As a result, the effect of reducing the inductance of the entire power conversion device 201 is increased.
　半導体モジュール２０８を冷却器の表面へ絶縁材を介して金属接合する直接冷却構造の場合は、半導体モジュール２０８や絶縁材、冷却器それぞれの線膨張係数の差があるため、グリース等で冷却器へ接続する間接冷却構造に比べて、熱応力が大きくなり、反り量が大きくなる。しかしながら本実施形態では、第３主電極２０９による抑えによって、半導体モジュール２０８の反りを軽減し、確実に半導体モジュール２０８と冷却器の表面の接触を保つことができ、直接冷却構造の信頼性を向上させることができる。 In the case of a direct cooling structure in which the semiconductor module 208 is metal-bonded to the surface of the cooler via an insulating material, there is a difference in the linear expansion coefficient between the semiconductor module 208, the insulating material, and the cooler. Compared with the indirect cooling structure to be connected, the thermal stress increases and the amount of warpage increases. However, in this embodiment, the warpage of the semiconductor module 208 can be reduced by the suppression by the third main electrode 209, and the contact between the semiconductor module 208 and the surface of the cooler can be reliably maintained, and the reliability of the direct cooling structure is improved. Can be made.
［第７実施形態の変形例１］
　図１１は、第７実施形態の変形例１に係る電力変換装置３０１の断面図を示している。電力変換装置２０１の説明の際に、図１０で示した断面図に対応する位置における電力変換装置３０１の断面を示している。この電力変換装置３０１は、前述した第１～第７実施形態と同様に、３相のインバータ装置の１つの相を構成するものである。 [Modification 1 of the seventh embodiment]
FIG. 11: has shown sectional drawing of the power converter device 301 which concerns on the modification 1 of 7th Embodiment. In the description of the power conversion device 201, a cross section of the power conversion device 301 at a position corresponding to the cross sectional view shown in FIG. This power conversion device 301 constitutes one phase of a three-phase inverter device, as in the first to seventh embodiments described above.
　また、変形例１に係る電力変換装置３０１は、電力変換装置２０１（図１０参照）と対比して、上アームと下アームが１つの半導体モジュール２０８Ｗ１内にパッケージされている点で相違する。以下、相違点についてのみ説明し、第７実施形態で示した電力変換装置３０１と同一部分は同一の符号を付して説明を省略する。 Also, the power conversion device 301 according to the modification 1 is different from the power conversion device 201 (see FIG. 10) in that the upper arm and the lower arm are packaged in one semiconductor module 208W1. Hereinafter, only differences will be described, and the same parts as those of the power conversion device 301 shown in the seventh embodiment are denoted by the same reference numerals, and description thereof will be omitted.
　図１１に示すように、半導体モジュール２０８Ｗ１は、半導体モジュール２０８と異なり、半導体素子２１０、第１主電極２０３、第２主電極２０２をそれぞれ２つずつ有しており、また、パワー端子２０７ａ，２０７ｂについても、それぞれ２つずつ有している。 As shown in FIG. 11, unlike the semiconductor module 208, the semiconductor module 208W1 has two semiconductor elements 210, two first main electrodes 203, and two second main electrodes 202, and power terminals 207a and 207b. There are also two each.
　半導体モジュール２０８Ｗ１は、２個の半導体モジュール２０８の構造を有するものであり、１個の半導体モジュール２０８Ｗ１によって、上下アーム回路を構成することができる。半導体モジュール２０８Ｗ１は、３相インバータの２つのアームに対応する部品であり、２ｉｎ１パワー半導体モジュールと呼ばれる。半導体モジュール２０８Ｗ１自身のパワー端子２０７ａ，２０７ｂを相互に接続し、上下アーム回路を構成することにより、１個の半導体モジュール２０８Ｗ１によって３相インバータ回路の１つの相を構成することができる。パワー端子２０７ａ，２０７ｂ間の接続方法は電力変換装置２０１の場合と同じである。 The semiconductor module 208W1 has the structure of two semiconductor modules 208, and a single semiconductor module 208W1 can constitute an upper and lower arm circuit. The semiconductor module 208W1 is a component corresponding to the two arms of the three-phase inverter and is called a 2-in-1 power semiconductor module. By connecting the power terminals 207a and 207b of the semiconductor module 208W1 itself to form an upper and lower arm circuit, one semiconductor module 208W1 can constitute one phase of a three-phase inverter circuit. The connection method between the power terminals 207a and 207b is the same as that of the power converter 201.
　変形例１においても、第３主電極２０９は、半導体モジュール２０８Ｗ１の上面に接して、半導体モジュール２０８Ｗ１の上面を覆うように配置されているため、第３主電極２０９は、封止剤２０５で絶縁される領域を挟んで、半導体モジュール２０８Ｗ１内に位置する２つの第２主電極２０２と近接する。そのため第１主電極２０３または第２主電極２０２の少なくとも一方と、第３主電極２０９との間で、相互インダクタンスが大きくなるため、電力変換装置３０１の全体でのインダクタンスを低減させることができる。 Also in the first modification, the third main electrode 209 is disposed so as to be in contact with the upper surface of the semiconductor module 208W1 and to cover the upper surface of the semiconductor module 208W1, so that the third main electrode 209 is insulated by the sealing agent 205. The two main main electrodes 202 located in the semiconductor module 208W1 are close to each other across the region to be processed. Therefore, since the mutual inductance increases between at least one of the first main electrode 203 or the second main electrode 202 and the third main electrode 209, the inductance of the entire power conversion device 301 can be reduced.
　変形例１においても、第３主電極２０９および冷却器ＲＧが、第１主電極２０３および第２主電極２０２と近接しており、第３主電極２０９と第１主電極２０３の間の距離、冷却器ＲＧと第２主電極２０２の間の距離が短くなっている。そのため、電力変換装置２０１と同様に、電力変換装置３０１の内部で生じた熱は第３主電極２０９および冷却器ＲＧに伝わって、電力変換装置３０１から排熱されやすくなっている。よって電力変換装置３０１の熱抵抗を低減することができる。 Also in Modification 1, the third main electrode 209 and the cooler RG are close to the first main electrode 203 and the second main electrode 202, and the distance between the third main electrode 209 and the first main electrode 203, The distance between the cooler RG and the second main electrode 202 is shortened. Therefore, similarly to the power converter 201, the heat generated inside the power converter 301 is transmitted to the third main electrode 209 and the cooler RG, and is easily exhausted from the power converter 301. Therefore, the thermal resistance of the power converter 301 can be reduced.
［第７実施形態の変形例２］
　図１２は、第７実施形態の変形例２に係る電力変換装置４０１の断面図を示している。電力変換装置２０１の説明の際に図１０で示した断面図に対応する位置での、電力変換装置４０１の断面を示している。この電力変換装置４０１は、前述した第１～第７実施形態と同様に、３相のインバータ装置の１つの相を構成するものである。 [Modification 2 of the seventh embodiment]
FIG. 12 shows a cross-sectional view of a power conversion device 401 according to Modification 2 of the seventh embodiment. The cross section of the power converter device 401 is shown at a position corresponding to the cross sectional view shown in FIG. 10 when the power converter device 201 is described. This power conversion device 401 constitutes one phase of a three-phase inverter device as in the first to seventh embodiments described above.
　また、変形例２に係る電力変換装置４０１は、電力変換装置３０１（図１０参照）と対比して、半導体モジュール２０８Ｗ２内に第３主電極２０９がパッケージされている点で相違する。以下、相違点についてのみ説明し、第７実施形態で示した電力変換装置３０１と同一部分は同一の符号を付して説明を省略する。 Also, the power conversion device 401 according to the modification 2 is different from the power conversion device 301 (see FIG. 10) in that the third main electrode 209 is packaged in the semiconductor module 208W2. Hereinafter, only differences will be described, and the same parts as those of the power conversion device 301 shown in the seventh embodiment are denoted by the same reference numerals, and description thereof will be omitted.
　図１２に示す電力変換装置４０１のように、半導体モジュール２０８内に第３主電極２０９を含めた場合は、封止剤２０５を第３主電極２０９と第２主電極２０２の間に確実に充填するため、第３主電極２０９を半導体モジュール２０８に外付けする場合と比較して封止剤２０５を第３主電極２０９と第２主電極２０２の間の距離を大きくするなど工夫が必要となる。しかしながら、図１２の変形例２によれば、第３主電極２０９の外付け作業が不要であるため、小型でありながら汎用性と量産性を向上させることができる。 When the third main electrode 209 is included in the semiconductor module 208 as in the power conversion device 401 shown in FIG. 12, the sealing agent 205 is reliably filled between the third main electrode 209 and the second main electrode 202. Therefore, it is necessary to devise measures such as increasing the distance between the third main electrode 209 and the second main electrode 202 with the sealant 205 as compared with the case where the third main electrode 209 is externally attached to the semiconductor module 208. . However, according to the second modification of FIG. 12, the external work of the third main electrode 209 is unnecessary, so that versatility and mass productivity can be improved while being small.
　また上アームを構成する部位と下アームを構成する部位間で発生する熱応力や機械的な応力が発生し、封止剤２０５では抑えきれない反りが発生しうる状況であっても、半導体モジュール２０８Ｗ２内で、上下アーム回路を覆うように設けられた第３主電極２０９が支えになり、熱応力や機械的な応力による半導体モジュール２０８Ｗ２の反りを軽減することができる。結果として、確実に半導体モジュール２０８Ｗ２と冷却器の表面との接触を保つことができる。 Even in a situation where thermal stress and mechanical stress generated between the part constituting the upper arm and the part constituting the lower arm are generated, and warpage that cannot be suppressed by the sealant 205 may occur, the semiconductor module Within 208W2, the third main electrode 209 provided so as to cover the upper and lower arm circuits is supported, and the warpage of the semiconductor module 208W2 due to thermal stress and mechanical stress can be reduced. As a result, the semiconductor module 208W2 can be reliably kept in contact with the surface of the cooler.
［第８実施形態の説明］
　次に、本発明の第８実施形態について説明する。この電力変換装置５０１は、第１実施形態～第７実施形態、および第７実施形態の変形例１、変形例２で説明した電力変換装置と同様に、３相インバータ回路の１つの相を構成するものである。 [Explanation of Eighth Embodiment]
Next, an eighth embodiment of the present invention will be described. This power conversion device 501 configures one phase of the three-phase inverter circuit, similarly to the power conversion devices described in the first to seventh embodiments and the first and second modifications of the seventh embodiment. To do.
　図１３は、第８実施形態に係る電力変換装置５０１の斜視図である。図１４（ａ）、図１４（ｂ）、図１４（ｃ）は、電力変換装置５０１の構成を示す図であり、図１４（ａ）は、電力変換装置５０１の平面図、図１４（ｂ）は、電力変換装置５０１の動作時における電流経路を示す概略図である。また、図１４（ｃ）は、電力変換装置５０１に使用される半導体モジュール２０８ＡＬ，２０８ＡＲ（半導体モジュール２０８Ａ）の内部構造を示す斜視図である。 FIG. 13 is a perspective view of the power conversion device 501 according to the eighth embodiment. FIG. 14A, FIG. 14B, and FIG. 14C are diagrams showing the configuration of the power converter 501. FIG. 14A is a plan view of the power converter 501. FIG. ) Is a schematic diagram showing a current path during operation of the power conversion device 501. FIG. 14C is a perspective view showing the internal structure of the semiconductor modules 208AL and 208AR (semiconductor module 208A) used in the power conversion device 501.
　電力変換装置５０１を構成する半導体モジュール２０８ＡＬ，２０８ＡＲは、同一の構造を有するものとして説明する。以降の説明において、半導体モジュール２０８ＡＬ，２０８ＡＲを半導体モジュール２０８Ａとして参照する場合がある。 The semiconductor modules 208AL and 208AR constituting the power conversion device 501 will be described as having the same structure. In the following description, the semiconductor modules 208AL and 208AR may be referred to as the semiconductor module 208A.
　本実施形態に係る電力変換装置５０１では、図１４（ｃ）に示すように、パワー端子２０７ａ，２０７ｂが、半導体素子２１０を挟んで、半導体モジュール２０８Ａの対向する面にそれぞれ配置されている。言い換えると、パワー端子２０７ａは、半導体モジュール２０８Ａの前面に配置され、パワー端子２０７ｂは半導体モジュール２０８Ａの後面に配置されている。そのため半導体モジュール２０８Ａ内で、パワー端子２０７ａ、半導体素子２１０、パワー端子２０７ｂは、この順で略同一直線状に並んで配置されている。 In the power conversion device 501 according to the present embodiment, as shown in FIG. 14C, the power terminals 207a and 207b are respectively disposed on the opposing surfaces of the semiconductor module 208A with the semiconductor element 210 interposed therebetween. In other words, the power terminal 207a is disposed on the front surface of the semiconductor module 208A, and the power terminal 207b is disposed on the rear surface of the semiconductor module 208A. Therefore, in the semiconductor module 208A, the power terminal 207a, the semiconductor element 210, and the power terminal 207b are arranged in substantially the same straight line in this order.
　そして、図１３および図１４（ａ）に示すように、上アームを構成する半導体モジュール２０８ＡＬのパワー端子２０７ａと、下アームを構成する半導体モジュール２０８ＡＲのパワー端子２０７ｂが隣り合うように配置されている。また上アームを構成する半導体モジュール２０８ＡＬのパワー端子２０７ｂと、下アームを構成する半導体モジュール２０８ＡＲのパワー端子２０７ａが隣り合うように配置されている。 As shown in FIGS. 13 and 14A, the power terminal 207a of the semiconductor module 208AL constituting the upper arm and the power terminal 207b of the semiconductor module 208AR constituting the lower arm are arranged adjacent to each other. . The power terminal 207b of the semiconductor module 208AL constituting the upper arm and the power terminal 207a of the semiconductor module 208AR constituting the lower arm are arranged adjacent to each other.
　上アームを構成する半導体モジュール２０８ＡＬのパワー端子２０７ｂと、下アームを構成する半導体モジュール２０８ＡＲのパワー端子２０７ａとが、第３主電極２０９Ａによって電気的に接続され、半導体モジュール２０８ＡＬと半導体モジュール２０８ＡＲは、上下アーム回路を形成するように直列に接続されている。 The power terminal 207b of the semiconductor module 208AL constituting the upper arm and the power terminal 207a of the semiconductor module 208AR constituting the lower arm are electrically connected by the third main electrode 209A, and the semiconductor module 208AL and the semiconductor module 208AR are They are connected in series so as to form upper and lower arm circuits.
　図１４（ａ）に示すように、本実施形態では２つの半導体モジュール２０８Ａのうち片方を１８０度回転させて並べ、半導体モジュール２０８ＡＬ，２０８ＡＲとしている。そのため、図１４（ｂ）に示す電流経路のように、上下アーム回路のＰ側からＮ側に流れる電流の流れは、点Ｐ１、Ｐ２、Ｐ３、Ｐ４の順に進み、点Ｐ５で折り返して、その後、点Ｐ６、Ｐ７、Ｐ８、Ｐ９の順に、流れる経路をたどる。このように電流は折り返すように流れるため、図１４（ｂ）の電流経路において、点Ｐ４から点Ｐ６にかけての辺の長さを短くすることにより、半導体モジュール２０８ＡＬ側の電流経路（点Ｐ１から点Ｐ４までの辺）と、半導体モジュール２０８ＡＲ側の電流経路（点Ｐ６から点Ｐ９までの辺）の間の相互インダクタンスを大きくすることができる。その結果、電力変換装置５０１の全体でのインダクタンスを低減する効果が大きくなる。 As shown in FIG. 14A, in this embodiment, one of the two semiconductor modules 208A is rotated 180 degrees and arranged to form semiconductor modules 208AL and 208AR. Therefore, as in the current path shown in FIG. 14B, the flow of current flowing from the P side to the N side of the upper and lower arm circuits proceeds in the order of points P1, P2, P3, and P4, and then turns back at point P5. , Following the flowing path in the order of points P6, P7, P8, and P9. Since the current flows in such a manner as shown in FIG. 14B, by shortening the length of the side from the point P4 to the point P6 in the current path in FIG. 14B, the current path (from the point P1 to the point on the semiconductor module 208AL side). The mutual inductance between the side up to P4) and the current path on the semiconductor module 208AR side (side from the point P6 to the point P9) can be increased. As a result, the effect of reducing the inductance of the entire power conversion device 501 is increased.
　半導体モジュール２０８Ａでは、パワー端子２０７ａ，２０７ｂが、半導体素子２１０を挟んで、半導体モジュール２０８Ａの対向する面にそれぞれ配置されているため、半導体モジュール２０８Ａの幅を狭くすることができる。また、第７実施形態で示した半導体モジュール２０８のようにパワー端子２０７ａ，２０７ｂを同一の側の面（前面）に配置する場合と比較して、半導体モジュール２０８Ａのパワー端子２０７ａ，２０７ｂの間の絶縁距離を短くしやすいため、半導体モジュール２０８Ａを並べる際の、半導体モジュール２０８Ａ同士の間の幅も狭くすることができる。これらの特徴により、電力変換装置５０１の小型化が可能である。 In the semiconductor module 208A, since the power terminals 207a and 207b are respectively disposed on the opposing surfaces of the semiconductor module 208A with the semiconductor element 210 interposed therebetween, the width of the semiconductor module 208A can be reduced. Further, as compared with the case where the power terminals 207a and 207b are arranged on the same side surface (front surface) as in the semiconductor module 208 shown in the seventh embodiment, between the power terminals 207a and 207b of the semiconductor module 208A. Since the insulation distance can be easily shortened, the width between the semiconductor modules 208A when the semiconductor modules 208A are arranged can be narrowed. With these features, the power conversion device 501 can be downsized.
［第９実施形態の説明］
　次に、本発明の第９実施形態について説明する。この電力変換装置６０１は、第１実施形態～第８実施形態で説明した電力変換装置と同様に、３相インバータ回路の１つの相を構成するものである。 [Description of Ninth Embodiment]
Next, a ninth embodiment of the present invention will be described. This power conversion device 601 constitutes one phase of a three-phase inverter circuit, similarly to the power conversion devices described in the first to eighth embodiments.
　図１５に示す電力変換装置６０１は、特に第８実施形態で説明した電力変換装置５０１の、第３主電極２０９Ａの上に、絶縁体２３５を介して別途、２枚の第３主電極２０９Ｂ，２０９Ｃが配置された状態を示している。その他の構成は第８実施形態の電力変換装置５０１と変わらないので説明を省略する。なお、図１５において、第３主電極２０９Ａ，２０９Ｂ，２０９Ｃが有する、外部回路との接続用の端子は省略している。 The power conversion device 601 shown in FIG. 15 includes two third main electrodes 209B and 209B separately on the third main electrode 209A of the power conversion device 501 described in the eighth embodiment via an insulator 235. The state where 209C is arranged is shown. Since other configurations are the same as those of the power conversion device 501 of the eighth embodiment, description thereof is omitted. In FIG. 15, terminals for connection with external circuits included in the third main electrodes 209A, 209B, and 209C are omitted.
　第３主電極２０９Ｃは、連結金具２２１によって、半導体モジュール２０８ＡＬのパワー端子２０７ａと電気的に接続されている。また第３主電極２０９Ｂは、連結金具２２２によって、半導体モジュール２０８ＡＲのパワー端子２０７ｂと電気的に接続されている。そのため、第３主電極２０９Ｃは上下アーム回路のＰ側に接続され、第３主電極２０９Ｂは上下アーム回路のＮ側に接続されている。 The third main electrode 209C is electrically connected to the power terminal 207a of the semiconductor module 208AL by a connecting fitting 221. In addition, the third main electrode 209B is electrically connected to the power terminal 207b of the semiconductor module 208AR by a connecting fitting 222. Therefore, the third main electrode 209C is connected to the P side of the upper and lower arm circuit, and the third main electrode 209B is connected to the N side of the upper and lower arm circuit.
　ここで、Ｐ側に接続される第３主電極２０９Ｃでの電流方向は、半導体モジュール２０８ＡＬのパワー端子２０７ａ（Ｐ側）の電流方向と対抗するように設けられているため、電流が折り返す効果によって、第３主電極２０９Ｃと半導体モジュール２０８ＡＬの間で相互インダクタンス効果を発生させることが可能となる。Ｎ側に接続される第３主電極２０９Ｂでの電流方向は、半導体モジュール２０８ＡＲのパワー端子２０７ｂ（Ｎ側）の電流方向と対抗するように設けられているため、同様に、第３主電極２０９Ｂと半導体モジュール２０８ＡＲの間においても、相互インダクタンス効果を発生させることが可能となる。 Here, since the current direction at the third main electrode 209C connected to the P side is provided to oppose the current direction of the power terminal 207a (P side) of the semiconductor module 208AL, the effect of current folding back is provided. A mutual inductance effect can be generated between the third main electrode 209C and the semiconductor module 208AL. Since the current direction in the third main electrode 209B connected to the N side is provided to oppose the current direction of the power terminal 207b (N side) of the semiconductor module 208AR, the third main electrode 209B is similarly provided. It is possible to generate a mutual inductance effect between the semiconductor module 208AR and the semiconductor module 208AR.
　複数の第３主電極２０９Ａ，２０９Ｂ，２０９Ｃの上下の並びは、半導体モジュール２０８ＡＬ，２０８ＡＲとの構成によって自由に変えることができ、所定の効果が得られるよう最適な並びを選択することができる。また、第３主電極２０９Ａ，２０９Ｂ，２０９Ｃ同士を重ねたまま回路先のコンデンサやモーター、電池などへ接続させれば、接続先までのインダクタンスも低減させることができる。 The upper and lower arrangement of the plurality of third main electrodes 209A, 209B, and 209C can be freely changed depending on the configuration with the semiconductor modules 208AL and 208AR, and an optimum arrangement can be selected so as to obtain a predetermined effect. In addition, if the third main electrodes 209A, 209B, and 209C are connected to a capacitor, a motor, a battery, or the like at a circuit destination while the third main electrodes 209A, 209B, and 209C are overlapped, inductance to the connection destination can be reduced.
［その他の実施の形態］
　本発明の第１実施形態～第９実施形態では、半導体素子５，８，２１０のそれぞれは単一の素子部品であるものとして説明した。しかしながら、スイッチング動作と還流動作を行うものであれば、必ずしも単一の素子部品として形成される必要はなく、半導体素子５，８，２１０のそれぞれが、複数の素子部品を組み合わせて形成されるものであっても構わない。例えば、ＭＯＳＦＥＴは、スイッチング動作と、ＭＯＳＦＥＴに内蔵されるＰＮダイオードで還流動作が可能であるため、１個のＭＯＳＦＥＴを素子部品として使用することにより半導体素子５，８，２１０を構成することができる。その他、ＩＧＢＴ等、逆方向に流れづらい素子を素子部品として使用する場合は、ＦＷＤ（ダイオード）を設けても良い。半導体素子５，８，２１０はＳｉやＳｉＣ、他からなるものでもよい。 [Other embodiments]
In the first to ninth embodiments of the present invention, each of the semiconductor elements 5, 8, and 210 has been described as a single element part. However, if the switching operation and the reflux operation are performed, it is not necessarily formed as a single element part, and each of the semiconductor elements 5, 8, 210 is formed by combining a plurality of element parts. It does not matter. For example, a MOSFET can perform a switching operation and a recirculation operation with a PN diode built in the MOSFET, so that the semiconductor elements 5, 8, and 210 can be configured by using one MOSFET as an element component. . In addition, when an element such as an IGBT that is difficult to flow in the reverse direction is used as an element part, an FWD (diode) may be provided. The semiconductor elements 5, 8, 210 may be made of Si, SiC, or the like.
　また、直流の電源の電圧をスイッチング素子によってそのまま出力にスイッチングして繋げる回路構成のインバータ、すなわち電圧型インバータを例として説明した。直流の電源からインダクタを介して一定の電流を流し、その電流が流れ込む端子をスイッチングにより切り替える回路構成のインバータ、すなわち電流型インバータに対して適用しても同じ効果を得ることができる。すなわちインバータを構成するバスバと半導体素子の間での容量結合を増大させることで、インバータ全体のインダクタンスを低減させることができ、インダクタンスに起因して生じるサージ電圧の発生を抑制することが可能となる。 Also, an inverter having a circuit configuration in which the voltage of a DC power supply is directly connected to an output by a switching element and connected, that is, a voltage type inverter has been described as an example. The same effect can be obtained even when applied to an inverter having a circuit configuration in which a constant current is supplied from a DC power source via an inductor and a terminal into which the current flows is switched by switching, that is, a current type inverter. In other words, by increasing the capacitive coupling between the bus bar constituting the inverter and the semiconductor element, the inductance of the entire inverter can be reduced, and the generation of a surge voltage caused by the inductance can be suppressed. .
　本発明の第７実施形態～第９実施形態では、第３主電極２０９，２０９Ａは、上下アーム回路の、上アームと下アームとの接続点の電位を出力するものとして説明した。その他、代わりに第３主電極２０９，２０９Ａは、上下アーム回路のＰ側の電位を出力、あるいはＮ側の電位を出力するものであってもよい。この場合においても、第３主電極２０９，２０９Ａが半導体モジュール２０８，２０８Ｗ１，２０８Ｗ２，２０８Ａ内の第２主電極２０２と近接して設けられ、また上下アーム回路を覆うように配置される場合には、第７実施形態～第９実施形態と同じ効果をもつ。 In the seventh to ninth embodiments of the present invention, it has been described that the third main electrodes 209 and 209A output the potential at the connection point between the upper arm and the lower arm of the upper and lower arm circuits. In addition, the third main electrodes 209 and 209A may alternatively output the P-side potential or the N-side potential of the upper and lower arm circuits. Also in this case, when the third main electrodes 209 and 209A are provided close to the second main electrode 202 in the semiconductor modules 208, 208W1, 208W2 and 208A and are arranged so as to cover the upper and lower arm circuits. This has the same effect as the seventh to ninth embodiments.
　半導体モジュール２０８Ｌ，２０８Ｒ、あるいは半導体モジュール２０８ＡＬ，２０８ＡＲは、互いに同じ構造（半導体モジュール２０８，２０８Ａ）を有するものとして説明しているが、３相インバータ回路の相を構成する上アーム、下アームとしての機能を発揮でき、半導体モジュール２０８Ｌを流れる電流によって生じる磁気と、半導体モジュール２０８Ｒを流れる電流によって生じる磁気とが互いに打ち消し合うような構造であれば、必ずしも同じ構造を有している必要はない。 The semiconductor modules 208L and 208R or the semiconductor modules 208AL and 208AR have been described as having the same structure ( semiconductor modules 208 and 208A), but the upper and lower arms constituting the phases of the three-phase inverter circuit The structure is not necessarily the same as long as the structure is such that the magnetism generated by the current flowing through the semiconductor module 208L and the magnetism generated by the current flowing through the semiconductor module 208R cancel each other.
　パワー端子２０７ａ，２０７ｂは、それぞれ第１主電極２０３、第２主電極２０２とは別部材で設けられ、接合材２０６を介して、それぞれ第１主電極２０３、第２主電極２０２と電気的に接続されるものとして説明した。しかしながら、このような構造に限定されるものではなく、パワー端子２０７ａと第１主電極２０３とは、一体的に形成されたものであってもよい。同様に、パワー端子２０７ｂと第２主電極２０２とは、一体的に形成されたものであってもよい。 The power terminals 207a and 207b are provided as separate members from the first main electrode 203 and the second main electrode 202, respectively, and are electrically connected to the first main electrode 203 and the second main electrode 202 through the bonding material 206, respectively. Described as connected. However, it is not limited to such a structure, and the power terminal 207a and the first main electrode 203 may be integrally formed. Similarly, the power terminal 207b and the second main electrode 202 may be integrally formed.
　パワー端子２０７ａ，２０７ｂと第３主電極２０９の間の接続・固定方法、およびパワー端子２０７ａ，２０７ｂとバスバ２０７Ｐ，２０７Ｎの間の接続・固定方法は、ねじ止めによるものとして説明したが、この他にも、溶接したり、はんだなどの接合材によって接合したりする方法によっても実現可能である。バスバ２０７Ｐ，２０７Ｎを、それぞれパワー端子２０７ａ，２０７ｂに接続・固定するものであれば、これらの方法に限られない。 The connection / fixation method between the power terminals 207a, 207b and the third main electrode 209 and the connection / fixation method between the power terminals 207a, 207b and the bus bars 207P, 207N have been described as being screwed. Moreover, it is realizable also by the method of welding or joining with joining materials, such as solder. As long as the bus bars 207P and 207N are respectively connected and fixed to the power terminals 207a and 207b, they are not limited to these methods.
　封止剤２０５としてトランスファーモールド法やコンプレッション法でエポキシなどの熱硬化性樹脂を使用し、半導体モジュール２０８，２０８Ｗ１，２０８Ｗ２，２０８Ａの外装を成形することが望ましいが、ＰＰＳやゲルなどを使用してもよい。また、接合材２０６には、はんだなど、電気的に導通できるものを用いる。 It is desirable to use a thermosetting resin such as epoxy as a sealant 205 by a transfer molding method or a compression method to mold the exterior of the semiconductor modules 208, 208W1, 208W2, 208A, but using PPS, gel, etc. Also good. In addition, as the bonding material 206, a material that can be electrically connected, such as solder, is used.
　第１主電極２０３、第２主電極２０２、第３主電極、半導体素子２１０の封止に、磁性体材料や高誘電率材料を用いれば、第１主電極２０３、第２主電極２０２、第３主電極、半導体素子２１０の間に生じる容量結合を高めることができる。その結果、電力変換装置２０１、３０１、４０１、５０１の全体のインダクタンスを、さらに低減することができる。 If a magnetic material or a high dielectric constant material is used for sealing the first main electrode 203, the second main electrode 202, the third main electrode, and the semiconductor element 210, the first main electrode 203, the second main electrode 202, Capacitive coupling generated between the three main electrodes and the semiconductor element 210 can be enhanced. As a result, the overall inductance of the power conversion devices 201, 301, 401, and 501 can be further reduced.
　半導体素子２１０は、接合材２０６で直接、第１主電極２０３、第２主電極２０２に接続しているとして説明したが、半導体素子２１０と第１主電極２０３の間、あるいは半導体素子２１０と第２主電極２０２の間に、銅や銅モリブデンからなる導電性の物質を介して間に挟んで、半導体素子２１０を接続してもよい。 Although the semiconductor element 210 has been described as being directly connected to the first main electrode 203 and the second main electrode 202 by the bonding material 206, the semiconductor element 210 is connected between the semiconductor element 210 and the first main electrode 203 or between the semiconductor element 210 and the second main electrode 203. The semiconductor element 210 may be connected between the two main electrodes 202 with a conductive substance made of copper or copper molybdenum interposed therebetween.
　絶縁材は樹脂などからなる絶縁シートやセラミクスからなる絶縁基板などが挙げられる。また冷却器ＲＧへの接合方法としては、はんだや蝋材などの直接接合やグリースなどの間接接合する方法がある。冷却器ＲＧは空冷でも水冷でもよい。 Examples of the insulating material include an insulating sheet made of resin and an insulating substrate made of ceramic. In addition, as a method of joining to the cooler RG, there are a method of direct joining such as solder or wax material or indirect joining such as grease. The cooler RG may be air-cooled or water-cooled.
　本発明の第７実施形態において説明した変形例１および変形例２は、その他の第８、第９実施形態に対しても適用可能である。すなわち、１個のアームに対応する半導体モジュール２０８，２０８Ａの代わりに、２個のアーム回路が１つにパッケージされた半導体モジュール２０８Ｗ１，２０８Ｗ２を利用することが可能である。また、２個以上のアーム回路を１個にパッケージした半導体モジュールを使用することも可能である。 Modification 1 and Modification 2 described in the seventh embodiment of the present invention can be applied to the other eighth and ninth embodiments. That is, instead of the semiconductor modules 208 and 208A corresponding to one arm, the semiconductor modules 208W1 and 208W2 in which two arm circuits are packaged in one can be used. It is also possible to use a semiconductor module in which two or more arm circuits are packaged.
　上述した実施形態では、２つのアームに対応する２ｉｎ１パワー半導体モジュールの場合を示したが、６つのアームに対応して、１部品で３相コンバータ装置のすべての相を構成することができる６ｉｎ１パワー半導体モジュールなどの構成であってもよい。 In the above-described embodiment, the case of a 2-in-1 power semiconductor module corresponding to two arms is shown. However, a 6-in-1 power capable of configuring all phases of a three-phase converter device with one component corresponding to six arms. The configuration may be a semiconductor module or the like.
　本発明の第９実施形態は、その他の第７実施形態、およびその変形例１，２、また第８実施形態に対しても適用可能である。すなわち、上アームおよび下アームの接続点の電位を出力するための第３主電極２０９に加えて、上下アーム回路のＰ側、およびＮ側のそれぞれに電気的に接続される第３主電極を設けてもよい。 The ninth embodiment of the present invention can also be applied to the other seventh embodiment, its modifications 1 and 2, and the eighth embodiment. That is, in addition to the third main electrode 209 for outputting the potential at the connection point of the upper arm and the lower arm, the third main electrode electrically connected to the P side and the N side of the upper and lower arm circuits, respectively. It may be provided.
　以上、本発明の実施形態について説明したが、これらの実施形態は本発明の理解を容易にするために記載された単なる例示に過ぎず、本発明は当該実施形態に限定されるものではない。本発明の技術的範囲は、上記実施形態で開示した具体的な技術事項に限らず、そこから容易に導きうる様々な変形、変更、代替技術なども含むものである。 As mentioned above, although embodiment of this invention was described, these embodiment is only the mere illustration described in order to make an understanding of this invention easy, and this invention is not limited to the said embodiment. The technical scope of the present invention is not limited to the specific technical matters disclosed in the above-described embodiment, but includes various modifications, changes, alternative techniques, and the like that can be easily derived therefrom.
　本出願は、２０１３年６月２４日に出願された日本国特許願第２０１３－１３１７１３号に基づく優先権を主張しており、この出願の全内容が参照により本明細書に組み込まれる。 This application claims priority based on Japanese Patent Application No. 2013-131713 filed on June 24, 2013, the entire contents of which are incorporated herein by reference.
　本願発明では、プラス側平板形状部、マイナス側平板形状部、及び出力側平板形状部と、第１半導体素子、及び第２半導体素子の主面が略平行となるように配置されるので、導電部材の間の容量結合、および導電部材と半導体素子との間の容量結合を増大させることができ、電力変換装置全体に存在するインダクタンスを低減することが可能となる。 In the present invention, the plus-side flat plate-shaped portion, the minus-side flat plate-shaped portion, and the output-side flat plate-shaped portion are arranged so that the main surfaces of the first semiconductor element and the second semiconductor element are substantially parallel. The capacitive coupling between the members and the capacitive coupling between the conductive member and the semiconductor element can be increased, and the inductance existing in the entire power conversion device can be reduced.
　１，２１　バスバ部
　２，２２ａ，２２ｂ　パワーモジュール部
　３　支持基板
　４，７，１０，２０７Ｎ，２０７Ｐ　バスバ
　４ａ，７ａ，１０ａ　平板形状部
　４ｂ，７ｂ，１０ｂ　導電部
　４ｃ，１０ｃ　ブラケット
　５　第１半導体素子
　６，９　接続線
　８　第２半導体素子
　２３ａ，２３ｂ　支持基板
　２４，２５，２６，２７　封止剤
　２４ａ，２４ｂ，２５ａ，２５ｂ，２６ａ，２６ｂ，２７ａ，２７ｂ　樹脂
　２９　コンデンサ
　１０１，１０２，１０３，１０４，１０５，１０６，２０１，３０１，４０１，５０１　電力変換装置
　２０２　第２主電極
　２０３　第１主電極
　２０５　封止剤
　２０６　接合材
　２０７ａ，２０７ｂ　パワー端子（第１主端子部、第２主端子部）
　２０８，２０８Ｒ，２０８Ｌ，２０８ＡＲ，２０８ＡＬ，２０８Ｗ１，２０８Ｗ２　半導体モジュール
　２０９，２０９Ａ　第３主電極
　２１０　半導体素子
　２２１，２２２　連結金具
　２３５　絶縁体
　ＲＧ　冷却器 DESCRIPTION OF SYMBOLS 1,21 Bus bar part 2,22a, 22b Power module part 3 Support board | substrate 4,7,10,207N, 207P Bus bar 4a, 7a, 10a Flat plate part 4b, 7b, 10b Conductive part 4c, 10c Bracket 5 1st semiconductor element 6, 9 Connection line 8 Second semiconductor element 23a, 23b Support substrate 24, 25, 26, 27 Sealant 24a, 24b, 25a, 25b, 26a, 26b, 27a, 27b Resin 29 Capacitor 101, 102, 103, 104 , 105, 106, 201, 301, 401, 501 Power converter 202 Second main electrode 203 First main electrode 205 Sealant 206 Bonding material 207a, 207b Power terminal (first main terminal portion, second main terminal portion)
208, 208R, 208L, 208AR, 208AL, 208W1, 208W2 Semiconductor module 209, 209A Third main electrode 210 Semiconductor element 221, 222 Connecting bracket 235 Insulator RG Cooler

Claims (17)

  1. 　上アームを構成する第１半導体素子と、
    　下アームを構成する第２半導体素子と、
    　前記上アームにプラス電位を供給するプラス側導電部材と、
    　前記下アームにマイナス電位を供給するマイナス側導電部材と、
    　前記上アームと前記下アームとの接続点の電位を出力する出力側導電部材と、
    　を備え、
    　前記プラス側導電部材は、半導体素子の主面に対して略平行となるように配置されるプラス側平板形状部を有し、
    　前記マイナス側導電部材は、前記主面に対して略平行となるように配置されるマイナス側平板形状部を有し、
    　前記出力側導電部材は、前記半導体素子の主面に対して略平行となるように配置される出力側平板形状部を有すること
    　を特徴とする電力変換装置。     A first semiconductor element constituting an upper arm;
    A second semiconductor element constituting a lower arm;
    A positive-side conductive member that supplies a positive potential to the upper arm;
    A negative conductive member for supplying a negative potential to the lower arm;
    An output-side conductive member that outputs a potential at a connection point between the upper arm and the lower arm;
    With
    The plus side conductive member has a plus side flat plate-shaped portion arranged so as to be substantially parallel to the main surface of the semiconductor element,
    The negative side conductive member has a negative side flat plate-shaped portion disposed so as to be substantially parallel to the main surface,
    The output-side conductive member has an output-side flat plate-shaped portion disposed so as to be substantially parallel to the main surface of the semiconductor element.
  2. 　請求項１に記載の電力変換装置であって、
    　前記プラス側平板形状部は、前記第１半導体素子の主面の全体に対して重複するように配置されること、もしくは、
    　前記マイナス側平板形状部は、前記第２半導体素子の主面の全体に対して重複するように配置されること、
    の少なくとも１つが成立するように前記プラス側平板形状部と前記マイナス側平板形状部とが配置されていること
    を特徴とする電力変換装置。     The power conversion device according to claim 1,
    The plus side flat plate-shaped portion is disposed so as to overlap with the entire main surface of the first semiconductor element, or
    The minus side flat plate-shaped portion is disposed so as to overlap the entire main surface of the second semiconductor element;
    The power conversion apparatus is characterized in that the plus-side flat plate-shaped portion and the negative-side flat plate-shaped portion are arranged so that at least one of the following holds.
  3. 　請求項１または請求項２のいずれかに記載の電力変換装置であって、
    　前記第１半導体素子の一端側と前記第２半導体素子の一端側が接続され、
    　前記プラス側導電部材は、前記第１半導体素子の他端側と接続され、
    　前記マイナス側導電部材は、前記第２半導体素子の他端側に接続されること
    を特徴とする電力変換装置。     The power conversion device according to claim 1 or 2,
    One end side of the first semiconductor element and one end side of the second semiconductor element are connected,
    The positive-side conductive member is connected to the other end side of the first semiconductor element;
    The power conversion apparatus, wherein the minus side conductive member is connected to the other end side of the second semiconductor element.
  4. 　請求項１～請求項３のいずれか１項に記載の電力変換装置であって、
    　前記出力側導電部材は、前記第１半導体素子、及び前記第２半導体素子の、少なくとも一方の主面全体に対して重複するように配置されること
    を特徴とする電力変換装置。     The power conversion device according to any one of claims 1 to 3,
    The power conversion device, wherein the output-side conductive member is disposed so as to overlap with the entire main surface of at least one of the first semiconductor element and the second semiconductor element.
  5. 　請求項１～請求項４のいずれか１項に記載の電力変換装置であって、
    　前記プラス側平板形状部、前記マイナス側平板形状部、及び前記出力側平板形状部を、樹脂にて封止すること
    を特徴とする電力変換装置。     The power conversion device according to any one of claims 1 to 4,
    The power conversion device, wherein the plus side flat plate portion, the minus side flat plate shape portion, and the output side flat plate shape portion are sealed with resin.
  6. 　請求項５に記載の電力変換装置であって、
    　前記プラス側導電部材と前記マイナス側導電部材との間を接続するコンデンサを更に備え、
    　前記プラス側平板形状部、前記マイナス側平板形状部、及び前記出力側平板形状部に加え、前記コンデンサを前記樹脂にて封止すること
    を特徴とする電力変換装置。     The power conversion device according to claim 5,
    A capacitor for connecting between the plus side conductive member and the minus side conductive member;
    In addition to the plus side flat plate portion, the negative side flat plate portion, and the output side flat plate portion, the capacitor is sealed with the resin.
  7. 　請求項１～請求項６のいずれか１項に記載の電力変換装置であって、
    　前記第１半導体素子と前記第２半導体素子とを前記主面とは反対側の面で支持する支持基板を更に備え、
    　前記プラス側導電部材、前記マイナス側導電部材、及び前記出力側導電部材は、それぞれ前記支持基板に直接的に固定するための固定面を有し、
    　更に、
    　　前記第１半導体素子は、前記プラス側導電部材の前記固定面に設置され、
    　　前記第２半導体素子は、前記出力側導電部材の前記固定面に設置され、
    　前記支持基板の少なくとも一部と、前記固定面、及び前記第１半導体素子、前記第２半導体素子を樹脂にて封止すること
    を特徴とする電力変換装置。     The power conversion device according to any one of claims 1 to 6,
    A support substrate for supporting the first semiconductor element and the second semiconductor element on a surface opposite to the main surface;
    The positive side conductive member, the negative side conductive member, and the output side conductive member each have a fixing surface for fixing directly to the support substrate,
    Furthermore,
    The first semiconductor element is installed on the fixed surface of the plus side conductive member,
    The second semiconductor element is installed on the fixed surface of the output-side conductive member,
    At least a part of the support substrate, the fixing surface, the first semiconductor element, and the second semiconductor element are sealed with resin.
  8. 　請求項１に記載の電力変換装置であって、
    　アームは、
    　　前記半導体素子と、
    　　前記半導体素子に前記主面で接続される第１主電極と、
    　　前記半導体素子に前記主面とは反対側の面で接続される第２主電極と、
    　を有する半導体モジュールからなり、
    　各アーム内で、前記第１主電極には、前記第２主電極よりも高電位の電位が印加され、
    　複数の半導体モジュールは、上下アーム回路を形成するように直列に接続されており、
    　前記プラス側導電部材、前記マイナス側導電部材、前記出力側導電部材のいずれかの一部を構成する第３主電極は、少なくとも前記第１主電極または前記第２主電極に平行する部位が垂直方向に重なる部分を有するように、前記半導体モジュールの冷却面と反対側に配置されること
    を特徴とする電力変換装置。     The power conversion device according to claim 1,
    The arm
    The semiconductor element;
    A first main electrode connected to the semiconductor element at the main surface;
    A second main electrode connected to the semiconductor element on a surface opposite to the main surface;
    Comprising a semiconductor module having
    Within each arm, the first main electrode is applied with a higher potential than the second main electrode,
    The plurality of semiconductor modules are connected in series so as to form upper and lower arm circuits,
    The third main electrode constituting a part of any of the plus side conductive member, the minus side conductive member, and the output side conductive member has at least a portion parallel to the first main electrode or the second main electrode. The power conversion device, wherein the power conversion device is disposed on a side opposite to a cooling surface of the semiconductor module so as to have a portion overlapping in a direction.
  9. 　請求項８に記載の電力変換装置であって、
    　前記第３主電極は、前記複数のアームの間を、少なくとも前記第１主電極または前記第２主電極に平行してまたがるように配置されること
    を特徴とする電力変換装置。     The power conversion device according to claim 8, wherein
    The power converter according to claim 1, wherein the third main electrode is disposed so as to straddle between the plurality of arms in parallel with at least the first main electrode or the second main electrode.
  10. 　請求項８または請求項９のいずれかに記載の電力変換装置であって、
    　前記第３主電極は、１つないし複数の前記半導体素子と垂直方向に重なるように配置されること
    を特徴とする電力変換装置。     The power conversion device according to claim 8 or 9, wherein
    The power converter according to claim 3, wherein the third main electrode is disposed so as to overlap the one or more semiconductor elements in a vertical direction.
  11. 　請求項８～請求項１０のいずれか１項に記載の電力変換装置であって、
    　前記半導体モジュールは、外部と接続する第１主端子部および第２主端子部を更に有し、
    　前記第１主端子部および前記第２主端子部は、それぞれ前記第１主電極および前記第２主電極と電気的に接続され、共に前記半導体モジュールの前面に配置されていること
    を特徴とする電力変換装置。     The power conversion device according to any one of claims 8 to 10,
    The semiconductor module further includes a first main terminal portion and a second main terminal portion connected to the outside,
    The first main terminal portion and the second main terminal portion are electrically connected to the first main electrode and the second main electrode, respectively, and are both disposed on the front surface of the semiconductor module. Power conversion device.
  12. 　請求項８～請求項１０のいずれか１項に記載の電力変換装置であって、
    　前記半導体モジュールは、外部と接続する第１主端子部および第２主端子部を更に有し、
    　前記第１主端子部および前記第２主端子部は、それぞれ前記第１主電極および前記第２主電極と電気的に接続され、前記第１主端子部は、前記半導体モジュールの前面に配置され、前記第２主端子部は、前記半導体モジュールの後面に配置されていること
    を特徴とする電力変換装置。     The power conversion device according to any one of claims 8 to 10,
    The semiconductor module further includes a first main terminal portion and a second main terminal portion connected to the outside,
    The first main terminal portion and the second main terminal portion are electrically connected to the first main electrode and the second main electrode, respectively, and the first main terminal portion is disposed on the front surface of the semiconductor module. The second main terminal portion is disposed on the rear surface of the semiconductor module.
  13. 　請求項８～請求項１２のいずれか１項に記載の電力変換装置であって、
    　前記半導体モジュールは、金型成形で樹脂封止されること
    を特徴とする電力変換装置。     A power conversion device according to any one of claims 8 to 12,
    The power conversion device, wherein the semiconductor module is resin-sealed by molding.
  14. 　請求項１３に記載の電力変換装置であって、
    　前記第３主電極は、前記半導体モジュールの樹脂表面に面接地している部位を有すること
    を特徴とする電力変換装置。     The power conversion device according to claim 13,
    The power converter according to claim 3, wherein the third main electrode has a surface grounded to the resin surface of the semiconductor module.
  15. 　請求項１３に記載の電力変換装置であって、
    　前記半導体モジュールは、樹脂封止された少なくとも１つ以上の前記アームを有し、
    　前記第３主電極は、前記半導体モジュール内に樹脂封止されること
    を特徴とする電力変換装置。     The power conversion device according to claim 13,
    The semiconductor module has at least one or more arms sealed with resin,
    The third main electrode is resin-sealed in the semiconductor module.
  16. 　請求項８～請求項１５のいずれか１項に記載の電力変換装置であって、
    　前記半導体モジュールの前記冷却面が、絶縁材を介して冷却器に金属接合されること
    を特徴とする電力変換装置。     The power conversion device according to any one of claims 8 to 15,
    The power conversion device, wherein the cooling surface of the semiconductor module is metal-bonded to a cooler via an insulating material.
  17. 　請求項８～請求項１６のいずれか１項に記載の電力変換装置であって、
    　複数の第３主電極は、
    　　前記プラス側導電部材の一部を構成する、少なくとも１つの第３主電極と、
    　　前記マイナス側導電部材の一部を構成する、少なくとも１つの第３主電極と、
    　　前記出力側平板形状部の一部を構成する、少なくとも１つの第３主電極と、
    　から構成され、
    　前記複数の第３主電極は、前記第１主電極または前記第２主電極の上に平行して重なる部分を有するように配置されること
    を特徴とする電力変換装置。     The power conversion device according to any one of claims 8 to 16,
    The plurality of third main electrodes are
    At least one third main electrode constituting part of the positive side conductive member;
    At least one third main electrode constituting a part of the negative side conductive member;
    At least one third main electrode constituting a part of the output side plate-shaped portion;
    Consisting of
    The plurality of third main electrodes are arranged so as to have a portion overlapping in parallel with the first main electrode or the second main electrode.
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