WO2014206178A1 - 电源管理芯片的启动电路及电源管理芯片 - Google Patents

电源管理芯片的启动电路及电源管理芯片 Download PDF

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Publication number
WO2014206178A1
WO2014206178A1 PCT/CN2014/078912 CN2014078912W WO2014206178A1 WO 2014206178 A1 WO2014206178 A1 WO 2014206178A1 CN 2014078912 W CN2014078912 W CN 2014078912W WO 2014206178 A1 WO2014206178 A1 WO 2014206178A1
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Prior art keywords
circuit
power management
management chip
voltage
starting capacitor
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PCT/CN2014/078912
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English (en)
French (fr)
Inventor
张楠
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无锡华润上华半导体有限公司
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Priority to US14/901,482 priority Critical patent/US9954431B2/en
Publication of WO2014206178A1 publication Critical patent/WO2014206178A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters

Definitions

  • the present invention relates to a power management chip, and more particularly to a startup circuit of a power management chip and a power management chip.
  • the power management chip is a chip that manages the power of each module in the system. It generally uses an external resistor to achieve voltage reduction from high voltage and start of the chip.
  • FIG. 1 is a schematic diagram of a startup circuit of a conventional power management chip. As shown in FIG. 1, the alternating current is rectified by the rectifier 1 and filtered by the filter capacitor C1, and then connected to the power management chip 2 through the start resistor R1. The power management chip 2 is powered by the startup resistor R1 to charge the startup capacitor C2. When the startup capacitor C2 reaches the startup voltage, the power management chip 2 starts operating.
  • a problem with the above circuit is that the startup resistor R1 continues to consume power after the power management chip 2 starts operating.
  • a power management chip is also provided.
  • a startup circuit of a power management chip includes: a startup capacitor for connecting to a power source through an external resistor for charging; a switching circuit connected between the external resistor and the startup capacitor; and a voltage detection circuit for detecting The voltage on the starting capacitor is connected to the switching circuit to control the switching of the switching circuit; the voltage maintaining circuit is connected between the starting capacitor and the working circuit of the power management chip for working from the power management chip The circuit obtains a voltage for maintaining the startup capacitor; wherein the voltage detection circuit controls the switch circuit to open when detecting that the startup capacitor reaches a startup voltage of the power management chip.
  • the switching circuit includes an N-type junction field effect transistor Q1, NMOS transistors Q2 and Q3, and a PMOS transistor Q4;
  • the drain of the N-type junction field effect transistor Q1 is connected to the external power supply and the gate is connected to the reference ground;
  • the source of the N-type junction field effect transistor Q1 is connected to the drain of the NMOS transistor Q2 and the gate of the NMOS transistor Q3 through the first resistor network.
  • a diode connected to the drain of the NMOS transistor Q3 and the gate of the PMOS transistor Q4 through the second resistor network, and the source of the PMOS transistor Q4 through the diode D1; wherein the source of the N-type junction FET Q1 and the diode D1 Positive connection
  • the gate of the NMOS transistor Q2 is connected to the voltage detecting circuit, and receives the high and low level signals output by the voltage detecting circuit, and the source and the substrate of the NMOS transistors Q2 and Q3 are connected to the reference ground;
  • the source and the substrate of the PMOS transistor Q4 are connected to the cathode of the diode D1, and the drain is connected to the startup capacitor.
  • the voltage maintaining circuit includes a secondary inductor L1 and a diode D2 connected in series, wherein the secondary inductor L1 is coupled to the primary inductor of the working circuit in the power management chip for obtaining power from the operating circuit
  • the voltage of the starting capacitor C3 is maintained; the anode of the diode D2 is connected to the secondary inductor L1, and the cathode is connected to the starting capacitor.
  • a power management chip includes the above startup circuit.
  • a startup circuit of a power management chip includes: a startup capacitor for connecting to a power source through an external resistor for charging; a switching circuit connected between the external resistor and the startup capacitor; and a voltage maintaining circuit connected at startup And a working circuit between the capacitor and the power management chip for obtaining a voltage for maintaining the startup capacitor from the working circuit of the power management chip; wherein the power management chip detects that the startup capacitor reaches a startup voltage of the power management chip The switch circuit is controlled to be open.
  • the switching circuit includes an N-type junction field effect transistor Q1, NMOS transistors Q2 and Q3, and a PMOS transistor Q4;
  • the drain of the N-type junction field effect transistor Q1 is connected to the external power supply and the gate is connected to the reference ground;
  • the source of the N-type junction field effect transistor Q1 is connected to the drain of the NMOS transistor Q2 and the gate of the NMOS transistor Q3 through the first resistor network.
  • a diode connected to the drain of the NMOS transistor Q3 and the gate of the PMOS transistor Q4 through the second resistor network, and the source of the PMOS transistor Q4 through the diode D1; wherein the source of the N-type junction FET Q1 and the diode D1 Positive connection
  • the gate of the NMOS transistor Q2 is connected to the voltage detecting circuit of the power management chip for detecting the voltage on the starting capacitor, and receives the high and low level signals output by the voltage detecting circuit, and the source of the NMOS transistors Q2 and Q3.
  • the substrate is connected to the reference ground;
  • the source and the substrate of the PMOS transistor Q4 are connected to the cathode of the diode D1, and the drain is connected to the startup capacitor.
  • the voltage maintaining circuit includes a secondary inductor L1 and a diode D2 connected in series, wherein the secondary inductor L1 is coupled to the primary inductor of the working circuit in the power management chip for obtaining power from the operating circuit
  • the voltage of the starting capacitor C3 is maintained; the anode of the diode D2 is connected to the secondary inductor L1, and the cathode is connected to the starting capacitor.
  • a power management chip includes a voltage detecting circuit and the foregoing starting circuit, and the voltage detecting circuit is configured to detect whether a starting capacitor reaches a starting voltage of the power management chip.
  • the starting circuit and the power management chip can turn off the connection between the external power source and the starting capacitor after the working circuit of the power management chip is started, thereby reducing power consumption.
  • the circuit structure is also very simple, and does not increase the area of the power management chip.
  • FIG. 1 is a schematic diagram of a startup circuit of a conventional power management chip
  • FIG. 2 is a block diagram of a startup circuit of a power management chip according to an embodiment
  • FIG. 3 is a schematic diagram of a startup circuit of the power management chip of the embodiment shown in FIG.
  • the startup circuit 10 includes a switching circuit 100, a voltage detecting circuit 200, a starting capacitor C3, and a voltage maintaining circuit 300.
  • the switch circuit 100 is connected between the external resistor R2 and the start capacitor C3.
  • the voltage detecting circuit 200 is for detecting the voltage on the starting capacitor C3, and is connected to the switching circuit 100 to control the switching of the switching circuit 100. Specifically, the voltage detecting circuit 200 controls the switching circuit 100 to open when detecting that the starting capacitor C3 reaches the starting voltage of the power management chip.
  • the voltage maintaining circuit 300 is connected between the starting capacitor C3 and the operating circuit 20 of the power management chip for obtaining the voltage for maintaining the starting capacitor C3 from the operating circuit 20 of the power management chip.
  • the voltage detecting circuit 200 may not belong to the starting circuit but as part of the power management chip.
  • the starting capacitor C3 when the starting capacitor C3 reaches the starting voltage of the power management chip, it is detected by the voltage detecting circuit 200, and the voltage detecting circuit 200 controls the switching circuit 100 to be disconnected. At this time, the external power source cannot continue to pass through the external resistor R2. The capacitor C3 is activated to charge, and the external resistor R2 no longer consumes power. At the same time, since the working circuit 20 of the power management chip has started to operate, there is power supply, and the voltage maintaining circuit 300 obtains the voltage for maintaining the starting capacitor C3 from the working circuit 20, thereby ensuring the normal operation of the working circuit 20.
  • FIG. 3 it is a schematic diagram of the startup circuit of the embodiment shown in FIG. 2.
  • the switching circuit 100 includes an N-type junction field effect transistor (N-JFET) Q1, NMOS transistors Q2 and Q3, and a PMOS transistor Q4.
  • N-JFET N-type junction field effect transistor
  • the drain of the N-type junction field effect transistor Q1 is connected to an external power supply and a gate connection reference ground.
  • the source of the N-type junction field effect transistor Q1 is connected to the drain of the NMOS transistor Q2 and the gate of the NMOS transistor Q3 through the first resistor network 110, and the drain of the NMOS transistor Q3 and the PMOS transistor Q4 are connected through the second resistor network 120.
  • the gate and the source of the PMOS transistor Q4 are connected through a diode D1, wherein the source of the N-type junction field effect transistor Q1 is connected to the anode of the diode D1.
  • the first resistor network 110 and the second resistor network 120 can obtain a desired resistance value by a series-parallel or varistor of a fixed resistor.
  • the gate of the NMOS transistor Q2 is connected to the voltage detecting circuit 200, and receives a high-low level signal output from the voltage detecting circuit 200.
  • the source and substrate of the NMOS transistors Q2 and Q3 are connected to a reference ground.
  • the source and the substrate of the PMOS transistor Q4 are connected to the cathode of the diode D1, and the drain is connected to the startup capacitor C3.
  • the diode D1 can prevent the body diode from being forward-biased in the PMOS transistor Q4, and is used to prevent the voltage of the starting capacitor C3 from dropping too fast.
  • the voltage maintaining circuit 300 includes a secondary inductor L1 and a diode D2 connected in series, wherein the secondary inductor L1 is coupled to a primary inductor (not shown) of the working circuit in the power management chip for maintaining power from the operating circuit. Start the voltage of capacitor C3.
  • the anode of the diode D2 is connected to the secondary inductor L1, and the cathode is connected to the starting capacitor C3 for preventing the starting capacitor C3 from discharging the inductor L1.
  • the voltage detecting circuit 200 is a conventional circuit in the field, and can implement voltage detection and high and low level signal output by using a chip, which will not be described herein.
  • the gate of the NMOS transistor Q2 is initially at a low level, and the voltage on the startup capacitor C3 is zero.
  • the drain of the N-type junction field effect transistor Q1 starts to be powered up, since the gate of the NMOS transistor Q2 is at a low level, the NMOS transistor Q2 is in an off state, and the NMOS transistor Q3 is in an on state, and the gate of the PMOS transistor Q4 is turned on. Extremely low level, PMOS tube Q4 is turned on. The current charges the starting capacitor C3 through the N-type junction field effect transistor Q1, the diode D1, and the PMOS transistor Q4, and the voltage thereon gradually increases.
  • the voltage detecting circuit 200 outputs a signal to provide a high level for the gate of the NMOS transistor Q2, thereby opening the NMOS transistor Q2 to output a low level.
  • the NOMS tube Q3 When the NOMS tube Q3 is turned off, the NOMS tube Q3 outputs a high level for turning off the PMOS transistor Q4 for ending the charging state of the starting capacitor C3, the voltage of the starting capacitor C3 stops rising, and the starting circuit is turned off. , reducing the power consumption of the startup circuit.
  • the startup process is completed, the system starts to work, and the voltage on the startup capacitor C3 begins to drop.
  • N-type junction field effect transistor Q1, NMOS transistors Q2 and Q3, and PMOS transistor Q4 can also be replaced by other high voltage tubes, such as a high voltage depletion tube, an LDMOS tube, and the like.
  • the above circuit can turn off the connection between the external power source and the starting capacitor after the working circuit of the power management chip is started, thereby reducing power consumption.
  • the circuit structure is also very simple, and does not increase the area of the power management chip.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

一种电源管理芯片的启动电路（10），包括：启动电容（C3），用于通过外置电阻（R2）与电源连接以进行充电；开关电路（100），连接在所述外置电阻（R2）与启动电容（C3）之间；电压检测电路（200），用于检测所述启动电容（C3）上的电压，并与所述开关电路（100）连接控制开关电路（100）的通断；电压维持电路（300），连接在启动电容（C3）和电源管理芯片的工作电路之间，用于从所述电源管理芯片的工作电路获取维持启动电容（C3）的电压；其中所述电压检测电路（200）在检测到启动电容（C3）到达所述电源管理芯片的启动电压时，控制所述开关电路（100）断路；以及一种包含上述启动电路（10）的电源管理芯片。在电源管理芯片的工作电路启动后关断外部电源与启动电容连接，能够减少电能消耗。

Description

电源管理芯片的启动电路及电源管理芯片
【技术领域】
本发明涉及电源管理芯片，特别是涉及一种电源管理芯片的启动电路和一种电源管理芯片。
【背景技术】
电源管理类芯片是对系统中各个模组进行用电管理的芯片。其一般都采用外置电阻实现从高压取电完成降压及芯片的启动。图1是一种传统的电源管理类芯片的启动电路原理图。如图1所示，交流电经过整流器1整流、经过滤波电容C1滤波后，通过启动电阻R1连接至电源管理芯片2。电源管理芯片2通过启动电阻R1取电，为启动电容C2充电。当启动电容C2达到启动电压时，电源管理芯片2开始工作。
上述电路存在的问题是，启动电阻R1在电源管理芯片2开始工作后，仍然在持续地消耗电能。
【发明内容】
基于此，有必要提供一种能够在电源管理芯片开始工作后切断外置电阻供电以减少电能消耗的电源管理芯片的启动电路。
此外，还提供一种电源管理芯片。
一种电源管理芯片的启动电路，包括：启动电容，用于通过外置电阻与电源连接以进行充电；开关电路，连接在所述外置电阻与启动电容之间；电压检测电路，用于检测所述启动电容上的电压，并与所述开关电路连接控制开关电路的通断；电压维持电路，连接在启动电容和电源管理芯片的工作电路之间，用于从所述电源管理芯片的工作电路获取维持启动电容的电压；其中，所述电压检测电路在检测到启动电容到达所述电源管理芯片的启动电压时，控制所述开关电路断路。
在其中一个实施例中，所述开关电路包括N型结型场效应管Q1、NMOS管Q2和Q3以及PMOS管Q4； N型结型场效应管Q1的漏极连接外部电源、栅极连接参考地；N型结型场效应管Q1的源极通过第一电阻网络连接NMOS管Q2的漏极和NMOS管Q3的栅极、通过第二电阻网络连接NMOS管Q3的漏极和PMOS管Q4的栅极、以及通过二极管D1连接PMOS管Q4的源极；其中N型结型场效应管Q1的源极与二极管D1的正极连接； NMOS管Q2的栅极与所述电压检测电路连接，接收电压检测电路输出的高低电平信号，NMOS管Q2和Q3的源极和衬底都连接参考地； PMOS管Q4的源极和衬底都连接二极管D1的负极，漏极连接启动电容。
在其中一个实施例中，电压维持电路包括串联的次级电感线圈L1和二极管D2，其中次级电感线圈L1与电源管理芯片中的工作电路的初级电感线圈耦合，用于从工作电路中获得电能维持启动电容C3的电压；二极管D2的正极与次级电感线圈L1连接、负极与启动电容连接。
一种电源管理芯片，包括上述启动电路。
一种电源管理芯片的启动电路，包括：启动电容，用于通过外置电阻与电源连接以进行充电；开关电路，连接在所述外置电阻与启动电容之间；电压维持电路，连接在启动电容和电源管理芯片的工作电路之间，用于从所述电源管理芯片的工作电路获取维持启动电容的电压；其中，所述电源管理芯片在检测到启动电容到达所述电源管理芯片的启动电压时控制所述开关电路断路。
在其中一个实施例中，所述开关电路包括N型结型场效应管Q1、NMOS管Q2和Q3以及PMOS管Q4； N型结型场效应管Q1的漏极连接外部电源、栅极连接参考地；N型结型场效应管Q1的源极通过第一电阻网络连接NMOS管Q2的漏极和NMOS管Q3的栅极、通过第二电阻网络连接NMOS管Q3的漏极和PMOS管Q4的栅极、以及通过二极管D1连接PMOS管Q4的源极；其中N型结型场效应管Q1的源极与二极管D1的正极连接； NMOS管Q2的栅极用于与所述电源管理芯片中的检测所述启动电容上的电压的电压检测电路连接，接收电压检测电路输出的高低电平信号，NMOS管Q2和Q3的源极和衬底都连接参考地； PMOS管Q4的源极和衬底都连接二极管D1的负极，漏极连接启动电容。
在其中一个实施例中，电压维持电路包括串联的次级电感线圈L1和二极管D2，其中次级电感线圈L1与电源管理芯片中的工作电路的初级电感线圈耦合，用于从工作电路中获得电能维持启动电容C3的电压；二极管D2的正极与次级电感线圈L1连接、负极与启动电容连接。
一种电源管理芯片，包括电压检测电路和前述的启动电路，所述电压检测电路用于检测启动电容是否到达所述电源管理芯片的启动电压。
上述启动电路和电源管理芯片能够在电源管理芯片的工作电路启动后关断外部电源与启动电容连接，减少电能消耗。同时电路结构也很简单，不会增加电源管理芯片的面积。
【附图说明】
图1为传统的电源管理芯片的启动电路原理图；
图2为一实施例的电源管理芯片的启动电路模块图；
图3是图2所示实施例的电源管理芯片的启动电路原理图。
【具体实施方式】
如图2所示，为一实施例的电源管理芯片的启动电路模块图。该启动电路10包括开关电路100、电压检测电路200、启动电容C3以及电压维持电路300。开关电路100连接在外置电阻R2和启动电容C3之间。电压检测电路200用于检测启动电容C3上的电压，并与开关电路100连接控制开关电路100的通断。具体地，是电压检测电路200在检测到启动电容C3到达所述电源管理芯片的启动电压时，控制开关电路100断路。电压维持电路300连接在启动电容C3和电源管理芯片的工作电路20之间，用于从所述电源管理芯片的工作电路20获取维持启动电容C3的电压。其中电压检测电路200也可以不属于启动电路，而是作为电源管理芯片的一部分。
基于上述电路，当启动电容C3到达电源管理芯片的启动电压时，被电压检测电路200检测到，并且电压检测电路200控制开关电路100断路，此时，外部电源将不能继续通过外置电阻R2对启动电容C3进行充电，外置电阻R2不再消耗电能。同时，由于电源管理芯片的工作电路20已经开始工作，会有电源供电，电压维持电路300从工作电路20获得维持启动电容C3的电压，从而保证工作电路20的正常工作。
如图3所示，为图2所示实施例的启动电路原理图。
开关电路100包括一个N型结型场效应管（N-JFET）Q1、NMOS管Q2和Q3以及PMOS管Q4。N型结型场效应管Q1的漏极连接外部电源、栅极连接参考地。N型结型场效应管Q1的源极通过第一电阻网络110连接NMOS管Q2的漏极和NMOS管Q3的栅极、通过第二电阻网络120连接NMOS管Q3的漏极和PMOS管Q4的栅极、以及通过二极管D1连接PMOS管Q4的源极，其中N型结型场效应管Q1的源极与二极管D1的正极连接。
第一电阻网络110和第二电阻网络120可以通过固定电阻的串并联或者变阻器获得所需阻值。
NMOS管Q2的栅极与电压检测电路200连接，接收电压检测电路200输出的高低电平信号。NMOS管Q2和Q3的源极和衬底都连接参考地。
PMOS管Q4的源极和衬底都连接二极管D1的负极，漏极连接启动电容C3。当N型结型场效应管Q1源端电压降低到小于启动电容C3的电压时，二极管D1可以防止PMOS管Q4出现体二极管正偏导通现象，用于防止启动电容C3的电压下降过快。
电压维持电路300包括串联的次级电感线圈L1和二极管D2，其中次级电感线圈L1与电源管理芯片中的工作电路的初级电感线圈（图未示）耦合，用于从工作电路中获得电能维持启动电容C3的电压。二极管D2的正极与次级电感线圈L1连接、负极与启动电容C3连接，用于防止启动电容C3对电感L1放电。
电压检测电路200为本领域常规电路，可以采用芯片实现电压检测及高低电平信号输出，在此不赘述。
基于上述电路，简述工作原理如下。
NMOS管Q2的栅极初始为低电平，启动电容C3上的电压为0。当N型结型场效应管Q1的漏极开始上电，由于NMOS管Q2的栅极为低电平，则NMOS管Q2处于关断状态，NMOS管Q3处于导通状态，则PMOS管Q4的栅极为低电平，PMOS管Q4导通。电流经过N型结型场效应管Q1、二极管D1、PMOS管Q4对启动电容C3充电，其上的电压逐渐增大。
随着启动电容C3的电压升高达到启动电压，电压检测电路200会输出一个信号，为NMOS管Q2的栅极提供一个高电平，从而打开NMOS管Q2，使其输出一个低电平，用于关断NOMS管Q3，则NOMS管Q3输出高电平，用于关断PMOS管Q4，用于结束对启动电容C3的充电状态，则启动电容C3的电压会停止上升，启动电路被关断，降低了启动电路的功耗。同时启动过程完成，系统开始工作，启动电容C3上的电压开始下降。
当系统电路开始工作后，依靠次级电感线圈L1为启动电容C3提供能量。
可以理解，上述的N型结型场效应管Q1、NMOS管Q2和Q3以及PMOS管Q4的还可以采用其他的高压管来替代，例如高压耗尽管、LDMOS管等。
可以理解，将上述启动电路集成到电源管理芯片中即可让该电源管理芯片能够在启动后关断外部电源对启动电容的充电，减少电能消耗。
上述电路能够在电源管理芯片的工作电路启动后关断外部电源与启动电容连接，减少电能消耗。同时电路结构也很简单，不会增加电源管理芯片的面积。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (8)

  1. 一种电源管理芯片的启动电路，包括：
    启动电容，用于通过外置电阻与电源连接以进行充电；
    开关电路，连接在所述外置电阻与启动电容之间；
    电压检测电路，用于检测所述启动电容上的电压，并与所述开关电路连接控制开关电路的通断；
    电压维持电路，连接在启动电容和电源管理芯片的工作电路之间，用于从所述电源管理芯片的工作电路获取维持启动电容的电压；
    其中，所述电压检测电路在检测到启动电容到达所述电源管理芯片的启动电压时，控制所述开关电路断路。
  2. 根据权利要求1所述的电源管理芯片的启动电路，其特征在于，所述开关电路包括N型结型场效应管Q1、NMOS管Q2和Q3以及PMOS管Q4；
    N型结型场效应管Q1的漏极连接外部电源、栅极连接参考地；N型结型场效应管Q1的源极通过第一电阻网络连接NMOS管Q2的漏极和NMOS管Q3的栅极、通过第二电阻网络连接NMOS管Q3的漏极和PMOS管Q4的栅极、以及通过二极管D1连接PMOS管Q4的源极；其中N型结型场效应管Q1的源极与二极管D1的正极连接；
    NMOS管Q2的栅极与所述电压检测电路连接，接收电压检测电路输出的高低电平信号，NMOS管Q2和Q3的源极和衬底都连接参考地；
    PMOS管Q4的源极和衬底都连接二极管D1的负极，漏极连接启动电容。
  3. 根据权利要求1所述的电源管理芯片的启动电路，其特征在于，电压维持电路包括串联的次级电感线圈L1和二极管D2，其中次级电感线圈L1与电源管理芯片中的工作电路的初级电感线圈耦合，用于从工作电路中获得电能维持启动电容C3的电压；二极管D2的正极与次级电感线圈L1连接、负极与启动电容连接。
  4. 一种电源管理芯片，包括如权利要求1所述的启动电路。
  5. 一种电源管理芯片的启动电路，包括：
    启动电容，用于通过外置电阻与电源连接以进行充电；
    开关电路，连接在所述外置电阻与启动电容之间；
    电压维持电路，连接在启动电容和电源管理芯片的工作电路之间，用于从所述电源管理芯片的工作电路获取维持启动电容的电压；
    其中，所述电源管理芯片在检测到启动电容到达所述电源管理芯片的启动电压时控制所述开关电路断路。
  6. 根据权利要求5所述的电源管理芯片的启动电路，其特征在于，所述开关电路包括N型结型场效应管Q1、NMOS管Q2和Q3以及PMOS管Q4；
    N型结型场效应管Q1的漏极连接外部电源、栅极连接参考地；N型结型场效应管Q1的源极通过第一电阻网络连接NMOS管Q2的漏极和NMOS管Q3的栅极、通过第二电阻网络连接NMOS管Q3的漏极和PMOS管Q4的栅极、以及通过二极管D1连接PMOS管Q4的源极；其中N型结型场效应管Q1的源极与二极管D1的正极连接；
    NMOS管Q2的栅极用于与所述电源管理芯片中的检测所述启动电容上的电压的电压检测电路连接，接收电压检测电路输出的高低电平信号，NMOS管Q2和Q3的源极和衬底都连接参考地；
    PMOS管Q4的源极和衬底都连接二极管D1的负极，漏极连接启动电容。
  7. 根据权利要求5所述的电源管理芯片的启动电路，其特征在于，电压维持电路包括串联的次级电感线圈L1和二极管D2，其中次级电感线圈L1与电源管理芯片中的工作电路的初级电感线圈耦合，用于从工作电路中获得电能维持启动电容C3的电压；二极管D2的正极与次级电感线圈L1连接、负极与启动电容连接。
  8. 一种电源管理芯片，包括电压检测电路和如权利要求5所述的启动电路，所述电压检测电路用于检测启动电容是否到达所述电源管理芯片的启动电压。
PCT/CN2014/078912 2013-06-25 2014-05-30 电源管理芯片的启动电路及电源管理芯片 WO2014206178A1 (zh)

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