WO2014205845A1 - Procédé de configuration, procédé d'allègement et système pour mise en miroir de mémoire dans un système numa, et nœud principal - Google Patents

Procédé de configuration, procédé d'allègement et système pour mise en miroir de mémoire dans un système numa, et nœud principal Download PDF

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Publication number
WO2014205845A1
WO2014205845A1 PCT/CN2013/078508 CN2013078508W WO2014205845A1 WO 2014205845 A1 WO2014205845 A1 WO 2014205845A1 CN 2013078508 W CN2013078508 W CN 2013078508W WO 2014205845 A1 WO2014205845 A1 WO 2014205845A1
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Prior art keywords
node
memory
mirroring
target node
target
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PCT/CN2013/078508
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English (en)
Chinese (zh)
Inventor
张斌
卢广
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2013/078508 priority Critical patent/WO2014205845A1/fr
Priority to CN201380000684.9A priority patent/CN103649923B/zh
Publication of WO2014205845A1 publication Critical patent/WO2014205845A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

Definitions

  • the present invention relates to the field of information technology, and in particular, to a non-uniform memory access NUMA system memory mirror configuration method, a method, a system, and a master node.
  • the Non-Uniform Memory Access (NUMA) system maintains a single operating system copy of the Symmetric Multi-Processor architecture, a simple application programming model, and easy-to-manage features.
  • the scalability of the Massive Parallel Processing mode can effectively expand the scale of the system.
  • stability, availability and serviceability are key to competitiveness.
  • Memory mirroring is an important guarantee for memory stability, availability, and serviceability. It can achieve memory error recovery and is the most powerful memory fault tolerance tool. However, after memory mirroring, the amount of NUMA system memory is halved, which causes the memory image in NUMA system to lose too much memory space.
  • the embodiment of the invention provides a non-uniform memory access NUMA system memory mirror configuration method, a lifting method, a system and a master node.
  • an embodiment of the present invention provides a NUMA system memory mirroring configuration method, where the method includes:
  • the master node of the NUMA system receives a node memory mirroring instruction, and the node memory mirroring instruction carries the identifier of the target node and the memory mirroring mode information;
  • the memory mirroring mode information is used to indicate that the target node is configured as a central processor memory mirroring mode.
  • the memory mirroring mode information is used to indicate that the target node is configured as a central processor memory mirroring mode.
  • the memory address addressing mode of the target node is cross-addressing.
  • the method further includes:
  • the memory address information of the target node is sent to an operating system of the NUMA system.
  • an embodiment of the present invention provides a method for releasing a memory image of a NUMA system, where the method includes:
  • the master node of the NUMA system receives the node mirroring instruction for releasing the node; the master node releases the memory mirror of the mirroring node according to the identifier of the image-removing node carried in the node mirroring instruction; The memory address is contiguous.
  • the master node is After the image of the unmirrored node carried in the node mirroring instruction is released, the memory mirror of the unmirrored node is released, and the method further includes:
  • the master node sends the memory address information of each node to an operating system of the NUMA system.
  • an embodiment of the present invention provides a NUMA system, where the NUMA system includes a primary node and a target node, and the primary node is configured to receive a node memory mirroring instruction, where the node memory mirroring instruction carries the target node. Identification and memory mirroring mode information;
  • the master node is configured to configure a memory mirror of the target node according to the identifier of the target node and the memory mirror mode information; wherein, the memory address of the target node is continuous.
  • the memory mirroring mode information is used to indicate that the target node is configured as a central processor memory mirroring mode.
  • the memory mirroring mode information is used to indicate that the target node is configured as a central processor memory mirroring mode.
  • the first or second possible implementation manner of the third aspect in a third possible implementation manner, is cross-addressing.
  • the master node is further configured to receive a node memory mirroring instruction
  • the master node is further configured to: cancel the memory mirror of the unmirrored node according to the identifier of the unmirrored node carried in the node storage mirroring instruction; wherein, the releasing The mirror node is at least one of the target nodes.
  • an embodiment of the present invention provides a primary node of a NUMA system, where the primary node includes a receiving unit and a configuration unit;
  • the receiving unit is configured to receive a node memory mirroring instruction, where the node memory mirroring instruction carries an identifier of the target node and memory mirroring mode information;
  • the configuration unit is configured to configure a memory image of the target node according to the identifier of the target node and the memory mirror mode information received by the receiving unit, where the memory address of the target node is continuous.
  • the memory mirroring mode information is used to indicate that the target node is configured as a central processor memory mirroring mode.
  • the memory mirroring mode information is used to indicate that the target node is configured as a central processor memory mirroring mode.
  • the first or second possible implementation manner of the fourth aspect in a third possible implementation manner, is cross-addressing.
  • the master node further includes a releasing unit, and the receiving unit is further configured to receive a node memory mirroring instruction
  • the releasing unit is configured to cancel the memory mirroring of the image-removing node according to the identifier of the image-removing node carried in the node-free mirroring instruction received by the receiving unit; wherein the image-removing node is in the target node At least one of them.
  • an embodiment of the present invention provides a non-transitory computer readable storage medium, where the non-volatile computer readable storage medium stores computer instructions, when NUMA When the master node of the system executes the computer instructions, it implements:
  • node memory mirroring instruction carries the identifier of the target node and the memory mirroring mode information
  • the memory mirroring mode information is used to indicate that the target node is configured as a central processor memory mirroring mode.
  • the memory mirroring mode information is used to indicate that the target node is configured as a central processor memory mirroring mode.
  • the master node receives the node memory mirroring instruction, and the node memory mirroring instruction carries the identifier of the target node. And the memory mirroring mode information, the master node configures the memory mirror of the target node according to the identifier of the target node and the memory mirroring mode information, and implements a memory mirror with granularity of a single node, thereby effectively solving the memory mirroring in the NUMA system. The problem of losing too much memory space.
  • Figure 1 is a schematic diagram of a NUMA system structure
  • 2 is a schematic structural diagram of a NUMA node
  • 3 is a flow chart of a NUMA system node memory mirroring method
  • FIG. 4 is a schematic diagram of a memory mirroring mode between central processors of a NUMA system node;
  • FIG. 5 is a schematic diagram of a memory mirroring mode in a central processor of a NUMA system node;
  • FIG. 6 is a schematic diagram of memory cross-addressing in a central processor of a NUMA system node; Schematic diagram of memory cross-addressing between central processors of system nodes;
  • Figure 8 is a schematic diagram of node selection interface of NUMA system;
  • Figure 9 is a schematic structural diagram of a node controller
  • Figure 10 is a flow chart of the method for releasing the memory mirroring of the NUMA system node
  • Figure 11 is a schematic diagram showing the structure of the master node of the NUMA system
  • Figure 12 is another schematic diagram of the main node of the NUMA system.
  • NUMA Non-Uniform Memory Access
  • Any central processor of any node can access all memory addresses of this node and non-local nodes. Thereby greatly improving parallelism.
  • the central processor is divided into multiple nodes, each of which is allocated local memory.
  • the central processor in all nodes can access the full physical memory of the NUMA system.
  • the NUMA system consists of four nodes, each of which is 10. 11, 12 and 13.
  • Each node includes two central processors and one node controller.
  • the two central processors on the node are directly connected through a Quick Path Interconnect (QPI) link, and the two central processors on the node are connected to other nodes through the node controller.
  • QPI Quick Path Interconnect
  • the number of nodes and the number of central processors on the nodes are not limited to the present invention, and the links connected between the central processors are not limited to QPI links.
  • components such as memory are omitted on nodes 10, 11, 12, and 13, and a more detailed structure of the nodes will be described in detail below.
  • a master node also called a zero node, which can be loaded with a NUMA operating system.
  • the node 10 is used as a master node.
  • the node 10 includes central processing units 101 and 102, and the central processing units 101 and 102 are connected through a QPI link, and the central processing unit. 101 and 102 are connected to the node controller 103, and the node controller 103 is connected through the network
  • NI Network Interface
  • FIG. 2 provides a detailed structural diagram of the node 11 shown in FIG. 1.
  • the node 11 includes a central processing unit 111 and a central processing unit 112, and the central processing unit 111 and the central processing unit 112 are connected by a QPI link.
  • the central processor 111 and the central processing unit 112 are respectively linked to the node controller 113, which is connected to the NI of the node controller of the node 10, the node 12, and the node 13, respectively, by the NI.
  • the central processing unit 111 is connected to the memory controller 1111 and the memory controller 1112, respectively. In a specific implementation, the memory controller 1111 and the memory controller 1112 can be integrated in the central processor 111.
  • the central processing unit 112 is connected to the memory controller 1121 and the memory controller 1122, respectively.
  • the memory controller 1121 and the memory controller 1122 can be integrated.
  • the memory controllers 1111, 1112, 1121, and 1122 are respectively connected to the memory through a memory buffer.
  • the structure of the nodes 10, 12 and 13 in the NUMA system shown in FIG. 1 can be referred to FIG. 2 and will not be described again.
  • the NUMA system has a total memory space of 256GB.
  • the memory address range of node 10 is 0 to (64 GB-1 byte)
  • the memory address range of node 11 is 64 GB to (128 GB-1 byte)
  • the memory of node 12 The address range is 128GB to (192GB-1 byte)
  • the memory address of node 13 ranges from 192GB to (256GB-1 byte). That is, the memory addresses of nodes 10, 11, 12, and 13 are continuous. Therefore, when a node is selected for memory mirroring from the NUMA system shown in FIG. 1, since the memory address of each node is continuous, the memory mirroring configuration can be performed by the selected node controller, thereby implementing the node as Granular memory mirroring.
  • node 11 is selected as the target node, that is, memory mirroring is configured for node 11.
  • the specific steps include:
  • Step 301 The master node of the N medical system A receives a node memory mirroring instruction, where the node memory mirroring instruction carries the identifier of the target node and the memory mirroring mode information.
  • Step 302 The master node configures a memory mirror of the target node according to the identifier of the target node and the memory mirroring mode information.
  • the memory address of the target node is continuous.
  • a memory mirror maintains two identical pieces of data between two memory controllers within the same node.
  • the two memory controllers perform the same write operation, that is, the data is written into the memory controlled by the two memory controllers separately; and for the read operation request, only on the main memory controller. Execute, ie read only the main memory controller control In-memory data.
  • the memory mirroring mode includes Inter Socket Mirroring and Intra Socket Mirroring.
  • the inter-processor memory mirroring mode refers to two memory controllers that maintain two identical data on two different central processors on the same node.
  • the memory controller 1111 constituting the memory mirror relationship between the central processors is located on the central processing unit 111, and the memory controller 1121 is located on the central processing unit 112;
  • the memory controller 1112 of the memory mirror relationship between the central processing units is located on the central processing unit 111, and the memory controller 1122 is located on the central processing unit 112.
  • the primary node of the NUMA system according to the node memory mirroring instruction carries the identifier of the target node and the memory mirroring mode.
  • Configuring the memory mirror of the target node the information includes: the master node configuring the target node as a central processor according to the identifier of the target node and the memory mirror mode information carried by the node memory mirroring instruction Memory mirroring mode.
  • the memory mirror mode in the central processing unit means that two memory controllers that maintain two identical data are located on the same central processor of the same node.
  • the memory controller 1111 constituting the memory mirror relationship in the central processing unit is located on the central processing unit 111, and the memory controller 1112 is located on the central processing unit 111;
  • the memory controller 1121 of the memory mirror relationship between the central processing units is located on the central processing unit 112, and the memory controller 1122 is located on the central processing unit 112.
  • the master node of the NUMA system configures the memory mirror of the target node according to the identifier of the target node and the memory mirroring mode information carried by the node memory mirroring instruction, which specifically includes:
  • the master node configures the target node as a memory mirroring mode in the central processing unit according to the identifier of the target node and the memory mirroring mode information carried by the node memory mirroring instruction.
  • the node 11 is configured to perform the same memory by the two memory controllers that are mirrored. Data write operation.
  • the memory address addressing mode of the node 11 can be set to an inter-letter mode.
  • FIG. 6 a cross addressing method is shown in FIG. 6 , which is a cross addressing of a memory address of a memory controller inside the same central processing unit, that is, a memory controller 1111 of the central processing unit 111 and a memory of the memory controller 1112 .
  • the address is cross-addressed, and the memory addresses of the memory controller 1121 of the central processing unit 112 and the memory controller 1122 are cross-addressed.
  • the memory address of the node 11 ranges from 64 GB to (128 GB - 1 byte), and the memory space of each memory controller is 16 GB, which is on the central processing unit 111.
  • the memory controller 1111 and the memory controller 1112 have a memory address ranging from 64 GB to (96 GB-1 byte), and the memory address is cross-addressed with 256 bytes, and the memory controller 1121 and the memory controller 1122 on the central processing unit 112.
  • Figure 7 is the cross-addressing of the memory address of the memory controller between the central processors in the same node, that is, the central processing unit.
  • the memory addresses of the memory controllers 1111, 1112, 1121, and 1122 of the central processor 112 are both cross-addressed. Taking the memory space of the node 11 as 64 GB as an example, in the implementation of the present invention, the memory address range of the node 11 is 6408 to (128 GB-1 byte), and the memory address range is 6408 to (128 GB-1 byte).
  • the controllers 1111, 1112, 1121, and 1122 sequentially perform cross-addressing of memory addresses in 256 bytes.
  • An implementation of the memory mirroring configuration of the NUMA system in the embodiment of the present invention selects a node that needs to perform memory mirroring configuration from the user interface, and selects the node 11 to perform memory mirroring configuration as an example.
  • Node 11 is selected to determine the memory mirroring mode of node 11.
  • a memory mirroring instruction is issued through a baseboard management controller (Baseboard Management Controller), a basic output output system (BIOS), or an operating system (opera system sys, OS).
  • Baseboard Management Controller Basic output output system
  • BIOS basic output output system
  • OS operating system sys, OS
  • the target node is a node that performs memory mirroring, and is a node 11 in the embodiment of the present invention.
  • the memory mirroring mode information is used to indicate which memory mirror mode configuration is performed on the target node, that is, the node 11.
  • the memory mirroring mode includes a central processor inter-memory mirroring mode and a central processor in-memory mirroring mode.
  • the master node 10 configures a memory mirror of the target node according to the identifier of the target node and the memory mirror mode information carried by the node memory mirroring instruction.
  • the master node 10 receives the memory mirroring instruction, determines that the node 11 is the target node, and determines that the memory mirroring mode of the node 11 is the memory mirror in the central processing unit, and the central node 111 of the node 11 to the node 11 of the node 11 112 and node controller 113 are configured to implement node 11 memory mirroring.
  • the memory address cross registers in the central processor 111 and the central processing unit 112 are configured. Configuring the memory address cross register includes source address resolution (Source Addres s Decode) and target address resolution (Target Addres s Decode).
  • the memory controller 1111 and the memory controller 1112 are configured as a memory mirror mode in the central processing unit, and the memory controller 1111 is designated as a main memory controller, designating the memory controller 1112 as a slave memory controller; configuring the memory controller 1121 and the memory controller 1122 into a central processor memory mirror mode, and designating the memory controller 1121 as a master memory controller, The memory controller 1122 is designated as a slave memory controller.
  • the identification of the main memory controller 1111 is stored in the mirror register of the central processor 111, and the identification of the main memory controller 1121 is stored in the mirror register of the central processor 112.
  • the entries in the target list of source address resolution and destination address resolution are configured as 1111, 1121, 1111, 1121, and the number of loops depends on the number of entries in the target list.
  • the target in the Inte l central processor is usually used.
  • the list has 16 entries. Each cycle takes 2 entries, and the number of cycles is 8.
  • the target list can be an array and stored in the memory address cross-register.
  • the 1111 and 1121 in the target list are the identifiers of the main memory controllers 1111 and 1121 respectively.
  • the specific representation of the main memory controller is not here. Make a limit.
  • the memory controllers 1112 and 1122 function as slave memory controllers.
  • the memory space above the node 11 includes only the memory spaces of the memory controllers 1111 and 1121.
  • the memory space of node 11 is 64 GB, and it becomes 32 GB after memory mirroring configuration.
  • the node controller 113 When the memory mirroring configuration is performed on the node 11, the node controller 113 needs to be configured.
  • a structure of the node controller 113 is as shown in FIG. 9, including the system interface 1131-0. And 1131-1, for connecting to the central processing unit 111 and the central processing unit 112, respectively.
  • the Packet Di spatcher is used to forward the message.
  • the Remote Pipeliner 1133 is an engine for processing protocol transactions at the remote end.
  • the protocol transactions at the far end refer to protocol transactions entered from NI 1136_0, 1136-1, and 1136-2, where NI refers to The network interface previously described in the embodiment of the present invention.
  • the local pipeline (Loca 1 P ipe l ine ) 1134 is an engine for processing local protocol transactions, and the local protocol transactions refer to protocol transactions issued by the central processors 111 and 112.
  • Network On Chip 1135 is a switching network for the connection of remote pipeline 1133, local pipeline 1134, and NI 1136-0, 1136-1, and 1136-2.
  • the memory address cross register of the local pipeline 1134 needs to be configured. As shown in FIG. 7, before the node 11 turns on the memory mirror between the central processors, the memory address is cross-addressed between the central processors of the node 11, that is, the memory addresses are in the memory controllers 1111, 1112, and 1121. Cross-addressing is performed between 1122 and 1122. For each memory controller, a local pipeline is required as an example. Four local pipelines are required.
  • node 11 sets the memory mirror
  • the memory controllers 1111 and 1121 are the main memory controllers
  • the target list can be an array and stored in the memory address cross-register.
  • the 1111 and 1121 in the target list are the identifiers of the main memory controllers 1111 and 1121, respectively.
  • the specific representation of the main memory controller is not here. Make a limit.
  • the memory cross-addressing is performed between the four memory controllers of the node 11, four local pipelines are needed to correspond to the four memories on the node 11 respectively. Controller.
  • the memory mirroring configuration of the node 11 is completed, only two memory controllers accept the memory access transaction.
  • the local pipeline can be modified, and only two local pipelines are opened corresponding to the memory controllers 1111 and 1121, respectively, of course, the memory controller 1111 and The 1121 can also use multiple local pipelines for better performance.
  • the mirrored protected memory address range is reported to the NUMA operating system.
  • One implementation is to report the image protection to the operating system through the advanced configuration and power management interface (Advanced Conf igurat and Power Management Interface).
  • the memory address range that is, the memory address range of the node 11 master controllers 1111 and 1121, so that important data can be placed in the mirror-protected memory space.
  • the NUMA system node memory mirroring method can select a required node for memory mirroring according to requirements, and implement a memory mirror with granularity of nodes, thereby effectively solving the problem of excessive memory space of memory mirroring loss in the NUMA system, and increasing the problem.
  • the flexibility of the NUMA system memory mirroring configuration The master node of the NUMA system usually stores important information of the system. Therefore, the master node usually performs memory mirroring by default, which is not limited by the present invention.
  • the embodiment of the present invention provides a method for configuring a memory mirroring of a NUMA system. After performing a memory mirroring configuration on a NUMA system node, the memory mirroring of the node can be released as needed, as shown in FIG.
  • the master node of the NUMA system receives a node memory mirroring command
  • the master node performs the cancellation mirror according to the canceling the node memory mirroring instruction.
  • the identifier of the node is released from the memory mirror of the unmirrored node; wherein the unmirrored node is at least one of the target nodes.
  • the node 11 is used as the mirroring node, and the node 11 is used as the memory mirroring node.
  • the interface shown in FIG. 8 is still taken as an example.
  • the node is released by the baseboard management controller or the operating system.
  • the memory mirroring instruction, the master node 10 receives the node memory mirroring command.
  • the node memory mirroring command carries the identifier of the mirror node.
  • the unmirrored node is a node that needs to be unmapped from memory, in the embodiment of the present invention, node 11. When there are multiple nodes configured as memory mirroring, at least one node can be selected as the mirroring node.
  • the master node 10 releases the mirror image of the unmirrored node according to the identifier of the unmirrored node carried in the memory mirroring instruction.
  • the master node 10 configures the central processors 111, 112 of the node 11 and the node controller 113.
  • the method includes: canceling the identifiers of the main memory controllers 1111 and 1121 in the mirror register, modifying the source address resolution and the target address resolution of the node 11, and reconfiguring the memory space from the memory controllers 1112 and 1122 to the node in the memory mirror mode. 11 memory space. Since the node 11 is configured as the inter-processor node mirroring mode, the target list of source address resolution and destination address resolution is configured to be 1111 before the mirroring is released.
  • the number of loops depends on the number of entries in the target list. For example, in the Inte l central processor, there are 16 entries in the target list, and each loop needs to occupy 4 entries, and the number of loops is 4 times.
  • the target list can be an array and stored in the memory address cross register.
  • the 1111, 1112, 1121, and 1122 in the target list are respectively memory.
  • the identification of the controllers 1111, 1112, 1121, and 1122, and the specific representation of the identifier of the memory controller are not limited herein. In this way, the memory space of the memory controller 1112 and the memory controller 1122 can be reincorporated into the memory space of the node 11, thereby increasing the memory space of the NUMA system.
  • the main memory controllers 1111 and 1121 respectively open one local pipeline, and for the slave memory controllers 1112 and 1122, the local pipeline is not turned on. After the mirroring is released, the memory space of the four memory controllers 1111, 1112, 1121, and 1122 in node 11 enters the memory space of the NUMA system.
  • the circular queues of 1111, 1112, 1121, 1122, 1111, 1112, 1121, 1122 are written into the target list of the memory address cross register of the node controller 113, wherein the target list can be one.
  • the array is stored in the memory address cross-register, and the identifiers of the memory controllers 1111, 1112, 1121, and 1122 are respectively defined by the memory controllers 1111, 1112, 1121, and 1122, and the specific representation of the identifier of the memory controller is not limited herein.
  • the method for releasing the memory of the NUMA system provided by the embodiment of the present invention can perform the memory mirroring on the NUMA system with a single node as the granularity, and can flexibly release the memory space.
  • the method for mirroring the memory of the NUMA system of the above embodiment of the present invention can also be used at the center.
  • the addressing mode of the memory address in the node can also use the inter-processor cross-addressing method. That is, the addressing mode of the node memory mirroring mode and the node memory address can be freely combined, and the memory address in the node can also be used without the cross-addressing mode.
  • the configuration and cancellation of the memory mirroring mode in the central processing unit are not described again.
  • the embodiment of the present invention only gives an exemplary description.
  • the number of nodes configuring the node memory mirroring may be specifically determined according to actual needs, and the number of nodes for releasing the node memory mirroring may also be specifically determined according to requirements.
  • the master node 111 includes a receiving unit 1110 and a configuration unit 1111.
  • the receiving unit 1110 is configured to receive a node memory mirroring instruction, where the node memory mirroring instruction carries the identifier of the target node and the memory mirroring mode information.
  • the configuration unit 1111 is configured to use the target node received by the receiving unit 1111.
  • the identifier and the memory mirroring mode information configure a memory image of the target node; wherein, the memory address of the target node is continuous.
  • the configuration unit 1111 when the memory mirror mode information is used to indicate that the target node is configured as a central processor memory mirror mode, the configuration unit 1111 is configured to receive according to the The identifier of the target node and the memory mirroring mode information received by the unit 1110, and the memory mirroring of the target node, specifically include: the configuring unit 1111 is configured to use the node memory image received by the receiving unit The identifier of the target node and the memory mirroring mode information carried by the instruction configure the target node as a central processor memory mirroring mode.
  • the master node of the NUM A system shown in FIG. 11 is configured when the memory mirror mode information is used to indicate that the target node is configured as a central processor memory mirror mode.
  • the unit 1111 is configured to configure the memory mirror of the target node according to the identifier of the target node and the memory mirroring mode information received by the receiving unit 1110, and specifically includes: the configuring unit 1111 is configured to use, according to the receiving unit 1110, The received identifier of the target node and the memory mirror mode information configure the target node as a memory mirror mode in the central processing unit.
  • the memory address addressing mode of the target node can be cross-addressed.
  • the NUMA system provided by the embodiment of the present invention can implement the node memory mirroring configuration by referring to the method description of the node memory mirroring configuration in the foregoing embodiment, and details are not described herein again.
  • the number of the target nodes may be determined according to the number of system nodes and specific requirements, and may be one or multiple.
  • the NUMA system performs the node memory mirroring configuration, once the memory mirroring configuration is performed on the node, all the nodes need to perform the memory mirroring configuration, thereby halving the memory space of the NUMA system and affecting the performance of the NUMA system.
  • the NUMA system node memory mirroring method provided by the embodiment of the present invention can select a required node for memory mirroring according to requirements, and implement a memory mirror with granularity of a single node, thereby effectively solving the problem of excessive memory space of memory mirroring loss in the NUMA system, and increasing The flexibility of the NUMA system memory mirroring configuration.
  • the master node 110 further includes a releasing unit 1112. As shown in FIG. 12, the receiving unit 1110 is further configured to receive a node memory mirroring instruction.
  • the releasing unit 1112 is configured to cancel the memory mirroring of the mirroring node according to the identifier of the image-removing node carried by the releasing node memory mirroring instruction received by the receiving unit 1110.
  • the unmirrored node is at least one of the target nodes. That is, when there are multiple target nodes, the undo unit 1 1 12 can release the memory mirror of some nodes in the target node according to the node memory mirroring instruction. When the target node is one, the unmirror node is the target node.
  • the NUMA system provided by the embodiment of the present invention can implement the node memory image release by referring to the method description of the node memory image release in the foregoing embodiment, and details are not described herein again.
  • the NUMA system can be used as a granularity of a single node as needed to release the memory image of the node and release the node memory space.
  • the elements and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present invention.
  • a person skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and details are not described herein again.
  • the disclosed systems and methods can be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication through some interface, device or unit. Connections can be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separate, and the components displayed as the units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment scheme.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable non-volatile storage medium.
  • the medium includes instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing non-volatile storage medium includes: a medium that can store program codes, such as a USB flash drive, a removable hard disk, a read-only memory (ROM), a magnetic disk, or an optical disk.

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Abstract

La présente invention porte sur un procédé de configuration, un procédé d'allègement et un système pour mise en miroir de mémoire dans un système NUMA, et un nœud principal. Le procédé de configuration pour mise en miroir de mémoire dans un système NUMA comprend les opérations suivantes: un nœud principal dans un système NUMA reçoit une instruction de mise en miroir de mémoire de nœud, l'instruction de mise en miroir de mémoire de nœud véhiculant un identifiant d'un nœud cible et des informations de motif de mise en miroir de mémoire; et le nœud principal configure une mise en miroir de mémoire du nœud cible conformément à l'identificateur du nœud cible et aux informations de motif de mise en miroir de mémoire, l'adresse mémoire du nœud cible étant continue, pour qu'une mise en miroir de mémoire utilisant un seul nœud comme taille de particule soit réalisée, et le problème de trop forte consommation d'espace mémoire par la mise en miroir de mémoire dans le système NUMA soit effectivement résolu.
PCT/CN2013/078508 2013-06-29 2013-06-29 Procédé de configuration, procédé d'allègement et système pour mise en miroir de mémoire dans un système numa, et nœud principal WO2014205845A1 (fr)

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CN201380000684.9A CN103649923B (zh) 2013-06-29 2013-06-29 一种numa系统内存镜像配置方法、解除方法、系统和主节点

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