WO2019149031A1 - Procédé et appareil de traitement de données appliqués à un système de nœuds - Google Patents

Procédé et appareil de traitement de données appliqués à un système de nœuds Download PDF

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Publication number
WO2019149031A1
WO2019149031A1 PCT/CN2019/070388 CN2019070388W WO2019149031A1 WO 2019149031 A1 WO2019149031 A1 WO 2019149031A1 CN 2019070388 W CN2019070388 W CN 2019070388W WO 2019149031 A1 WO2019149031 A1 WO 2019149031A1
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Prior art keywords
data
node
processor
state
listening
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PCT/CN2019/070388
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English (en)
Chinese (zh)
Inventor
程永波
贺成洪
兰可嘉
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华为技术有限公司
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Publication of WO2019149031A1 publication Critical patent/WO2019149031A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/06—Management of faults, events, alarms or notifications
    • H04L41/0654—Management of faults, events, alarms or notifications using network fault recovery
    • H04L41/0663—Performing the actions predefined by failover planning, e.g. switching to standby network elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
    • H04L43/0811—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking connectivity
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
    • H04L43/0817—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking functioning

Definitions

  • the present application relates to the field of electronic technologies, and in particular, to a data processing method and apparatus applied to a node system.
  • CC-NUMA Cache Coherence Non-Uniform Memory Access
  • N node controller
  • All the processors on each node can have consistent access to the memory of all the processors in the system. Because of the different delays of accessing the memory in the node and other remote nodes, it is called CC-NUMA system.
  • a node In a CC-NUMA system, a node consists of several processors interconnected by node controllers. However, a node controller has limited processing power and limited bandwidth. Therefore, in order to alleviate the bandwidth pressure, the two-node controller is often used for cross-node expansion, that is, two node controllers of one node are respectively connected with two node controllers of another node to form two NC planes, two The NC plane shares the load.
  • the load sharing of the two planes here refers only to the performance load sharing. In fact, the two planes respectively process the services of their respective management scopes, and record the corresponding directory information, and there is no business intersection between them.
  • the embodiment of the present application provides a data processing method and device applied to a node system, so as to solve the system downtime problem when any node controller fails.
  • an embodiment of the present application provides a data processing method applied to a node system, where a node system includes multiple nodes, each of which includes two node controllers and at least one processor, where multiple nodes include a first node and a second node, the second node comprising a first node controller, comprising:
  • the first node controller sends a interception request to a processor in all nodes connected to the second node, the interception request is used to indicate that the processor in all the nodes connected to the second node determines the first according to the type of the interception request The state of the data;
  • the first node controller receives a listening response sent by the first target processor for the first data
  • the first target processor is a processor that caches the first data in a processor among all the nodes connected to the second node,
  • the listening response for the first data includes a state of the first data
  • the first node controller acquires the first data according to the state of the first data in the listening response
  • the first node controller sends the first data to the first node.
  • the service processed by the NC plane where the second node controller is located is transferred to another NC plane where the first node controller is located, and broadcast listening is performed. This allows the system to still perform normal data processing without downtime.
  • the state of the first data is an invalid state
  • the first data is included in the listening response, indicating that the first node has been changed in the other nodes in the system, and then the first node controller needs to be updated.
  • the first data is returned to the requesting party of the data access request, that is, the first node.
  • the state of the first data is a shared state
  • the first node controller obtains the first memory from the second node according to the shared state of the first data in the listening response.
  • One data is a shared state
  • the state of the first data is a shared state
  • the listening response does not include the first data, indicating that the first data is not changed in other nodes in the system, so the first node controller only needs to be from the inside.
  • the first node that retrieves the first data in the memory and returns it to the data access request is the first node.
  • the type of the interception request includes a shared listening request or an exclusive listening request .
  • an embodiment of the present application provides a data processing method applied to a node system, where a node system includes multiple nodes, each of which includes two node controllers and at least one processor, wherein multiple nodes include a second node, the second node comprising a second node controller, comprising:
  • the second node controller sends an exclusive listening request to the processor in all the nodes connected to the second node, the exclusive listening request is used to indicate the type of the processor in all the nodes connected to the second node according to the exclusive listening request Determining that the state of the second data is an invalid state;
  • the second node controller determines that the data cache directory of the second data managed by the second node controller is in an invalid state, and the data cache directory of the second data is in an invalid state indicating the number of processors in all nodes connected to the second node The status of the two data is invalid.
  • the second node controller resumes working, sending the exclusive listening broadcast, the second data cached in all other nodes can be invalidated, and only the second data in the internal memory is Effective, thereby restoring control of the second data.
  • the exclusive listening response further includes the second data; the second node controller further sends the second data to the internal memory of the second node, where the second data is used in the replacement The second data in the memory.
  • the exclusive listening response includes the second data, indicating that the other node in the system has changed the second data, then the second node controller needs to replace the latest second data in the internal memory. Second data so that the latest second data is saved in the internal memory
  • the multiple nodes further include a third node
  • the second node controller sends a interception request to a processor in all nodes connected to the second node, the interception request is used to indicate that the processor in all the nodes connected to the second node determines the second according to the type of the interception request The state of the data;
  • the second node controller acquires the second data according to the state of the second data in the listening response and sends the second data to the third node;
  • the second node controller records the state of the second data in a data cache directory of the second data.
  • the second node controller can also synchronously use the broadcast interception method to process the data access request, so that the system can also run normally before the directory invalidation is completed. .
  • a third aspect of the present application provides a data processing apparatus applied to a node system. Includes cache coherency protocol processor, memory, and communication interface.
  • the cache coherency protocol processor is coupled to the memory and communication interface, such as a cache coherency protocol processor that can be coupled to the memory and communication interface via a bus.
  • the communication interface is used to communicate with other devices.
  • the memory is used to store program code, directory data, and the like.
  • the cache coherency protocol processor is operative to perform any of the possible implementations described in the above aspects or aspects.
  • FIG. 1 is a schematic structural diagram of a data processing system applied to a node system according to an embodiment of the present application
  • FIG. 3 is a schematic flowchart of another data processing method applied to a node system according to an embodiment of the present application
  • FIG. 5 is a schematic structural diagram of a data processing apparatus applied to a node system according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another data processing apparatus applied to a node system according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another data processing apparatus applied to a node system according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another data processing apparatus applied to a node system according to an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a data processing system applied to a node system according to an embodiment of the present disclosure.
  • the nodes in the embodiments of the present application may include a server, a personal computer, an access network device, and a core network device.
  • the node system is an interconnected system composed of multiple nodes connected to each other.
  • the data processing system includes a plurality of nodes (FIG. 1 shows node 10 and node 20), wherein each node includes a plurality of processors (FIG. 1 shows that node 10 includes processor 101 and processor 102, node 20 A processor 201 and a processor 202) and two node controllers are included (FIG.
  • two node controllers of each node are respectively connected to two node controllers of another node to form two NC planes, and the two NC planes share the load.
  • the node controller 103 in the node 10 in FIG. 1 is connected to the node controller 203 in the node 20 to form an NC plane 00; the node controller 104 in the node 10 is connected to the node controller 204 in the node 20.
  • all processors on each node can perform consistent access to the internal memory of all processors in the system.
  • a data cache directory (Directory) is stored in each node, and the data in the node is recorded by the processor of other nodes, including the state of the recorded data. And location.
  • the data cache directory can be stored in a separate entity, in a node controller, or in other entities mentioned above.
  • the data processing system in the embodiment of the present application belongs to a dual NC plane processing system, and each of the two NC planes in each node processes a part of the services it is responsible for and records in the corresponding data cache directory, that is, two.
  • the services between the NC planes are independent and do not produce an intersection. Therefore, the corresponding node controller on one NC plane does not have a data cache directory of the service processed by another NC plane.
  • the embodiment of the present application is applicable to a scenario in which a node controller in a certain node fails but the system is not down, and the method for processing the data of the node controller that has not failed in the scenario and the faulty node are described.
  • FIG. 2 is a schematic flowchart diagram of a data processing method applied to a node system according to an embodiment of the present application. The method includes but is not limited to the following steps:
  • the second node controller in the second node fails, the administrator starts the hot removal process, and the system enters silence (ie, all processes are suspended.
  • the system enters silence (ie, all processes are suspended.
  • all services that should be processed by the NC plane 01 where the second node controller is located are configured to be processed by the NC plane 00 where the first node controller is located, thereby executing S201-S206.
  • the first node sends a data access request to the first node controller of the second node.
  • the first data is stored in the internal memory of the second node, and when the first processor of the first node wishes to cache the first data, thereby performing a read/write operation on the first data, a data access request for the first data is sent.
  • the data access request is used to request to acquire the first data.
  • the address information of the first data may be carried to indicate that the first data corresponding to the address information is desired to be obtained.
  • the data access request sent by the first node may be transparently transmitted by the first processor in the first node to the first node controller through the third node controller, that is, the third node controller does not parse the data for the first data.
  • the access request; the data access request sent by the first node may also be sent by the first processor to the third node controller, and the third node controller performs the operation of changing the destination address after the parsing, and the first data is managed.
  • the original NC plane 00 handles the data service with the last bit of all routing addresses being 0, and the NC plane 01 handles the data service with the last bit of all routing addresses being 1; however, because the second node controller fails, the routing
  • the data service whose last bit of the address is 0 is also configured to be processed by NC plane 01. S202.
  • the first node controller determines that the first data is not managed by the first node controller.
  • the first node controller Since in the dual NC system, the two node controllers of each node share the load, the first node controller stores the address information of the part of the data that is responsible for management, and the corresponding data cache directory exists.
  • the first node controller may determine, according to the address information of the first data, whether the first data is managed by itself. If it is managed by itself, the first node controller processes the data access request according to the data cache directory corresponding to the first data; if not managed by itself, the first node controller needs to adopt broadcast listening The method is processed, that is, S203 is executed.
  • the first node controller sends a interception request to a processor in all nodes connected to the second node.
  • the processors in all the nodes connected to the second node are all the processors in all other nodes except the second node in the system. That is, the first node controller initiates a broadcast snoop in the system.
  • the interception request is for indicating that the processor in all nodes connected to the second node determines the state of the first data according to the type of the interception request.
  • Different data access requests correspond to different listening requests. For example, when the data access request indicates that it is desired to share the first data, that is, the first data is not modified, the type of the interception request issued by the first node controller is a shared listening request; when the data access request is for the first data Indicates that it is possible to monopolize the first data, that is, it is possible to modify the first data, and then the type of the interception request issued by the first node controller is an exclusive listening request.
  • the processor in all nodes connected to the second node determines the state of the first data according to the type of the interception request.
  • the processor in the node connected to the second node may first query whether the first data is cached by itself. If the first data is not cached, the listening response that the first data does not exist may be fed back. If the first data is cached, the current state of the first data may be acquired, and then the state of the first data is determined in conjunction with the type of the interception request.
  • the processor in all the nodes connected to the second node determines that the state of the first data is the shared state according to the listening request and the current state of the first data. That is, if the interception request is a shared listening request, it may indicate that there is currently another processor that wishes to share the first data, and the first data cached in the processor in all nodes connected to the second node at this time is currently If the state is a shared state, then the user does not need to change and continues to be in the shared state; at this time, if the current state of the first data cached in the processor in all the nodes connected to the second node is exclusive, then the exclusive state needs to be monopolized. The state is changed to the shared state to support other processors to share the first data. After changing to the shared state, the processor in all nodes connected to the second node cannot modify the first data.
  • the processor in all nodes connected to the second node determines that the state of the first data is an invalid state according to the listening request and the current state of the first data. That is to say, if the interception request is an exclusive listening request, it may indicate that there are other processors currently wishing to monopolize the first data, and the first data cached in the processor in all the nodes connected to the second node is currently current.
  • the state whether it is a shared state or an exclusive state, needs to be modified to an invalid state, that is, the processor in all the nodes connected to the second node is no longer able to read/write the first data, and if it is necessary to read/write the first data, Then you need to request again from the first node controller.
  • the first target processor sends a listening response for the first data to the first node controller.
  • the first target processor is a processor in which a first data is cached in a processor among all nodes connected to the second node.
  • the first target processor after determining the state of the first data, transmits a listening response for the first data to the first node controller.
  • the listening response for the first data includes the status of the first data.
  • the processor that caches the first data may also send a listening response to the first node controller, but the listening response is used to indicate The first data does not exist.
  • the listening response for the first data further includes: buffering in the first target processor The first data. That is, it is possible for the first target processor to modify the first data, and then the first target processor needs to return its latest first data to the first node controller.
  • the first node controller acquires the first data according to the state of the first data in the listening response.
  • the first node controller directly responds from the interception Get the first data.
  • the first node controller can obtain the internal memory of the second node.
  • the first node controller may not record the data cache directory of the first data because the part of the service of the second node controller is temporarily processed.
  • the first node controller sends the first data to the first node.
  • the first node controller may acquire the first data from the listening response sent by the first target processor or the internal memory of the second node, and then send the first data to the first node. In response to a data access request.
  • sending the first data to the first node may be transparently transmitted to the first processor by the third node controller, or may be sent to the third node controller first, and the third node controller parses the target data. An operation such as a change in address, sent to the first processor.
  • FIG. 3 is a schematic flowchart diagram of another data processing method applied to a node system according to an embodiment of the present application. The method includes but is not limited to the following steps:
  • the second node controller sends an exclusive listening request to a processor in all nodes connected to the second node.
  • the processors in all the nodes connected to the second node are all the processors in all other nodes except the second node in the system. That is to say, after the new second node controller is replaced, the second node controller initiates broadcast exclusive listening in the system.
  • the exclusive listening request is for indicating that the processor in all the nodes connected to the second node determines that the state of the second data is an invalid state according to the type of the exclusive listening request.
  • S300 can also be included before S301:
  • the memory access controller sends an exclusive access request for the second data to the second node controller.
  • the DMA (Direct Memory Access) controller may start to traverse all the address information managed by the second node controller, and respectively send each address information for the management of the second node controller.
  • An exclusive access request for the data to trigger the second node controller to broadcast an exclusive listening request for data corresponding to each address information it manages.
  • the exclusive access request for the second data is sent to the second node controller to trigger the second node controller to execute S301.
  • the memory access controller can then read the next data and trigger a broadcast exclusive listening process for the data until the memory access controller manages the second node controller. All address information traversal ends.
  • the processor in all nodes connected to the second node determines that the state of the second data is an invalid state according to the type of the exclusive listening request.
  • the purpose of the exclusive listening request is to enable the first data cached in the processors in all the nodes connected to the second node to be in an invalid state, that is, all connected to the second node.
  • the processor in the node is no longer able to read/write the first data.
  • the second target processor sends an exclusive listening response for the second data to the second node controller.
  • the second target processor is a processor in which a second data is cached in a processor among all nodes connected to the second node.
  • the second target processor after determining the state of the second data, transmits an exclusive listening response for the second data to the second node controller.
  • the listening response for the second data includes the state of the second data being an invalid state.
  • the processor that caches the second data may also send an exclusive listening response to the second node controller, but the exclusive listening response is used in the exclusive listening response. Indicates that the second data does not exist.
  • the second node controller determines that the data cache directory of the second data managed by the second node controller is in an invalid state.
  • the data cache directory of the second data is in an invalid state indicating that the state of the second data in the second processor is an invalid state. That is, the second node controller invalidates the second data cached in all other nodes, and only the second data stored in its own internal memory is valid, thereby restoring the control of the second data.
  • the exclusive listening response for the second data further includes the second data cached in the second target processor, and the S303 further includes :
  • the second node controller sends the second data to the internal memory of the second node.
  • the second data in the exclusive listening response is used to replace the second data in the internal memory, that is, to store the latest second data in the internal memory of the second node.
  • the processor of the other node for example, the third node shown in FIG. 3
  • the second node The controller executes S306-S313.
  • the third node sends a data access request to the second node controller of the second node.
  • a data access request is used to request acquisition of the second data.
  • the second node controller sends a interception request to a processor in all nodes connected to the second node.
  • the S308 may further include S307:
  • the second node controller determines that the memory scan end notification sent by the memory access controller is not received.
  • the memory scan end notification is used to notify the second node controller that the data corresponding to each address information managed by the second node controller has been traversed and broadcast exclusive operation, that is, the memory of the node to which the second node controller belongs is indicated.
  • the data cache directory of all data managed by the two-node controller is invalid.
  • the second node controller After the second node controller receives the memory scan end notification sent by the memory access controller, the data processing is performed according to the data cache directory, and no broadcast snooping is performed. Therefore, before performing broadcast snooping in S308, it is necessary to confirm The memory scan end notification was not received.
  • the processor in all nodes connected to the second node determines the state of the second data according to the type of the interception request.
  • the third target processor sends a listening response for the second data to the second node controller.
  • a processor of the second data is cached in a processor of all nodes connected to the second node by the third target processor.
  • S309-S310 For the specific implementation method of S309-S310, refer to S204-S205, and details are not described herein again.
  • the second node controller acquires the second data according to the state of the second data in the listening response.
  • the second node controller sends the second data to the third node.
  • the second node controller records the state of the second data in a data cache directory of the second data.
  • the second node controller After processing the data access request for the second data, the second node controller records the state of the second data in the data cache directory of the second data. That is, the second node controller records the states of the nodes in which the second data is cached based on the feedback response of the feedback, and the state of the second data in the processors. For example, if the listening response returned by the processor 123 of a certain node A includes the state in which the second data is intercepted as the shared state, then the second node controller records "node A" in the data cache directory of the second data. Processor 123, shared state.”
  • the second node controller can also synchronously use the broadcast interception method to process the data access request, so that the system can also run normally before the directory invalidation is completed.
  • S301-S305 and S306-S313 can be executed at the same time without prioritization.
  • the data cache directory of all the data managed by the second node controller is in an invalid state, that is, the data cache directory of all the data managed by the second node controller is invalid, and then the second node controller performs data according to the data cache directory.
  • the data processing method for performing broadcast snooping is not performed again in S306-S313.
  • the second node controller determines that the data cache directory of all data managed by the node is invalid.
  • the method may be: receiving a memory scan end notification sent by the memory access controller, indicating that the data cache directory of all data managed by the second node controller in the node memory of the second node controller is in an invalid state.
  • the second node controller can be restored to the normal working state before the failure, and only needs to perform data processing according to the data cache directory recorded therein, without performing broadcast listening.
  • the data processing device applied to the node system includes hardware structures and/or software modules corresponding to the execution of the respective functions in order to implement the above functions.
  • the embodiments of the present application can be implemented in a combination of hardware or hardware and computer software in combination with the elements of the examples and algorithm steps described in the embodiments disclosed in the application. Whether a function is implemented in hardware or computer software to drive hardware depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the technical solutions of the embodiments of the present application.
  • the embodiment of the present application may perform the division of the function module or the function unit corresponding to the data processing device for the node system according to the above method example.
  • each function module or function unit may be divided according to each function, or two or more may be divided.
  • the functionality is integrated in a processing module or processing unit.
  • the above integrated modules or units can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules or units in the embodiments of the present application is schematic, and is only a logical function division. In actual implementation, there may be another division manner. Please see the specifics below.
  • FIG. 5 is a schematic structural diagram of a data processing apparatus applied to a node system according to an embodiment of the present application.
  • the apparatus can be used to implement the first node controller of the embodiment shown in Figure 2 above.
  • the device includes:
  • the receiving module 501 is configured to receive a data access request sent by the first node, where the data access request is used to request to acquire the first data;
  • the processing module 502 determines that the first data is not managed by the first node controller
  • a sending module 503 configured to send a listening request to a processor in all nodes connected to the second node, where the listening request is used to indicate a processor in all nodes connected to the second node Determining a state of the first data according to a type of the interception request;
  • the receiving module 501 is further configured to: receive a listening response sent by the first target processor for the first data, where the first target processor is a processor in all nodes connected to the second node a processor that caches the first data, the listening response for the first data includes a state of the first data;
  • the processing module 502 is further configured to: acquire the first data according to a state of the first data in the listening response;
  • the sending module 503 is further configured to: send the first data to the first node.
  • the state of the first data is an invalid state
  • the listening response for the first data further includes the first data
  • the processing module 502 is configured to: acquire the first data from the listening response according to the invalid state of the first data in the listening response.
  • the state of the first data is a shared state
  • the processing module 502 is configured to:
  • the type of the listening request includes a shared listening request or an exclusive listening request.
  • FIG. 6 is a schematic structural diagram of another data processing apparatus applied to a node system according to an embodiment of the present application.
  • the data processing apparatus 600 applied to the node system shown in FIG. 6 includes: a cache coherency protocol processor. 601 and communication interface 603, the cache coherency protocol processor 601 is configured to support information transmission between the data processing device 600 and other devices.
  • the cache coherency protocol processor 601 and the communication interface 603 are communicatively coupled, such as by a bus.
  • the data processing device 600 applied to the node system may also include a memory 602.
  • the memory 602 is configured to store program code and directory data for execution by the data processing apparatus 600, and the cache coherency protocol processor 601 is configured to execute the application code stored in the memory 602 to implement the first node provided by the embodiment shown in FIG. The action of the controller.
  • the memory 602 may include a volatile memory such as a random access memory (RAM); the memory 602 may also include a non-volatile memory such as a read-only memory (read- Only memory, ROM), flash memory, hard disk drive (HDD) or solid-state drive (SSD); the memory 602 may also include a combination of the above types of memories.
  • RAM random access memory
  • ROM read- Only memory
  • HDD hard disk drive
  • SSD solid-state drive
  • the memory 602 may also include a combination of the above types of memories.
  • a computer storage medium which can be used to store computer software instructions used by the first node controller in the embodiment shown in FIG. 2, and is configured to execute the first node in the foregoing embodiment.
  • the storage medium includes, but is not limited to, a flash memory, a hard disk, a solid state disk.
  • a computer program product is also provided.
  • the data processing method applied to the node system designed for the first node controller in the foregoing embodiment of FIG. 2 may be executed.
  • FIG. 7 is a schematic structural diagram of another data processing apparatus applied to a node system according to an embodiment of the present application.
  • the apparatus can be used to implement the second node controller of the embodiment shown in Figure 3 above.
  • the device includes:
  • the sending module 701 is configured to send, to the processor in all the nodes connected to the second node, an exclusive listening request, where the exclusive listening request is used to indicate that all the nodes connected to the second node are
  • the processor determines, according to the type of the exclusive listening request, that the state of the second data is an invalid state
  • the receiving module 702 is configured to receive, by the second target processor, an exclusive listening response for the second data, where the second target processor is cached in a processor in all nodes connected to the second node.
  • the processor of the second data, the listening response for the second data includes a state in which the second data is in an invalid state;
  • the processing module 703 is configured to determine that the data cache directory of the second data managed by the second node controller is in an invalid state, and the data cache directory of the second data is in an invalid state to indicate the second node The state of the second data in the processors in all of the connected nodes is in an invalid state.
  • the exclusive listening response further includes the second data
  • the sending module 701 is further configured to:
  • the multiple nodes further include a third node
  • the receiving module 702 is further configured to: receive a data access request sent by the third node, where the data access request is used to request to acquire the second data;
  • the sending module 701 is further configured to: send a listening request to a processor in all nodes connected to the second node, where the listening request is used to indicate all nodes connected to the second node
  • the processor determines a state of the second data according to a type of the interception request
  • the receiving module 702 is further configured to: receive a listening response sent by the third target processor for the second data, where the third target processor is in a processor among all nodes connected to the second node a processor that caches the second data, the listening response for the second data including a state of the second data;
  • the processing module 703 is further configured to: acquire the second data according to a state of the second data in the listening response, and send the second data to the third node; in the second data The state of the second data is recorded in a data cache directory.
  • the receiving module 702 is further configured to: receive, by the second node controller, the exclusive access request for the second data that is sent by the memory access controller;
  • the processing module 703 is further configured to: the second node controller determines that the memory scan end notification sent by the memory access controller is not received, and the memory scan end notification is used to indicate that the second node controller belongs to The data cache directory of all data managed by the second node controller in the node memory is in an invalid state.
  • the data processing apparatus applied to the node system in the above-described embodiment shown in FIG. 7 can be implemented by the data processing apparatus 800 applied to the node system shown in FIG.
  • FIG. 8 is a schematic structural diagram of another data processing apparatus applied to a node system according to an embodiment of the present application.
  • the data processing apparatus 800 applied to the node system shown in FIG. 8 includes: a cache coherency protocol processor. 801 and communication interface 803, the cache coherency protocol processor 801 is configured to support information transmission between the data processing device 800 and other devices.
  • the cache coherency protocol processor 801 and the communication interface 803 are communicatively coupled, such as by a bus.
  • the data processing device 800 applied to the node system may also include a memory 802.
  • the memory 802 is configured to store program code and directory data for execution by the data processing apparatus 800, and the cache coherency protocol processor 801 is configured to execute the application code stored in the memory 802 to implement the second node provided by the embodiment shown in FIG. The action of the controller.
  • the memory 802 may include a volatile memory such as a random access memory (RAM); the memory 802 may also include a non-volatile memory such as a read-only memory (read- Only memory, ROM), flash memory, hard disk drive (HDD) or solid-state drive (SSD); the memory 802 may also include a combination of the above types of memory.
  • RAM random access memory
  • ROM read- Only memory
  • HDD hard disk drive
  • SSD solid-state drive
  • the memory 802 may also include a combination of the above types of memory.
  • a computer storage medium which can be used to store computer software instructions used by the second node controller in the embodiment shown in FIG. 3, and is configured to execute the second node in the foregoing embodiment.
  • the storage medium includes, but is not limited to, a flash memory, a hard disk, a solid state disk.
  • a computer program product is also provided.
  • the data processing method applied to the node system designed for the second node controller in the foregoing embodiment of FIG. 3 may be executed.

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Environmental & Geological Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
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Abstract

Conformément à des modes de réalisation, la présente invention concerne un procédé et un appareil de traitement de données appliqués à un système de nœuds. Le procédé comprend les étapes suivantes : un premier contrôleur de nœud reçoit une demande d'accès à des données envoyée par un premier nœud, et détermine que des premières données ne sont pas gérées par le premier contrôleur de nœud ; le premier contrôleur de nœud envoie une demande d'écoute à des processeurs de tous les nœuds connectés à un second nœud ; le premier contrôleur de nœud reçoit une réponse d'écoute, en ce qui concerne les premières données, envoyée par un premier processeur cible, le premier processeur cible étant le processeur, dans les processeurs de tous les nœuds connectés au second nœud, mettant en cache les premières données ; et le premier contrôleur de nœud obtient, en fonction de l'état des premières données dans la réponse d'écoute, les premières données et envoie les premières données au premier nœud. Selon la présente solution, lorsqu'une défaillance se produit dans un second contrôleur de nœud, en transférant un service à un premier contrôleur de nœud sur un autre plan de commande numérique en vue d'un traitement, et en réalisant une écoute de diffusion, le système peut toujours traiter des données normalement sans tomber en panne.
PCT/CN2019/070388 2018-01-30 2019-01-04 Procédé et appareil de traitement de données appliqués à un système de nœuds WO2019149031A1 (fr)

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Citations (3)

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US20120311267A1 (en) * 2011-05-31 2012-12-06 Gaither Blaine D External cache operation based on clean castout messages
CN103870435A (zh) * 2014-03-12 2014-06-18 华为技术有限公司 服务器及数据访问方法
CN104899160A (zh) * 2015-05-30 2015-09-09 华为技术有限公司 一种缓存数据控制方法、节点控制器和系统

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120311267A1 (en) * 2011-05-31 2012-12-06 Gaither Blaine D External cache operation based on clean castout messages
CN103870435A (zh) * 2014-03-12 2014-06-18 华为技术有限公司 服务器及数据访问方法
CN104899160A (zh) * 2015-05-30 2015-09-09 华为技术有限公司 一种缓存数据控制方法、节点控制器和系统

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