WO2014169534A1 - 消除关机残影的电路及阵列基板 - Google Patents

消除关机残影的电路及阵列基板 Download PDF

Info

Publication number
WO2014169534A1
WO2014169534A1 PCT/CN2013/078706 CN2013078706W WO2014169534A1 WO 2014169534 A1 WO2014169534 A1 WO 2014169534A1 CN 2013078706 W CN2013078706 W CN 2013078706W WO 2014169534 A1 WO2014169534 A1 WO 2014169534A1
Authority
WO
WIPO (PCT)
Prior art keywords
terminal
switch unit
input
units
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2013/078706
Other languages
English (en)
French (fr)
Inventor
刘荣铖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Hefei BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US14/236,218 priority Critical patent/US9424796B2/en
Publication of WO2014169534A1 publication Critical patent/WO2014169534A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0245—Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a circuit and an array substrate for eliminating the afterimage of a shutdown. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the embodiment of the invention provides a circuit and an array substrate for eliminating the residual image of the shutdown, which can eliminate the residual image phenomenon generated by the display device after the shutdown.
  • a circuit for eliminating a residual image of a shutdown comprising a charging module and a discharging module;
  • the charging module is connected to the first voltage end for storing the charge under the control of the first voltage signal input by the first voltage terminal;
  • the discharging module is connected to the charging module and the second voltage terminal for supplying the charge stored by the charging module to the gate line when the power is turned off under the control of the second voltage signal input by the second voltage terminal.
  • the circuit further includes an input module, and the input module is connected to the discharge module, and is configured to output the second voltage signal to the second voltage terminal when the power is turned off.
  • the charging module includes at least one group of charging units, each of the charging units including a capacitor and a first switching unit;
  • the capacitor includes: a first electrode and a second electrode, wherein the first electrode of the capacitor is connected to a reference voltage terminal;
  • the first switching unit includes: a first control end, a first input end, and a first output end, wherein the first output end of the first switch unit is connected to the second electrode of the capacitor, the first switch unit The first input terminal is connected to the first control terminal.
  • the first control terminal of the first switching unit in each group of charging units is also connected to the first voltage terminal.
  • the charging module includes N sets of charging units, and the first output end of the first switching unit of the i-th charging unit is connected to the first input end of the first switching unit of the (i+1)th charging unit, A first input end of the first switching unit of the first group of charging units is connected to the first voltage terminal; the N is the number of the gate lines, and i is an integer greater than or equal to 1 and less than N.
  • the capacitance values of the first m capacitors are sequentially increased, and the capacitance values of the remaining capacitors are the same and greater than the capacitance values of the mth capacitor, wherein m is an integer greater than zero and less than N.
  • the discharge module includes a plurality of second switch units; wherein each second switch unit includes: a second control end, a second input end, and a second output end; second control of each second switch unit The end is connected to the second voltage end, the second output end of each second switch unit is respectively connected to a gate line, and the second input end of the at least two second switch units and the first one of the set of charging units The first output of the switch unit is connected, and the second input of the remaining second switch unit is respectively connected to the first output of the first switch unit of the other group of charging units.
  • each second switch unit includes: a second control end, a second input end, and a second output end; second control of each second switch unit The end is connected to the second voltage end, the second output end of each second switch unit is respectively connected to a gate line, and the second input end of the at least two second switch units and the first one of the set of charging units The first output of the switch unit is connected, and the second input of the remaining second switch unit is respectively connected to the first output of the first switch
  • the discharge module includes a plurality of second switch units
  • Each of the second switch units includes: a second control end, a second input end, and a second output end; the second control end of the jth second switch unit is connected to the second voltage end, the jth second switch unit The second input end is connected to the first output end of the first switch unit of the jth group of charging units, and the second output end of the jth second switch unit is connected to one of the gate lines, each of the The gate line is connected to one of the second switching units, and j is an integer greater than zero and less than or equal to N.
  • the discharge module further includes a plurality of third switch units
  • the third switching unit includes: a third control terminal, a third input terminal, and a third output terminal; wherein a third control terminal of the i-th third switching unit is connected to the second voltage terminal, the ith The third input end of the third switch unit is connected to the second output end of the i-th second switch unit, and the third output end of the i-th third switch unit and the first i+1 second switch unit The two outputs are connected.
  • an array substrate including the above-described circuit for eliminating shutdown afterimage.
  • the charging module of the circuit for eliminating the afterimage of the shutdown includes a plurality of capacitors, the first electrodes of all the capacitors are connected, and the first electrodes are electrically connected to the common electrode lines of the array substrate .
  • the effective relative areas of the first electrode and the second electrode of the first m of the plurality of capacitors are sequentially increased, and the effective relative areas of the first electrode and the second electrode of the remaining capacitors are equal. And greater than the effective relative area of the first electrode and the second electrode of the mth capacitor.
  • the embodiment of the present invention provides a circuit for eliminating the afterimage of the shutdown and the array substrate.
  • the circuit includes a charging module and a discharging module, and the charging module is configured to store a charge under the control of the first voltage signal input by the first voltage terminal.
  • the discharge module is configured to supply the charge stored by the charging module to the gate line when the power is turned off under the control of the second voltage signal input by the second voltage terminal; thus, when the power is off, the discharge module can charge the module under the control of the second voltage signal
  • the stored charge is supplied to the gate line to keep all the thin film transistors turned on, so that the residual charge stored in the liquid crystal capacitor is quickly released, eliminating the image sticking phenomenon caused by the liquid crystal display device after shutdown.
  • FIG. 1 is a block diagram of a circuit for eliminating a residual image of a shutdown according to an embodiment of the present invention
  • FIG. 2 is a block diagram of another circuit for eliminating a residual image of a shutdown according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a circuit for eliminating shutdown afterimages including a plurality of third switching units according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a circuit for eliminating a residual image after shutdown according to Embodiment 2 of the present invention
  • FIG. 6 is a schematic structural diagram of a capacitor according to an embodiment of the present invention.
  • the embodiment of the present invention provides a circuit for eliminating the afterimage of the shutdown.
  • the circuit includes a charging module 10 and a discharging module 20, wherein the charging module 10 is connected to the first voltage terminal VI.
  • the discharging module 20 is connected to the charging module 10 and the second voltage terminal V2 for the second voltage terminal V2
  • the input second voltage signal is controlled to supply the charge stored by the charging module 10 to the gate line when the power is turned off.
  • the second voltage signal input to the second voltage terminal may not be constant, which is not limited herein.
  • the second voltage signal input by the second voltage terminal V2 can be combined with the function of Xon (the control signal that turns all the thin film transistors on all lines when the circuit is turned off) in the prior art, that is, when the power is turned off.
  • the Xon function is turned on, and the discharge module 20 supplies the charge stored in the charging module 10 to the gate line under the control of the second voltage signal input by the second voltage terminal V2, so as to keep all the thin film transistors connected to the gate lines open.
  • the Xon function is turned off, and the discharge module 20 does not supply the charge stored by the charging module 10 to the gate line under the control of the second voltage signal input by the second voltage terminal V2.
  • the first voltage signal outputted by the first voltage terminal VI is determined to enable the opening of the thin film transistor connected to all the gate electrodes, which is not limited herein.
  • the Xon function, the first voltage terminal, the second voltage terminal, and the like may be integrated into the gate driving IC, or may be used alone, which is not limited herein.
  • the embodiment of the invention provides a circuit for eliminating the afterimage of the shutdown, comprising a charging module and a discharging module, wherein the charging module is configured to store a charge under the control of a first voltage signal input by the first voltage terminal, and the discharging module is used for At the second voltage terminal input, the second voltage signal is controlled under shutdown Supplying the charge stored by the charging module to the gate line; thus, when the power is off, the discharging module can supply the stored charge of the charging module to the gate line under the control of the second voltage signal, so as to keep all the thin film transistors turned on, thereby storing the liquid crystal in the liquid crystal The residual charge in the capacitor is quickly released, eliminating the image sticking phenomenon caused by the liquid crystal display device after shutdown.
  • the circuit for eliminating the afterimage of the shutdown may further include: an input module 30; the input module 30 is connected to the discharge module 20, and configured to output the second voltage when the power is turned off. Signaling to the second voltage terminal V2.
  • the Xon function module can be integrated into the input module 30.
  • the Xon function is turned on, and the input module 30 is controlled to input a second voltage signal to the second voltage terminal V2, thereby controlling the discharge module 20 to be The charge stored in the charging module 10 is supplied to the gate line.
  • the input module 30 can also input a second voltage signal to the second voltage terminal V2, but the second voltage signal cannot cause the discharge module 20 to provide the charge stored by the charging module 10. Give the grid line.
  • the charging module 10 includes at least one group of charging units, and each group of the charging units includes a capacitor and a first switching unit.
  • the capacitor includes: a first electrode 101 and a second electrode 102, and the first electrode 101 of the capacitor is connected to the reference voltage terminal V0.
  • the first switching unit includes a first control terminal 201, a first input terminal 202, and a first output terminal 203.
  • the first output terminal 203 of the first switching unit is connected to the second electrode 102 of the capacitor.
  • the first input terminal 202 of the first switching unit is connected to the first voltage terminal VI.
  • first control terminal 201 of the first switching unit can also be connected to the first voltage terminal VI, so that the first switching unit can be kept open all the time.
  • the number of the capacitors may be the same as or different from the number of the first switch units, and the specific number thereof may be set according to actual conditions, as long as the function of charge storage of the charging unit can be realized. This is not limited here. Further, the number of the charging units is not limited.
  • the discharging module 20 includes a plurality of second switching units.
  • Each of the second switch units includes: a second control terminal 301, a second input terminal 302, and a second output terminal 303; the second control terminal 301 of the second switch unit is coupled to the second voltage terminal V2, a second input end 302 of the second switching unit and a first input of the first switching unit
  • the output terminal 203 is connected, and the second output end 303 of the second switch unit is connected to a gate line, and each of the gate lines is connected to a second switch unit.
  • the second voltage signal outputted by the second voltage terminal V2 controls all the second switch units to be turned on when the Xon function is turned on.
  • the number of the second switching units is the number of gate lines. For example, a resolution is
  • the number of the first switch unit or the capacitor may be different from the number of the second switch unit, that is, may be the first output end 203 of the first switch unit and several second The second input end 302 of the switch unit is connected; of course, the number of the first switch unit or the capacitor may be the same as the number of the second switch unit, which is not limited herein, only each second The voltage output from the second output terminal 303 of the switching unit enables all of the thin film transistors on the gate line connected thereto to be opened.
  • the embodiment of the present invention provides a circuit for eliminating the afterimage of the shutdown.
  • the circuit includes: a plurality of capacitors d, C 2 ... C X , and a plurality of first switching units T and T1 2 .. .T1 X , and a plurality of second switching units T2 T2 2 , ⁇ 2 3 , ⁇ 2 4 ... ⁇ 2 ⁇ ; ⁇ is the number of gate lines, X is less than
  • Each of the capacitors includes: a first electrode 101 and a second electrode 102, and the first electrode 101 of the capacitor is connected to the reference voltage terminal V0.
  • Each of the first switching units includes: a first control terminal 201, a first input terminal 202, and a first output terminal 203; the first output terminal 203 of the first switching unit is connected to the second electrode 102 of the capacitor, A first control terminal 201 and a first input terminal 202 of a switching unit are connected to the first voltage terminal VI.
  • the first input terminal 202 and the first input terminal 202 are connected to the first voltage terminal VI, and the first output terminal 203 of the first first switching unit T1 j is connected to the second electrode 102 of the first capacitor d; the second first a first switch control terminal unit Tl 2 201 202 and a first input terminal connected to said first voltage terminal VI, first the second output terminal of the first switching unit 203 Tl with a second capacitance C 2 of 2
  • the two electrodes 102 are connected; and so on.
  • first first switching unit and the first first capacitor constitute a group of charging bills Element; a second first switching element Tl 2 c 2 and the second capacitor charging unit constituting a group; and so on.
  • Each of the second switch units includes: a second control terminal 301, a second input terminal 302, and a second output terminal 303; the second control terminal 301 of the second switch unit is coupled to the second voltage terminal V2, the second The second input end 302 of the switch unit is connected to the first output end 203 of the first switch unit, the second output end 303 of the second switch unit is connected to a gate line, and each gate line is connected to a second switch.
  • Unit T2 N Each of the second switch units includes: a second control terminal 301, a second input terminal 302, and a second output terminal 303; the second control terminal 301 of the second switch unit is coupled to the second voltage terminal V2, the second The second input end 302 of the switch unit is connected to the first output end 203 of the first switch unit, the second output end 303 of the second switch unit is connected to a gate line, and each gate line is connected to a second switch.
  • Unit T2 N Unit
  • the second input terminal 302 of the first second switching unit T2i and the second second switching unit T2 2 and the first of the first first switching unit T output terminal 203 is connected; a second input of the third second and fourth switching element T2 3 T2 4 second switching unit 302 and the first output terminal of the second switching element Tl 2 first terminal 203 is connected;
  • the second input end of at least one of the second switching units may be connected to the first output end of one of the first switching units, which will not be described in detail herein.
  • the embodiment of the present invention is not limited to the above, and may be set according to actual conditions, and only the charge stored in any one of the capacitors can be enabled when the second switch unit is turned on. All of the TFTs on the gate line to which the second electrode is electrically connected may be opened.
  • the first voltage signal provided by the first voltage terminal VI can cause all the first switching units TL.Tlx to be turned on, and the capacitor connected to the first output terminal 203 ( ⁇ .. ( ⁇ Charging, when the power is turned off (Xon function is on), the second voltage signal provided by the second voltage terminal V2 can turn on all the second switching units T2L . . . T2 n , the charged capacitor
  • the circuit further includes a plurality of third switching units.
  • Each third switching unit includes: a third control terminal 401, a third input terminal 402, and a third output terminal 403; the third control terminal 401 of the third switching unit is connected to the second voltage terminal V2, The third input end 402 of the third switch unit is connected to the second output end 303 of the second switch unit, and the third output end 403 of the third switch unit is connected to the adjacent gate line, and the adjacent gate line The third switching unit is disposed between.
  • the third switch unit is disposed between adjacent gate lines, specifically, the third input end 402 of the third switch unit is connected to the second output end 303 of the second switch unit, that is, The third input terminal 402 of the third switching unit is connected to a gate line such as GLi, and the third output terminal 403 of the third switching unit is adjacent to the gate line, that is, the gate line adjacent to the gate line GLi. , for example, GL i+1 connection.
  • the number of the third switching units located between the adjacent gate lines is not limited as long as the adjacent gate lines can be controlled to be turned on or off.
  • the third input terminal 402 of the first third switching unit T3i is connected to the second output terminal 303 of the first second switching unit T2i, and the first third switching unit T3 i
  • the third output terminal 403 is connected to the second output terminal 303 of the second second switching unit T2 2 ; the third input terminal 402 of the second third switching unit ⁇ 3 2 and the second second switching unit ⁇ 2 2 an output terminal 303 connected to the second output of the third switching unit a third terminal 403 ⁇ 3 2 connected to the second output terminal of the second switching unit 303 the third ⁇ 2 3; the third, and the third switching unit behind ⁇ 3 3
  • the third switching unit and so on.
  • the second output terminal 303 of some of the second switching units has no voltage output due to partial circuit failure of the circuit, the second output terminal is used for each second switching unit by the action of the third switching unit.
  • the 303 still guarantees a voltage output, increasing the reliability of the circuit.
  • the charging module 10 includes at least one charging unit, and each of the charging units includes a capacitor and a second switching unit, the charging module includes one capacitor and one first switching unit.
  • the first output end 203 of the i-th first switching unit is connected to the second electrode 102 of the i-th capacitor.
  • the first control terminal 201 of the i-th first switching unit and the first input terminal 202 of the i-th first switching unit are connected to the first voltage terminal VI, and the i+1th first
  • the first control terminal 201 and the first input terminal 202 of the switch unit are connected to the first output end 203 of the i th first of the first switch units, where N is the number of the gate lines, and i is greater than or equal to 1 and A positive integer less than N.
  • the first voltage signal provided by the first voltage terminal VI can cause the first switching units T, ⁇ 1 2 ... ⁇ 1 . ⁇ 1 ⁇ to be sequentially turned on, and sequentially given first
  • the capacitors d, C 2 ... Ci ... C N connected to the output terminal 203 are charged.
  • the second voltage signal provided by the second voltage terminal V2 enables all the second switching units T2.
  • T2 2 ... T2i...T2 N is turned on, the charged capacitor d, (3 2 ... ( ⁇ ... (3 ⁇ 4 can be kept with the gate line 01 ⁇ , All the TFTs connected by GL 2 ... GLi...GL N are turned on, so that the residual charge stored in the liquid crystal capacitor is quickly released, eliminating the image sticking phenomenon generated after the liquid crystal display device is turned off;
  • the TFT connected to the gate line is turned on by the first voltage signal, and the gate turn-on voltage is kept constant by the capacitor electrically connected to the gate line, thereby avoiding the problem that the gate drive IC of all TFTs is simultaneously turned on in the prior art. .
  • the embodiment of the invention provides a circuit for eliminating the afterimage of the shutdown.
  • the circuit includes: a plurality of capacitors d, C 2 ... Ci ... C N , and a plurality of first switching units Ti Tl 2 ... Tli ... Tl N, a plurality of second switching elements T2 T2 2 ... T2i ... T2 N , and a plurality of third switching unit T3 ⁇ 3 2 ... ⁇ 3 ⁇ ... ⁇ 3 ⁇ - 1 ; N is the number of gate lines, and i is an integer greater than 1 and less than N.
  • Each of the capacitors Ci includes: a first electrode 101 and a second electrode 102, and the first electrode 101 of the capacitor is connected to the reference voltage terminal V0.
  • Each of the first switching units Tli includes: a first control terminal 201, a first input terminal 202, and a first output terminal 203.
  • the first control terminal 201 and the first input terminal 202 of the first first switching unit are connected to the first voltage terminal VI, and the first output terminal 203 of the first first switching unit T and the first capacitor d the second electrode 102 is connected;
  • a first switching element Tl second control terminal 201 of a first and a second end 202 with a first output terminal of the first switching unit 203 is connected a first input, a second first switch Tl unit 203 and a first output terminal of the second capacitance C 2 of the second electrode 102 2 is connected;
  • a first output terminal 203 of a switching unit ⁇ 1 ⁇ is connected, and a first output terminal 203 of the i-th first switching unit Tli is
  • Each of the second switching units T2i includes: a second control terminal 301, a second input terminal 302, and a second output terminal 303.
  • the first control terminal 301 of the first second switch unit T2i is connected to the second voltage terminal V2
  • the second input terminal 302 of the first second switch unit T2i and the first first switch unit Tli are An output terminal 203 is connected
  • a second output terminal 303 of the first second switching unit T2i is connected to the first gate line
  • a second control terminal 301 of the second second switching unit T2 2 is connected to the second voltage terminal V2.
  • second switching means a second input of the second 2 [tau] 2 of the second end 302 of the first switching element Tl a first output terminal 203 of the connection, the second output terminal of the second switching unit of the second and 303 ⁇ 2 2
  • the second gate line GL 2 is connected; the second control terminal 301 of the i-th second switching unit T2i is connected to the second voltage terminal V2, and the ith second switching unit T2i
  • the second input terminal 302 is connected to the first output terminal 203 of the i-th first switching unit Tli, and the second output terminal 303 of the i-th second switching unit T2i is connected to the ith gate line GLi; and so on.
  • Each of the third switching units T3i includes: a third control terminal 401, a third input terminal 402, and a third output terminal 403. Specifically, the third input terminal 402 and the third output terminal 403 of the first third switching unit T3i are respectively connected to the first gate line and the second gate line GL 2 , and the first third switching unit T3i The third control terminal 401 is connected to the second voltage terminal V2; and so on.
  • the second voltage signal provided by the second voltage terminal V2 turns on all the second switching unit and the third switching unit, and the first voltage signal provided by the first voltage terminal VI can be combined with a All TFTs connected by the gate lines are turned on, and in addition, the charged capacitors d, C 2 ... Ci...C N can keep all TFTs connected to the gate lines GL GL 2 ... GLi...GL N open .
  • the third switching unit is also turned on, so that all the gate lines are connected, which increases reliability.
  • the first m places The capacitance values of the capacitors are sequentially increased, and the capacitance values of the remaining capacitors are the same and larger than the capacitance values of the mth capacitor; wherein m is a positive integer smaller than N. Wherein, m is calculated from the scanning line of the first scanning line in the scanning order of the gate lines.
  • the capacitance values of the first m capacitors are sequentially increased, and the capacitance values of the capacitors starting from the m+1th are equal and larger than the mth capacitance value.
  • the number of m and the capacitance value of the capacitor are set according to actual conditions, and are not limited herein.
  • the predetermined number is three, and the capacitances (ie, d, C 2 , C 3 ) electrically connected to the first three gate lines (ie, GL GL 2 , GL 3 ) through the second switching unit in the scanning order of the gate lines. sequentially increases a capacitance value, the capacitance value of the same and larger than the rest of the capacitance value of the capacitance C 3.
  • the first capacitor C ⁇ capacitance value electrically connected to the first gate line through the first second switching unit T2i can be set to be 1/3 of the high level time provided by the first voltage terminal VI Full of inside.
  • the control terminal of the switch unit is the gate of the thin film transistor.
  • the input end of the switching unit is the drain of the thin film transistor, and the output end of the switching unit is the source of the thin film transistor.
  • Embodiments of the present invention provide an array substrate, including any of the above-mentioned circuits for eliminating the afterimage of shutdown.
  • Embodiments of the present invention provide an array substrate, in which a TFT connected to each gate line is discharged by a discharge module electrically connected to the gate line, and does not have to pass an ACF (Anisotropic Conductive Film).
  • ACF Anisotropic Conductive Film
  • the charge is drawn on the PCBA (Printed Circuit Board + Assembly), thereby avoiding the phenomenon that the joint is broken by burning the gold ball particles in the AFC at the joint.
  • the charging module of the above circuit includes a plurality of capacitors
  • the first electrode of the common electrode is connected to the reference voltage terminal, considering that there is a common electrode line for supplying power to the common electrode on the array substrate, it is preferable that all of the capacitors
  • the first electrodes 101 are connected together, and the first electrodes 101 are electrically connected to the common electrode lines. This saves the process when preparing the array substrate.
  • the second electrodes 102 of all the capacitors are connected, there may be a problem that all the capacitors cannot be charged due to local defects. Therefore, in the embodiment of the present invention, preferably, the second electrodes 102 of all the capacitors are not connected. Together, that is, the second electrode of each capacitor is independent and has no electrical connection.
  • the capacitance values of the first few capacitors are too large, the starting current at the moment of starting up is significantly increased. Therefore, preferably, the capacitance values of the first m capacitors are sequentially increased, and the rest are described.
  • the capacitance values of the capacitors are the same and larger than the capacitance values of the mth capacitors, wherein m is counted from the first scanned gate line in the scanning order of the gate lines.
  • the requirement of the capacitance value of the above capacitance can be satisfied by changing the relative area of the first electrode 101 and the second electrode 102 of the capacitor. That is, the effective relative areas of the first electrode 101 and the second electrode 102 of the first m capacitors sequentially increase, and the effective relative areas of the first electrode 101 and the second electrode 102 of the remaining capacitors are equal, and are greater than the mth capacitor. The effective relative area of one electrode 101 and second electrode 102.
  • the capacitance of the first three gate lines ie, GL GL 2 , GL 3
  • the first electrode 101 of d, C 2 , C 3 is a flat plate
  • the area of the second electrode 102 of the capacitor ie, d, C 2 , C 3
  • the effective relative areas of the electrode and the second electrode are sequentially increased, and the effective relative areas of the first electrode 101 and the second electrode 102 of the remaining capacitors (here, for example, C 4 , C 5 ) are the same, and are greater than the first of C 3
  • the area of the electrode 101 and the second electrode 102 are 3
  • the effective relative areas of the first electrode 101 and the second electrode 102 of the remaining capacitors here, for example, C 4 , C 5
  • the area of each of the second electrodes can be 3 pixels, and the first electrode is a flat plate (the area of which is larger than the area sum of all the second electrodes). Since the capacitance of each gate line is about 200pF, which is equivalent to a capacitor of about 128000 ⁇ 2 in the GOA (Gate Driver On Array) design, the area of one pixel (RGB) is about It can be seen that the capacitance of the three pixel size area is equivalent to the capacitance of one gate line. Therefore, when the ⁇ function is turned on, the circuit can separately supply 1/2V voltage for each gate line to turn on the TFT corresponding to the sub-pixel. .
  • the first electrode 101 of the capacitor may be disposed in the same layer as the gate line, and the second electrode 102 may be disposed in the same layer as the data line.
  • the switching unit it may be the same TFT as the TFT connected to the gate line, so that when the array substrate is prepared, the switching unit can be formed together with the TFT connected to the gate line, reducing the number of process steps.
  • the circuit for eliminating the residual image of the machine is disposed on the opposite side of the array line of the array substrate.
  • Embodiments of the present invention provide a liquid crystal display device including the above array substrate.
  • the display device may be a display device such as a liquid crystal display or an electronic paper, and any display product or component such as a television, a digital camera, a mobile phone, a tablet computer or the like including the display device.
  • the liquid crystal display device controls the light transmittance through the liquid crystal by the electric field to display an image.
  • the liquid crystal display device is roughly classified into a vertical electric field drive type and a horizontal electric field drive type in accordance with the direction of the electric field for driving the liquid crystal.
  • the vertical electric field-driven liquid crystal display device is provided with a common electrode and a pixel electrode opposite to each other on the upper and lower substrates, and a vertical electric field is formed between the common electrode and the pixel electrode to drive the liquid crystal, such as a TN (Twist Nematic) type, VA (Vertical Alignment) type liquid crystal display device.
  • the horizontal electric field-driven liquid crystal display device has a common electrode and a pixel electrode disposed on the lower substrate, and a horizontal electric field is formed between the common electrode and the pixel electrode to drive the liquid crystal, such as ADS (Advanced-Super Dimensional Switching).
  • ADS Advanced-Super Dimensional Switching
  • Type, IPS In Plane Switch type liquid crystal display device.
  • the display device provided by the present invention may be any of the above liquid crystal display devices.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

公开了一种消除关机残影的电路及阵列基板，可消除显示装置在关机后产生的残影现象。该电路包括充电模块（10）和放电模块（20）。该充电模块（10）连接第一电压端（V1），用于在该第一电压端（V1）输入的第一电压信号控制下储存电荷。该放电模块（20）连接该充电模块（10）和第二电压端（V2），用于在该第二电压端（V2）输入的第二电压信号控制下将该充电模块（10）储存的电荷提供给栅线（GL1—GLn）。

Description

消除关机残影的电路及阵列基板
技术领域
本发明涉及显示技术领域， 尤其涉及一种消除关机残影的电路及阵列 基板。 背景技术
目前， 薄膜晶体管液晶显示器 （ Thin Film Transistor Liquid Crystal Display, 筒称 TFT-LCD )广泛应用在笔记本电脑、 手机及电视等与生活息 息相关的电子产品中。 然而， 在 TFT-LCD供电电源关闭时， 通常还会残留 一部分以前的图像， 这是由于在显示器经过长时间显示图像之后， 会在两 个相对电极之间的液晶电容中累积电荷， 而累积的电荷在电源关闭后并不 能立即释放， 从而在关机后仍会残留一部分以前的图像。 发明内容
本发明实施例提供了一种消除关机残影的电路及阵列基板， 可消除显 示装置在关机后产生的残影现象。
相应地， 本发明的实施例采用如下技术方案：
一方面， 提供了一种消除关机残影的电路， 该电路包括充电模块和放 电模块；
所述充电模块连接第一电压端， 用于在所述第一电压端输入的第一电 压信号控制下储存电荷；
所述放电模块连接所述充电模块和第二电压端， 用于在所述第二电压 端输入的第二电压信号控制下在关机时将所述充电模块储存的电荷提供给 栅线。
可选的， 所述电路还包括输入模块； 所述输入模块， 连接所述放电模 块， 用于在关机时输出所述第二电压信号到所述第二电压端。
优选的， 所述充电模块包括至少一组充电单元， 每一组所述充电单元 包括电容和第一开关单元； 其中
所述电容包括： 第一电极和第二电极， 所述电容的第一电极连接参考 电压端； 所述第一开关单元包括： 第一控制端、 第一输入端以及第一输出端， 所述第一开关单元的第一输出端与所述电容的第二电极相连， 所述第一开 关单元的第一输入端与所述第一控制端连接。
优选地， 每组充电单元中的第一开关单元的第一控制端还连接到所述第 一电压端。
优选的， 所述充电模块包括 N组充电单元， 第 i组充电单元中的第一 开关单元的第一输出端连接到第 i+1组充电单元中的第一开关单元的第一输 入端， 第一组充电单元中的第一开关单元的第一输入端连接到所述第一电压 端； 所述 N为所述栅线的条数， i取大于等于 1且小于 N的整数。
优选地， 前 m个所述电容的电容值依次增大， 其余所述电容的电容值 相同且大于第 m个所述电容的电容值， 其中， m为大于零小于 N的整数。
优选地， 所述放电模块包括多个第二开关单元； 其中， 每个第二开关单 元包括： 第二控制端、 第二输入端以及第二输出端； 每个第二开关单元的第 二控制端与所述第二电压端相连接， 每个第二开关单元的第二输出端分别与 一条栅线连接， 至少两个第二开关单元的第二输入端与一组充电单元中的第 一开关单元的第一输出端连接， 剩余的第二开关单元的第二输入端分别与其 它组充电单元中的第一开关单元的第一输出端连接。
优选的， 所述放电模块包括多个第二开关单元； 其中
每个第二开关单元包括： 第二控制端、 第二输入端以及第二输出端； 第 j个第二开关单元的第二控制端与第二电压端相连接， 第 j个第二开关 单元的第二输入端与第 j组充电单元中的第一开关单元的第一输出端连 接， 所述第 j个第二开关单元的第二输出端与一条所述栅线连接， 每一条 所述栅线连接一个所述第二开关单元， j为大于零小于等于 N的整数。
优选的， 所述放电模块还包括多个第三开关单元； 其中，
所述第三开关单元包括： 第三控制端、 第三输入端以及第三输出端； 其中第 i个第三开关单元的第三控制端与所述第二电压端连接， 所述第 i 个第三开关单元的第三输入端与第 i个第二开关单元的第二输出端连接， 所述第 i个第三开关单元的第三输出端与第 i+1个第二开关单元的第二输 出端连接。
另一方面， 提供了一种阵列基板， 包括上述的一种消除关机残影的电 路。 优选的， 在所述消除关机残影的电路的充电模块包括多个电容的情况 下， 所有所述电容的第一电极相连， 且所述第一电极与所述阵列基板的公 共电极线电连接。
优选地，所述多个电容中的前 m个所述电容的第一电极和第二电极的 有效相对面积依次增大， 其余所述电容的第一电极和第二电极的有效相对 面积相等，并大于第 m个所述电容的第一电极和第二电极的有效相对面积。
本发明实施例提供了一种消除关机残影的电路及阵列基板， 该电路包 括充电模块和放电模块， 所述充电模块用于在第一电压端输入的第一电压 信号控制下存储电荷， 所述放电模块用于在第二电压端输入的第二电压信 号控制下在关机时将充电模块存储的电荷提供给栅线； 这样在关机时， 放 电模块可在第二电压信号控制下将充电模块存储的电荷提供给栅线， 以保 持所有薄膜晶体管打开， 从而使存储在液晶电容中的残留电荷快速释放， 消除了液晶显示装置在关机后产生的残影现象。 附图说明 实施例或现有技术描述中所需要使用的附图作筒单地介绍， 显而易见地， 下面描述中的附图仅仅是本发明的一些实施例， 对于本领域普通技术人员 来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附 图。
图 1为本发明实施例提供的一种消除关机残影的电路的框图； 图 2为本发明实施例提供的另一种消除关机残影的电路的框图； 图 3为本发明实施例一提供的一种消除关机残影的电路的示意图； 图 4为本发明实施例提供的一种包括多个第三开关单元的消除关机残 影的电路的示意图；
图 5为本发明实施例二提供的一种消除关机残影的电路的示意图； 图 6为本发明实施例提供的电容的结构示意图。
附图标记说明：
充电模块 -10; 放电模块 -20; 输入模块 -30; 栅线 -GL; 电容 -C, 第一 电极 -101 , 第二电极 -102; 第一开关单元 -T1 , 第一控制端 -201 , 第一输入 端 -202 , 第一输出端 -203 ; 第二开关单元 -T2 , 第二控制端 -301 , 第二输入 端 -302, 第二输出端 -303; 第三开关单元 -T3 , 第三控制端 -401 , 第三输入 端 -402, 第三输出端 -403; 参考电压端 - V0; 第一电压端 -VI ; 第二电压端 -V2。 具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进 行清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没 有做出创造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的 范围。
本发明实施例提供了一种消除关机残影的电路， 如图 1和图 2所示， 该电路包括充电模块 10和放电模块 20; 其中， 所述充电模块 10, 连接第 一电压端 VI , 用于在所述第一电压端 VI输入的第一电压信号控制下储存 电荷； 所述放电模块 20, 连接所述充电模块 10和第二电压端 V2, 用于在 所述第二电压端 V2输入的第二电压信号控制下在关机时将所述充电模块 10储存的电荷提供给栅线。
其中， 对于所述第二电压端， 其输入的第二电压信号可以不恒定， 在 此不做限定。
示例的， 在发明实施例中， 第二电压端 V2输入的第二电压信号可以 与现有技术中 Xon (关机时使所有行的薄膜晶体管全部开启的控制信号)功 能相结合， 即当关机时， Xon功能开启， 所述放电模块 20在所述第二电压 端 V2输入的第二电压信号控制下将充电模块 10储存的电荷提供给栅线， 以保持所有栅线连接的薄膜晶体管打开， 当开机时， Xon功能关闭， 所述 放电模块 20在所述第二电压端 V2输入的第二电压信号控制下不将充电模 块 10存储的电荷提供给栅线。 对于所述第一电压端 VI输出的第一电压信 号以能使与所有栅极连接的薄膜晶体管打开为准， 在此不做限定。
此外， Xon功能、 第一电压端、 第二电压端等， 可集成于栅极驱动 IC 中， 也可单独使用， 在此不做限定。
本发明实施例提供了一种消除关机残影的电路， 包括充电模块和放电 模块， 所述充电模块用于在第一电压端输入的第一电压信号控制下存储电 荷， 所述放电模块用于在第二电压端输入的第二电压信号控制下在关机时 将充电模块存储的电荷提供给栅线； 这样在关机时， 放电模块可在第二电 压信号控制下将充电模块的存储的电荷提供给栅线， 以保持所有薄膜晶体 管打开， 从而使存储在液晶电容中的残留电荷快速释放， 消除了液晶显示 装置在关机后产生的残影现象。
可选的， 如图 2所示， 所述消除关机残影的电路还可以包括： 输入模 块 30; 所述输入模块 30, 连接所述放电模块 20, 用于在关机时输出所述 第二电压信号到所述第二电压端 V2。
示例的， 可以将 Xon功能模块集成到该输入模块 30中， 当关机时， Xon功能开启， 控制该输入模块 30输入第二电压信号到所述第二电压端 V2, 从而控制放电模块 20将所述充电模块 10存储的电荷提供给栅线。 当 然， 在开机时， Xon功能关闭， 输入模块 30也可以输入第二电压信号到所 述第二电压端 V2, 但该第二电压信号不能使放电模块 20将所述充电模块 10存储的电荷提供给栅线。
可选的， 所述充电模块 10包括至少一组充电单元， 每一组所述充电 单元包括电容和第一开关单元。
其中， 所述电容包括： 第一电极 101和第二电极 102, 所述电容的第 一电极 101连接参考电压端 V0。所述第一开关单元包括：第一控制端 201、 第一输入端 202以及第一输出端 203;所述第一开关单元的第一输出端 203 与所述电容的第二电极 102相连， 所述第一开关单元的第一输入端 202与 所述第一电压端 VI连接。
当然， 第一开关单元的第一控制端 201也可以与所述第一电压端 VI 连接， 只需能使第一开关单元一直打开即可。
需要说明的是， 所述电容的个数与所述第一开关单元的个数可以相同 也可以不同， 其具体数量可根据实际情况进行设定， 只要能实现充电单元 电荷存储的功能即可， 在此不进行限定。 此外， 对于所述充电单元的个数 也不做限定。
在上述充电模块 10包括至少一组充电单元， 且每一组充电单元包括 电容和第一开关单元的情况下， 所述放电模块 20包括多个第二开关单元。
其中， 每个第二开关单元包括： 第二控制端 301、 第二输入端 302以 及第二输出端 303 ; 所述第二开关单元的第二控制端 301与第二电压端 V2 连接， 所述第二开关单元的第二输入端 302与所述第一开关单元的第一输 出端 203连接， 所述第二开关单元的第二输出端 303与一条栅线连接， 每 一条栅线连接一个第二开关单元。
此处可以为： 当 Xon功能开启时， 所述第二电压端 V2输出的第二电 压信号控制所有第二开关单元打开。
所述第二开关单元的个数即为栅线的条数。 例如对于一个分辨率为
1024*768的显示装置来说， 总共会有 768条栅线， 则第二开关单元的个数 也为 768个。
需要说明的是， 所述第一开关单元或电容的个数可以与所述第二开关 单元的个数不相同， 即， 可以是一个第一开关单元的第一输出端 203与几 个第二开关单元的第二输入端 302均连接； 当然， 所述第一开关单元或电 容的个数也可以与所述第二开关单元的个数相同， 在此不做限定， 只需每 一个第二开关单元的第二输出端 303输出的电压能使与之连接的栅线上的 所有薄膜晶体管打开即可。
实施例一
本发明实施例提供了一种消除关机残影的电路， 如图 3所示， 该电路 包括： 多个电容 d、 C2...CX、 多个第一开关单元 T 、 T12...T1X、 以及多 个第二开关单元 T2 T22、 Τ23、 Τ24...Τ2Ν ； Ν为栅线的条数， X为小于
Ν的正整数。
其中， 每一个电容包括： 第一电极 101和第二电极 102, 所述电容的 第一电极 101连接参考电压端 V0。
每个第一开关单元包括： 第一控制端 201、 第一输入端 202以及第一 输出端 203; 所述第一开关单元的第一输出端 203与电容的第二电极 102 相连， 所述第一开关单元的第一控制端 201和第一输入端 202与所述第一 电压端 VI连接。
此处， 参考图 3所示， 例如， 第一个第一开关单元 的第一控制端
201和第一输入端 202与所述第一电压端 VI连接， 第一个第一开关单元 Tl j的第一输出端 203与第一个电容 d的第二电极 102连接； 第二个第一 开关单元 Tl2的第一控制端 201和第一输入端 202与所述第一电压端 VI 连接， 第二个第一开关单元 Tl2的第一输出端 203与第二个电容 C2的第二 电极 102连接； 依次类推。
其中，第一个第一开关单元 和第一个第一电容 (^构成一组充电单 元； 第二个第一开关单元 Tl2和第二个电容 c2构成一组充电单元； 依次类 推。
每个第二开关单元包括： 第二控制端 301、 第二输入端 302以及第二 输出端 303 ; 所述第二开关单元的第二控制端 301与第二电压端 V2连接， 所述第二开关单元的第二输入端 302与所述第一开关单元的第一输出端 203连接， 所述第二开关单元的第二输出端 303与一条栅线连接， 每一条 栅线连接一个第二开关单元 T2N。
此处， 参考图 3所示， 例如， 第一个第二开关单元 T2i和第二个第二 开关单元 T22的第二输入端 302均与所述第一个第一开关单元 T 的第一 输出端 203连接； 第三个第二开关单元 T23和第四个第二开关单元 T24的 第二输入端 302与所述第二个第一开关单元 Tl2的第一输出端 203连接； 对于其余所述第二开关单元， 例如可以是至少一个所述第二开关单元的第 二输入端与一个所述第一开关单元的第一输出端连接， 在此不做详述。
需要说明的是， 本发明实施例并不限于上述情况， 具体可根据实际情 况自行设定，只需任一个电容中储存的电荷能在所述第二开关单元打开时， 能使与该电容的第二电极电连接的栅线上的所有 TFT打开即可。
这样当开机（Xon功能关闭） 时， 第一电压端 VI提供的第一电压信 号可以使所有第一开关单元 TL .Tlx被打开，并给与之第一输出端 203连 接的电容（^ ...(^充电， 当关机（Xon功能开启） 时， 第二电压端 V2提供 的第二电压信号可使所有第二开关单元 T2L . .T2n打开， 充好电的电容
(^ ...Cx便可保持与栅线 GL^ .GLN连接的所有 TFT打开，从而使存储在液 晶电容中的残留电荷快速释放； 此外， 由于与每条栅线连接的 TFT通过第 一电压信号开启， 并通过与该条栅线电连接的电容保持栅极开启电压的一 致， 可避免现有技术中同时开启所有 TFT的栅极驱动 IC能力不足的问题。
进一步优选的， 如图 4所示， 在所述放电模块 20包括多个第二开关 单元的情况下， 所述电路还包括多个第三开关单元。
其中， 每个第三开关单元包括： 第三控制端 401、 第三输入端 402以 及第三输出端 403 ; 所述第三开关单元的第三控制端 401与所述第二电压 端 V2连接， 所述第三开关单元的第三输入端 402与所述第二开关单元的 第二输出端 303连接， 所述第三开关单元的第三输出端 403与相邻栅线连 接， 相邻栅线之间设置所述第三开关单元。 需要说明的是， 相邻栅线之间设置所述第三开关单元， 具体是指， 第 三开关单元的第三输入端 402与所述第二开关单元的第二输出端 303连接， 也就是所述第三开关单元的第三输入端 402与一条栅线例如 GLi连接， 并 且所述第三开关单元的第三输出端 403与相邻栅线， 即与上述栅线 GLi相 邻的栅线， 例如 GLi+1连接。 同时， 位于相邻栅线之间的第三开关单元的 个数不做限定， 只要能控制相邻栅线之间导通或关断即可。
即： 参考图 4所示， 第一个第三开关单元 T3i的第三输入端 402与第 一个第二开关单元 T2i的第二输出端 303连接， 第一个第三开关单元 T3 i 的第三输出端 403与第二个第二开关单元 T22的第二输出端 303连接； 第 二个第三开关单元 Τ32的第三输入端 402与第二个第二开关单元 Τ22的第 二输出端 303连接， 第二个第三开关单元 Τ32的第三输出端 403与第三个 第二开关单元 Τ23的第二输出端 303连接； 第三个第三开关单元 Τ33以及 后面的第三开关单元， 以此类推。
这样即使由于该电路的部分电路失效而使得某些第二开关单元的第 二输出端 303无电压输出， 通过第三开关单元的作用， 对于每个第二开关 单元来说， 其第二输出端 303仍然能保证有电压输出， 增加了该电路的可 靠性。
进一步地， 在上述充电模块 10包括至少一组充电单元， 且每一组充 电单元包括电容和第二开关单元的的情况下， 所述充电模块包括 Ν个电容 和 Ν个第一开关单元。
其中， 第 i个所述第一开关单元的第一输出端 203与第 i个所述电容 的第二电极 102连接。 第 i个所述第一开关单元的第一控制端 201和第 i 个所述第一开关单元的第一输入端 202与所述第一电压端 VI连接，第 i+1 个所述第一开关单元的第一控制端 201和第一输入端 202与第 i个所述第 一开关单元的第一输出端 203连接， 所述 N为所述栅线的条数， i取大于 等于 1且小于 N的正整数。
这样， 当开机（Xon功能关闭） 时， 第一电压端 VI提供的第一电压 信号可以使第一开关单元 T 、 Τ12...Τ1 .Τ1Ν被依次打开， 并依次给与之 第一输出端 203连接的电容 d、 C2...Ci...CN充电， 当关机（Xon功能开启 ) 时， 第二电压端 V2提供的第二电压信号可使所有第二开关单元 T2
T22...T2i...T2N打开， 充好电的电容 d、 （32...(^...(¾便可保持与栅线01^、 GL2...GLi...GLN连接的所有 TFT打开，从而使存储在液晶电容中的残留电 荷快速释放， 消除了液晶显示装置在关机后产生的残影现象； 此外， 由于 与每条栅线连接的 TFT通过第一电压信号开启， 并通过与该条栅线电连接 的电容保持栅极开启电压的一致， 可避免现有技术中同时开启所有 TFT的 栅极驱动 IC能力不足的问题。
实施例二
本发明实施例提供了一种消除关机残影的电路， 如图 5所示， 该电路 包括： 多个电容 d、 C2...Ci...CN, 多个第一开关单元 Ti Tl2...Tli...TlN, 多个第二开关单元 T2 T22...T2i...T2N, 以及多个第三开关单元 T3 Τ32...Τ3ι...Τ3Ν-1 ; N为栅线的条数， i取大于 1且小于 N的整数。
每一个电容 Ci包括： 第一电极 101和第二电极 102 , 所述电容的第一 电极 101连接参考电压端 V0。
每一个第一开关单元 Tli包括： 第一控制端 201、第一输入端 202以及 第一输出端 203。 具体的， 第一个第一开关单元 的第一控制端 201和 第一输入端 202与第一电压端 VI连接， 第一个第一开关单元 T 的第一 输出端 203与第一个电容 d的第二电极 102连接； 第二个第一开关单元 Tl2的第一控制端 201和第一输入端 202与第一个第一开关单元 的第一 输出端 203连接， 第二个第一开关单元 Tl2的第一输出端 203与第二个电 容 C2的第二电极 102连接； 第 i个第一开关单元 Tli的第一控制端 201和 第一输入端 202与第 i-1个第一开关单元 Τ1μι的第一输出端 203连接， 第 i个第一开关单元 Tli的第一输出端 203与第 i个电容 Q的第二电极 102连 接； 依此类推。
每一个第二开关单元 T2i包括： 第二控制端 301、第二输入端 302以及 第二输出端 303。 具体的， 第一个第二开关单元 T2i的第一控制端 301与 第二电压端 V2连接， 第一个第二开关单元 T2i的第二输入端 302与第一 个第一开关单元 Tli的第一输出端 203连接， 第一个第二开关单元 T2i的 第二输出端 303与第一条栅线 连接； 第二个第二开关单元 T22的第二 控制端 301与第二电压端 V2连接， 第二个第二开关单元 Τ22的第二输入 端 302与第二个第一开关单元 Tl2的第一输出端 203连接， 第二个第二开 关单元 Τ22的第二输出端 303与第二条栅线 GL2连接； 第 i个第二开关单 元 T2i的第二控制端 301与第二电压端 V2连接， 第 i个第二开关单元 T2i 的第二输入端 302与第 i个第一开关单元 Tli的第一输出端 203连接， 第 i 个第二开关单元 T2i的第二输出端 303与第 i条栅线 GLi连接； 依此类推。
每一个第三开关单元 T3i包括： 第三控制端 401、第三输入端 402以及 第三输出端 403。 具体的， 第一个第三开关单元 T3i的第三输入端 402和 第三输出端 403分别与第一条栅线 和第二条栅线 GL2连接， 第一个第 三开关单元 T3i的第三控制端 401与第二电压端 V2连接； 依此类推。
其中， 当关机（Xon功能开启） 时， 第二电压端 V2提供的第二电压 信号使所有第二开关单元和第三开关单元打开， 第一电压端 VI提供的第 一电压信号可使与一条栅线连接的所有 TFT打开， 此外， 充好电的电容 d、 C2...Ci...CN可保持与栅线 GL GL2...GLi...GLN连接的所有 TFT打开。
在本发明实施例中， 在第二开关单元打开的同时， 第三开关单元也打 开， 从而使得所有栅线连接起来， 增加了可靠性。
进一步考虑到当该电路用于消除关机残影时， 在开机时， 若前几个电 容的电容值过大， 会导致开机瞬间的开机电流显著增大， 因此， 进一步优 选的， 前 m个所述电容的电容值依次增大， 其余所述电容的电容值相同且 大于第 m个所述电容的电容值； 其中， m为小于 N的正整数。 其中， 按所 述栅线的扫描顺序， m以从最先被扫描的栅线开始起算。
此处， 即为， 前 m个电容的电容值是依次增大的， 从第 m+1个开始 的电容的电容值相等并大于第 m个的电容值。此外，对于 m的个数和电容 的电容值根据实际情况进行设定， 在此不做限定。
例如，预定数量为 3个，按栅线的扫描顺序， 与前三条栅线（即， GL GL2、 GL3 )通过第二开关单元电连接的电容（即， d、 C2、 C3 ) 的电容值 依次增大， 其余所述电容的电容值相同且大于 C3的电容值。 其中， 与第一 条栅线 通过第一个第二开关单元 T2i电连接的第一个电容 C 々电容值 可以设定为， 在第一电压端 VI提供的高电平时间的 1/3期间内充满。
此处， 仅以按栅线扫描顺序， 以前 3条栅线为例进行说明， 但本发明 实施例并不限于此。 管， 开关单元的控制端为薄膜晶体管的栅极。 在薄膜晶体管为 N型的情况 下， 开关单元的输入端为薄膜晶体管的漏极， 开关单元的输出端为薄膜晶 体管的源极。 本发明实施例提供了一种阵列基板， 包括上述的任一种消除关机残影 的电路。
本发明实施例提供了一种阵列基板， 由于与每条栅线连接的 TFT是通 过与该条栅线电连接的放电模块放电打开的，而不必通过 ACF( Anisotropic Conductive Film,异性导电胶膜）在 PCBA( Printed Circuit Board +Assembly, 成品线路板）上汲取电荷，从而避免了烧毁连接处 AFC中的金球粒子而导 致该连接处断开的现象。
在上述电路的充电模块包括多个电容的情况下， 由于公共电极的第一 电极连接参考电压端， 考虑到在阵列基板上存在给公共电极供电的公共电 极线， 因此优选的， 所有电容中的第一电极 101被连接在一起， 且所述第 一电极 101与公共电极线电连接。 这样在制备该阵列基板时， 节省工艺。
考虑若将所有电容的第二电极 102连接起来， 可能会由于局部不良而 导致所有电容都无法充电的问题， 因此， 在本发明实施例中， 优选的， 所 有电容的第二电极 102不被连接在一起， 即， 每个电容的第二电极均是独 立的， 没有电连接关系。
进一步地， 考虑到在开机时， 若前几个电容的电容值过大， 会导致开 机瞬间的开机电流显著增大， 因此， 优选的， 前 m个电容的电容值依次增 大， 其余所述电容的电容值相同且大于第 m个所述电容的电容值， 其中， 按栅线的扫描顺序， m从最先被扫描的栅线开始起算。
进一步地， 可通过改变电容的第一电极 101和第二电极 102的相对面 积来满足上述电容的电容值的需求。 即， 前 m个电容的第一电极 101和第 二电极 102的有效相对面积依次增大， 其余电容的第一电极 101和第二电 极 102的有效相对面积相等， 并大于第 m个电容的第一电极 101和第二电 极 102的有效相对的面积。
例如， 如图 6所示， 例如取 m为 3 , 按所述栅线的扫描顺序， 与前三 条栅线（即， GL GL2、 GL3 )通过第二开关单元电连接的电容（即， d、 C2、 C3 ) 的第一电极 101为平板， 所述电容（即， d、 C2、 C3 ) 的第二电 极 102的面积依次增大， 即， 该三个电容的第一电极和第二电极的有效相 对面积依次增大， 其余所述电容（此处例如 C4、 C5 ) 的第一电极 101和第 二电极 102的有效相对面积相同， 并大于 C3的第一电极 101和第二电极 102的面积。 以笔记本产品为例， 对于其余电容， 其每个第二电极的面积可以取 3 个像素面积大小，其第一电极为平板（其面积大于所有第二电极的面积和）。 由于其每根栅线的电容约 200pF， 相当于 GOA ( Gate Driver On Array, 阵 列基板行驱动）设计中面积约 128000μηι2大小的电容， 一个像素 (RGB)面 积约为
Figure imgf000013_0001
由此可知， 3个像素大小面积的电容相 当于一根栅线的电容， 因此， 当 Χοη功能开启时， 该电路单独能够为每根 栅线提供 1/2V的电压来开启子像素对应的 TFT。
此外， 所述电容的第一电极 101可以与所述栅线同层设置， 所述第二 电极 102可以与数据线同层设置。对于开关单元，可以是与栅线连接的 TFT 相同的 TFT,这样在制备该阵列基板时，开关单元可以和与栅线连接的 TFT 一同形成， 减少工艺步骤。
此外， 由于目前阵列基板在其相对栅线引线的一侧布线较为宽松， 因 此， 优选的， 所述消除该机残影的电路设置于所述阵列基板的相对栅线引 线一侧。
本发明实施例提供了一种液晶显示装置， 包括上述的阵列基板。 所述 显示装置可以为液晶显示器、 电子纸等显示器件以及包括这些显示器件的 电视、 数码相机、 手机、 平板电脑等任何具有显示功能的产品或者部件。
需要说明的是， 液晶显示装置利用电场通过液晶控制光透性以显示图 像。 根据驱动液晶的电场方向， 将液晶显示装置大致分为垂直电场驱动型 和水平电场驱动型。 垂直电场驱动型液晶显示装置在上下基板上彼此相对 设置公共电极和像素电极， 在所述公共电极和像素电极之间形成垂直的电 场以驱动液晶，如 TN( Twist Nematic，扭曲向列）型、 VA( Vertical Alignment , 多畴垂直取向） 型液晶显示装置。 水平电场驱动型液晶显示装置在下基板 上设置公共电极和像素电极， 在所述公共电极和像素电极之间形成水平的 电场以驱动液晶， 如 ADS ( Advanced-Super Dimensional Switching, 高级 超维场开关）型、 IPS ( In Plane Switch, 横向电场效应）型液晶显示装置。 本发明提供的显示装置可以为上述任一种液晶显示装置。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局 限于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可 轻易想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明 的保护范围应以所述权利要求的保护范围为准。

Claims

权 利 要 求 书
1、 一种消除关机残影的电路， 其特征在于， 包括充电模块和放电模块； 所述充电模块连接第一电压端， 用于在所述第一电压端输入的第一电压 信号控制下储存电荷；
所述放电模块连接所述充电模块和第二电压端， 用于在所述第二电压端 输入的第二电压信号控制下在关机时将所述充电模块储存的电荷提供给栅 线。
2、 根据权利要求 1所述的电路，， 还包括输入模块；
所述输入模块连接所述放电模块， 用于在关机时输出所述第二电压信号 到所述第二电压端。
3、根据权利要求 1或 2所述的电路， 其中， 所述充电模块包括至少一组 充电单元， 每一组充电单元包括电容和第一开关单元； 其中
所述电容包括第一电极和第二电极， 所述电容的第一电极连接参考电压 端；
所述第一开关单元包括： 第一控制端、 第一输入端以及第一输出端， 所 述第一开关单元的第一输出端与所述电容的第二电极相连， 所述第一开关单 元的第一输入端和第一控制端连接。
4、根据权利要求 3所述的电路， 其中， 每组充电单元中的第一开关单元 的第一控制端还连接到所述第一电压端。
5、 根据权利要求 3所述的电路， 其中， 充电模块包括 N组充电单元， 第 i组充电单元中的第一开关单元的第一输出端连接到第 i+1组充电单元中的 第一开关单元的第一输入端， 第一组充电单元中的第一开关单元的第一输入 端连接到所述第一电压端， 所述 N为所述栅线的条数， i取大于等于 1且小 于 N的整数。
6、 根据权利要求 4或 5所述的电路， 其中， 前 m个电容的电容值依次 增大， 其余电容的电容值相同且大于第 m个电容的电容值， 其中， m为大于 零小于 N的整数。
7、根据权利要求 4所述的电路， 其中， 所述放电模块包括多个第二开关 单元； 其中
每个第二开关单元包括： 第二控制端、 第二输入端以及第二输出端； 每 个第二开关单元的第二控制端与所述第二电压端相连接， 每个第二开关单元 的第二输出端分别与一条栅线连接， 至少两个第二开关单元的第二输入端与 一组充电单元中的第一开关单元的第一输出端连接， 剩余的第二开关单元的 第二输入端分别与其它组充电单元中的第一开关单元的第一输出端连接。
8、根据权利要求 5所述的电路， 其中， 所述放电模块包括多个第二开关 单元； 其中
每个第二开关单元包括： 第二控制端、 第二输入端以及第二输出端； 第 j个第二开关单元的第二控制端与所述第二电压端相连接， 第 j个第二开关单 元的第二输入端与第 j 组充电单元中的第一开关单元的第一输出端连接， 所 述第 j 个第二开关单元的第二输出端与一条栅线连接， 其中每一条栅线连接 一个第二开关单元， j为大于零小于等于 N的整数。
9、根据权利要求 7或 8所述的电路， 其中， 所述放电模块还包括多个第 三开关单元； 其中，
所述第三开关单元包括： 第三控制端、 第三输入端以及第三输出端； 其 中第 i个第三开关单元的第三控制端与所述第二电压端连接，第 i个第三开关 单元的第三输入端和第 i个第二开关单元的第二输出端连接，第 i个第三开关 单元的第三输出端和第 i+1个第二开关单元的第二输出端连接。
10、 一种阵列基板， 其特征在于， 包括权利要求 1至 9任一项所述的消 除关机残影的电路。
11、根据权利要求 10所述的阵列基板， 其中， 在所述消除关机残影的电 路的充电模块包括多个电容的情况下， 所有所述电容的第一电极相连， 且所 述第一电极与所述阵列基板的公共电极线电连接。
12、 根据权利要求 11 所述的阵列基板， 其中， 所述多个电容中的前 m 个电容的第一电极和第二电极的有效相对面积依次增大， 其余电容的第一电 极和第二电极的有效相对面积相等， 并大于第 m个电容的第一电极和第二电 极的有效相对面积。
PCT/CN2013/078706 2013-04-19 2013-07-02 消除关机残影的电路及阵列基板 Ceased WO2014169534A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/236,218 US9424796B2 (en) 2013-04-19 2013-07-02 Circuit for eliminating shut down image sticking and array substrate comprising the circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310138533.1 2013-04-13
CN201310138533.1A CN103280199B (zh) 2013-04-19 2013-04-19 一种消除关机残影的电路及阵列基板

Publications (1)

Publication Number Publication Date
WO2014169534A1 true WO2014169534A1 (zh) 2014-10-23

Family

ID=49062697

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/078706 Ceased WO2014169534A1 (zh) 2013-04-19 2013-07-02 消除关机残影的电路及阵列基板

Country Status (3)

Country Link
US (1) US9424796B2 (zh)
CN (1) CN103280199B (zh)
WO (1) WO2014169534A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106486085A (zh) * 2017-01-03 2017-03-08 京东方科技集团股份有限公司 移位寄存器电路、驱动方法、goa电路和显示装置
CN109003590B (zh) * 2018-08-30 2021-01-29 京东方科技集团股份有限公司 放电电路及显示装置
CN109068175B (zh) * 2018-08-31 2021-01-29 冠捷显示科技（厦门）有限公司 一种oled电视保护方法
CN109119016B (zh) * 2018-09-20 2021-10-29 上海中航光电子有限公司 一种显示面板及显示装置
CN109509417A (zh) * 2018-12-19 2019-03-22 惠科股份有限公司 显示面板驱动电路、显示装置及显示屏
CN109509413A (zh) * 2018-12-19 2019-03-22 惠科股份有限公司 显示面板测试电路、显示面板测试装置及显示屏
CN110133926B (zh) * 2019-04-04 2020-12-29 惠科股份有限公司 一种显示面板和显示装置
CN113436587B (zh) * 2021-06-22 2022-09-23 昆山龙腾光电股份有限公司 调控电路
CN115101020B (zh) * 2022-06-23 2024-01-26 惠科股份有限公司 控制电路和显示装置
CN115240583A (zh) * 2022-09-23 2022-10-25 广州华星光电半导体显示技术有限公司 残留电荷释放电路和显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1801303A (zh) * 2004-07-30 2006-07-12 统宝光电股份有限公司 残影消除电路、集成电路、显示器以及电子装置
CN1845233A (zh) * 2005-04-06 2006-10-11 中华映管股份有限公司 液晶显示器以及改善其残影现象的方法
CN101174038A (zh) * 2006-11-01 2008-05-07 群康科技(深圳)有限公司 液晶显示器
US20120212472A1 (en) * 2011-02-21 2012-08-23 Kenji Harada Liquid crystal display device and method of driving liquid crystal display device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100405026B1 (ko) * 2000-12-22 2003-11-07 엘지.필립스 엘시디 주식회사 액정표시장치
KR100863145B1 (ko) * 2001-02-16 2008-10-14 코닌클리케 필립스 일렉트로닉스 엔.브이. 디스플레이 장치
TWI354967B (en) * 2006-10-27 2011-12-21 Chimei Innolux Corp Liquid crystal display
CN101546529B (zh) * 2008-03-28 2011-06-15 群康科技(深圳)有限公司 液晶显示装置
TWI412982B (zh) * 2009-04-30 2013-10-21 Innolux Corp 影像顯示系統與輸入位置判斷方法
US8836626B2 (en) * 2011-07-15 2014-09-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for driving the same
KR101925993B1 (ko) * 2011-12-13 2018-12-07 엘지디스플레이 주식회사 방전회로를 포함하는 액정표시장치 및 액정표시장치 구동방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1801303A (zh) * 2004-07-30 2006-07-12 统宝光电股份有限公司 残影消除电路、集成电路、显示器以及电子装置
CN1845233A (zh) * 2005-04-06 2006-10-11 中华映管股份有限公司 液晶显示器以及改善其残影现象的方法
CN101174038A (zh) * 2006-11-01 2008-05-07 群康科技(深圳)有限公司 液晶显示器
US20120212472A1 (en) * 2011-02-21 2012-08-23 Kenji Harada Liquid crystal display device and method of driving liquid crystal display device

Also Published As

Publication number Publication date
US9424796B2 (en) 2016-08-23
CN103280199A (zh) 2013-09-04
CN103280199B (zh) 2015-08-19
US20150029172A1 (en) 2015-01-29

Similar Documents

Publication Publication Date Title
CN103280199B (zh) 一种消除关机残影的电路及阵列基板
US9997117B2 (en) Common circuit for GOA test and eliminating power-off residual images
JP6360892B2 (ja) アレイ基板及び液晶表示装置
US11335289B2 (en) Blur eliminating circuit
US9953561B2 (en) Array substrate of display apparatus and driving method thereof and display apparatus
CN104503113B (zh) 液晶面板及显示装置
CN105679266B (zh) 关机用电路、外围驱动装置和液晶面板
CN104297969A (zh) 液晶显示面板及其放电方法和显示装置
CN101546529B (zh) 液晶显示装置
US20080100331A1 (en) Liquid crystal display having discharging circuit
CN105913828A (zh) 残影消除电路、栅极驱动电路及显示装置
WO2013127224A1 (zh) 像素电路及其驱动方法、显示装置及显示方法
CN105489182B (zh) 显示基板和显示装置
WO2019033792A1 (zh) 阵列基板及其驱动方法和显示装置
CN116543716B (zh) 显示面板的驱动方法、公共电压输出电路及显示面板
US11088178B2 (en) Array substrate, display panel and display device
US20150340000A1 (en) Array substrate and method for driving the same, and liquid crystal display panel
US8217876B2 (en) Liquid crystal display for reducing residual image phenomenon
US8797249B2 (en) Thin-film transistor (TFT) array structure and liquid crystal display (LCD) panel thereof
US20140293180A1 (en) Liquid crystal display
CN106409252A (zh) 一种阵列基板及其驱动方法、显示面板、显示装置
JP6733054B2 (ja) Ｌｃｄアレイ基板、ｌｃｄパネル及びｌｃｄ画素回路
US9412322B2 (en) Liquid crystal display device and method for driving same
WO2020019657A1 (zh) 驱动电路及驱动方法
CN101344691B (zh) 像素电路、平面显示器及像素电路的驱动方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14236218

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13882427

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13882427

Country of ref document: EP

Kind code of ref document: A1