Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3824—Operand accessing
  • G06F9/383—Operand prefetching
  • G06F9/3832—Value prediction for operands; operand history buffers
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30003—Arrangements for executing specific machine instructions
  • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
  • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3824—Operand accessing
  • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
  • G06F9/3828—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage with global bypass, e.g. between pipelines, between clusters

Definitions

• the invention relates to microprocessors.
• a data dependency stall is the most common stall involving instructions attempting to dispatch to their respective pipelines for execution, where a stalled instruction waits for the producer of an operand to complete. Delays in forwarding the needed operand from its producer to the stalled instruction results in degraded CPU performance.
• Embodiments of the invention are directed to systems and methods for forwarding literal generated data to dependent instructions more efficiently using a cache for storing constants (literals or immediates).
• a processor includes a register, a first pipeline, a cache, and a controller.
• the controller stores a value in an entry in the cache in response to the first pipeline decoding an instruction, wherein the instruction writes the value to the register upon completing execution, and wherein the value is determined or available when the first pipeline decodes the instruction.
• the controller sets a tag field in the entry to tag the entry with the register, and sets a flag field in the entry to indicate that the entry is valid.
• the instruction may be a move immediate instruction.
• a method in another embodiment, includes decoding a first instruction in a first pipeline, wherein the first instruction writes a value to a register upon completing execution, and wherein the value is determined or available when the first pipeline decodes the first instruction.
• the method further includes storing the value in an entry in a cache; tagging the entry with the register; and setting the entry as valid.
• a processor in another embodiment, includes a first pipeline to decode a first instruction, wherein the first instruction writes a value to a register upon completing execution, and wherein the value is determined or available when the first pipeline decodes the first instruction.
• the processor further includes a means for storing, the means for storing to store the value in an entry in a cache; a means for tagging, the means for tagging to tag the entry with the register; and a means for setting, the means for setting to set the entry as valid.
• a non-transitory computer readable medium has stored instructions to cause a processor to perform a process.
• the process includes decoding a first instruction in a first pipeline, wherein the first instruction writes a value to a register upon completing execution, and wherein the value is determined or available when the first pipeline decodes the first instruction; storing the value in an entry in a cache; tagging the entry with the register; and setting the entry as valid.
• Figure 1 illustrates a processor according to an embodiment.
• Figure 2 illustrates a method according to an embodiment.
• Figure 3 illustrates a wireless communication system in which embodiments may find application.
• Figure 1 illustrates components of a processor 100, where for ease of illustration not all components are illustrated. Many processors are superscalar processor, employing more than one pipeline. Two pipelines are illustrated in Figure 1, labeled 102a and 102b, although in practice there may be more than two pipelines in a superscalar processor. For simplicity, three stages are shown in each pipeline, but in practice more than three stages are likely used. [0018] Illustrated in the pipelines of Figure 1 are instruction fetch stages 104a and 104b, decode stages 106a and 106b, and execution stages 108a and 108b.
• a pipeline may include other stages such as register fetch, hazard checking, cache hit detection, data fetch, and write back for loads and register-to-register operations, to name a few examples.
• a move instruction is a commonly used instruction for moving (copying or writing) data from one location to another.
• a move instruction is often written as MOV, and that convention will be followed here.
• a common use of a move instruction is to copy the value of a constant into an architected register.
• the constant value to be copied may be referred to as an immediate or literal.
• a move instruction for moving a constant to a register may be termed a move immediate instruction and written as MOV Rm ⁇ constant, where constant refers to the constant value and Rm refers to the architected register to which the constant value is written.
• the register Rm is labeled 118 and is illustrated as a register within the register file 120.
• an embodiment Upon decoding a move immediate instruction, an embodiment stores the constant as part of an entry in a cache, referred to as a constant cache and labeled 112 in Figure 1.
• An entry in the constant cache 112 is labeled 114 in Figure 1, and comprises three fields: a tag field labeled 114a, a constant field labeled 114b, and a flag field labeled 114c.
• the constant field 114b stores the constant value associated with the entry.
• the tag field 114a identifies the register to which the constant value is to be written (or moved).
• the flag field 114c comprises one or more bits to indicate the status of the entry 114. For some embodiment, the flag field 114c may be one bit in width, indicating whether the entry is valid or not.
• the constant cache 112 may be realized in the processor 100 as a register file. In the illustration of Figure 1, the constant cache 112 is shown as a separate structure from the register file 120. However, the constant cache 112 need not necessarily be independent of the register file 120. For example, the constant cache 112 may be part of the register file 120, or both structures may be included in a larger register file structure.
• a move immediate instruction requires no subsequent execution to calculate its result.
• a constant is generated, it is consumed immediately by a subsequent (in program order) consuming instruction.
• subsequent consuming instructions have access to the stored constant value before the constant value is written to the destination architected register.
• the contents of the constant cache 112 may be viewed as being organized into a table, where the constant value stored in an entry is written by a move immediate instruction and tagged according to the destination register of the move immediate instruction.
• execution of the consuming instruction need not wait for the result of the move immediate instruction to be forwarded, nor wait for the move immediate instruction to complete execution. Rather, the consuming instruction may use as its operand the constant value stored in the entry in the constant cache 112 associated with the move immediate instruction that it depends upon. As a result, no data forwarding is required and no data stall need occur regardless of whether the move immediate instruction has completed or is still in a pipeline.
• the move immediate instruction and the data dependent consuming instruction may be at the same stage in different pipelines, and yet for some embodiments the data dependent consuming instruction may obtain its operand with zero pipeline cycle delay.
• the flag field 114c associated with the entry is set to indicate that the contents of the entry are valid.
• the validity of an entry is checked before the immediate stored in the entry is forwarded to the consuming instruction. If the flag field associated with an entry indicates that the immediate stored in the entry is not valid, then the stored immediate is not forwarded to the consuming instruction.
• controller 110 may be configured so that for other types of instructions that write values to a destination register, an entry may be generated in the constant cache 112 as described with respect to the move immediate instruction, so that the stored value may be forwarded to a consuming instruction. Examples of such instructions are branch and link instructions, and program control relative branches, to name a few.
• the described embodiments may be apply to instructions that write a result to the register file, where the result can be determined by either information contained in the decode of the instruction or available at the time of decode. Such instructions do not have any operands that must read the register file.
• the embodiments disclosed herein are described for a move immediate instruction, where a move immediate instruction merely serves as example instruction for which embodiments may be of utility.
• the controller 110 invalidates any entry in the constant cache 114 with a tag matching the architected register. In this case, the controller 110 sets the flag field of the matching entry to a value indicating that the constant value stored in the entry is not valid.
• Controller 110 updates entries in the constant cache 114 according to the above- described embodiments. These actions are may be performed completely by hardware. For some embodiments, instructions stored in a memory, such as for example the memory 116, may carry out the above-described actions.
• the memory 116 may in general be a non-transitory computer readable medium.
• FIG. 2 illustrates the above-described actions.
• an instruction is decoded.
• the decoded instructions is a move immediate instruction, denoted as MOV R m #C to indicate that a constant value C is to be moved into architected register R m .
• step 206 indicates that the constant value C is stored in an entry in the constant cache 112, where the entry is tagged with the register R m , and the flag field of the entry is set to indicate that the entry is valid.
• the decoded instruction is a consumer of the architected register R m , as indicated in step 208, then provided there is a valid entry in the constant cache 112 associated (tagged) with the architected register R m , the constant value C stored in the constant field of that entry is forwarded to the consumer, as indicated in step 210. If the decoded instruction is an instruction that completes execution and writes (or copies) a constant value to the architected register R m , as indicated in step 212, then the controller 110 invalidates the entry (provided there is one) in the constant cache 112 associated (tagged) with the architected register R m , as indicated in step 214.
• Figure 3 illustrates a wireless communication system in which embodiments may find application.
• Figure 3 illustrates a communication network 302 comprising base stations 304A, 304B, and 304C.
• Figure 3 shows a communication device, labeled 306, which may be a mobile cellular communication device such as a cellular phone (e.g., a smart phone), a tablet, or other kind of communication device suitable for a cellular phone network, such as a computer system.
• the communication device 306 need not be mobile.
• the communication device 306 is located within the cell associated with the base station 304C.
• Arrows 308 and 310 pictorially represent the uplink channel and the downlink channel, respectively, by which the communication device 306 communicates with the base station 304C.
• Embodiments may be used in data processing systems associated with the communication device 306, or with the base station 304C, or both, for example.
• Figure 3 illustrates only one application among many in which the embodiments described herein may be employed.
• a software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
• An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
• an embodiment of the invention can include a computer readable media embodying a method for forwarding literal generated data to dependent instructions more efficiently using a constant cache.

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• General Physics & Mathematics (AREA)
• Advance Control (AREA)
• Executing Machine-Instructions (AREA)
• Memory System Of A Hierarchy Structure (AREA)

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• 2013
  • 2013-03-14 US US13/827,867 patent/US20140281391A1/en not_active Abandoned
• 2014
  • 2014-03-14 WO PCT/US2014/026907 patent/WO2014152064A1/en not_active Ceased
  • 2014-03-14 CN CN201480010778.9A patent/CN105009073B/zh not_active Expired - Fee Related
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