CN105009073B - 用于将数据更高效地转发到依赖指令的方法和设备 - Google Patents

用于将数据更高效地转发到依赖指令的方法和设备 Download PDF

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Publication number
CN105009073B
CN105009073B CN201480010778.9A CN201480010778A CN105009073B CN 105009073 B CN105009073 B CN 105009073B CN 201480010778 A CN201480010778 A CN 201480010778A CN 105009073 B CN105009073 B CN 105009073B
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China
Prior art keywords
instruction
entry
pipeline
constant value
register
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Expired - Fee Related
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CN201480010778.9A
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English (en)
Chinese (zh)
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CN105009073A (zh
Inventor
詹姆斯·诺里斯·迪芬德费尔
迈克尔·威廉·莫罗
罗德尼·韦恩·史密斯
杰弗里·M·斯科特米勒
丹尼尔·S·希格登
迈克尔·斯科特·麦克勒瓦伊内
布莱恩·迈克尔·斯坦普尔
库林·纳伦德拉·科塔里
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G06F9/3828—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage with global bypass, e.g. between pipelines, between clusters

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN201480010778.9A 2013-03-14 2014-03-14 用于将数据更高效地转发到依赖指令的方法和设备 Expired - Fee Related CN105009073B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/827,867 2013-03-14
US13/827,867 US20140281391A1 (en) 2013-03-14 2013-03-14 Method and apparatus for forwarding literal generated data to dependent instructions more efficiently using a constant cache
PCT/US2014/026907 WO2014152064A1 (en) 2013-03-14 2014-03-14 Method and apparatus for forwarding literal generated data to dependent instructions more efficiently using a constant cache

Publications (2)

Publication Number Publication Date
CN105009073A CN105009073A (zh) 2015-10-28
CN105009073B true CN105009073B (zh) 2019-01-15

Family

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Family Applications (1)

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CN201480010778.9A Expired - Fee Related CN105009073B (zh) 2013-03-14 2014-03-14 用于将数据更高效地转发到依赖指令的方法和设备

Country Status (6)

Country Link
US (1) US20140281391A1 (enExample)
EP (1) EP2972791B1 (enExample)
JP (1) JP6352386B2 (enExample)
KR (1) KR102055228B1 (enExample)
CN (1) CN105009073B (enExample)
WO (1) WO2014152064A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150019845A1 (en) * 2013-07-09 2015-01-15 Texas Instruments Incorporated Method to Extend the Number of Constant Bits Embedded in an Instruction Set
US10324723B2 (en) * 2014-07-02 2019-06-18 Nxp Usa, Inc. Systems and methods for processing both instructions and constant values from a memory of a digital processor accessed by separate pointers
US20160092219A1 (en) * 2014-09-29 2016-03-31 Qualcomm Incorporated Accelerating constant value generation using a computed constants table, and related circuits, methods, and computer-readable media
US20160170770A1 (en) * 2014-12-12 2016-06-16 Qualcomm Incorporated Providing early instruction execution in an out-of-order (ooo) processor, and related apparatuses, methods, and computer-readable media
US10671398B2 (en) * 2017-08-02 2020-06-02 International Business Machines Corporation Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4197580A (en) * 1978-06-08 1980-04-08 Bell Telephone Laboratories, Incorporated Data processing system including a cache memory
US5123097A (en) * 1989-01-05 1992-06-16 Bull Hn Information Systems Inc. Apparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategy
US5638526A (en) * 1991-11-20 1997-06-10 Fujitsu Limited Apparatus for operand data bypassing having previous operand storage register connected between arithmetic input selector and arithmetic unit
US6311261B1 (en) * 1995-06-12 2001-10-30 Georgia Tech Research Corporation Apparatus and method for improving superscalar processors
US6505293B1 (en) * 1999-07-07 2003-01-07 Intel Corporation Register renaming to optimize identical register values
CN1468397A (zh) * 2000-10-06 2004-01-14 ض� 寄存器移动操作
US20040024997A1 (en) * 2002-07-31 2004-02-05 Texas Instruments Incorporated Test with immediate and skip processor instruction
US20060095722A1 (en) * 2004-10-20 2006-05-04 Arm Limited Program subgraph identification

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04130942A (ja) * 1990-09-21 1992-05-01 Hitachi Ltd ディジタル信号処理装置
US6742112B1 (en) * 1999-12-29 2004-05-25 Intel Corporation Lookahead register value tracking
US7105576B2 (en) * 2002-04-24 2006-09-12 Research Development Foundation Synergistic effects of nuclear transcription factor NF-κB inhibitors and anti-neoplastic agents
SE527350C8 (sv) * 2003-08-18 2006-03-21 Gallaher Snus Ab Lock till snusdosa
US9557994B2 (en) * 2004-07-13 2017-01-31 Arm Limited Data processing apparatus and method for performing N-way interleaving and de-interleaving operations where N is an odd plural number
WO2007027671A2 (en) * 2005-08-29 2007-03-08 Searete Llc Scheduling mechanism of a hierarchical processor including multiple parallel clusters
US8176265B2 (en) * 2006-10-30 2012-05-08 Nvidia Corporation Shared single-access memory with management of multiple parallel requests
US7900027B2 (en) * 2008-01-31 2011-03-01 International Business Machines Corporation Scalable link stack control method with full support for speculative operations
US20100004994A1 (en) * 2008-07-02 2010-01-07 Global Launch Incorporated Methods for facilitating communications between businesses and consumers
US20110047357A1 (en) * 2009-08-19 2011-02-24 Qualcomm Incorporated Methods and Apparatus to Predict Non-Execution of Conditional Non-branching Instructions

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4197580A (en) * 1978-06-08 1980-04-08 Bell Telephone Laboratories, Incorporated Data processing system including a cache memory
US5123097A (en) * 1989-01-05 1992-06-16 Bull Hn Information Systems Inc. Apparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategy
US5638526A (en) * 1991-11-20 1997-06-10 Fujitsu Limited Apparatus for operand data bypassing having previous operand storage register connected between arithmetic input selector and arithmetic unit
US6311261B1 (en) * 1995-06-12 2001-10-30 Georgia Tech Research Corporation Apparatus and method for improving superscalar processors
US6505293B1 (en) * 1999-07-07 2003-01-07 Intel Corporation Register renaming to optimize identical register values
CN1468397A (zh) * 2000-10-06 2004-01-14 ض� 寄存器移动操作
US20040024997A1 (en) * 2002-07-31 2004-02-05 Texas Instruments Incorporated Test with immediate and skip processor instruction
US20060095722A1 (en) * 2004-10-20 2006-05-04 Arm Limited Program subgraph identification

Also Published As

Publication number Publication date
US20140281391A1 (en) 2014-09-18
WO2014152064A1 (en) 2014-09-25
KR102055228B1 (ko) 2019-12-12
KR20150129822A (ko) 2015-11-20
EP2972791A1 (en) 2016-01-20
CN105009073A (zh) 2015-10-28
EP2972791B1 (en) 2019-08-07
JP6352386B2 (ja) 2018-07-04
JP2016512366A (ja) 2016-04-25

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