WO2014150400A1 - Réduction des dislocations dans le plan basal dans du sic épitaxial au moyen d'un procédé de gravure in situ - Google Patents

Réduction des dislocations dans le plan basal dans du sic épitaxial au moyen d'un procédé de gravure in situ Download PDF

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WO2014150400A1
WO2014150400A1 PCT/US2014/023148 US2014023148W WO2014150400A1 WO 2014150400 A1 WO2014150400 A1 WO 2014150400A1 US 2014023148 W US2014023148 W US 2014023148W WO 2014150400 A1 WO2014150400 A1 WO 2014150400A1
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bpds
etching
bpd
etch
substrate
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PCT/US2014/023148
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Rachael L. MYERS-WARD
David Kurt Gaskill
Charles R. Eddy, Jr.
Robert E. Stahlbush
Nadeemmullah A. MAHADIK
Virginia D. WHEELER
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The Government Of The United States Of America, As Represented By The Secretary Of The Navy
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Publication of WO2014150400A1 publication Critical patent/WO2014150400A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/02447—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the present disclosure is generally related to SiC epitaxial growth.
  • the substrate BPDs are converted to threading edge dislocations (TEDs) and the resulting BPD density in the epitaxy is typically in the 100-1000 cm 2 range; a further reduction to ⁇ 1 cm 2 is required for device production, based on the area of desired devices.
  • TEDs threading edge dislocations
  • Another technique is to grow the epitaxial layers on wafers with an offcut angle lower than the standard 8° angle used for 4H-SiC (Chen et al., J. Appl. Phys. 98 (2005) 114907).
  • the tradeoff is that lowering the offcut angle tends to introduce 3C inclusions that degrade device performance (Kojima et al., J. Cryst. Growth, 269 (2004) 367-376).
  • Growth on 4° offcut substrates has also been demonstrated to convert BPDs to TEDs throughout the epitaxial growth process (U.S. Patent Appl. Pub. No. 2011/0045281).
  • a method comprising: providing an off-axis silicon carbide substrate; and etching the surface of the substrate with a dry gas, hydrogen, or an inert gas.
  • Fig. 1 shows a UVPL image of UID film showing various lengths of BPDs
  • Image sizes are 3 mm x 3 mm.
  • Fig. 2 shows BPD density as a function of etch temperature
  • Fig. 3 shows BPD density as a function of etch pressure.
  • the method may be employed in a wide range of bipolar SiC device technologies enabling them to achieve higher performance levels. Such devices range from power diodes and switches to rf transistors and UV photodetectors.
  • the purpose of using a hydrogen etch prior to a SiC epitaxial growth process on 4° off-axis substrates is to reduce BPDs within the active regions of SiC devices leading to improved device performance and reliability.
  • the etch process is used to increase the conversion of basal plane dislocations into threading edge dislocations and have the converted BPDs in a thin highly doped buffer layer.
  • BPDs cause increasing forward voltage drift in bipolar SiC devices and there are also reports in the literature that they can degrade majority carrier mobility and increase reverse-biased leakage (Agarwal et al., Elec. Dev. Lett., 28 (2007) 587).
  • BPD reduction processes that utilize epitaxial growth are all based on the principle of converting BPDs into TEDs, which have negligible adverse effects on the SiC devices.
  • an off-axis silicon carbide substrate is used, which may be, for example, a 4H-SiC substrate or a 6H-S1C substrate.
  • the off angle may be, but is not limited to, 4-8°.
  • the surface of the substrate is then etched with a dry gas, hydrogen, or an inert gas, such as argon.
  • the gas may include a halogen or silane addition, or may exclude such additions.
  • the etching may take place before any epitaxial growth or other processing steps. Suitable etching conditions include, but are not limited to, 1450-1800°C or 1620-1665°C, 30-500 or 40-130 mbar of the etching gas, and up to 5-90 minutes of etching.
  • a doped buffer layer may be grown on the substrate.
  • the buffer layer may be doped with, for example, N +" or P + , and may be about 0.5-30 ⁇ or 6.5-8 ⁇ thick.
  • An epitaxial silicon carbide layer may then be grown on the buffer layer.
  • X-ray diffraction (XRD) rocking curve maps of the symmetric (0008) reflection were analyzed to determine the off-cut angle of the substrates.
  • the manufacturer labels the wafers off -cut on the substrate wafer carrier, however, this is not always the exact off-cut. Additionally, this angle is not typically constant across the wafers (100, 75, or 50 mm) due to lattice curvature associated with the manufacturing process of the wafers.
  • the precise, spatially-resolved off-cut angle determined from the XRD rocking curve measurement maps was used for each sample in the NRL research investigation which typically consisted of a quartered 75 or 100 mm wafer to determine what a full length BPD would be if it extended through to the epi surface.
  • the third key ingredient was measuring the precise thickness of the epitaxial films, evaluated using Fourier transform infrared measurements.
  • the plan view length of a BPD could be converted to a z-axis distance that the BPD covered from the beginning of growth to where it ends. If the distance is found to be less than that of the epitaxial layer thickness, then the BPD is known to have converted in to a threading edge dislocation (TED). If the distance is equal to that of the epitaxial layer thickness, then the BPD did not convert to a TED in the epitaxial layer.
  • the injected carrier lifetimes of some of the samples were evaluated using room temperature time -resolved photoluminescence, were they varied from 1000 to 1800 ns.
  • the surface roughness of a film may also influence the device properties as well as make processing difficult; therefore, AFM analysis was also performed to determine surface roughness.
  • Samples investigated resulted in similar surface morphology, with a surface roughness of ⁇ 3.0 nm RMS.
  • Carrier concentrations were also measured on several of the samples using Hg probe CV measurements, where the net carrier concentration was ⁇ 2.5 x 10 14 cm "3 .
  • Table 1 summarizes the results of several experiments.
  • the films were either unintentionally (UID) or intentionally doped (ID) net carrier concentration ⁇ 4 x 10 14 cm “3 using a nitrogen source gas. All films were grown at a temperature of ⁇ 1600°C, pressure of 100 mbar and gas phase carbon-to- silicon (C/Si) ratio of 1.55 using an Aixtron VP508 reactor. The temperature was ramped from room temperature to a temperature of 1400°C in a hydrogen atmosphere. At this time, either the pressure was maintained at 100 mbar, or it was adjusted to a value between 40 mbar and 130 mbar. The temperature was then ramped to the etch temperature (between 1620°C and 1665°C).
  • the epitaxial layer may have less than 20, 10, 5, or 2 BPDs/cm 2 in the epitaxial layer or surface, or less than any of the BPD densities shown in Table 1.
  • the full length of continuous BPDs were determined using XRD rocking curve maps and film thicknesses found by using FTIR measurements.
  • the spatially-resolved XRD maps were used to determine the accurate off-cut angle of each quarter wafer prior to growth. After growth, incorporating the spatially-resolved thickness measurements combined with the off-cut angle, the expected full length BPD was determined.
  • the BPD lengths were then measured from the UVPL images using the software program, "ImageJ" by measuring the horizontal length from left to right of the BPD, see Fig. 1.
  • the lengths of the BPDs were then tallied and the conversion efficiency (number of BPDs that have converted to threading edge dislocations) was based on comparing the actual length of each BPD to the full length BPD.
  • the BPD density is found using KOH etching, which creates etch pits on the surface of the wafer, and these pits are counted.
  • KOH etching A low BPD density that has been published in the literature is 2.6 cm 2 using KOH etching (Chen et al., J. Appl. Phys. 98 (2005) 114907). If the above samples had been investigated using KOH etching, the BPD density would be zero for the majority of the samples. However, from the UVPL images, it can be seen that the BPDs are turning throughout the film on 4° off-cut substrates.
  • the number of BPDs in the active region may be much higher than what is at the surface of the epilayer. This means that conclusions given by prior investigations using the KOH etching approach are not accurate and have only limited value in developing methods for BPD reduction.
  • the UVPL technique By employing the UVPL technique, the total number of BPD in the entire active region is determined. Therefore, the result of 10 BPDs in the epilayer shown in Table 1 is significant.
  • a phenomenon called "step bunching” may influence the conversion of BPDs into TEDs during the growth of epitaxial films on 4 degree off-cut substrates.
  • the formation of multi-unit cell high surface steps may create a potential barrier to continued basal plane dislocation propagation out of the substrate and that an energy balance may be created that makes it more favorable for the BPD to convert to a TED than to continue propagating.
  • Ha et al., J. Cryst. Growth 244 (2002) 257-266 describes that the image force is the driving force of BPD conversion to TED, speculates that "when the critical distance is small in the range of several bilayers or several nanometers, a dislocation can see two surfaces of the step structure, the terrace and the step, which are different from the average off-axis surface.
  • etch pits may be formed on the surface and the BPDs may be converted to TEDs at the pit.
  • a hydrogen etch process prior to the epitaxial growth process on 4° off-axis enables the conversion of BPDs into TEDs - making it extremely manufacturable. It has been found experimentally that the BPDs convert to TEDs after the hydrogen etch process, followed by a thin, -6.5 ⁇ highly doped N + buffer layer and the lowest density of BPDs was 1.8 cm "2 . The process is easy to implement into a manufacturable process. Growing the N + buffer layer will enable one to bury the BPDs in a thinner buffer layer, producing a BPD free active region. This is the optimal situation as it will permit the economic realization of a wide range of high voltage, bipolar devices.
  • the first is patterning the surface of the SiC wafer before the epitaxial growth, which increases the BPD-to-TED conversion at the beginning of the growth. It has the tendency to increase other detrimental extended defects such as ingrown faults.
  • the second technique is to etch the wafer in molten KOH before epitaxial growth. This creates pits at each of the dislocations including the BPDs, and this technique also increases the BPD-to-TED conversion at the beginning of the growth.
  • the top of the growth surface remains pitted creating challenges for device manufacturing. An initial layer is grown and the wafer is polished to restore a smooth surface.
  • the third technique from Chen and Capano is to use wafers with a smaller offcut angle than the standard 8° angle. As with the previous techniques, it increases the BPD-to- TED conversion at the beginning of the growth. The tradeoff is that lowering the offcut angle results in step bunching which is more difficult to control. Further, such growths can lead to SiC polytype inclusions that are also device killers.
  • the reduction of BPDs relies on the conversion of BPDs to threading edge dislocations (TEDs) during the epitaxial growth process and/or the substrate/epilayer interface due to the etch process prior to growth as the surface is modified during the etch to improve the conversion of BPDs.
  • the growth process includes a step that consists of ramping the temperature from room temperature to growth temperature, during which time hydrogen is flowing. The etching takes place for a certain amount of time, after which the growth process takes place. There are many parameters which may be varied during the ramp process and the growth process which may influence the BPD conversion efficiency and rate.

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  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

L'invention concerne un procédé qui consiste à fournir un substrat en carbure de silicium excentré, et à graver la surface du substrat avec un gaz sec, de l'hydrogène ou un gaz inerte.
PCT/US2014/023148 2013-03-15 2014-03-11 Réduction des dislocations dans le plan basal dans du sic épitaxial au moyen d'un procédé de gravure in situ WO2014150400A1 (fr)

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Cited By (1)

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KR20180016585A (ko) * 2015-07-29 2018-02-14 신닛테츠스미킨 카부시키카이샤 에피택셜 탄화규소 단결정 웨이퍼의 제조 방법

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US4912064A (en) * 1987-10-26 1990-03-27 North Carolina State University Homoepitaxial growth of alpha-SiC thin films and semiconductor devices fabricated thereon
US20060011128A1 (en) * 2004-07-19 2006-01-19 Norstel Ab Homoepitaxial growth of SiC on low off-axis SiC wafers
US20070108450A1 (en) * 2004-03-01 2007-05-17 O'loughlin Michael J Reduction of carrot defects in silicon carbide epitaxy
WO2012067112A1 (fr) * 2010-11-17 2012-05-24 新日本製鐵株式会社 Procédé de fabrication d'un substrat monocristallin de carbure de silicium épitaxial

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US4912064A (en) * 1987-10-26 1990-03-27 North Carolina State University Homoepitaxial growth of alpha-SiC thin films and semiconductor devices fabricated thereon
US20070108450A1 (en) * 2004-03-01 2007-05-17 O'loughlin Michael J Reduction of carrot defects in silicon carbide epitaxy
US20060011128A1 (en) * 2004-07-19 2006-01-19 Norstel Ab Homoepitaxial growth of SiC on low off-axis SiC wafers
WO2012067112A1 (fr) * 2010-11-17 2012-05-24 新日本製鐵株式会社 Procédé de fabrication d'un substrat monocristallin de carbure de silicium épitaxial

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Title
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180016585A (ko) * 2015-07-29 2018-02-14 신닛테츠스미킨 카부시키카이샤 에피택셜 탄화규소 단결정 웨이퍼의 제조 방법
CN107709635A (zh) * 2015-07-29 2018-02-16 新日铁住金株式会社 外延碳化硅单晶晶片的制造方法
EP3330415A4 (fr) * 2015-07-29 2019-03-20 Showa Denko K.K. Procédé de production de plaquette de monocristal de carbure de silicium épitaxiale
US10626520B2 (en) 2015-07-29 2020-04-21 Showa Denko K.K. Method for producing epitaxial silicon carbide single crystal wafer
KR102106722B1 (ko) * 2015-07-29 2020-05-04 쇼와 덴코 가부시키가이샤 에피택셜 탄화규소 단결정 웨이퍼의 제조 방법
CN107709635B (zh) * 2015-07-29 2021-02-26 昭和电工株式会社 外延碳化硅单晶晶片的制造方法

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