WO2014131305A1

WO2014131305A1 - Apparatus and system for correcting capacitor on chip

Info

Publication number: WO2014131305A1
Application number: PCT/CN2013/089351
Authority: WO
Inventors: 周栋梁; 陆京辉; 刘永才; 谢豪律
Original assignee: 中兴通讯股份有限公司
Priority date: 2013-02-26
Filing date: 2013-12-13
Publication date: 2014-09-04
Also published as: CN104009747A

Abstract

Embodiments of the present invention disclose an apparatus and a system for correcting a capacitor on chip. The apparatus comprises a corrected resistor, a switch capacitor array, a comparator circuit, a logic control circuit, and a switch. A compactor outputs a comparison result to the logic control circuit by comparing voltages passing through the corrected resistor and the switch capacitor array, and then outputs a correction end signal, or controls opening or closing of the switch, and controls charge, discharge and comparison of the switch capacitor array according to the comparison result. By means of the apparatus and the method, the complexity of a comparator circuit can be reduced and the required commissioning range of a capacitor array is decreased, thereby improving the accuracy and precision of the capacitor correction.

Description

On-chip capacitance correcting device and method

Technical field

The present invention relates to the field of mobile communications, and in particular, to an on-chip capacitance correcting apparatus and method. Background technique

In a mobile communication system, such as an RF transceiver, as shown in Figure 1, a high-precision analog-to-digital converter (ADC), a receive link/transmit link filter (RX/TX Filter) is required. In order to achieve high precision ADC and Filter, high precision on-chip capacitors are required. However, general capacitors have a large error variation with process, temperature and other factors, such as TSMC 40匪 process. The capacitance error is approximately ± 20%. Therefore, a correction circuit is required to automatically correct the capacitance to achieve a high accuracy (for example, ± 1%).

The structure of the traditional calibration circuit is shown in Figure 2. In the figure, the corpse 1 ₂ flows through the resistor to generate a voltage V _l 1 ₂ to charge the capacitor to generate a voltage V ₂ . The comparator compares the voltage of V ₂ to adjust the capacitance. The purpose of debugging the filter. However, in this circuit structure, the resistance is similar to the capacitance, and there is a large error variation (error of ± 20%) with changes in process, temperature, etc., and therefore, the generated voltage V also changes. This will increase the accuracy and difficulty of the two voltage comparisons, and will also increase the range of debugging required for the capacitor array, thereby reducing the accuracy of the capacitance correction. Summary of the invention

The embodiment of the invention provides an on-chip capacitance correcting device and method for solving the problem that the accuracy and precision of the capacitance calibration circuit in the related art are low and the demand is not satisfied.

The technical solutions used in the embodiments of the present invention are as follows:

In one aspect, an embodiment of the present invention provides an on-chip capacitance correcting apparatus, including: a corrected resistor, a switched capacitor array, a comparator circuit, a logic control circuit, and a switch, wherein one end of the switch is grounded, and the other end is coupled to the switched capacitor array Connected

Input current I flows through the corrected resistor to generate a voltage VI;

The input current k1 charges the switched capacitor array for T time to generate a voltage V2; wherein k Is a positive integer;

The comparator circuit compares VI with V2 and outputs the comparison result to the logic control circuit;

The logic control circuit outputs a correction end signal when the VI is less than or equal to V2; the logic control circuit controls the switch to be closed when VI is greater than V2, and controls the switch to be off after the switched capacitor array is discharged to zero. After the switch capacitor array is controlled to decrease the set value of the capacitor value, the charging and comparing processes are repeated.

Optionally, the apparatus of the embodiment of the present invention further includes: a current mirror circuit, wherein the current I and the current k1 are currents output by the current mirror circuit.

Optionally, in the device of the embodiment of the invention, the comparator circuit performs a comparison wait after the charging capacitor array is charged for T time, and compares VI and V2 when the set comparison dwell time arrives.

Optionally, in the device of the embodiment of the invention, the sum of the charging time T, the comparison dwell time, and the discharging time is one clock cycle.

Optionally, in the device of the embodiment of the invention, the set value of the capacitance is a unit capacitance value.

On the other hand, an embodiment of the present invention provides an on-chip capacitance correction method, which is applied to the calibration apparatus of the embodiment of the present invention, and includes:

The input current I flows through the corrected resistor to generate a voltage VI; the input current k1 charges the switched capacitor array for a time T to generate a voltage V2; wherein k is a positive integer;

The logic control circuit outputs a correction end signal when the VI is less than or equal to V2; the logic control circuit controls the switch to be closed when VI is greater than V2, and controls the switch to be turned off after the discharge capacitor array is discharged to zero, and controls After the switched capacitor array reduces the set capacitance value, the input current I flows through the corrected resistor to generate a voltage VI; the input current k1 charges the switched capacitor array for a T time to generate a voltage V2.

Optionally, in the method of the embodiment of the present invention, the input current I flows through the corrected resistor. The voltage VI is generated; the input current k1 charges the switched capacitor array for T time, and the generated voltage V2, the current I and the current k1 are the currents output by the current mirror circuit.

Optionally, in the method of the embodiment of the present invention, the comparator circuit compares VI and V2, and outputs the comparison result to a logic control circuit, where the comparator circuit charges T in the switched capacitor array. After the time, the comparison waits and compares VI and V2 when the set comparison dwell time arrives.

Optionally, in the method of the embodiment of the present invention, the sum of the charging time T, the comparison dwell time, and the discharging time is one clock cycle.

Optionally, in the method of the embodiment of the present invention, the set value of the capacitance is a unit capacitance value.

The beneficial effects of the embodiments of the present invention are as follows:

The method and apparatus of the embodiments of the present invention not only can reduce the difficulty of the comparator circuit by using the corrected resistance, but also reduce the range of debugging required for the capacitor array, and improve the accuracy of the capacitance correction. BRIEF abstract

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are set forth in the accompanying claims Other drawings can also be obtained from these drawings on the premise of creative labor.

1 is a scenario diagram of an on-chip capacitor application in the related art;

2 is a structural diagram of a capacitance correcting circuit in the related art;

3 is a structural block diagram of an on-chip capacitance correcting apparatus according to Embodiment 1 of the present invention;

4 is a structural block diagram of an on-chip capacitance correcting apparatus according to Embodiment 2 of the present invention;

5 is a flowchart of implementing capacitance correction by the apparatus according to Embodiment 2 of the present invention;

FIG. 6 is a flowchart of a method for correcting on-chip capacitance according to Embodiment 3 of the present invention. Preferred embodiment of the invention

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

Embodiments of the present invention provide an on-chip capacitance correction apparatus and method. The device uses a corrected resistor R-cal for capacitance correction, which greatly improves the calibration accuracy, and the correction accuracy of the resistor is higher, and the correction accuracy of the capacitor is also increased. In this embodiment, the correction accuracy of the resistor is recommended. Up to ± 1%. It should be noted that, in this embodiment, the method for correcting the resistance is not specifically limited, and those skilled in the art can perform resistance correction according to any correction technology currently available, and the correction accuracy is higher.

The embodiment provides an on-chip capacitance correcting device. As shown in FIG. 3, the method includes: a corrected resistor R-cal, a switched capacitor array Cap-switch, a comparator circuit, a logic control circuit, and a switch SW, wherein the switch SW- The terminal is grounded, and the other end is connected to the switched capacitor array;

The input current I flows through the corrected resistor R_cal to generate a voltage VI;

The input current k1 charges the switched capacitor array Cap-switch for a time T, and generates a voltage V2; wherein k is a positive integer;

The comparator circuit compares VI and V2, and outputs the comparison result to the logic control circuit; the logic control circuit outputs a correction end signal when the VI is less than or equal to V2; when the VI is greater than V2, the control switch SW is closed, and the capacitor array to be switched After the Cap-switch is discharged to zero, the control switch SW is turned off, and after the capacitor array of the control switch SW is decreased by the set amount of capacitance, the above charging and comparison processes are repeated.

Optionally, the comparator circuit compares and waits after the switched capacitor array Cap-switch is charged for T time, and compares VI and V2 when the set comparison dwell time arrives. That is to say, after the comparator circuit is charged by the Cap-switch of the switched capacitor array, the voltage comparison is not immediately performed, but waits for a period of time, and after the V2 is stabilized, the comparison is performed, which can further improve the correction accuracy. Optionally, in this embodiment, the sum of the charging time τ, the comparison dwell time, and the discharging time is one clock cycle; and the capacitance of the set amount is a unit capacitance value.

Embodiment 2

An embodiment of the present invention provides an on-chip capacitance correcting device, as shown in FIG. 4, including a Comparator circuit (comparator circuit), an R_cal resistor (corrected resistor), an OPA circuit (op amp circuit), and a Cap_switch (switched capacitor array). Mirror circuit (current mirror circuit), SW (switch), SAR-logic control circuit (successive approximation logic control circuit). The SAR-logic control circuit is used to gradually reduce the capacitance value in the Cap-switch circuit, and the Comparator circuit continuously compares the voltage values on the R eal resistor and the Cap-switch circuit to achieve high-accuracy capacitance correction.

In this embodiment, an appropriate Vref and a desired R-cal resistance value are selected according to specific needs. The current I generates a voltage VI through the R-cal resistor, while the current I charges the capacitor in the Cap-switch circuit through a high-precision (within ± 1%) current mirror k1 and generates a voltage V ₂ ; , V! =1^ cal , ^c , C is the capacitance value of Cap-switch. Based on the above circuit structure, the overall flow chart of the capacitance correction in the present embodiment will be described in detail below, as shown in FIG. When the SAR-logic control circuit receives a signal that the correction starts, at the beginning of one clock cycle, SW is turned off. At this time, the current kl starts to charge the Cap-switch circuit (the charging time is T, which is half of the clock cycle). V2 starts to increase slowly. After T time, the charging stops. At this time, in order to keep the voltage V2 on the Cap-switch circuit unchanged to ensure the accuracy of the comparison between VI and V2, the SW is still disconnected (compare The time is a quarter of a time period). When it is detected that the VI is less than or equal to V2, the Comparator circuit outputs a correction end signal, and the correction ends. When it is detected that the VI is greater than V2, there is no correction signal output. After the comparison time is over, in order to ensure the accuracy of the next cycle comparison and the accuracy of the overall correction circuit, the SW starts to be turned on so that Cap- The charge in the switch begins to be released until the voltage V2 is zero. For sufficient discharge, the discharge time is a quarter time period. At the same time, the SAR logic control circuit reduces the capacitance of an LSB in the Cap-switch. When the next clock cycle begins, the SW is again disconnected, and the current kl begins to charge the adjusted Cap-switch again. V2 again Slowly rise, after charging T time, the charging stops, the Comparator circuit compares the VI and V2 again, so that the charging, comparing, discharging and SAR-logic control circuits reduce the capacitance of an LSB in the Cap-switch. When the Comparator circuit detects that V2 is greater than or equal to VI, it outputs a correction end signal and the calibration ends. At this time, the capacitance value in the Cap-switch is the corrected high-precision capacitance.

Embodiment 3

As shown in FIG. 6, the embodiment of the present invention provides an on-chip capacitance correction method, which is applied to the calibration apparatus according to the first or second embodiment, and specifically includes:

Step S601, the input current I flows through the corrected resistor to generate a voltage VI; the input current k1 charges the switched capacitor array for a time T, and generates a voltage V2; wherein k is a positive integer;

Optionally, in this step, the current I and the current k1 are currents output by the current mirror circuit, and the k is a proportional coefficient of the replica current.

Step S602, the comparator circuit compares VI with V2, and outputs the comparison result to the logic control circuit;

Optionally, in this step, the comparator circuit waits for comparison after the charging capacitor array is charged for T time, and compares VI and V2 when the set comparison dwell time arrives.

Step S603, the logic control circuit outputs a correction end signal when the VI is less than or equal to V2; otherwise, the control switch is closed, and after the switched capacitor array is discharged to zero, the switch is controlled to be turned off, and the switched capacitor array is controlled to be reduced. After a small amount of capacitance value is returned, the process returns to step S601.

Optionally, in this step, the set value of the capacitance value is a unit capacitance value;

Alternatively, the sum of the above charging time τ, the comparison dwell time, and the discharge time is one clock cycle.

In summary, the apparatus and method provided by the embodiments of the present invention can not only reduce the difficulty of the comparator circuit but also reduce the range of debugging required by the capacitor array, and improve the capacitance by performing capacitance correction using the corrected resistor. The accuracy of the correction. The spirit and scope of the invention. Thus, if such modifications and variations of the present invention are claimed in the present invention The invention is also intended to cover such modifications and variations within the scope of the invention.

INDUSTRIAL APPLICABILITY The method and apparatus of the embodiments of the present invention can not only reduce the difficulty of the comparator circuit but also reduce the range of debugging required for the capacitor array by improving the capacitance correction by using the corrected resistor, and improve the capacitance correction. Precision.

Claims

claims

1. An on-chip capacitance correction device, including: a corrected resistor, a switched capacitor array, a comparator circuit, a logic control circuit, and a switch, one end of the switch is grounded, and the other end is connected to the switched capacitor array;

The input current I flows through the corrected resistor, generating a voltage VI;

The input current kl charges the switched capacitor array for T time to generate voltage V2; where k is a positive integer;

The comparator circuit compares VI with V2 and outputs the comparison result to the logic control circuit; and

The logic control circuit outputs a correction end signal when VI is less than or equal to V2; the logic control circuit controls the switch to close when VI is greater than V2, and controls the switch to open after the switched capacitor array is discharged to zero. After turning on and controlling the switched capacitor array to reduce the capacitance value by a set amount, the charging and comparison process is repeated.

2. The device according to claim 1, wherein the device further includes: a current mirror circuit, and the current I and the current kl are currents output by the current mirror circuit.

3. The device according to claim 1 or 2, wherein the comparator circuit waits for comparison after charging the switched capacitor array for T time, and when the set comparison dwell time is reached, compares VI and V2 Compare.

4. The device according to claim 3, wherein the sum of the charging time T, the comparison dwell time, and the discharging time is one clock cycle.

5. The device according to claim 1, 2, or 4, wherein the set amount of capacitance value is a unit capacitance value.

6. A method for on-chip capacitance correction using the device of claim 1, including: input current I flows through the corrected resistor to generate voltage VI; input current kl charges the switched capacitor array for T time to generate voltage V2; wherein, k is a positive integer;

The logic control circuit outputs a correction end signal when VI is less than or equal to V2; the logic control circuit When VI is greater than V2, the circuit controls the switch to close, and after the switched capacitor array is discharged to zero, it controls the switch to open, and after controlling the switched capacitor array to reduce the capacitance value by a set amount, the input current I flows. After the corrected resistance, the voltage VI is generated; the input current kl charges the switched capacitor array for T time, generating the voltage V2.

7. The method of claim 6, wherein the input current I flows through the corrected resistor to generate the voltage VI; the input current kl charges the switched capacitor array for T time to generate the voltage V2, the current I and the current kl are The current output by the current mirror circuit.

8. The method according to claim 6 or 7, wherein the comparator circuit compares VI and V2 and outputs the comparison result to the logic control circuit, and the comparator circuit charges the switched capacitor array After T time, wait for comparison, and when the set comparison dwell time arrives, compare VI and V2.

9. The method of claim 8, wherein the sum of the charging time T, the comparison dwell time, and the discharging time is one clock cycle.

10. The method of claim 6, 7, or 9, wherein the set amount of capacitance value is a unit capacitance value.