CN201766572U - DAC calibration circuit - Google Patents

Abstract

The utility model relates to a DAC calibration circuit, including a first switch, a second switch, a first comparator, a second comparator, a capacitor, and a calibration module. The first switch is connected between a LSB unit and the capacitor so as to make the LSB unit to charge the capacitor based on control of a first signal. The second switch is connected between a MSB unit and the capacitor so as to make the MSB unit to charge the capacitor based on control of a second signal. A homophase end of the first comparator is connected to a connection point of the MSB unit, the LSB unit and the capacitor, and an antiphase end is of a first fixed voltage. A homophase end of the second comparator is connected with the homophase end of the first comparator, an antiphase end of the second comparator is of a second fixed voltage. The calibration module is connected with output ends of the first comparator and the second comparator, so as to adjust current of the MSB unit and/or LSB unit real time. The calibration circuit has a high calibration accuracy and can be widely used for high precision DAC.

Description

A kind of DAC calibration circuit

Technical field

The utility model relates to mixed signal circuit, relates in particular to DAC (digital-to-analogconverter, digital analog converter).

Background technology

N position precision current mode DAC circuit is made up of two parts usually, and a part is by 2 of MSB (MostSignificant Bit, highest significant position) unit current source composition ^a-1 cell array, another part are by 2 of LSB (Least Significant Bit, least significant bit) unit current source composition ^b-1 cell array, and satisfy

n＝a+b

I _MSB＝2 ^b·I _LSB (1)

I _total＝(2 ^a-1)·I _MSB+(2 ^b-1)·I _LSB

Wherein, n is the precision figure place of DAC circuit, I _MSBBe the electric current of MSB unit, I _LSBBe the electric current of LSB unit, I _TotalIt is the total current of DAC circuit.

Fig. 1 is a current mode DAC structural representation, wherein, and the MSB piece schematic diagram that left figure is made up of the MSB unit, the LSB piece schematic diagram that right figure is made up of the LSB unit.

Among Fig. 1, the MSB piece is provided with bias voltage by two different biasings (bias) circuit respectively with the LSB piece and produces electric current.Because the factor of chip technology can cause MSB electric current and LSB quiescent current not to match, this is very fatal in high-precision DAC design.In order to mate MSB and LSB electric current, can in chip, add a calibration circuit (calibration) usually, make MSB and LSB current error not influence the static properties of DAC.

Fig. 2 is traditional DAC calibration circuit structured flowchart, and this calibration circuit comprises MSB unit, LSB unit, resistance R 1, resistance R 2 and comparator OA.

Among Fig. 2, the MSB unit links to each other with resistance R 1, the LSB unit links to each other with resistance R 2, and comparator OA in-phase end is connected to the tie point V2 between MSB unit and the resistance R 2, comparator OA end of oppisite phase is connected to the tie point V1 between LSB unit and the resistance R 1, comparator OA output is connected to the MSB unit adjusting the MSB cell current, and resistance R 2, R1 satisfy

R2＝2 ^b·R1 (2)

Wherein, 2 ^bRelation between expression LSB cell current and the MSB cell current.

Because V is connected with resistance R 1 in the MSB unit ₁=I _MSBR1, V is connected with resistance R 2 in the LSB unit ₂=I _LSBR2, so V1, V2 voltage difference delta V are

ΔV＝I _MSB·R1-I _LSB·R2 (3)

Formula (2) substitution formula (3) is got,

$I_{\mathrm{MSB}}-I_{\mathrm{LSB}}\·2^b=\frac{\mathrm{\ΔV}}{R1}---\left(4\right)$

Comparator OA is V1, V2 voltage difference relatively, and adjusts the electric current of MSB unit according to its comparative result, and when this voltage difference delta V was in the design allowed band, calibration finished.

There are two inherent shortcomings in conventional calibration circuit among Fig. 2, and one is the matching error of resistance R 1, R2 itself, and another is the DC deviation (DC offset) of comparator OA itself.These two kinds of design defect can make the comparative result of comparator have certain error, directly cause MSB electric current and LSB quiescent current well to be mated, and therefore, this kind calibration circuit can't be applied among the high-precision DAC.

The utility model content

The utility model provides a kind of DAC calibration circuit that can overcome the above problems.

In first aspect, the utility model provides a kind of DAC calibration circuit.This DAC calibration circuit comprises MSB unit, LSB unit, first switch, second switch, first comparator, second comparator, electric capacity and calibration circuit.

This first switch is connected between LSB unit and the electric capacity, so that it is based on the control of first signal and this LSB unit is charged to electric capacity.This second switch is connected between MSB unit and the electric capacity, so that it is based on the control of secondary signal and this MSB unit is charged to electric capacity.This first comparator in-phase end is connected to the tie point between MSB unit, LSB unit, the electric capacity, and its end of oppisite phase is first fixed voltage, and its output is connected to calibration module.This second comparator in-phase end links to each other with this first comparator in-phase end, and its end of oppisite phase is second fixed voltage, and its output is connected to calibration module.This calibration module receives the comparative result of this first comparator, second comparator, and adjusts MSB unit and/or LSB cell current in real time based on this comparative result, so that MSB cell current and LSB cell current are complementary.

The utility model compares LSB unit, MSB cell current in the DAC circuit for twice, and the DC deviation that relatively produces obtained in the comparison procedure offsetting in the second time for the first time, therefore solved the error of bringing by the comparator DC deviation, in addition, the utility model adopts the capacitor charge and discharge mode to obtain voltage, replace the mode of obtaining voltage in the traditional circuit by two resistance respectively, therefore solved unmatched problem between two different resistance.Therefore, DAC calibration circuit of the present utility model is a high-precision calibration circuit, and it can extensively be incorporated in the high-precision DAC circuit.

Description of drawings

Below with reference to accompanying drawings specific embodiments of the present utility model is described in detail, in the accompanying drawings:

Fig. 1 is a current mode DAC structural representation;

Fig. 2 is traditional DAC calibration circuit structured flowchart;

Fig. 3 is the DAC calibration circuit structured flowchart of an embodiment of the utility model.

Embodiment

Fig. 3 is the DAC calibration circuit structured flowchart of an embodiment of the utility model, and this calibration circuit comprises MSB unit, LSB unit, K switch 1, K switch 2, clock L1, clock L2, capacitor C, comparator OA1, comparator OA2, voltage source V 1, voltage source V 2, calibration module 310.

The MSB unit links to each other with K switch 1, with the conducting state of control MSB unit; The LSB unit links to each other with K switch 2, with the conducting state of control LSB unit; Clock L1 clock signal is to K switch 1, with the opening and closing of control switch K1; Clock L2 also clock signal to K switch 2, with the opening and closing of control switch K2.

K switch 1, K2 and capacitor C are connected in the n point, so that by K switch 1, K2 opening control MSB unit or LSB unit discharging and recharging capacitor C.Particularly, the MSB unit charges to capacitor C when K switch 1 closure, and the LSB unit charges to capacitor C when K switch 2 closures.If the tie point between K switch 1, K2 and the capacitor C (n point) voltage is Vn, promptly MSB unit or LSB unit charging voltage that capacitor C is charged is Vn.

Comparator OA1 in-phase end links to each other with capacitor C, K switch 1, K switch 2, and (tie point is a), so comparator OA1 homophase input voltage is the charging voltage Vn that MSB unit or LSB unit charge to capacitor C; Comparator OA1 end of oppisite phase links to each other with voltage source V 1, so this comparator OA1 is used for the size of comparison Vn and V1, and comparative result OP1 is sent to calibration module 310.End links to each other with capacitor C and comparator OA1 in-phase end comparator OA2 in the same way that (tie point is a), so comparator OA1 homophase input voltage is the charging voltage Vn that MSB unit or LSB unit charge to capacitor C; Comparator OA2 end of oppisite phase links to each other with voltage source V 2, so this comparator OA2 is used for the size of comparison Vn and V2, and comparative result OP2 is sent to calibration module 310.

Elaborate the operation principle of calibration module 310, MSB unit, LSB unit, K switch 1, K switch 2 below.

The voltage that the voltage that setting voltage source V1 produces produces less than voltage source V 2, i.e. V1＜V2.When clock L2 control switch K2 was closed, LSB charged to capacitor C the unit, and charging voltage is Vn, through the t2 time, made V1＜Vn＜V2, and this time t2 is controlled by clock L2 and obtains.At this moment, the output signal OP1 that comparator OA1 exports calibration module 310 to is a high level, and the output signal OP2 that comparator OA2 exports calibration module 310 to is a low level, and this moment, calibration module 310 was not taked any operation.

When clock L1 control switch K1 is closed, MSB charges to capacitor C the unit, through t1 time (this time t1 control and obtain) by clock L1, calibration module 310 judges that specifically adjustment mode has two kinds from the output OP1 of comparator OA1 and from the output OP2 of comparator OA2 and according to this OP1, OP2 magnitude relationship adjustment MSB cell current size:

(1) when OP1 and OP2 are high level, promptly during V1＜V2＜Vn, calibration module 310 is adjusted the electric current I of MSB unit _MSB, reduce the MSB electric current I _MSB

(2) when OP1 and OP2 are low level, promptly during Vn＜V1＜V2, calibration module 310 increases the electric current I of MSB unit _MSB

Adjusting so repeatedly, is high level up to OP1, and OP2 is a low level, and calibration module 310 calibrations finish.

After calibration finishes, according to the capacitor charge and discharge formula

As can be known, MSB electric current I _MSBWith the LSB electric current I _LSBBetween error can represent by following formula,

I _LSB·t2-I _MSB·t1＝(V2-V1)·C (5)

Promptly

I _LSB·t2-I _MSB·t1＝ΔV·C (6)

Make t2=2 ^bT1 is then with t2=2 ^bT1 substitution formula (6),

$I_{\mathrm{LSB}}\·2^b-I_{\mathrm{MSB}}=\frac{\mathrm{\ΔV}\·C}{t1}---\left(7\right)$

The difference that voltage V1, V2 are set is enough little, and promptly Δ V is enough little, then I _LSB2 ^b≈ I _MSB, so Fig. 3 calibration circuit has very high calibration accuracy.

By above narration as can be known, the utility model calibration circuit is for the conventional calibration circuit, and at first, what the utility model adopted is a capacitor C, and the conventional calibration circuit adopts is two resistance (R1 and R2), so the utility model can not cause error because of R1, R2 mismatch problem; Secondly, the utility model compares Vn, V1, V2 voltage by twice, the DC deviation that relatively produce the feasible first time obtained in the comparison procedure offsetting in the second time, so there is not the problem of being brought error in the conventional calibration circuit by the comparator DC deviation in the utility model.

Preferably, the switch of employing small size or big electric capacity are with solution, thereby the employing on-off mode carries out introducing in the charging process problem that electric charge brings the Vn error to capacitor C.

Preferably, adopt high accuracy clock L1 control K1 closing time, thereby make time t1 error minimum, adopt high accuracy clock L2 control switch K2 closing time simultaneously, thereby make time t2 error minimum.In addition, also can adopt a high precision clock to come the closing time of control switch K1 and K switch 2.

Need to prove, more than only with by calibration module 310 calibration MSB cell current I _MSBFor example is set forth, in fact also can calibrate LSB cell current I _LSB, perhaps promptly calibrate MSB cell current I _MSBAlso calibrate simultaneously LSB cell current I _LSB

Obviously, under the prerequisite that does not depart from true spirit of the present utility model and scope, the utility model described here can have many variations.Therefore, the change that all it will be apparent to those skilled in the art that all should be included within the scope that these claims contain.The utility model scope required for protection is only limited by described claims.

Claims (4)

1. DAC calibration circuit, wherein, this DAC calibration circuit comprises MSB unit and LSB unit, it is characterized in that, comprises first switch, second switch, first comparator, second comparator, electric capacity and calibration circuit;

This first switch is connected between described LSB unit and the electric capacity, so that it is based on the control of first signal and this LSB unit is charged to this electric capacity; This second switch is connected between described MSB unit and the electric capacity, so that it is based on the control of secondary signal and this MSB unit is charged to this electric capacity;

This first comparator in-phase end is connected to the tie point between this MSB unit, LSB unit, the electric capacity, and its end of oppisite phase is first fixed voltage (V1), and its output is connected to described calibration module; This second comparator in-phase end links to each other with this first comparator in-phase end, and its end of oppisite phase is second fixed voltage (V2), and its output is connected to described calibration module;

This calibration module links to each other with the output of this first comparator, second comparator, to receive the comparative result of this first comparator, second comparator, and adjust MSB unit and/or LSB cell current in real time based on this comparative result, so that MSB cell current and LSB cell current are complementary.

2. a kind of DAC calibration circuit as claimed in claim 1, it is characterized in that, comprise first clock and second clock, this first clock is used to produce described first signal, this second clock is used to produce described secondary signal, and this first clock, second clock are high precision clock.

3. a kind of DAC calibration circuit as claimed in claim 1 is characterized in that, comprises clock, and this clock is used to produce described first signal, secondary signal, and this clock is a high precision clock.

4. a kind of DAC calibration circuit as claimed in claim 1 is characterized in that described switch is the small size switch, and described electric capacity is big capacitance electric capacity.

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