WO2014119810A1 - Mems device manufacturing method - Google Patents

Mems device manufacturing method Download PDF

Info

Publication number
WO2014119810A1
WO2014119810A1 PCT/KR2013/000832 KR2013000832W WO2014119810A1 WO 2014119810 A1 WO2014119810 A1 WO 2014119810A1 KR 2013000832 W KR2013000832 W KR 2013000832W WO 2014119810 A1 WO2014119810 A1 WO 2014119810A1
Authority
WO
WIPO (PCT)
Prior art keywords
amorphous carbon
carbon film
forming
layer
insulating support
Prior art date
Application number
PCT/KR2013/000832
Other languages
French (fr)
Korean (ko)
Inventor
임성규
김영수
김희연
강민호
오재섭
이귀로
Original Assignee
한국과학기술원
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 한국과학기술원 filed Critical 한국과학기술원
Priority to PCT/KR2013/000832 priority Critical patent/WO2014119810A1/en
Priority to CN201380071919.3A priority patent/CN104955765B/en
Publication of WO2014119810A1 publication Critical patent/WO2014119810A1/en

Links

Images

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00555Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
    • B81C1/00595Control etch selectivity
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00Basic microelectromechanical structures
    • B81B2203/01Suspended structures, i.e. structures allowing a movement
    • B81B2203/0109Bridges
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00Manufacture or treatment of microstructural devices or systems
    • B81C2201/01Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0102Surface micromachining
    • B81C2201/0105Sacrificial layer
    • B81C2201/0109Sacrificial layers not provided for in B81C2201/0107 - B81C2201/0108
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00Manufacture or treatment of microstructural devices or systems
    • B81C2201/01Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0128Processes for removing material
    • B81C2201/013Etching
    • B81C2201/0133Wet etching

Definitions

  • the present invention relates to semiconductor devices, and more particularly, to a MEMS (Micro Electro Mechanical Systems) device and a manufacturing method thereof.
  • MEMS Micro Electro Mechanical Systems
  • MEMS devices refer to devices incorporating mechanical component parts, sensors, actuators, and electronic circuits on a single silicon substrate, and are currently available as printer heads, pressure sensors, acceleration sensors, gyroscopes, and DMDs. Projector).
  • sacrificial layer etching which is not used for fabricating a semiconductor integrated circuit, needs to be formed because the semiconductor integrated circuit is manufactured as a process of processing a plane. Included. This process uses a sacrificial layer and a structure thin film on a silicon substrate to pattern the shape of the structure and remove the sacrificial layer to fabricate the structure. Silicon or organic polyimide (Polyimide) has been used as a sacrificial layer for maintaining a constant space between the lower electrode or the lower structure and the upper structure.
  • the etching selectivity with the oxide film is excellent, but the etching selectivity with the metal such as nitride film and tungsten is not good, and the polyimide is used as the sacrificial layer.
  • the quality is reduced by using a lift off method that is contained, and proceeds at a low temperature in the subsequent process.
  • the present invention is to solve the various problems including the above problems, has an excellent etching selectivity with various kinds of inorganic materials, and can easily adjust the thickness of the film according to the device, the conventional MEMS in terms of performance and shape It is an object of the present invention to provide a MEMS device and a manufacturing method which are superior to devices and can utilize existing semiconductor processes.
  • these problems are exemplary, and the scope of the present invention is not limited thereby.
  • the method of manufacturing a MEMS device includes forming a lower structure; Forming an amorphous carbon film on the lower structure as a sacrificial layer; Forming an insulating support layer on the amorphous carbon film; Forming an etch passivation layer on the insulating support layer and etching the insulating support layer and the amorphous carbon film at once to form via holes through the insulating support layer and the amorphous carbon film to expose the lower structure; Forming an upper structure including a sensor structure on the insulating support layer; Forming at least one through hole penetrating the insulating support layer; And removing all of the amorphous carbon film through the through holes so that the lower structure and the upper structure are spaced apart from each other.
  • the step of forming the amorphous carbon film may be performed using chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • removing the amorphous carbon film may include a dry etching method.
  • the dry etching method may be performed by using an oxygen (O 2 ) plasma.
  • the forming of the upper structure may further include forming an insulating support layer on the amorphous carbon film.
  • the manufacturing method may further include forming metal anchors on the lower electrodes to be connected to the lower electrodes through the via holes.
  • the forming of the upper structure may further include forming an absorbing layer on the insulating support layer.
  • the lower structure may include a read integrated circuit (ROIC) for controlling the sensor structure.
  • ROIC read integrated circuit
  • the sensor structure may include an infrared sensor.
  • forming the via holes exposing the lower structure through the insulating support layer and the amorphous carbon film may be performed by only one photolithography process.
  • the present invention has an excellent etching selectivity with various kinds of inorganic materials, it is easy to adjust the thickness of the film according to the device is superior to the conventional MEMS device in terms of performance and shape
  • MEMS devices that can utilize existing semiconductor processes can be implemented.
  • the scope of the present invention is not limited by these effects.
  • 1 to 6 are cross-sectional views schematically showing a MEMS device and a method of manufacturing the same according to an embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional view of a MEMS device manufactured in accordance with another embodiment of the present invention.
  • FIGS. 8 to 11 are cross-sectional views illustrating a method of manufacturing a MEMS device according to another embodiment of the present invention.
  • 1 to 6 are cross-sectional views schematically showing a MEMS device and a method of manufacturing the same according to an embodiment of the present invention.
  • a lower structure 12 may be provided.
  • the lower structure 12 may include a suitable logic circuit, such as a Read Out Integrated Circuit (ROIC).
  • the read integrated circuit can be manufactured by forming a CMOS device on a substrate.
  • the lower structure 12 may further include an insulating layer 15 on the substrate, a lower electrode 14b and a reflective layer 14c on the insulating layer 15.
  • the lower electrode 14b may be used to electrically connect the circuit element and the sensor element in the logic circuit.
  • the lower electrode 14b may be formed to protrude on the insulating layer 15 or may be formed by forming a trench pattern in the insulating layer 15 and then filling it with a metal layer.
  • Reflective layer 14c may be used to reflect light incident on underlying structure 12.
  • the amorphous carbon film which will be described later, is formed by chemical vapor deposition. It can be very advantageous in terms of planarization when forming.
  • the sacrificial layer 16 may be formed on the lower structure 12.
  • the sacrificial layer 16 is used to support the upper structure (23 of FIG. 6) described below on the lower structure 12, but finally at least some or all may be removed.
  • the sacrificial layer 16 may include an amorphous carbon film.
  • the sacrificial layer 16 may be formed using chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • the amorphous carbon film 16 may be deposited by various techniques, but for example, plasma enhanced CVD (PECVD) may be used due to the cost efficiency and the possibility of adjusting the film properties.
  • PECVD plasma enhanced CVD
  • helium and argon may be introduced into the chamber as a plasma starting gas and a material including a liquid or gaseous hydrocarbon in a carrier gas.
  • the plasma can be transferred into the chamber to produce excited CH-radicals, which can be chemically constrained to the surface of the substrate located in the chamber to form an a-C: H film on the surface of the substrate.
  • a damascene method may be used to form a trench pattern in the insulating layer 15 and then embed it with a metal layer to implement the lower electrode 14b and the reflective layer 14c.
  • the sacrificial layer 16 composed of the amorphous carbon film does not need to perform a separate planarization process such as CMP. If depositing the amorphous carbon film on the uneven lower metal structure and planarizing the amorphous carbon film through the CMP, peeling may occur because the adhesion between the metal and the amorphous carbon film is not good.
  • the process of forming the sacrificial layer 16 may be performed to be compatible with a back-end process such as a metal wiring process of a semiconductor device. That is, the sacrificial layer 16 may be formed using a post-process used in manufacturing a conventional semiconductor device, not a MEMS process. Therefore, following the formation of the lower structure 12, it is possible to proceed with the sacrificial layer 16 and the subsequent metal process by applying most of the process technology used in the existing semiconductor post-process as it is to reduce the manufacturing cost and easy mass production Become.
  • the sacrificial layer 16 is formed using a material such as polyimide, it is not easy to apply a high temperature process in a subsequent metal deposition process due to problems such as moisture resorption, so that lift off is performed instead of CVD.
  • the metal must be deposited using the method. In this case, there is a disadvantage in that the step coverage is not good and many impurities remain inside the metal.
  • the sacrificial layer 16 may be formed of an amorphous carbon film using the CVD method in the medium temperature range, about 200 ° C to 600 ° C.
  • the metal deposition process can be performed using the CVD method.
  • the CVD method is excellent in step coverage and excellent in the shape and electrical properties of the wiring, and can increase the reliability of the metal deposition process.
  • the thickness of the sacrificial layer 16 may be appropriately selected in consideration of the separation distance between the lower structure 12 and the upper structure and the subsequent removal burden.
  • the thickness of the sacrificial layer 16 may be selected in the range of 0.5 to 5 ⁇ m.
  • the thickness of the sacrificial layer 16 may be selected without being limited to this range.
  • an insulating support layer 17 may be formed on the sacrificial layer 16.
  • the insulating support layer 17 can be formed of an oxide film using the CVD method.
  • the insulating support layer 17 and the sacrificial layer 16 may be patterned by a single photolithography process to simultaneously form the sacrificial layer 16d having the via holes 19 and the insulating support layer 17a.
  • the via holes 19 may be formed by forming a photoresist pattern using photolithography, and simultaneously etching the insulating support layer 17 and the sacrificial layer 16 using the photoresist pattern as an etch protective film.
  • the via holes 19 may be formed to expose the lower electrodes 14b, and then may be used as a passage connecting the lower electrodes 14b to the upper structure.
  • the insulating support layer 17 may be formed. 2 It must be separately etched by a photolithography process. Since outgassing occurs in the polyimide exposed by the first photolithography process, a separate process for covering the exposed portion of the polyimide is required before the second photolithography process. to be. However, in the embodiments of the present application, since the sacrificial layer 16 is composed of an amorphous carbon film, the above-described problem of outgassing does not occur, and thus, there is no need to prevent the exposure of the amorphous carbon film in the etching process.
  • the insulating support layer 17 and the sacrificial layer 16 can be etched at once, that is, simultaneously.
  • the inventor By replacing the sacrificial layer 16 with an amorphous carbon film in polyimide, the inventor not only avoids the problems such as water resorption, poor step coverage, impurities in subsequent processes, etc., but also uses the characteristics of the amorphous carbon film.
  • the number of photolithography processes is simplified from two times to one time, thereby providing a manufacturing method that can significantly reduce the manufacturing cost.
  • metal anchors 21 may be formed to be connected to the lower electrodes 14b through the via holes 19.
  • the metal anchors 21 may be formed by forming and patterning a metal layer on the lower electrodes 14b exposed by the via holes 19 using the CVD method.
  • a metal layer a tungsten (W) layer is mentioned, for example.
  • W tungsten
  • an upper structure may be formed on the sacrificial layer 16d.
  • the absorbent layer 22 may be formed on the resultant metal anchors 21 formed thereon and the sensor structure 23 may be formed on the absorbent layer 22.
  • the absorber layer 22 can be patterned to include a plurality of holes.
  • the absorber layer 22 may include a metal capable of absorbing infrared rays.
  • the sensor structure 23 may include various sensors used in the MEMS structure, and may include, for example, an infrared sensor, an ultraviolet sensor, an X-ray sensor, a laser sensor, and the like.
  • an infrared sensor may include a resistance element, a thermoelectric element, and the like.
  • the resistance may vary depending on the degree of infrared rays absorbed, for example, amorphous silicon, vanadium oxide, or the like.
  • a second insulating support layer 25 may be formed on the sensor structure 23.
  • the second insulating support layer 25 may include an oxide film.
  • through holes 27 penetrating through the second insulating support layer 25, the sensor structure 23, the absorbing layer 22, and the insulating support layer 17a may be formed.
  • the through holes 27 form a photoresist pattern using a photolithography technique, and the second insulating support layer 25, the sensor structure 23, and the absorption layer 22 using the photoresist pattern as an etch protective film.
  • the insulating support layer 17a may be formed by etching.
  • the number of through holes 27 may be appropriately selected in one or more ranges in consideration of the etching speed of the sacrificial layer 16d.
  • the shape of the through holes 27 may be variously modified, and a cantilever pattern may be realized by the through holes 27.
  • the sacrificial layer 16d may be removed through the through holes 27 to define the empty space C.
  • the empty space C may contribute to increasing the infrared absorption efficiency by reflecting the infrared rays through the reflective layer 14c and entering the sensor structure 23 again.
  • the sacrificial layer 16d when the sacrificial layer 16d is an amorphous carbon film, the sacrificial layer 16d may be etched using wet etching or dry etching. However, when wet etching is used, stiction may occur, but dry etching may be free from such a problem. For example, dry etching may be performed using an oxygen (O 2 ) plasma.
  • O 2 oxygen
  • the MEMS device thus formed may comprise an upper structure including a lower structure 12 and a sensor structure 23.
  • An empty space C from which the sacrificial layers 16 and 16d are removed may be defined between the lower structure 12 and the sensor structure 23.
  • the sensor structure 23 may be electrically connected to the lower electrodes 14b through the metal anchors 21. Accordingly, the sensor circuit 23 and the logic circuits of the lower structure 12, such as the read integrated circuit, may be structurally connected to each other to constitute a MEMS device.
  • Such MEMS devices may include a variety of sensor structures, such as infrared sensors, ultraviolet sensors, X-ray sensors, laser sensors, and the like.
  • FIG. 7 is a schematic cross-sectional view of a MEMS device manufactured in accordance with another embodiment of the present invention.
  • a lower electrode 14 may be formed in the first substrate 12a.
  • the lower electrode 14 may be formed by implanting impurities of the second conductive type into the first substrate 12a of the first conductive type and heat treating the first substrate 12a.
  • the first conductive type and the second conductive type may be n-type and p-type, or vice versa.
  • the lower electrode 14 may be disposed to protrude on the top surface of the first substrate 12a without being formed in the first substrate 12a.
  • An amorphous carbon film pattern 16c may be formed on a portion of the first substrate 12a.
  • the amorphous carbon film pattern 16c does not exist on the remaining portion of the first substrate 12a.
  • the amorphous carbon film pattern 16c may be formed to expose at least a portion of the first substrate 12a around the upper surface of the lower electrode 14 and the lower electrode 14.
  • the second substrate 18a and the upper electrode 20 are disposed on the amorphous carbon film pattern 16c.
  • the upper electrode 20 may be disposed at a position facing the lower electrode 14. Therefore, the lower electrode 14 may be spaced apart from the upper electrode 20 by the amorphous carbon film pattern 16c.
  • the amorphous carbon film pattern 16c may not be interposed between the lower electrode 14 and the upper electrode 20.
  • the structure including the first substrate 12a and / or the lower electrode 14 described above is referred to as a lower structure
  • the structure including the second substrate 18a and / or the upper electrode 20 is referred to as an upper structure. You can name it.
  • the upper structure and the lower structure may be spaced apart by the amorphous carbon film pattern 16c.
  • an upper structure may be disposed on the first substrate 12a and the amorphous carbon film pattern 16c.
  • the upper structure may further include a solder bonding layer 24 and a packaging cap layer 26 in addition to the second substrate 18a and the upper electrode 20.
  • the second substrate 18a may correspond to a device layer in the MEMS device. The thickness of the device layer can be arbitrarily adjusted and can have various types of structures.
  • the second substrate 18a may include an upper electrode 20, and the upper electrode 20 injects a second conductive material into a predetermined portion of the second substrate 18a and the second substrate. (18a) can be formed by heat treatment.
  • the upper electrode 20 may be formed at a position facing the lower electrode 14 through the amorphous carbon film pattern 16c.
  • the upper electrode 20 and the lower electrode 14 are spaced apart by a distance d1 corresponding to the thickness of the amorphous carbon film pattern 16c. Therefore, the upper electrode 20 may be formed so that the position on the lower electrode 14 can be changed.
  • the capacitance between the two electrodes is proportional to the area of the two electrodes facing the dielectric constant of the medium between the two electrodes, It may be approximated to a value inversely proportional to the separation distance d1 between two electrodes.
  • the gap or overlapping area between the two electrodes changes to change the capacitance. Therefore, by outputting the change in capacitance as an electrical signal it is possible to measure the relative displacement between the two electrodes.
  • the packaging cap layer 26 may be disposed on the second substrate 18a.
  • the packaging cap layer 26 may serve to protect the MEMS device from the outside.
  • the interior 28 of the packaging cap layer 26 may be sealed to maintain vacuum.
  • a solder joint layer 24 may be interposed between the second substrate 18a and the packaging cap layer 26.
  • the solder joint layer 24 may include at least one of gold, silver, copper, tin, indium, and silicon.
  • the MEMS device further includes a through electrode 32 penetrating the first substrate 12a and / or the amorphous carbon film pattern 16c to electrically connect the lower electrode 14 and / or the upper electrode 20 to the outside.
  • the lower surface of the first substrate 12a may further include a conductive pad 34 electrically connected to the through electrode 32.
  • the through electrode 32 may be made of a conductive material, for example, may be made of a material such as copper, tungsten, and aluminum.
  • the MEMS device according to this embodiment can be used as a gyro sensor, but the scope of this embodiment is not limited thereto.
  • FIGS. 8 through 11 are cross-sectional views schematically showing a manufacturing process of a MEMS device according to another embodiment of the present invention.
  • the first substrate 12 may be a silicon substrate, and may include various semiconductor materials such as group IV semiconductors, group III-V compound semiconductors, or group II-VI oxide semiconductors.
  • the group IV semiconductor may include germanium or silicon-germanium in addition to silicon.
  • the substrate may be formed of a gallium arsenide substrate, a ceramic substrate, a quartz substrate, a display glass substrate, or the like.
  • the lower electrode 14 may be formed in the first substrate 12 without protruding from the upper surface of the first substrate 12.
  • the lower electrode 14 thus formed has the same level as the upper surface of the lower electrode 14 and the upper surface of the first substrate 12.
  • the lower electrode 14 may be disposed to protrude on the upper surface of the first substrate 12a.
  • the process of injecting impurities may include an ion implant process or a doping process.
  • an n-type impurity source such as PH 3 , AsH 3, or the like, or a p-type impurity source such as BF 3 , BCl 3, or the like may be used.
  • the lower electrode 14 may have characteristics of a conductor having excellent electrical conductivity.
  • An amorphous carbon film can be formed on the substrate 12a as a sacrificial layer.
  • an amorphous carbon film 16 may be formed on the first substrate 12 having the lower electrode 14 formed therein.
  • the amorphous carbon film 16 may be formed using chemical vapor deposition.
  • the amorphous carbon film 16 may be deposited by various techniques, but, for example, plasma enhanced chemical vapor deposition (PECVD) may be used due to the cost efficiency and the possibility of adjusting the film properties.
  • PECVD plasma enhanced chemical vapor deposition
  • the temperature for performing the chemical vapor deposition method may be carried out at 200 °C to 600 °C.
  • the substrate temperature may be reduced to as low as about 300 ° C. during deposition.
  • Lower processing temperatures for the substrate can lower the thermal budget of the process to protect the devices formed on the substrate from dopant movement.
  • the process may be performed at the same temperature as the semiconductor post-process. Therefore, the manufacturing cost can be lowered because the process technology already used in the existing semiconductor process can be fully utilized.
  • an upper structure may be formed on the first substrate 12 and the amorphous carbon film 16.
  • the upper structure may include a second substrate 18a and an upper electrode 20.
  • the second substrate 18a may be, for example, a silicon substrate.
  • the second substrate 18a may correspond to a device layer in the MEMS device.
  • the thickness of the device layer can be arbitrarily adjusted through bonding and / or thinning of the silicon substrate, for example, can range from 10 ⁇ m to 100 ⁇ m.
  • the second substrate 18a is subjected to exposure, etching, and cleaning processes.
  • the etching process may be performed by using a so-called Deep RIE (Reactive Ion Etching) method.
  • the second substrate 18a may include a predetermined structure of various forms.
  • the upper electrode 20 may be formed by implanting impurities into a predetermined portion of the second substrate 18a and heat treating the second substrate 18a.
  • the process of injecting impurities may include an ion implant process or a doping process.
  • an n-type impurity source such as PH 3 , AsH 3, or the like, or a p-type impurity source such as BF 3 or BCl 3 may be used.
  • Forming the upper structure may further include depositing tungsten by chemical vapor deposition.
  • Tungsten deposition by chemical vapor deposition can be produced using a WF 6 / H 2 mixed gas.
  • WF 6 can be reduced by silicon, hydrogen and silane, and upon contact with silicon, a selective reaction can be started from the reduction reaction of silicon.
  • Hydrogen reduction reactions can rapidly deposit tungsten on the nucleation layer while forming plugs, and silane reduction reactions can achieve faster deposition rates and smaller tungsten grain sizes than those obtainable in hydrogen reduction reactions.
  • the tungsten thin film formed by such a reaction has a good step coverage property and a low resistance component compared to other materials, and thus may be treated as an important conductor material.
  • a portion of the amorphous carbon film 16 interposed between the lower electrode 14 and the upper electrode 20 may be removed to form the amorphous carbon film pattern 16b.
  • the process of removing a portion of the amorphous carbon film 16 may be removed after forming at least one of the upper structures, for example, the second substrate 18a, and may use wet etching and / or dry etching.
  • a portion of the amorphous carbon film 16 may be easily removed by using an oxygen (O 2) plasma, which is one of dry etching methods.
  • O 2 plasma By using an oxygen (O 2) plasma, it is possible to have an excellent etching selectivity with many kinds of inorganic materials and to easily control the film thickness. Therefore, the lower electrode 14 may be easy to adjust the separation distance between the upper electrode 20 and the two, it is easy to ensure the uniformity of the capacitance can ensure a stable operation of the MEMS device.
  • the upper structure may further include a solder bonding layer 24 and a packaging cap layer 26 in addition to the second substrate 18a and the upper electrode 20.
  • the packaging cap layer 26 may be attached on the second substrate 18a, and the interior 28 of the packaging cap layer 26 may be sealed to maintain a vacuum, and the second substrate 18a and the packaging cap layer (
  • the solder joint layer 24 can be interposed between 26).
  • the material for forming the solder joint layer 24 may include at least one of gold, silver, copper, tin, indium, and silicon.
  • the solder bonding layer 24 may be made of various binary or ternary solder alloys such as copper / tin, gold / indium, gold / tin, gold / silicon, copper / gold / tin, and the like.
  • the MEMS device forms an amorphous carbon film pattern as a sacrificial layer on a silicon substrate, so that a tungsten deposition process by chemical vapor deposition can be used, thereby providing excellent step coverage.
  • a device excellent in the shape and electrical properties of the wiring can be manufactured.
  • the process since the process is performed at the same temperature as the post-semiconductor process, the process technology already used in the existing semiconductor process can be fully utilized.

Abstract

A MEMS device manufacturing method using an amorphous carbon film as a sacrificial layer is provided. According to an embodiment of the present invention, a lower structure is formed. An amorphous carbon film is formed as a sacrificial layer on the lower structure. An upper structure including a sensor structure is formed on the amorphous carbon film. The amorphous carbon film is removed so that the lower structure and the upper structure are spaced apart from each other.

Description

멤스 디바이스 제조방법MEMS device manufacturing method
본 발명은 반도체 디바이스에 관한 것으로서, 특히 멤스(MEMS: Micro Electro Mechanical Systems) 디바이스 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a MEMS (Micro Electro Mechanical Systems) device and a manufacturing method thereof.
일반적으로 멤스 디바이스는 기계요소 부품, 센서, 액츄에이터, 전자 회로를 하나의 실리콘 기판상에 집적화한 디바이스를 가리키며, 현재 제품으로서 시판되고 있는 것으로서는 프린터 헤드, 압력 센서, 가속도 센서, 자이로스코프, DMD(프로젝터) 등이 있다.In general, MEMS devices refer to devices incorporating mechanical component parts, sensors, actuators, and electronic circuits on a single silicon substrate, and are currently available as printer heads, pressure sensors, acceleration sensors, gyroscopes, and DMDs. Projector).
주요 부분은 반도체 프로세스를 이용해 제작되지만 반도체 집적회로가 평면을 가공하는 프로세스로 제작되는데 대해 입체 형상을 형성할 필요가 있어 반도체 집적회로의 제작에는 사용되지 않는 희생층(sacrificial layer) 식각으로 불리는 프로세스가 포함된다. 이 프로세스는 실리콘 기판 위에 희생층과 구조물 박막을 사용하여 구조물의 모양을 패터닝하고, 희생층을 제거하여 구조물을 제작하는 방법이다. 이러한 하부 전극 또는 하부 구조물과 상부 구조물 사이의 공간을 일정하게 유지 시켜 주기 위한 희생층으로 실리콘이나 유기물인 폴리이미드(Polyimide)를 사용하여왔다.Although the main part is manufactured using a semiconductor process, a process called sacrificial layer etching, which is not used for fabricating a semiconductor integrated circuit, needs to be formed because the semiconductor integrated circuit is manufactured as a process of processing a plane. Included. This process uses a sacrificial layer and a structure thin film on a silicon substrate to pattern the shape of the structure and remove the sacrificial layer to fabricate the structure. Silicon or organic polyimide (Polyimide) has been used as a sacrificial layer for maintaining a constant space between the lower electrode or the lower structure and the upper structure.
그러나 이러한 종래의 MEMS 디바이스 제작에 있어서 희생층으로 실리콘을 사용할 경우 산화막과의 식각 선택 비는 우수하나 질화막이나 텅스텐 등의 금속과는 식각 선택비가 좋지 않고, 희생층으로 폴리이미드를 사용할 경우 불순물이 많이 함유되고, 후속 공정시 저온에서 진행하는 리프트 오프(Lift off) 방법을 주로 사용하여 품질이 저하되는 문제점이 있었다.However, in the conventional MEMS device fabrication, when the silicon is used as the sacrificial layer, the etching selectivity with the oxide film is excellent, but the etching selectivity with the metal such as nitride film and tungsten is not good, and the polyimide is used as the sacrificial layer. There is a problem that the quality is reduced by using a lift off method that is contained, and proceeds at a low temperature in the subsequent process.
본 발명은 상기와 같은 문제점을 포함하여 여러 문제점들을 해결하기 위한 것으로서, 다양한 종류의 무기물과도 우수한 식각 선택비를 가지며, 디바이스에 따라 필름의 두께를 쉽게 조절할 수 있어 성능과 모양면에서 기존의 MEMS 디바이스에 비해 뛰어나고, 기존의 반도체 공정을 활용할 수 있는 MEMS 디바이스 및 제조 방법을 제공하는 것을 목적으로 한다. 그러나 이러한 과제는 예시적인 것으로, 이에 의해 본 발명의 범위가 한정되는 것은 아니다.The present invention is to solve the various problems including the above problems, has an excellent etching selectivity with various kinds of inorganic materials, and can easily adjust the thickness of the film according to the device, the conventional MEMS in terms of performance and shape It is an object of the present invention to provide a MEMS device and a manufacturing method which are superior to devices and can utilize existing semiconductor processes. However, these problems are exemplary, and the scope of the present invention is not limited thereby.
본 발명의 일 관점에 따른 멤스 디바이스 제조 방법이 제공된다. 상기 멤스 디바이스 제조 방법은 하부 구조물을 형성하는 단계; 상기 하부 구조물 상에 희생층으로서 비정질 탄소막을 형성하는 단계; 상기 비정질 탄소막 상에 절연지지층을 형성하는 단계; 상기 절연지지층 상에 식각 보호막을 형성하고 상기 절연지지층 및 상기 비정질 탄소막을 한 번에 식각하여, 상기 절연지지층 및 상기 비정질 탄소막을 관통하여 상기 하부 구조물을 노출하는 비어홀들을 형성하는 단계; 상기 절연지지층 상에 센서 구조를 포함하는 상부 구조물을 형성하는 단계; 상기 절연지지층을 관통하는 적어도 하나의 관통홀을 형성하는 단계; 및 상기 하부 구조물과 상기 상부 구조물이 서로 이격되어 배치되도록, 상기 관통홀들을 통해서 상기 비정질 탄소막을 모두 제거하는 단계;를 포함한다. MEMS device manufacturing method according to an aspect of the present invention is provided. The method of manufacturing a MEMS device includes forming a lower structure; Forming an amorphous carbon film on the lower structure as a sacrificial layer; Forming an insulating support layer on the amorphous carbon film; Forming an etch passivation layer on the insulating support layer and etching the insulating support layer and the amorphous carbon film at once to form via holes through the insulating support layer and the amorphous carbon film to expose the lower structure; Forming an upper structure including a sensor structure on the insulating support layer; Forming at least one through hole penetrating the insulating support layer; And removing all of the amorphous carbon film through the through holes so that the lower structure and the upper structure are spaced apart from each other.
상기 제조 방법에 있어서, 상기 비정질 탄소막을 형성하는 단계는 화학기상증착법(CVD)을 이용하여 수행할 수 있다.In the manufacturing method, the step of forming the amorphous carbon film may be performed using chemical vapor deposition (CVD).
상기 제조 방법에 있어서, 상기 비정질 탄소막을 제거하는 단계는 건식 식각 방식을 포함할 수 있다. 나아가, 상기 건식 식각 방식은 산소(O2) 플라즈마(Plasma)를 이용하여 수행할 수 있다.In the manufacturing method, removing the amorphous carbon film may include a dry etching method. In addition, the dry etching method may be performed by using an oxygen (O 2 ) plasma.
상기 제조 방법에 있어서, 상기 상부 구조물을 형성하는 단계는, 상기 비정질 탄소막 상에 절연지지층을 형성하는 단계를 더 포함할 수 있다.In the manufacturing method, the forming of the upper structure may further include forming an insulating support layer on the amorphous carbon film.
상기 제조 방법에 있어서, 상기 비어홀들을 형성하는 단계 후, 상기 비어홀들을 통해서 상기 하부 전극들과 연결되도록 상기 하부 전극들 상에 금속 앵커들을 형성하는 단계를 더 포함할 수 있다. The manufacturing method may further include forming metal anchors on the lower electrodes to be connected to the lower electrodes through the via holes.
상기 제조 방법에 있어서, 상기 상부 구조물을 형성하는 단계는, 상기 절연지지층 상에 흡수층을 형성하는 단계를 더 포함할 수 있다.In the manufacturing method, the forming of the upper structure may further include forming an absorbing layer on the insulating support layer.
상기 제조 방법에 있어서, 상기 하부 구조물은 상기 센서 구조를 제어하기 위한 판독집적회로(ROIC)를 포함할 수 있다.In the manufacturing method, the lower structure may include a read integrated circuit (ROIC) for controlling the sensor structure.
상기 제조 방법에 있어서, 상기 센서 구조는 적외선 센서를 포함할 수 있다.In the manufacturing method, the sensor structure may include an infrared sensor.
상기 제조 방법에 있어서, 상기 상기 절연지지층 및 상기 비정질 탄소막을 관통하여 상기 하부 구조물을 노출하는 비어홀들을 형성하는 단계는 한 번의 포토리소그래피 공정만으로 수행될 수 있다. In the manufacturing method, forming the via holes exposing the lower structure through the insulating support layer and the amorphous carbon film may be performed by only one photolithography process.
상기한 바와 같이 이루어진 본 발명의 일 실시예에 따르면, 다양한 종류의 무기물과도 우수한 식각 선택비를 가지며, 디바이스에 따라 필름의 두께를 쉽게 조절할 수 있어 성능과 모양면에서 기존의 MEMS 디바이스에 비해 뛰어나고, 기존의 반도체 공정을 활용할 수 있는 MEMS 디바이스를 구현할 수 있다. 물론 이러한 효과에 의해 본 발명의 범위가 한정되는 것은 아니다.According to one embodiment of the present invention made as described above, it has an excellent etching selectivity with various kinds of inorganic materials, it is easy to adjust the thickness of the film according to the device is superior to the conventional MEMS device in terms of performance and shape In addition, MEMS devices that can utilize existing semiconductor processes can be implemented. Of course, the scope of the present invention is not limited by these effects.
도 1 내지 도 6은 본 발명의 일 실시예에 따른 MEMS 디바이스 및 그 제조 방법을 개략적으로 도시하는 단면도들이다.1 to 6 are cross-sectional views schematically showing a MEMS device and a method of manufacturing the same according to an embodiment of the present invention.
도 7은 본 발명의 다른 실시예에 따라 제조된 MEMS 디바이스를 개략적으로 도시하는 단면도이다.7 is a schematic cross-sectional view of a MEMS device manufactured in accordance with another embodiment of the present invention.
도 8 내지 도 11은 본 발명의 다른 실시예에 따른 MEMS 디바이스의 제조방법을 도시하는 단면도들이다.8 to 11 are cross-sectional views illustrating a method of manufacturing a MEMS device according to another embodiment of the present invention.
이하, 첨부된 도면들을 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다. 그러나 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있는 것으로, 이하의 실시예는 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 또한 설명의 편의를 위하여 도면에서는 구성 요소들이 그 크기가 과장 또는 축소될 수 있다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and the following embodiments are intended to complete the disclosure of the present invention, to those skilled in the art It is provided to inform you completely. In addition, the components may be exaggerated or reduced in size in the drawings for convenience of description.
도 1 내지 도 6은 본 발명의 일 실시예에 따른 MEMS 디바이스 및 그 제조 방법을 개략적으로 도시하는 단면도들이다.1 to 6 are cross-sectional views schematically showing a MEMS device and a method of manufacturing the same according to an embodiment of the present invention.
도 1을 참조하면, 하부 구조물(12)을 제공할 수 있다. 예를 들어, 하부 구조물(12)은 적절한 로직회로, 예컨대 판독집적회로(Read Out Integrated Circuit; ROIC)를 포함할 수 있다. 판독집적회로는 기판 상에 CMOS 소자를 형성하여 제조할 수 있다. 나아가, 하부 구조물(12)은 기판 상의 절연층(15) 및 절연층(15) 상의 하부 전극(14b) 및 반사층(14c)을 더 포함할 수 있다.Referring to FIG. 1, a lower structure 12 may be provided. For example, the lower structure 12 may include a suitable logic circuit, such as a Read Out Integrated Circuit (ROIC). The read integrated circuit can be manufactured by forming a CMOS device on a substrate. Further, the lower structure 12 may further include an insulating layer 15 on the substrate, a lower electrode 14b and a reflective layer 14c on the insulating layer 15.
하부 전극(14b)은 로직회로 내의 회로 소자와 센서 소자를 전기적으로 연결하는 데 이용될 수 있다. 하부 전극(14b)은 절연층(15) 상에 돌출되게 형성하거나 또는 절연층(15) 내에 트렌치 패턴을 형성한 후 이를 금속층으로 매립하여 형성할 수 있다. 반사층(14c)은 하부 구조물(12)에 입사되는 빛을 반사시키는 데 이용될 수 있다. 특히, 절연층(15) 내에 트렌치 패턴을 형성한 후에 이를 금속층으로 매립하여 하부 전극(14b) 및 반사층(14c)을 구현하는 다마신 방법을 사용하는 경우, 후술할 비정질탄소막을 화학기상증착법에 의하여 형성할 때 평탄화 측면에서 매우 유리할 수 있다. The lower electrode 14b may be used to electrically connect the circuit element and the sensor element in the logic circuit. The lower electrode 14b may be formed to protrude on the insulating layer 15 or may be formed by forming a trench pattern in the insulating layer 15 and then filling it with a metal layer. Reflective layer 14c may be used to reflect light incident on underlying structure 12. In particular, in the case of using the damascene method of forming a trench pattern in the insulating layer 15 and then filling it with a metal layer to implement the lower electrode 14b and the reflective layer 14c, the amorphous carbon film, which will be described later, is formed by chemical vapor deposition. It can be very advantageous in terms of planarization when forming.
도 2를 참조하면, 하부 구조물(12) 상에 희생층(16)을 형성할 수 있다. 희생층(16)은 하부 구조물(12) 상에 후술하는 상부 구조물(도 6의 23)을 지지하는 데 이용되나 최종적으로는 적어도 일부 또는 전부가 제거될 수 있다. 예를 들어, 희생층(16)은 비정질 탄소막을 포함할 수 있다. Referring to FIG. 2, the sacrificial layer 16 may be formed on the lower structure 12. The sacrificial layer 16 is used to support the upper structure (23 of FIG. 6) described below on the lower structure 12, but finally at least some or all may be removed. For example, the sacrificial layer 16 may include an amorphous carbon film.
예를 들어, 이러한 희생층(16)은 화학기상증착법(Chemical Vapor Deposition; CVD)을 이용하여 형성할 수 있다. 비정질탄소막(16)은 여러 가지 기술에 의해 증착될 수 있지만, 비용 효율성 및 막 특성 조정 가능성으로 인해 예를 들어, 플라즈마 강화 화학기상증착(plasma enhanced CVD; PECVD)법을 사용할 수 있다. 플라즈마 강화 화학기상증착법은 캐리어 가스(carrier gas) 내에 액상 또는 기상의 탄화수소를 포함하는 물질과 플라즈마 개시 가스로서 헬륨 및 아르곤 등을 챔버 내에 도입할 수 있다. 플라즈마는 챔버 내에 전해져서 여기된 CH-라디칼을 생성하고, 여기된 CH-라디칼은 챔버내에 위치하는 기판의 표면에 화학적으로 구속되어 기판의 표면상에 a-C:H 막을 형성할 수 있다. 본 발명의 일실시예에서는, 상술한 것처럼, 절연층(15) 내에 트렌치 패턴을 형성한 후에 이를 금속층으로 매립하여 하부 전극(14b) 및 반사층(14c)을 구현하는 다마신 방법을 사용할 수 있으며, 이 경우, 비정질탄소막으로 구성된 희생층(16)은 CMP와 같은 별도의 평탄화 공정을 수행하지 않아도 된다. 만약, 평탄하지 않은 하부 금속 구조물 상에 비정질탄소막을 증착하고 CMP를 통하여 비정질탄소막을 평탄화하면 금속과 비정질탄소막 간의 접착력이 좋지 않기 때문에 필링(peeling)이 발생할 수 있다. For example, the sacrificial layer 16 may be formed using chemical vapor deposition (CVD). The amorphous carbon film 16 may be deposited by various techniques, but for example, plasma enhanced CVD (PECVD) may be used due to the cost efficiency and the possibility of adjusting the film properties. In the plasma enhanced chemical vapor deposition method, helium and argon may be introduced into the chamber as a plasma starting gas and a material including a liquid or gaseous hydrocarbon in a carrier gas. The plasma can be transferred into the chamber to produce excited CH-radicals, which can be chemically constrained to the surface of the substrate located in the chamber to form an a-C: H film on the surface of the substrate. In an embodiment of the present invention, as described above, a damascene method may be used to form a trench pattern in the insulating layer 15 and then embed it with a metal layer to implement the lower electrode 14b and the reflective layer 14c. In this case, the sacrificial layer 16 composed of the amorphous carbon film does not need to perform a separate planarization process such as CMP. If depositing the amorphous carbon film on the uneven lower metal structure and planarizing the amorphous carbon film through the CMP, peeling may occur because the adhesion between the metal and the amorphous carbon film is not good.
따라서, 이러한 희생층(16)의 형성 공정은 반도체 소자의 금속 배선 공정 등과 같은 후공정(back-end process)과 양립 가능하게 수행할 수 있다. 즉, 희생층(16)은 MEMS 공정이 아닌 기존 반도체 소자 제조 시 이용되는 후공정을 이용하여 형성할 수 있다. 따라서, 하부 구조물(12)의 형성에 이어서 기존 반도체 후공정에서 사용하는 대부분의 공정 기술들을 그대로 적용하여 희생층(16) 및 이후 금속 공정을 진행할 수 있게 되어 제조 단가를 낮출 수 있고 대량 생산이 용이해진다. Therefore, the process of forming the sacrificial layer 16 may be performed to be compatible with a back-end process such as a metal wiring process of a semiconductor device. That is, the sacrificial layer 16 may be formed using a post-process used in manufacturing a conventional semiconductor device, not a MEMS process. Therefore, following the formation of the lower structure 12, it is possible to proceed with the sacrificial layer 16 and the subsequent metal process by applying most of the process technology used in the existing semiconductor post-process as it is to reduce the manufacturing cost and easy mass production Become.
반면, 폴리이미드와 같은 재료를 사용하여 희생층(16)을 형성하는 경우, 수분 재흡수 등의 문제로 후속 금속 증착 공정에서 고온 공정을 적용하기 용이하지 않으므로 CVD 방식이 아닌 리프트 오프(Lift off) 방식을 사용하여 금속을 증착하여야 한다. 이 경우, 스텝 커버리지가 좋지 않고 금속의 내부에 불순물이 많이 남는다는 단점이 있었다. On the other hand, when the sacrificial layer 16 is formed using a material such as polyimide, it is not easy to apply a high temperature process in a subsequent metal deposition process due to problems such as moisture resorption, so that lift off is performed instead of CVD. The metal must be deposited using the method. In this case, there is a disadvantage in that the step coverage is not good and many impurities remain inside the metal.
하지만, 이 실시예에서 희생층(16)은 중온 범위, 약 200℃ 내지 600℃에서 CVD법을 사용하여 비정질탄소막으로 형성할 수 있다. 이 경우, 이후 CVD법을 이용하여 금속 증착 공정을 수행할 수 있게 된다. CVD법은 스텝 커버리지(Step Coverage)가 우수하고, 배선의 모양이나 전기적 특성 면에서 우수하여, 금속 증착 공정의 신뢰성을 높일 수 있다. However, in this embodiment, the sacrificial layer 16 may be formed of an amorphous carbon film using the CVD method in the medium temperature range, about 200 ° C to 600 ° C. In this case, the metal deposition process can be performed using the CVD method. The CVD method is excellent in step coverage and excellent in the shape and electrical properties of the wiring, and can increase the reliability of the metal deposition process.
한편, 희생층(16)의 두께는 하부 구졸물(12)과 상부 구조물의 이격거리와 이후 제거 부담을 고려하여 적절하게 선택될 수 있다. 예를 들어, 이 실시예와 같은 MEMS 구조에서 희생층(16)의 두께는 0.5 내지 5 ㎛ 범위에서 선택될 수 있다. 다만, 다른 실시예에서 희생층(16)의 두께는 이러한 범위에 국하되지 않고 선택될 수도 있다.On the other hand, the thickness of the sacrificial layer 16 may be appropriately selected in consideration of the separation distance between the lower structure 12 and the upper structure and the subsequent removal burden. For example, in the MEMS structure such as this embodiment, the thickness of the sacrificial layer 16 may be selected in the range of 0.5 to 5 μm. However, in another embodiment, the thickness of the sacrificial layer 16 may be selected without being limited to this range.
선택적으로, 희생층(16) 상에 절연지지층(17)을 형성할 수 있다. 예를 들어, 절연지지층(17)은 CVD법을 이용하여 산화막으로 형성할 수 있다.Optionally, an insulating support layer 17 may be formed on the sacrificial layer 16. For example, the insulating support layer 17 can be formed of an oxide film using the CVD method.
도 3을 참조하면, 절연지지층(17) 및 희생층(16)을 한 번의 포토리소그래피 공정에 의하여 패터닝하여 비어홀들(19)을 갖는 희생층(16d) 및 절연지지층(17a)을 동시에 형성할 수 있다. 예를 들어, 비어홀들(19)은 포토리소그래피를 이용하여 포토레지스트 패턴을 형성하고, 이 포토레지스트 패턴을 식각 보호막으로 하여 절연지지층(17) 및 희생층(16)을 동시에 식각하여 형성할 수 있다. 예를 들어, 비어홀들(19)은 하부 전극들(14b)을 노출하도록 형성될 수 있고, 이후 하부 전극들(14b)을 상부 구조물과 연결하는 통로로 이용될 수 있다. 만약, 희생층(16)이 유기물인 폴리이미드로 구성된다면, 비어홀들(19)을 형성하기 위하여, 희생층(16)을 제1 포토리소그래피 공정에 의하여 식각한 후에, 절연지지층(17)은 제2 포토리소그래피 공정에 의하여 별도로 식각되어야 한다. 이는 상기 제1 포토리소그래피 공정에 의하여 노출된 폴리이미드에서 아웃개싱(outgassing)이 발생되므로, 폴리이미드가 노출된 부분을 덮어주는 별도의 공정이, 상기 제2 포토리소그래피 공정 이전에 추가로 필요하기 때문이다. 하지만, 본원의 실시예들에서는, 희생층(16)이 비정질 탄소막으로 구성되므로 상술한 아웃개싱의 문제가 발생되지 않고, 따라서, 식각 공정에서 비정질 탄소막의 노출을 방지할 필요성이 없으므로, 한 번의 포토리소그래피 공정에 의하여 절연지지층(17)과 희생층(16)을 한 번에, 즉 동시에, 식각할 수 있다. 발명자는 희생층(16)을 폴리이미드에서 비정질 탄소막으로 대체함으로써, 상술한 수분 재흡수, 불량한 스텝 커버리지, 후속 공정에서의 불순물 등과 같은 문제점을 방지할 뿐만 아니라, 나아가, 비정질 탄소막의 특성을 이용하여 비어홀들(19)을 형성하는 공정에서 포토리소그래피 공정의 횟수를 2회에서 1회로 단순화하여 제조비용을 획기적으로 절감할 수 있는 제조방법을 제공한다. Referring to FIG. 3, the insulating support layer 17 and the sacrificial layer 16 may be patterned by a single photolithography process to simultaneously form the sacrificial layer 16d having the via holes 19 and the insulating support layer 17a. have. For example, the via holes 19 may be formed by forming a photoresist pattern using photolithography, and simultaneously etching the insulating support layer 17 and the sacrificial layer 16 using the photoresist pattern as an etch protective film. . For example, the via holes 19 may be formed to expose the lower electrodes 14b, and then may be used as a passage connecting the lower electrodes 14b to the upper structure. If the sacrificial layer 16 is made of organic polyimide, after the sacrificial layer 16 is etched by the first photolithography process to form the via holes 19, the insulating support layer 17 may be formed. 2 It must be separately etched by a photolithography process. Since outgassing occurs in the polyimide exposed by the first photolithography process, a separate process for covering the exposed portion of the polyimide is required before the second photolithography process. to be. However, in the embodiments of the present application, since the sacrificial layer 16 is composed of an amorphous carbon film, the above-described problem of outgassing does not occur, and thus, there is no need to prevent the exposure of the amorphous carbon film in the etching process. By the lithography process, the insulating support layer 17 and the sacrificial layer 16 can be etched at once, that is, simultaneously. By replacing the sacrificial layer 16 with an amorphous carbon film in polyimide, the inventor not only avoids the problems such as water resorption, poor step coverage, impurities in subsequent processes, etc., but also uses the characteristics of the amorphous carbon film. In the process of forming the via holes 19, the number of photolithography processes is simplified from two times to one time, thereby providing a manufacturing method that can significantly reduce the manufacturing cost.
도 4를 참조하면, 비어홀들(19)을 통해서 하부 전극들(14b)과 연결되도록 금속 앵커들(21)을 형성할 수 있다. 예를 들어, 비어홀들(19)에 의해서 노출된 하부 전극들(14b) 상에 CVD법을 이용하여 금속층을 형성하고, 이를 패터닝함으로써 금속 앵커들(21)을 형성할 수 있다. 이러한 금속층으로는 예컨대, 텅스텐(W)층을 들 수 있다. 이러한 금속 앵커들(21)은 하부 전극들(14b)을 상부 구조물과 전기적으로 연결하는 비어 플러그들로 이용될 수 있다.Referring to FIG. 4, metal anchors 21 may be formed to be connected to the lower electrodes 14b through the via holes 19. For example, the metal anchors 21 may be formed by forming and patterning a metal layer on the lower electrodes 14b exposed by the via holes 19 using the CVD method. As such a metal layer, a tungsten (W) layer is mentioned, for example. These metal anchors 21 may be used as via plugs that electrically connect the lower electrodes 14b with the upper structure.
도 5를 참조하면, 희생층(16d) 상에 상부 구조물을 형성할 수 있다. 예를 들어, 금속 앵커들(21)이 형성된 결과물 상에 흡수층(22)을 형성하고 흡수층(22) 상에 센서 구조(23)를 형성할 수 있다. 흡수층(22)은 복수의 홀들을 포함하도록 패터닝될 수 있다. 예를 들어, 흡수층(22)은 적외선을 흡수할 수 있는 금속을 포함할 수 있다.Referring to FIG. 5, an upper structure may be formed on the sacrificial layer 16d. For example, the absorbent layer 22 may be formed on the resultant metal anchors 21 formed thereon and the sensor structure 23 may be formed on the absorbent layer 22. The absorber layer 22 can be patterned to include a plurality of holes. For example, the absorber layer 22 may include a metal capable of absorbing infrared rays.
센서 구조(23)는 MEMS 구조에 이용되는 다양한 센서를 포함할 수 있으며, 예컨대 적외선 센서, 자외선 센서, 엑스선 센서, 레이저 센서 등을 포함할 수 있다. 예를 들어, 적외선 센서의 경우, 저항소자, 열전소자 등을 포함할 수 있다. 저항소자를 포함하는 볼로미터(bolometer)의 경우, 흡수되는 적외선 정도에 따라서 저항이 가변되는 물질, 예컨대 비정질 실리콘, 바나듐 산화물 등을 포함할 수 있다.The sensor structure 23 may include various sensors used in the MEMS structure, and may include, for example, an infrared sensor, an ultraviolet sensor, an X-ray sensor, a laser sensor, and the like. For example, an infrared sensor may include a resistance element, a thermoelectric element, and the like. In the case of a bolometer including a resistive element, the resistance may vary depending on the degree of infrared rays absorbed, for example, amorphous silicon, vanadium oxide, or the like.
도 6을 참조하면, 센서 구조(23) 상에 제2절연지지층(25)을 형성할 수 있다. 예를 들어, 제2절연지지층(25)은 산화막을 포함할 수 있다.Referring to FIG. 6, a second insulating support layer 25 may be formed on the sensor structure 23. For example, the second insulating support layer 25 may include an oxide film.
이어서, 제2절연지지층(25), 센서 구조(23), 흡수층(22) 및 절연지지층(17a)을 관통하는 관통홀들(27)을 형성할 수 있다. 예를 들어, 관통홀들(27)은 포토리소그래피 기술을 이용하여 포토레지스트 패턴을 형성하고, 이 포토레지스트 패턴을 식각 보호막으로 하여 제2절연지지층(25), 센서 구조(23), 흡수층(22) 및 절연지지층(17a)을 식각하여 형성할 수 있다. 관통홀들(27)의 개수는 희생층(16d)의 식각 속도를 고려하여 하나 또는 그 이상의 범위에서 적절하게 선택될 수 있다. 관통홀들(27)의 형상은 다양하게 변형될 수 있고, 관통홀들(27)에 의해서 캔틸레버(cantilever) 패턴이 구현될 수 있다.Subsequently, through holes 27 penetrating through the second insulating support layer 25, the sensor structure 23, the absorbing layer 22, and the insulating support layer 17a may be formed. For example, the through holes 27 form a photoresist pattern using a photolithography technique, and the second insulating support layer 25, the sensor structure 23, and the absorption layer 22 using the photoresist pattern as an etch protective film. ) And the insulating support layer 17a may be formed by etching. The number of through holes 27 may be appropriately selected in one or more ranges in consideration of the etching speed of the sacrificial layer 16d. The shape of the through holes 27 may be variously modified, and a cantilever pattern may be realized by the through holes 27.
이어서, 이러한 관통홀들(27)을 통해서 희생층(16d)을 제거하여 빈공간(C)을 한정할 수 있다. 이러한 빈공간(C)은 적외선이 반사층(14c)을 통해서 반사하여 다시 센서 구조(23)로 입사되게 함으로써, 적외선 흡수효율을 높이는 데 기여할 수 있다.Subsequently, the sacrificial layer 16d may be removed through the through holes 27 to define the empty space C. The empty space C may contribute to increasing the infrared absorption efficiency by reflecting the infrared rays through the reflective layer 14c and entering the sensor structure 23 again.
예를 들어, 희생층(16d)이 비정질 탄소막인 경우, 습식 식각 또는 건식 식각을 이용하여 희생층(16d)을 식각할 수 있다. 다만, 습식 식각을 이용한 경우 스틱션(stiction)이 발생할 수 있으나, 건식 식각의 경우에는 이러한 문제로부터 자유로울 수 있다. 예를 들어, 건식 식각은 산소(O2) 플라즈마(Plasma)를 이용하여 수행할 수 있다.For example, when the sacrificial layer 16d is an amorphous carbon film, the sacrificial layer 16d may be etched using wet etching or dry etching. However, when wet etching is used, stiction may occur, but dry etching may be free from such a problem. For example, dry etching may be performed using an oxygen (O 2 ) plasma.
이와 같이 형성된 MEMS 디바이스는 하부 구조물(12)과 센서 구조(23)를 포함하는 상부 구조물을 포함할 수 있다. 하부 구조물(12)과 센서 구조(23) 사이에는 희생층(16, 16d)이 제거된 빈공간(C)이 한정될 수 있다. 센서 구조(23)는 금속 앵커들(21)을 통해서 하부 전극들(14b)에 전기적으로 연결될 수 있다. 이에 따라, 센서 구조(23)와 하부 구조물(12)의 로직회로, 예컨대 판독집적회로가 서로 구조적으로 연결되어 MEMS 디바이스를 구성할 수 있다. 이러한 MEMS 디바이스는 다양한 센서 구조를 포함할 수 있으며, 예컨대 적외선 센서, 자외선 센서, 엑스선 센서, 레이저 센서 등을 포함할 수 있다.The MEMS device thus formed may comprise an upper structure including a lower structure 12 and a sensor structure 23. An empty space C from which the sacrificial layers 16 and 16d are removed may be defined between the lower structure 12 and the sensor structure 23. The sensor structure 23 may be electrically connected to the lower electrodes 14b through the metal anchors 21. Accordingly, the sensor circuit 23 and the logic circuits of the lower structure 12, such as the read integrated circuit, may be structurally connected to each other to constitute a MEMS device. Such MEMS devices may include a variety of sensor structures, such as infrared sensors, ultraviolet sensors, X-ray sensors, laser sensors, and the like.
도 7은 본 발명의 다른 실시예에 따라 제조된 MEMS 디바이스를 개략적으로 도시하는 단면도이다.7 is a schematic cross-sectional view of a MEMS device manufactured in accordance with another embodiment of the present invention.
도 7을 참조하면, 제1기판(12a) 내에 하부 전극(14)이 형성될 수 있다. 하부 전극(14)은 제1도전형의 제1기판(12a) 내에 제2도전형의 불순물을 주입하고 제1기판(12a)을 열처리하여 형성할 수 있다. 여기에서 제1도전형과 제2도전형은 각각 n형과 p형일 수 있으며, 또는 그 반대일 수도 있다. 또한 변형된 실시예에서, 하부 전극(14)은 제1기판(12a) 내에 형성하지 않고 제1기판(12a)의 상면 상에 돌출되어 배치될 수도 있다.Referring to FIG. 7, a lower electrode 14 may be formed in the first substrate 12a. The lower electrode 14 may be formed by implanting impurities of the second conductive type into the first substrate 12a of the first conductive type and heat treating the first substrate 12a. Herein, the first conductive type and the second conductive type may be n-type and p-type, or vice versa. In a modified embodiment, the lower electrode 14 may be disposed to protrude on the top surface of the first substrate 12a without being formed in the first substrate 12a.
제1기판(12a)의 일부분 상에는 비정질탄소막 패턴(16c)이 형성될 수 있다. 그리고 제1기판(12a)의 나머지 부분 상에는 비정질탄소막 패턴(16c)이 존재하지 않는다. 예를 들어, 비정질탄소막 패턴(16c)은 하부 전극(14)의 상부면과 하부 전극(14)의 주변에 있는 제1기판(12a) 적어도 일부가 노출되도록 형성될 수 있다. 비정질탄소막 패턴(16c) 상에는 제2기판(18a) 및 상부 전극(20)이 배치된다. 상부 전극(20)은 하부 전극(14)과 대향하는 위치에 배치될 수 있다. 따라서 하부 전극(14)은 상부 전극(20)과 비정질탄소막 패턴(16c)에 의하여 이격되어 배치될 수 있다. 물론, 하부 전극(14)과 상부 전극(20) 사이에는 비정질탄소막 패턴(16c)이 개재되지 않을 수 있다. An amorphous carbon film pattern 16c may be formed on a portion of the first substrate 12a. The amorphous carbon film pattern 16c does not exist on the remaining portion of the first substrate 12a. For example, the amorphous carbon film pattern 16c may be formed to expose at least a portion of the first substrate 12a around the upper surface of the lower electrode 14 and the lower electrode 14. The second substrate 18a and the upper electrode 20 are disposed on the amorphous carbon film pattern 16c. The upper electrode 20 may be disposed at a position facing the lower electrode 14. Therefore, the lower electrode 14 may be spaced apart from the upper electrode 20 by the amorphous carbon film pattern 16c. Of course, the amorphous carbon film pattern 16c may not be interposed between the lower electrode 14 and the upper electrode 20.
편의상 앞에서 설명한 제1기판(12a) 및/또는 하부 전극(14)을 포함하는 구조물을 하부 구조물로 명명하고, 제2기판(18a) 및/또는 상부 전극(20)을 포함하는 구조물을 상부 구조물로 명명할 수 있다. 이 경우 상부 구조물과 하부 구조물은 비정질탄소막 패턴(16c)에 의하여 이격되어 배치될 수 있다. For convenience, the structure including the first substrate 12a and / or the lower electrode 14 described above is referred to as a lower structure, and the structure including the second substrate 18a and / or the upper electrode 20 is referred to as an upper structure. You can name it. In this case, the upper structure and the lower structure may be spaced apart by the amorphous carbon film pattern 16c.
앞에서 설명한 것처럼, 제1기판(12a) 및 비정질탄소막 패턴(16c) 상에는 상부 구조물이 배치될 수 있다. 상부 구조물은 제2기판(18a) 및 상부 전극(20) 외에 솔더접합층(24) 및 패키징 캡층(26)을 더 포함할 수 있다. 제2기판(18a)은 MEMS 디바이스에서 디바이스층에 해당할 수 있다. 디바이스층의 두께는 임의로 조정될수 있으며, 다양한 형태의 구조를 가질 수 있다. 그리고, 제2기판(18a)은 상부 전극(20)을 포함할 수 있으며, 상부 전극(20)은 제2기판(18a)의 소정의 부위에 제2도전형의 물질을 주입하고, 제2기판(18a)을 열처리하여 형성할 수 있다. 상부 전극(20)은 비정질탄소막 패턴(16c)을 관통하여 하부 전극(14)과 대향하는 위치에 형성될 수 있다.As described above, an upper structure may be disposed on the first substrate 12a and the amorphous carbon film pattern 16c. The upper structure may further include a solder bonding layer 24 and a packaging cap layer 26 in addition to the second substrate 18a and the upper electrode 20. The second substrate 18a may correspond to a device layer in the MEMS device. The thickness of the device layer can be arbitrarily adjusted and can have various types of structures. The second substrate 18a may include an upper electrode 20, and the upper electrode 20 injects a second conductive material into a predetermined portion of the second substrate 18a and the second substrate. (18a) can be formed by heat treatment. The upper electrode 20 may be formed at a position facing the lower electrode 14 through the amorphous carbon film pattern 16c.
상부 전극(20)과 하부 전극(14)은 비정질탄소막 패턴(16c)의 두께에 해당하는 거리(d1)만큼 이격된다. 따라서, 상부 전극(20)은 하부 전극(14) 상에서 위치가 변동될 수 있도록 형성될 수도 있다.The upper electrode 20 and the lower electrode 14 are spaced apart by a distance d1 corresponding to the thickness of the amorphous carbon film pattern 16c. Therefore, the upper electrode 20 may be formed so that the position on the lower electrode 14 can be changed.
각각 도전성 평판인 상부 전극(20)과 하부 전극(14)이 서로 나란하게 대향되도록 배치될 때, 두 전극 사이의 전기용량은 두 전극 사이의 매질의 유전율과 마주보는 두 전극의 면적에 비례하고, 두 전극 사이의 이격 거리(d1)에 반비례하는 값으로 근사화될 수 있다. 두 전극이 상대적으로 상하 및/또는 좌우로 상대적인 이동이 발생하면 두 전극 사이의 간격이나 겹치는 면적이 변화하여 정전용량이 변화한다. 따라서, 이러한 정전용량의 변화를 전기적 신호로 출력하면 두 전극 사이의 상대적인 변위를 측정할 수 있다. When the upper electrode 20 and the lower electrode 14, each of which is a conductive plate, are disposed to face each other side by side, the capacitance between the two electrodes is proportional to the area of the two electrodes facing the dielectric constant of the medium between the two electrodes, It may be approximated to a value inversely proportional to the separation distance d1 between two electrodes. When the two electrodes move relative to each other up and down and / or left and right relatively, the gap or overlapping area between the two electrodes changes to change the capacitance. Therefore, by outputting the change in capacitance as an electrical signal it is possible to measure the relative displacement between the two electrodes.
제2기판(18a) 상에는 패키징 캡층(26)이 배치될 수 있다. 패키징 캡층(26)은 외부로부터 MEMS 디바이스를 보호하는 역할을 할 수 있다. 패키징 캡층(26)의 내부(28)는 진공을 유지할 수 있도록 밀봉될 수 있다. 제2기판(18a)과 패키징 캡층(26) 사이에는 솔더접합층(24)이 개재될 수 있다. 솔더접합층(24)은 금, 은, 구리, 주석, 인듐 및 실리콘 중에서 적어도 하나 이상을 포함할 수 있다.The packaging cap layer 26 may be disposed on the second substrate 18a. The packaging cap layer 26 may serve to protect the MEMS device from the outside. The interior 28 of the packaging cap layer 26 may be sealed to maintain vacuum. A solder joint layer 24 may be interposed between the second substrate 18a and the packaging cap layer 26. The solder joint layer 24 may include at least one of gold, silver, copper, tin, indium, and silicon.
나아가, MEMS 디바이스는 제1기판(12a) 및/또는 비정질탄소막 패턴(16c)을 관통하여 하부 전극(14) 및/또는 상부 전극(20)을 외부와 전기적으로 연결하는 관통전극(32)을 더 포함하고, 제1기판(12a)의 하부면에는 관통전극(32)과 전기적으로 연결되는 도전성 패드(34)를 더 포함할 수 있다. 단면 방향에 따라서, 단면도인 도 1에서는 상부 전극(20)과 제2기판(18a)이 분리되어 있는 것으로 도시되었지만, 실제로는 서로 연결되어 지지되는 구조를 가지므로 관통전극(32)과 상부 전극(20)은 전기적으로 연결될 수 있다. 관통전극(32)은 도전성 물질로 이루어질 수 있으며, 예를 들어, 구리, 텅스텐 및 알루미늄 등과 같은 물질로 이루어 질 수 있다.Furthermore, the MEMS device further includes a through electrode 32 penetrating the first substrate 12a and / or the amorphous carbon film pattern 16c to electrically connect the lower electrode 14 and / or the upper electrode 20 to the outside. The lower surface of the first substrate 12a may further include a conductive pad 34 electrically connected to the through electrode 32. According to the cross-sectional direction, although the upper electrode 20 and the second substrate 18a are shown as being separated in FIG. 1, which is a sectional view, the through electrode 32 and the upper electrode ( 20 may be electrically connected. The through electrode 32 may be made of a conductive material, for example, may be made of a material such as copper, tungsten, and aluminum.
예를 들어, 이 실시예에 따른 MEMS 디바이스는 자이로 센서로 이용될 수 있지만, 이 실시예의 범위가 이에 제한되는 것은 아니다.For example, the MEMS device according to this embodiment can be used as a gyro sensor, but the scope of this embodiment is not limited thereto.
도 8 내지 도 11은 본 발명의 다른 실시예에 따른 MEMS 디바이스의 제조 공정을 개략적으로 도시하는 단면도이다. 8 through 11 are cross-sectional views schematically showing a manufacturing process of a MEMS device according to another embodiment of the present invention.
도 8을 참조하면, 먼저 제1기판(12)을 준비한다. 제1기판(12)은 실리콘 기판일 수 있으며, 다양한 반도체 물질, 예컨대 IV족 반도체, III-V족 화합물 반도체, 또는 II-VI족 산화물 반도체를 포함할 수 있다. 예를 들어, IV족 반도체는 실리콘 이외에도 게르마늄 또는 실리콘-게르마늄을 포함할 수 있다. 기판의 종류로는 갈륨-비소 기판, 세라믹 기판, 석영 기판 및 디스플레이용 유리 기판 등으로 이루어질 수 있다.Referring to FIG. 8, first, a first substrate 12 is prepared. The first substrate 12 may be a silicon substrate, and may include various semiconductor materials such as group IV semiconductors, group III-V compound semiconductors, or group II-VI oxide semiconductors. For example, the group IV semiconductor may include germanium or silicon-germanium in addition to silicon. The substrate may be formed of a gallium arsenide substrate, a ceramic substrate, a quartz substrate, a display glass substrate, or the like.
그 다음, 제1기판(12) 내에 불순물을 주입하고 제1기판(12)을 열처리하여 하부 전극(14)을 형성한다. 불순물을 주입하여 하부 전극(14)을 형성하게 되면 하부 전극(14)은 제1기판(12)의 상부면에 돌출되지 않고 제1기판(12) 내에 형성할 수 있다. 이렇게 형성된 하부 전극(14)은 하부 전극(14)의 상부면과 제1기판(12)의 상부면 동일한 레벨(level)을 가진다. 한편, 변형된 실시예에서는, 하부 전극(14)은 제1기판(12a)의 상면 상에 돌출되게 배치할 수도 있다. Then, impurities are injected into the first substrate 12 and the first substrate 12 is heat treated to form the lower electrode 14. When the lower electrode 14 is formed by injecting impurities, the lower electrode 14 may be formed in the first substrate 12 without protruding from the upper surface of the first substrate 12. The lower electrode 14 thus formed has the same level as the upper surface of the lower electrode 14 and the upper surface of the first substrate 12. On the other hand, in the modified embodiment, the lower electrode 14 may be disposed to protrude on the upper surface of the first substrate 12a.
불순물을 주입하는 공정은 이온임플란트공정 또는 도핑공정을 포함할 수 있다. 불순물을 주입하는 공정에서, 예를 들어, PH3, AsH3 등과 같은 n형 불순물 소스 또는 BF3, BCl3 등과 같은 p형 불순물 소스를 사용할 수 있다. 이때 하부 전극(14)은 전기전도가 우수한 도체의 특성을 가질 수 있다.The process of injecting impurities may include an ion implant process or a doping process. In the impurity implantation process, for example, an n-type impurity source such as PH 3 , AsH 3, or the like, or a p-type impurity source such as BF 3 , BCl 3, or the like may be used. In this case, the lower electrode 14 may have characteristics of a conductor having excellent electrical conductivity.
기판(12a) 상에는 희생층으로서 비정질 탄소막을 형성할 수 있다. 도 9를 참조하면, 하부 전극(14)이 내부에 형성된 제1기판(12) 상에 비정질탄소막(16)을 형성할 수 있다. 상기 비정질탄소막(16)을 형성하는 단계는 화학기상증착법을 이용하여 비정질탄소막(16)을 형성할 수 있다. 비정질탄소막(16)은 여러 가지 기술에 의해 증착될 수 있지만, 비용 효율성 및 막 특성 조정 가능성으로 인해 예를 들어, 플라즈마 강화 화학기상증착(PECVD)법을 사용할 수 있다.An amorphous carbon film can be formed on the substrate 12a as a sacrificial layer. Referring to FIG. 9, an amorphous carbon film 16 may be formed on the first substrate 12 having the lower electrode 14 formed therein. In the forming of the amorphous carbon film 16, the amorphous carbon film 16 may be formed using chemical vapor deposition. The amorphous carbon film 16 may be deposited by various techniques, but, for example, plasma enhanced chemical vapor deposition (PECVD) may be used due to the cost efficiency and the possibility of adjusting the film properties.
이러한 화학기상증착법을 수행하는 온도는 200℃ 내지 600℃에서 수행할 수 있다. 예를 들어, 아르곤을 희석 가스로 사용하는 경우 기판 온도는 증착 중에 약 300℃ 만큼 낮은 온도로 감소될 수 있다. 기판에 대해 더 낮은 처리 온도는 프로세스의 열부담(thermal budget)을 낮춰서 도펀트 이동으로부터 기판상에 형성된 디바이스를 보호할 수 있다. 또한 반도체 후공정과 동일한 온도에서 공정이 이루어질 수 있다. 따라서 기존의 반도체 공정에서 이미 사용되고 있는 공정 기술들을 충분히 이용할 수 있기 때문에 제조 단가를 낮출 수 있다.The temperature for performing the chemical vapor deposition method may be carried out at 200 ℃ to 600 ℃. For example, when argon is used as the diluent gas, the substrate temperature may be reduced to as low as about 300 ° C. during deposition. Lower processing temperatures for the substrate can lower the thermal budget of the process to protect the devices formed on the substrate from dopant movement. In addition, the process may be performed at the same temperature as the semiconductor post-process. Therefore, the manufacturing cost can be lowered because the process technology already used in the existing semiconductor process can be fully utilized.
도 10을 참조하면, 제1기판(12)과 비정질탄소막(16) 상에 상부 구조물을 형성할 수 있다. 상부 구조물은 제2기판(18a) 및 상부 전극(20)을 포함할 수 있다. 제2기판(18a)은 예를 들어, 실리콘 기판일 수 있다. 제2기판(18a)은 MEMS 디바이스에서 디바이스층에 해당할 수 있다. 디바이스층의 두께는 실리콘 기판의 접합 및/또는 박형화(thinning)를 통하여 임의로 조정될 수 있으며, 예를 들어 10 ㎛ 내지 100 ㎛의 범위를 가질 수 있다. 계속하여, 제2기판(18a)에 노광, 식각 및 세정 공정 등을 수행한다. 예를 들어, 상기 식각 공정은 소위 Deep RIE(Reactive Ion Etching) 방식을 사용하여 수행될 수 있다.Referring to FIG. 10, an upper structure may be formed on the first substrate 12 and the amorphous carbon film 16. The upper structure may include a second substrate 18a and an upper electrode 20. The second substrate 18a may be, for example, a silicon substrate. The second substrate 18a may correspond to a device layer in the MEMS device. The thickness of the device layer can be arbitrarily adjusted through bonding and / or thinning of the silicon substrate, for example, can range from 10 μm to 100 μm. Subsequently, the second substrate 18a is subjected to exposure, etching, and cleaning processes. For example, the etching process may be performed by using a so-called Deep RIE (Reactive Ion Etching) method.
제2기판(18a)은 다양한 형태의 소정의 구조물을 포함할 수 있다. 예를 들어, 제2기판(18a)의 소정의 부위에 불순물을 주입하고 제2기판(18a)을 열처리하여 상부 전극(20)을 형성할 수 있다. 불순물을 주입하는 공정은 이온임플란트공정 또는 도핑공정을 포함할 수 있다. 한편, 불순물을 주입하는 공정에서, 예를 들어, PH3, AsH3 등과 같은 n형 불순물 소스 또는 BF3, BCl3 등과 같은 p형 불순물 소스를 사용할 수 있다.The second substrate 18a may include a predetermined structure of various forms. For example, the upper electrode 20 may be formed by implanting impurities into a predetermined portion of the second substrate 18a and heat treating the second substrate 18a. The process of injecting impurities may include an ion implant process or a doping process. In the impurity implantation process, for example, an n-type impurity source such as PH 3 , AsH 3, or the like, or a p-type impurity source such as BF 3 or BCl 3 may be used.
상부 구조물을 형성하는 단계는 화학기상증착법에 의하여 텅스텐을 증착하는 단계를 더 포함할 수 있다. 화학기상증착법에 의한 텅스텐 증착은 WF6/H2 혼합가스를 이용하여 생성할 수 있다. WF6은 실리콘, 수소 및 실란(silane)에 의해 환원될 수 있고, 실리콘과 접촉하게 되면, 실리콘의 환원 반응으로부터 선택적 반응이 시작될 수 있다. 수소 환원 반응은 플러그를 형성하면서 핵 생성층 위에 빠르게 텅스텐을 증착할 수 있으며, 실란(silane) 환원 반응은 빠른 증착 속도와 수소 환원 반응에서 얻을 수 있는 것보다 더 작은 텅스텐 결정립 크기를 얻을 수 있다. 이러한 반응에 의해 형성된 텅스텐 박막은 스텝 커버리지(step coverage) 특성이 좋고 타 물질에 비해 저항 성분이 낮아 중요 도선재료로 취급될 수 있다.Forming the upper structure may further include depositing tungsten by chemical vapor deposition. Tungsten deposition by chemical vapor deposition can be produced using a WF 6 / H 2 mixed gas. WF 6 can be reduced by silicon, hydrogen and silane, and upon contact with silicon, a selective reaction can be started from the reduction reaction of silicon. Hydrogen reduction reactions can rapidly deposit tungsten on the nucleation layer while forming plugs, and silane reduction reactions can achieve faster deposition rates and smaller tungsten grain sizes than those obtainable in hydrogen reduction reactions. The tungsten thin film formed by such a reaction has a good step coverage property and a low resistance component compared to other materials, and thus may be treated as an important conductor material.
도 10 내지 도 11을 참조하면, 하부 전극(14)과 상부 전극(20) 사이에 개재되는 비정질탄소막(16)의 일부를 제거하여 비정질탄소막 패턴(16b)을 형성할 수 있다. 비정질탄소막(16)의 일부를 제거하는 공정은 상부 구조물 중 적어도 어느 하나 예를 들어, 제2기판(18a)을 형성한 후 제거할 수 있으며, 습식 식각 및/또는 건식 식각을 이용할 수 있다. 예를 들어, 건식 식각 방식 중 하나인 산소(O2) 플라즈마(Plasma)를 이용하여 비정질탄소막(16)의 일부를 선택적으로 쉽게 제거할 수 있다. 산소(O2) 플라즈마(Plasma)를 이용하게 되면, 많은 종류의 무기물과도 우수한 식각 선택비를 가질 수 있고, 필름 두께도 쉽게 조절할 수 있다. 따라서 하부 전극(14)은 상부 전극(20)과 둘 사이의 이격거리를 조절하는데 용이할 수 있으며, 정전용량의 균일성을 확보하기 쉬어 MEMS 디바이스의 안정적인 동작을 확보할 수 있다. 10 to 11, a portion of the amorphous carbon film 16 interposed between the lower electrode 14 and the upper electrode 20 may be removed to form the amorphous carbon film pattern 16b. The process of removing a portion of the amorphous carbon film 16 may be removed after forming at least one of the upper structures, for example, the second substrate 18a, and may use wet etching and / or dry etching. For example, a portion of the amorphous carbon film 16 may be easily removed by using an oxygen (O 2) plasma, which is one of dry etching methods. By using an oxygen (O 2) plasma, it is possible to have an excellent etching selectivity with many kinds of inorganic materials and to easily control the film thickness. Therefore, the lower electrode 14 may be easy to adjust the separation distance between the upper electrode 20 and the two, it is easy to ensure the uniformity of the capacitance can ensure a stable operation of the MEMS device.
한편, 상부 구조물은 제2기판(18a) 및 상부 전극(20) 이외에 솔더접합층(24) 및 패키징 캡층(26)을 더 포함할 수 있다. 패키징 캡층(26)은 제2기판(18a) 상에 부착될 수 있고, 패키징 캡층(26)의 내부(28)는 진공을 유지할 수 있도록 밀봉될 수 있으며, 제2기판(18a)과 패키징 캡층(26) 사이에는 솔더접합층(24)을 개재할 수 있다. 솔더접합층(24)을 형성하는 물질로는 금, 은, 구리, 주석, 인듐 및 실리콘 중에서 적어도 하나 이상을 포함하여 이루어질 수 있다. 예를 들어, 솔더접합층(24)은 구리/주석, 금/인듐, 금/주석, 금/실리콘, 구리/금/주석 등과 같은 다양한 이원계 또는 삼원계의 솔더 합금으로 이루어질 수 있다.The upper structure may further include a solder bonding layer 24 and a packaging cap layer 26 in addition to the second substrate 18a and the upper electrode 20. The packaging cap layer 26 may be attached on the second substrate 18a, and the interior 28 of the packaging cap layer 26 may be sealed to maintain a vacuum, and the second substrate 18a and the packaging cap layer ( The solder joint layer 24 can be interposed between 26). The material for forming the solder joint layer 24 may include at least one of gold, silver, copper, tin, indium, and silicon. For example, the solder bonding layer 24 may be made of various binary or ternary solder alloys such as copper / tin, gold / indium, gold / tin, gold / silicon, copper / gold / tin, and the like.
앞에서 살펴본 바와 같이, 본 발명의 기술적 사상에 따른 MEMS 디바이스는 실리콘기판 상에 희생층으로서 비정질탄소막 패턴을 형성하므로, 화학기상증착법에 의한 텅스텐 증착 공정을 사용할 수 있어, 스텝 커버리지(Step Coverage)가 우수하고, 배선의 모양이나 전기적 특성 면에서 우수한 디바이스를 제작할 수 있다. 또한 반도체 후공정과 동일한 온도에서 공정이 이루어지므로, 기존의 반도체 공정에서 이미 사용되고 있는 공정 기술들을 충분히 이용할 수 있다.As described above, the MEMS device according to the technical concept of the present invention forms an amorphous carbon film pattern as a sacrificial layer on a silicon substrate, so that a tungsten deposition process by chemical vapor deposition can be used, thereby providing excellent step coverage. In addition, a device excellent in the shape and electrical properties of the wiring can be manufactured. In addition, since the process is performed at the same temperature as the post-semiconductor process, the process technology already used in the existing semiconductor process can be fully utilized.
본 발명은 도면에 도시된 실시예를 참고로 설명되었으나 이는 예시적인 것에 불과하며, 당해 기술분야에서 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 다른 실시예가 가능하다는 점을 이해할 것이다. 따라서 본 발명의 진정한 기술적 보호 범위는 첨부된 특허청구범위의 기술적 사상에 의하여 정해져야 할 것이다.Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (12)

  1. 하부 구조물을 형성하는 단계;Forming an undercarriage;
    상기 하부 구조물 상에 희생층으로서 비정질 탄소막을 형성하는 단계;Forming an amorphous carbon film on the lower structure as a sacrificial layer;
    상기 비정질 탄소막 상에 절연지지층을 형성하는 단계;Forming an insulating support layer on the amorphous carbon film;
    상기 절연지지층 상에 식각 보호막을 형성하고 상기 절연지지층 및 상기 비정질 탄소막을 한 번에 식각하여, 상기 절연지지층 및 상기 비정질 탄소막을 관통하여 상기 하부 구조물을 노출하는 비어홀들을 형성하는 단계;Forming an etch passivation layer on the insulating support layer and etching the insulating support layer and the amorphous carbon film at once to form via holes through the insulating support layer and the amorphous carbon film to expose the lower structure;
    상기 절연지지층 상에 센서 구조를 포함하는 상부 구조물을 형성하는 단계;Forming an upper structure including a sensor structure on the insulating support layer;
    상기 절연지지층을 관통하는 적어도 하나의 관통홀을 형성하는 단계; 및Forming at least one through hole penetrating the insulating support layer; And
    상기 하부 구조물과 상기 상부 구조물이 서로 이격되어 배치되도록, 상기 관통홀들을 통해서 상기 비정질 탄소막을 모두 제거하는 단계;Removing all of the amorphous carbon film through the through holes such that the lower structure and the upper structure are spaced apart from each other;
    를 포함하는, 멤스 디바이스 제조 방법.Including, MEMS device manufacturing method.
  2. 제1항에 있어서,The method of claim 1,
    상기 비정질 탄소막을 형성하는 단계는 화학기상증착법(CVD)을 이용하여 수행하는, 멤스 디바이스 제조 방법.The forming of the amorphous carbon film is performed using chemical vapor deposition (CVD), MEMS device manufacturing method.
  3. 제2항에 있어서,The method of claim 2,
    상기 화학기상증착법을 수행하는 온도는 200℃ 내지 600℃인, 멤스 디바이스 제조 방법. The temperature for performing the chemical vapor deposition method is 200 ℃ to 600 ℃, MEMS device manufacturing method.
  4. 제1항에 있어서,The method of claim 1,
    상기 비정질 탄소막을 제거하는 단계는 건식 식각 방식을 포함하는, 멤스 디바이스 제조 방법Removing the amorphous carbon film includes a dry etching method, MEMS device manufacturing method
  5. 제4항에 있어서,The method of claim 4, wherein
    상기 건식 식각 방식은 산소(O2) 플라즈마(Plasma)를 이용하여 수행하는, 멤스 디바이스 제조 방법.The dry etching method is performed by using an oxygen (O 2 ) plasma (Plasma), MEMS device manufacturing method.
  6. 제1항에 있어서, 상기 상부 구조물을 형성하는 단계는, 상기 비정질 탄소막 상에 절연지지층을 형성하는 단계를 더 포함하는, 멤스 디바이스 제조 방법.The method of claim 1, wherein the forming of the upper structure further comprises forming an insulating support layer on the amorphous carbon film.
  7. 제1항에 있어서, 상기 비어홀들을 형성하는 단계 후, 상기 비어홀들을 통해서 상기 하부 전극들과 연결되도록 상기 하부 전극들 상에 금속 앵커들을 형성하는 단계를 더 포함하는, 멤스 디바이스 제조 방법.The method of claim 1, further comprising forming metal anchors on the lower electrodes to be connected to the lower electrodes through the via holes.
  8. 제6항에 있어서,The method of claim 6,
    상기 상부 구조물을 형성하는 단계는, 상기 절연지지층 상에 흡수층을 형성하는 단계를 더 포함하는, 멤스 디바이스 제조 방법.The forming of the upper structure further comprises forming an absorbing layer on the insulating support layer.
  9. 제1항에 있어서,The method of claim 1,
    상기 하부 구조물은 상기 센서 구조를 제어하기 위한 판독집적회로(ROIC)를 포함하는, 멤스 디바이스 제조 방법.And the lower structure includes a read integrated circuit (ROIC) for controlling the sensor structure.
  10. 제8항에 있어서,The method of claim 8,
    상기 센서 구조는 적외선 센서를 포함하는, 멤스 디바이스 제조 방법.And the sensor structure comprises an infrared sensor.
  11. 제1항에 있어서,The method of claim 1,
    상기 희생층의 두께는 0.5 내지 5㎛ 범위인, 멤스 디바이스 제조 방법.The thickness of the sacrificial layer is in the range of 0.5 to 5㎛, MEMS device manufacturing method.
  12. 제1항에 있어서,The method of claim 1,
    상기 상기 절연지지층 및 상기 비정질 탄소막을 관통하여 상기 하부 구조물을 노출하는 비어홀들을 형성하는 단계는 한 번의 포토리소그래피 공정만으로 수행되는, 멤스 디바이스 제조 방법.Forming via holes through the insulating support layer and the amorphous carbon film to expose the underlying structure using only one photolithography process.
PCT/KR2013/000832 2013-02-01 2013-02-01 Mems device manufacturing method WO2014119810A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/KR2013/000832 WO2014119810A1 (en) 2013-02-01 2013-02-01 Mems device manufacturing method
CN201380071919.3A CN104955765B (en) 2013-02-01 2013-02-01 MEMS manufacture method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/KR2013/000832 WO2014119810A1 (en) 2013-02-01 2013-02-01 Mems device manufacturing method

Publications (1)

Publication Number Publication Date
WO2014119810A1 true WO2014119810A1 (en) 2014-08-07

Family

ID=51262508

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2013/000832 WO2014119810A1 (en) 2013-02-01 2013-02-01 Mems device manufacturing method

Country Status (2)

Country Link
CN (1) CN104955765B (en)
WO (1) WO2014119810A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6664154B1 (en) * 2002-06-28 2003-12-16 Advanced Micro Devices, Inc. Method of using amorphous carbon film as a sacrificial layer in replacement gate integration processes
KR20040109999A (en) * 2003-06-19 2004-12-29 한국전자통신연구원 Infrared ray sensor using silicon oxide film as a infrared ray absorption layer and method for fabricating the same
US20060187523A1 (en) * 2003-10-27 2006-08-24 Pan Shaoher X Fabricating micro devices using sacrificial materials
US20100181631A1 (en) * 2009-01-21 2010-07-22 Joseph Damian Gordon Lacey Fabrication of mems based cantilever switches by employing a split layer cantilever deposition scheme
US20120170102A1 (en) * 2010-12-31 2012-07-05 Payne Justin Spatial Light Modulators and Fabrication Techniques
KR101250447B1 (en) * 2011-12-12 2013-04-08 한국과학기술원 Method for making mems devices

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102530831B (en) * 2010-12-27 2014-05-21 上海丽恒光微电子科技有限公司 Manufacture method for MEMS (Micro-electromechanical Systems) device
CN102693935A (en) * 2011-03-22 2012-09-26 中芯国际集成电路制造(上海)有限公司 Manufacturing method of interconnection structure
CN102180441B (en) * 2011-04-01 2012-12-19 上海丽恒光微电子科技有限公司 Micro electromechanical device and manufacturing method thereof
US8368152B2 (en) * 2011-04-18 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS device etch stop
CN102328904B (en) * 2011-09-30 2015-05-13 上海丽恒光微电子科技有限公司 Method for forming microelectro mechanical system (MEMS) device
CN102515090B (en) * 2011-12-21 2014-11-05 上海丽恒光微电子科技有限公司 Pressure sensor and formation method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6664154B1 (en) * 2002-06-28 2003-12-16 Advanced Micro Devices, Inc. Method of using amorphous carbon film as a sacrificial layer in replacement gate integration processes
KR20040109999A (en) * 2003-06-19 2004-12-29 한국전자통신연구원 Infrared ray sensor using silicon oxide film as a infrared ray absorption layer and method for fabricating the same
US20060187523A1 (en) * 2003-10-27 2006-08-24 Pan Shaoher X Fabricating micro devices using sacrificial materials
US20100181631A1 (en) * 2009-01-21 2010-07-22 Joseph Damian Gordon Lacey Fabrication of mems based cantilever switches by employing a split layer cantilever deposition scheme
US20120170102A1 (en) * 2010-12-31 2012-07-05 Payne Justin Spatial Light Modulators and Fabrication Techniques
KR101250447B1 (en) * 2011-12-12 2013-04-08 한국과학기술원 Method for making mems devices

Also Published As

Publication number Publication date
CN104955765B (en) 2018-02-13
CN104955765A (en) 2015-09-30

Similar Documents

Publication Publication Date Title
US9731962B2 (en) MEMS device and fabrication method
US7115853B2 (en) Micro-lens configuration for small lens focusing in digital imaging devices
TWI556331B (en) Micro-electromechanical device and method for forming the same
US7993950B2 (en) System and method of encapsulation
EP3542404B1 (en) Method of making a josephson junction based superconductor device
US10889493B2 (en) MEMS method and structure
KR101989271B1 (en) Integrated circuit and image sensing device having metal shielding layer and related fabricating method
KR101250447B1 (en) Method for making mems devices
TW202312378A (en) Systems and methods for providing getters in microelectromechanical systems
KR20120120143A (en) Method of making a support structure
KR101408904B1 (en) Method of fabricating MEMS devivce at high temperature process
KR20190062128A (en) Image sensor with pad structure
EP3635351B1 (en) Microelectromechanical (mems) fabry-perot interferometer, apparatus and method for manufacturing fabry-perot interferometer
CN111384077B (en) Semiconductor sensor package and method of forming the same
KR101388927B1 (en) Method of fabricating mems device using amorphous carbon layer with promoted adhesion
CN101625985B (en) Semiconductor structure and manufacturing method thereof
WO2014119810A1 (en) Mems device manufacturing method
US8691610B1 (en) Semiconductor device and method for manufacturing the same
TWI734502B (en) Integrated circuit device, method of manufacturing thereof, and semiconductor image sensing device
WO2018221753A1 (en) Mems device and manufacturing method therefor
CN102034756B (en) Interconnection packaging method of image sensor
KR102121898B1 (en) MEMS device package
CN102916026A (en) Forming method of image sensor
US8987034B2 (en) Backside illumination CMOS image sensor and method of manufacturing the same
CN102942158A (en) Manufacturing method of detection structure

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13873747

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13873747

Country of ref document: EP

Kind code of ref document: A1