CN102034756B - Interconnection packaging method of image sensor - Google Patents
Interconnection packaging method of image sensor Download PDFInfo
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- CN102034756B CN102034756B CN200910196809.5A CN200910196809A CN102034756B CN 102034756 B CN102034756 B CN 102034756B CN 200910196809 A CN200910196809 A CN 200910196809A CN 102034756 B CN102034756 B CN 102034756B
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Abstract
The invention discloses an interconnection packaging method of a COMS (complementary metal oxide semiconductor) image sensor. The method comprises the following steps: manufacturing a conducting channel at an area, which is used for manufacturing packaging wiring, on the surface of a wafer device; then manufacturing an image sensor at an area, which is used for manufacturing the device, on the surface of the wafer device; manufacturing a linkage structure used for connecting electrically the conducting channel and the image sensor at the area used for manufacturing the packaging wiring; and finally etching at the other side of the wafer, and forming a silicon through hole conducted with the conducting channel. The method also comprises: filling and doping silicon polycrystal or metal in a channel, so that the conducting channel and a conducting embolism of the CMOS image sensor are arranged to be in electrical contact, and the conducting channel is interconnected with the metal layer and electrode of the CMOS image sensor. By the method provided by the invention, the silicon through-hole method is improved, etching is carried out more easily, depth-to-width ratio of the silicon through hole is reduced, filling of a silicon through-hole insulating layer and the conducting metal is much easier, and the yield of finished products is improved.
Description
Technical field
The present invention relates to a kind of semiconductor fabrication techniques, particularly a kind of interconnection packaging method of imageing sensor.
Background technology
Sensitive integrated circuits is the important component part of imageing sensor, is widely used in digital camera, Digital Video, mobile phone and other many portable sets.In general, imageing sensor is a kind of semiconductor device, and its effect is that optical image signal is converted to the signal of telecommunication, and carries out storing and transmitting.Imageing sensor can be divided into two classes substantially, namely a class is charge coupled device (CCD, Charge-coupled Device), another kind of is CMOS (Complementary Metal Oxide Semiconductor) (CMOS, Complementary Metal Oxide Semiconductor).Both utilize photodiode to carry out opto-electronic conversion, optical imagery is converted to the signal of telecommunication, and its Main Differences is the mode difference of signal transmission.Ccd image sensor is by carrying out transmission of electric signals to the Sustainable Control of the potential well depth on electric signal transmission direction.Cmos image sensor (being included in pixel unit cell) one or more transistor and photodiode realize optical image sensing, and wherein photodiode is as optical pickocff.Because ccd image sensor compares the advantage that cmos image sensor has low noise, high sensitivity and high image quality (resolution), it is more suitable for digital camera.On the contrary, in general, it is less that cmos image sensor compares ccd image sensor power consumption, only has 1% of ccd image sensor.Especially, due to the semiconductor fabrication process that cmos image sensor adopts general semiconductor circuit the most frequently used, can easily cmos image sensor be integrated in peripheral circuit system, the operating system of such as amplifier and signal processor, thus greatly reduce manufacturing cost.In addition, cmos image sensor arithmetic speed is very fast.Therefore, cmos image sensor has been applied in the camera of mobile phone and personal digital assistant (PDA, Personal digital Assistant).But, along with the technical development of cmos image sensor, the technological disparity between cmos image sensor and ccd image sensor progressively reduces.Up to the present, be with the encapsulation of cmos image sensor chip lead associated methods in cmos image sensor manufacture.But, the foreign matter that wire bonding method produces can cause cmos image sensor to respond to the image deflects of window, therefore the rate of finished products in cmos image sensor encapsulation process reduces, and the dark wide height of cmos image sensor all can increase, and causes difficulty to the reduction of cmos image sensor size.Along with consumer is to the increase of equipment portability demand, a kind of development passing through the three-dimensional packaging technology that silicon through hole (TSV, Through Silicon Via) realizes substantially reduces the device size of cmos image sensor.But, when the size of the silicon through hole that interconnects is reduced to micron order, just challenge is proposed to semi-conductor industry technology now.Traditional silicon through hole etches from wafer device side, until wafer another side, but this method can cause the uneven of silicon via depth owing to not having etching stop layer, thus cause the difficulty that the cmp of wafer another side (CMP, Chemical Mechanical Polishing) controls.In order to overcome the problems referred to above, the patent application of U.S. Patent Publication No.: 20080217715A1 proposes a kind of method for packing of another side silicon through hole.
Fig. 1 is the method that prior art adopts silicon through hole method interconnection cmos image sensor, and Fig. 2 a ~ 2g is the method designs simplification profile that prior art adopts silicon through hole method interconnection cmos image sensor, and concrete steps are,
Step 101, is formed with source region isolation channel 30 at wafer 10 device side 10a;
This step comprises, and in wafer 10 device side 10a photoetching with etch isolated area 20, obtains structure as shown in Figure 2 a, comprises wafer 10 and isolated area 20;
In this step, the photoetching of isolated area 20 and etching comprise several step:
First one deck photoresist is smeared at wafer 10 device side 10a, then mask pattern as required carries out exposing and development makes photoresist patterned, do not etched by the part that photoetching agent pattern covers wafer 10 device side 10a, finally cleaning remains in the photoresist of wafer 10 device side 10a;
As Fig. 2 b, chemical vapour deposition (CVD) (CVD, Chemical VaporDeposition) method deposition of silica insulating material is adopted to the isolated area 20 etched, form isolation channel 30;
Step 102, wafer 10 device side 10a carries out the semiconductor fabrication process of cmos image sensor 70 and adds electrode 40 and cemented lens and glass 80, obtain structure as shown in Figure 2 c, comprise wafer 10, isolation channel 30, electrode 40, cmos image sensor 70 is (comprising the conductive plug arrangement of cmos image sensor and the metal level of cmos image sensor, do not draw), and lens above device and glass 80 (concrete structure omits, and does not draw);
In this step, lens and glass 80 are isolated cmos image sensor 70 and electrode 40 with external environment, play the effect of protection cmos image sensor 70 and electrode 40;
Step 103, carries out cmp to the another side 10b of wafer 10, obtains structure as shown in Figure 2 d, and the object of cmp makes more easily to carry out in the silicon through hole step at the another side 10b place of wafer 10 subsequently;
In this step, the wafer thickness after cmp wants the requirement that can meet wafer robustness (resistance to wear), in general, preferably controls between 50 microns to 100 microns to the thickness range of wafer after grinding;
Step 104, position etch silicon through hole 90 corresponding below the electrode 40 of wafer 10 another side 10b, silicon through hole 90 will be formed from wafer 10 another side 10b until penetrant structure below electrode 40, obtain structure as shown in Figure 2 e, comprise isolation channel 30, electrode 40, imageing sensor 70, lens and glass 80 and silicon through hole 90;
In this step, silicon through hole directly can be formed by the method for dry etching, and silicon through hole also can adopt first dry etching to form non-penetrative silicon through hole in addition, then removes the method formation of residual fraction on wafer with dry method or wet etching; Here, the diameter range of silicon through hole is 50 microns to 100 microns, and best value is 70 microns.Although silicon shape of through holes is generally circle, also can be various shape, such as: triangle, quadrangle or polygon; The size of silicon through hole can be greater than, be less than or equal to the size of size below electrode 40;
Whole silicon via process needs to etch each layer different materials, such as: the inter-level dielectric (ILD comprising COMS imageing sensor, Interlayer Dielectrics) and comprise the inter-metal medium (IMD of COMS imageing sensor, Intermetal Dielectrics), due to materials variances, cause the difficulty that etching controls.In addition, the silicon via depth that this silicon through hole method is formed is large, has larger depth-to-width ratio, can cause the difficulty of silicon through hole insulation film deposition and silicon via metal;
Step 105, at the surface deposition insulation film of silicon through hole and wafer another side;
In this step, insulation film deposition adopts chemical vapor deposition silicon dioxide insulator material;
Step 106, etches away the insulation film 100 of base part, exposes electrode, obtain structure as shown in figure 2f, comprise electrode 40, imageing sensor 70, lens and glass 80, silicon through hole 90 and insulation film 100;
In this step, first at insulation film 100 surface smear one deck photoresist of silicon through hole 90 and wafer 10 another side 10b, then mask pattern as required carries out exposing and development makes photoresist patterned, do not etched by the silicon through hole insulation film surface portion that photoetching agent pattern covers being positioned at base part, finally cleaning remains in the photoresist of the silicon dioxide insulator film surface of silicon through hole and wafer another side;
Step 107, inserts metal and adds soldered ball 120 in metal surface in silicon through hole 90, obtains structure as shown in Figure 2 g, comprises insulation film 100, metal SiClx through hole 110 and soldered ball 120;
Step 108, carries out Wafer Dicing.
In the above process, forming silicon via process needs to etch each layer different materials, due to materials variances, makes etching control difficulty.In addition, the silicon via depth that this silicon through hole method is formed is large, and has larger depth-to-width ratio, silicon through hole insulation film can be caused to deposit and metal filled difficulty, reduces manufacture feasibility and the rate of finished products of cmos image sensor.
Summary of the invention
In view of this, the technical problem that the present invention solves is: use silicon through hole method need to be etched through each layer different materials thus cause the difficulty that etching controls, and form larger silicon via depth and depth-to-width ratio, be unfavorable for the carrying out of insulation film deposition and metal filling processes subsequently.
For solving the problem, technical scheme of the present invention is specifically achieved in that
An interconnection packaging method for imageing sensor, the method comprises: the wafer device side of side makes conducting channel under the electrodes; Be used for the region making image transducer of making devices in described wafer device side, and make the syndeton for being electrically connected conducting channel and imageing sensor in the region for making package interconnects; Etch at wafer another side, form silicon through hole;
At silicon through-hole wall deposition insulation film;
After insulation film deposition, etch away the insulation film below conducting channel;
In silicon through hole, insert metal, and add soldered ball in metal surface.
The process of described making conducting channel is:
In the active area isolation stage, in wafer device side for making the increase channel region, region of package interconnects, after deposition of silica is as dielectric, photoetching and partial etching are carried out to the silicon dioxide of channel region, then in channel region deposits conductive material as conducting medium, last conducting channel carries out cmp, removes unnecessary surface conductance material and silicon dioxide insulator medium.
When the described silicon dioxide to raceway groove etches, the degree of depth is no more than the degree of depth of raceway groove.
In this step, in raceway groove, deposits conductive material is conducting metal or doped polycrystalline silicon;
The deposition chemical gaseous phase depositing process of described silicon dioxide and electric conducting material carries out.
The described process made for the syndeton being electrically connected conducting channel and imageing sensor in the region for making package interconnects is:
The conductive plug arrangement adding COMS imageing sensor above conducting channel forms electrical contact, then makes metal level and the conductive plug electric connection of COMS imageing sensor, until the electrode of conducting channel and wafer device side forms electric connection.
Describedly etching at wafer another side, is realize with dry etching.
Describedly etching at wafer another side, is until the silicon dioxide etched away below conducting channel exposes conducting channel.
Described formation silicon through hole, the degree of depth is less than 50 microns.
Described formation silicon through hole, diameter range is between 1 micron to 50 microns.
Describedly in silicon through hole, insert metal, be also included in metal surface and add soldered ball.
Described at silicon through-hole wall deposition insulation film, be realize with chemical vapor deposition silicon dioxide.
As seen from the above technical solutions, the present invention's square one-tenth conducting channel under the electrodes in active area isolation process, the conductive plug arrangement of cmos image sensor part is added above conducting channel, metal level and electrode, conducting channel and conductive plug arrangement is made to form electrical contact, and by conductive plug with being communicated with of each metal level of COMS imageing sensor make the electrode of conducting channel and wafer device side form electric connection, make can stop at conducting channel place in the silicon via etch of wafer another side subsequently, namely conducting channel is as the stop-layer of silicon via etch, reduce the control difficulty of silicon via etch, depth-to-width ratio, little silicon clear size of opening be not only conducive to insulation film deposition and metal filled, and electrode district area can be saved, increase the number of transistors of active area, thus raising silicon through hole method carries out manufacture feasibility and the rate of finished products of the cmos image sensor interconnected.
Accompanying drawing explanation
Fig. 1 is prior art silicon through hole method image sensor package interconnection flow chart;
Fig. 2 a ~ Fig. 2 g is the designs simplification profile of prior art silicon through hole method image sensor package interconnection process;
Fig. 3 is that the present invention adopts conducting channel silicon through hole method packaging interconnection imageing sensor flow chart;
Fig. 4 a ~ Fig. 4 i is the designs simplification profile that the present invention adopts conducting channel silicon through hole method packaging interconnection imageing sensor process.
Embodiment
For making object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in more detail.
The present invention proposes a kind of interconnection packaging method of cmos image sensor, first the method makes conducting channel in wafer device side for the region making package interconnects in active area isolation process, then the region making image transducer of making devices is used in wafer device side, and make the syndeton for being electrically connected conducting channel and imageing sensor in the region for making package interconnects, conductive plug as cmos image sensor part arranges, metal level and electrode, conducting channel and conductive plug arrangement is made to form electrical contact, and make the electrode of conducting channel and wafer device side form electric connection by conductive plug with being communicated with of metal level, finally etch at wafer another side, form the silicon through hole with conducting channel conducting, in silicon via etch, etching can stop at conducting channel place, namely conducting channel is as the stop-layer of wafer another side silicon via etch, reduce the control difficulty of silicon via etch, depth-to-width ratio, little silicon clear size of opening be not only conducive to insulation film deposition and metal filled, and electrode district area can be saved, increase the number of transistors of active area, thus raising silicon through hole method carries out manufacture feasibility and the rate of finished products of the conventional CMOS image sensor interconnected.
The designs simplification profile of the inter-level interconnects technological improvement wafer silicon through hole method of the employing conducting channel shown in composition graphs 4a ~ Fig. 4 i and cmos image sensor, illustrate the flow chart that electrical contact that the present invention shown in Fig. 3 adopts the conductive plug of conducting channel and cmos image sensor to arrange realizes reducing the silicon via etch degree of depth, its concrete steps are:
Step 301, form conducting channel 31 and active area isolation raceway groove 30 at wafer 10 device side 10a;
This step comprises, and first carries out photoetching, etching and silica deposit technique at wafer 10 device side 10a and is manufactured with source region isolation channel 30 and electrode position isolation channel 11, obtain the structure shown in Fig. 4 a;
Photoetching in this step and etching refer to, first smear one deck photoresist at wafer 10 device side 10a, then mask pattern as required carries out exposing and development makes photoresist patterned, to wafer 10 device side 10a not by partial etching that photoetching agent pattern covers, form isolated area, finally cleaning remains in the photoresist of wafer 10 device side 10a;
Silica deposit technique in this step refers to and adopts chemical vapor deposition silicon dioxide insulator material to the isolated area etched, and is formed with source region isolation channel 30 and electrode position isolation channel 11;
Secondly, photoetching and etch conducting channel district 21 in isolation channel 11, obtains the structure shown in Fig. 4 b;
Photoetching in this step and etching refer to, first one deck photoresist is smeared at wafer 10 device side 10a, then mask pattern as required carries out exposing and development makes photoresist patterned, do not etched by the part that photoetching agent pattern covers wafer 10 device side 10a, finally cleaning remains in the photoresist of wafer 10 device side 10a;
Again, deposits conductive material in conducting channel district 21, forms conducting channel 31, obtains the structure shown in Fig. 4 c;
Finally, cmp is carried out to wafer 10 device side 10a, unnecessary surface conductance material and silicon dioxide insulator medium;
In this step, active area isolation raceway groove 30 degree of depth is identical with isolation channel 31 degree of depth of electrode position;
In this step, being metal or doped polycrystalline silicon in raceway groove deposits conductive material, is good with polysilicon;
Step 302, the conductive plug arrangement 51 adding cmos image sensor part above conducting channel 31, metal level 61 and electrode 40, wherein, conducting channel 31 arranges 51 with the conductive plug of COMS imageing sensor and forms electrical contact, be connected with the metal level 61 of COMS imageing sensor by conductive plug arrangement 51 again, until conducting channel 31 forms electric connection with the electrode 40 of wafer device side, obtain the structure shown in Fig. 4 d;
In this step, above conducting channel 31, add the conductive plug arrangement 51 of cmos image sensor part, semiconductor fabrication process that metal level 61 and electrode 40 adopt is prior art, repeat no more here;
Above step 303, cmos image sensor 70 and electrode 40, cemented lens and glass 80, obtain the structure shown in Fig. 4 e;
In this step, lens and glass 80 are bonded as prior art, repeat no more here, and lens and glass 80 isolate cmos image sensor and electrode and external environment, play the effect of protection cmos image sensor and electrode;
Step 304, carry out cmp to wafer 10 another side 10b, obtain structure as shown in fig. 4f, the object of cmp makes more easily to carry out in the silicon through hole step at wafer 10 another side 10b place subsequently;
In this step, the wafer thickness after cmp wants the requirement that can meet wafer robustness (resistance to wear), in general, preferably controls between 5 microns to 50 microns to the thickness range of wafer after grinding;
Step 305, from wafer 10 another side 10b etch silicon through hole 91, obtain the structure shown in Fig. 4 g;
In this step, from wafer 10 another side 10b etch silicon through hole, be etched through the silicon substrate of wafer, until etch the silicon dioxide layer dropped to below conducting channel completely, using conducting channel as etching stop layer;
In this step, silicon through hole directly can be formed by the method for dry etching, silicon through hole also can adopt first dry etching to be formed until the silicon through hole of silicon dioxide layer below conducting channel in addition, then is formed by the method that dry method or wet etching remove the silicon dioxide layer below conducting channel; Here, the degree of depth of silicon through hole 91 is within 50 microns, and most preferably less than 30 microns, the diameter range of silicon through hole 91 is between 1 micron to 50 microns, and best value is 1 micron to 10 microns.Little silicon clear size of opening is not only conducive to the filling of metal, and can save electrode district area, increases the number of transistors of active area.Although silicon shape of through holes is generally circle, also can be various shape, such as: triangle, quadrangle or polygon; The size of silicon through hole can be greater than, be less than or equal to the size of size below electrode 40;
Step 306, deposit insulation film 100 at silicon through hole 91 and wafer 10 another side 10b;
In this step, insulation film deposition adopts chemical vapor deposition silicon dioxide insulator material;
Step 307, etch away insulation film below conducting channel, obtain the structure shown in Fig. 4 h;
In this step, first at insulation film surface smear one deck photoresist of silicon through hole and wafer another side, then mask pattern as required carries out exposing and development makes photoresist patterned, do not etched by the insulation film surface that photoetching agent pattern covers being positioned at base part, finally cleaning remains in the photoresist of the silicon dioxide insulator film surface of silicon through hole and wafer another side;
Step 308, metal filled silicon through hole 91 and making soldered ball 120, obtain the structure shown in Fig. 4 i;
Step 309, Wafer Dicing.
The above, be only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. an interconnection packaging method for imageing sensor, comprising: make conducting channel in wafer device side for the region making package interconnects, the process of described making conducting channel is:
In the active area isolation stage, in wafer device side for making the increase channel region, region of package interconnects, after deposition of silica is as dielectric, the silicon dioxide of channel region carries out photoetching and partial etching, then in channel region deposits conductive material as conducting medium, finally cmp is carried out to conducting channel, remove unnecessary surface conductance material and silicon dioxide insulator medium;
Be used for the region making image transducer of making devices in described wafer device side, and above described conducting channel, add the conductive plug arrangement of cmos image sensor, metal level and electrode; Etch at wafer another side, form silicon through hole, described silicon through hole and conducting channel conducting;
At silicon through-hole wall deposition insulation film;
After insulation film deposition, etch away the insulation film below conducting channel;
Metal is inserted in silicon through hole.
2. the method for claim 1, is characterized in that, described above conducting channel, add cmos image sensor part conductive plug arrangement, metal level and electrode process be:
The conductive plug arrangement adding COMS imageing sensor above conducting channel forms electrical contact, then makes metal level and the conductive plug electric connection of COMS imageing sensor, until the electrode of conducting channel and wafer device side forms electric connection.
3. the method for claim 1, is characterized in that, when the described silicon dioxide to raceway groove etches, the degree of depth is no more than the degree of depth of raceway groove.
4. the method for claim 1, is characterized in that, described in raceway groove deposits conductive material be conducting metal or doped polycrystalline silicon.
5. the method for claim 1, is characterized in that, the deposition chemical gaseous phase depositing process of described silicon dioxide and electric conducting material carries out.
6. the method for claim 1, is characterized in that, describedly etches at wafer another side, is realize with dry etching.
7. the method for claim 1, is characterized in that, describedly etches at wafer another side, is until the silicon dioxide etched away below conducting channel exposes conducting channel.
8. the method for claim 1, is characterized in that, described formation silicon through hole, the degree of depth is less than 50 microns.
9. the method for claim 1, is characterized in that, described formation silicon through hole, diameter range is between 1 micron to 50 microns.
10. the method for claim 1, is characterized in that, describedly in silicon through hole, inserts metal, is also included in metal surface and adds soldered ball.
11. the method for claim 1, is characterized in that, at silicon through-hole wall deposition insulation film, are realize with chemical vapor deposition silicon dioxide.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101356645A (en) * | 2005-10-11 | 2009-01-28 | 朴太锡 | Method for encapsulating and manufacturing CMOS image sensor wafer using silicium through-hole contact point |
| CN101393874A (en) * | 2007-09-21 | 2009-03-25 | 中芯国际集成电路制造(上海)有限公司 | Three-dimensional stacking encapsulation method based on silicon through-hole |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101356645A (en) * | 2005-10-11 | 2009-01-28 | 朴太锡 | Method for encapsulating and manufacturing CMOS image sensor wafer using silicium through-hole contact point |
| CN101393874A (en) * | 2007-09-21 | 2009-03-25 | 中芯国际集成电路制造(上海)有限公司 | Three-dimensional stacking encapsulation method based on silicon through-hole |
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