CN101356645A - Method for encapsulating and manufacturing CMOS image sensor wafer using silicium through-hole contact point - Google Patents
Method for encapsulating and manufacturing CMOS image sensor wafer using silicium through-hole contact point Download PDFInfo
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- CN101356645A CN101356645A CNA2005800518185A CN200580051818A CN101356645A CN 101356645 A CN101356645 A CN 101356645A CN A2005800518185 A CNA2005800518185 A CN A2005800518185A CN 200580051818 A CN200580051818 A CN 200580051818A CN 101356645 A CN101356645 A CN 101356645A
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Abstract
The present invention relates to a wafer level package of a CMOS image sensor using silicon via contacts and a method of manufacturing the same. A wafer level package of a CMOS image sensor includes: a wafer where image sensor elements including a plurality of electrode pads are formed; a transparent substrate attached to a front side of the wafer; a via hole formed from a back side of the wafer to underneath of a plurality of electrode pads of the front side; a passivation layer formed on a remaining portion except the underneath of the electrode pads in the via hole and whole back side of the wafer; a via contact formed in the via hole; and a solder bump formed on the via contact of the back side of the wafer.
Description
Technical field
The wafer level encapsulation that the invention relates to a kind of CMOS (Complementary Metal Oxide Semiconductor) (CMOS) imageing sensor with and manufacture method; Particular words it, the invention relates to a kind of wafer level encapsulation of cmos image sensor, with and manufacture method, the method is to form a plurality of image sensing assemblies in the front of a wafer, it comprises formation one sensing cell and an electrode connection pad, and it can be directly connected to this electrode connection pad one back side of this wafer to form a silicon through-hole contact point (a silicon via contact), and by on the silicon through-hole contact point that exposes on this chip back surface, forming a solder bump (a solderbump), and this solder bump is connected to a printed circuit board (PCB) (PCB) forms this wafer level encapsulation.
Background technology
Generally speaking, imageing sensor is a kind of semiconductor module, and it is in order to converting an optical imagery to electronic signal, and store images signal and transmit it to a display unit.
Imageing sensor is broadly divided into two kinds, and a kind of is that (charge-coupled device, CCD) imageing sensor, another kind then are cmos image sensors to charge coupled device.Ccd image sensor can be by controlling the degree of depth of potential energy trap continuously and transmit electric charge in the charge transfer direction.Cmos image sensor then is sensing image by the photodiode that uses one or more transistor and in the pixel cell born of the same parents, and wherein this photodiode is as optical sensor.
Because the noise of ccd image sensor is low and picture quality is better than cmos image sensor, thereby ccd image sensor is applicable to digital camera.On the contrary, cmos image sensor is less haply and manufacturing cost is lower compared to its power consumption of ccd image sensor, and is easy to integrate with peripheral circuit chip.Especially, cmos image sensor can integrate easily with the peripheral system that carries out amplification and processing signals, thereby manufacturing cost be lower with traditional semiconductor fabrication techniques manufacturing.In addition, the very fast and power consumption of the running speed of cmos image sensor only is 1% of a ccd image sensor approximately.Therefore, cmos image sensor has been used in camera cell phone and PDA(Personal Digital Assistant).
But, along with the technology of cmos image sensor is day by day developed, cmos image sensor and ccd image sensor good and bad situation technically gradually has growth and decline.The development speed of cmos image sensor technology heightens.For example, cmos image sensor is the imageing sensor that is used for the VGA camera cell phone in the past; But, cmos image sensor can be applicable to the imageing sensor of the camera cell phone that is higher than the 2-mega pixel in recent years.
Simultaneously, developed at present a kind of modularization processing procedure and use image sensing chip encapsulation in the wire bonds mode.But, cause sensing window that image fault is arranged, the productive rate of module assembling processing procedure is reduced owing to this wire bonds processing procedure can produce foreign substance, and because the degree of depth of module, width and highly all become big, and make the volume of this module be difficult for dwindling.
In recent years, (chip on flexible PCB, COF) technology begins to be used in new camera module method to cover brilliant flexible PCB.Wherein, the COF technology be to use be applied in usually the aeolotropic conductive film of making LCD (LCD) panel (anisotropic conductive film, ACF).
In korean patent application case 2003-0069321 number, disclose a kind of image component encapsulation of under wafer state, finishing the brilliant golden lug manufacturing process of covering of encapsulation and a kind of COF of utilization mounting technique with and manufacture method.
Fig. 1 is the camera module of the cmos image sensor chip of a use Prior Art.
In Fig. 1, a gold medal projection 120b who forms on the CIS chip 105 is that the conducting sphere via an anisotropy conducting film 104 is connected on the outer electrode connection pad 120a of a flexible PCB (FPC) 103, so finishes the connection of a CIS chip 105.Thereafter, this camera module is added an eyeglass 100, a mirror head outer shell 101 and an infrared filter (not shown).Mode according to this, by this anisotropy conducting film, CIS chip 105 can directly be attached on this FPC103 and go up and need not extra CIS encapsulation.
But, cover in the crystal method above-mentioned, because the sensing window 106 of employed sensing image faces this aeolotropic conductive film 104, when CIS chip 105 is attached with FPC103, the sensing window 106 that the foreign matter that is produced by aeolotropic conductive film 104 and FPC can enter the CIS chip.Therefore, productive rate can significantly reduce.
In order to address the above problem, the Shellcase of Israel company develops and a kind of new technology.Technology according to Shellcase, wafer is through etch processes, and have at the back side of this wafer an electrode (its be connected to the same lip-deep electrode pads of the sensing cell of this wafer) extend, and the sensing cell that makes the CIS chip towards with the opposite direction of different orientation film so that be attached to a FPC.
Fig. 2 to Fig. 6 shows that Shellcase makes the profile of the processing procedure of this CIS encapsulation.
With reference to figure 2,, on a positive 200a of wafer 200, form for example sensing cell 202 used of an electrode connection pad 201 and a sensing image of a plurality of CIS assemblies via a predetermined manufacturing processing procedure.After finishing following manufacturing image sensing encapsulation procedure, promptly cut chip along line of cut 250.
As shown in Figure 3, in this front of this wafer 200 with an epoxy resin 203 cover on one first glass substrate 204 thereafter.
Secondly, with reference to figure 4, with wafer 200 from back side 200b etching after this electrode connection pad 201 (position is in the front of this wafer 200) exposes shown in circular 206, re-use epoxy resin 203a one second glass substrate 207 sticked on it.
Secondly, as shown in Figure 5, this second glass substrate 207 through etching, behind formation and patterning one electric conductor, is just formed an outer electrode 208.208 of this outer electrodes and this electrode connection pad 201 form a T-joint 209.
Thereafter, as shown in Figure 6, after expose in a part of zone, to form a solder bump at this, heavy casket one layer insulating 211 and give patterning on this second glass substrate 207 and this outer electrode 208, promptly form a solder bump 210, and make chip separately along line of cut 250 cut crystals 200.
After this, see through a default processing procedure, just can form image device module, for example a camera.
But, in the method for above-mentioned manufacturing image sensor package, this T-joint 209 may chap, and therefore causes joint fault.In addition, this processing procedure is rather complicated, for example, must carry out patterning to form an outer electrode, reaches must form an insulating barrier to protect an outer electrode or to intercept scolding tin.Therefore, its productive rate reduces.
Summary of the invention
Application of the present invention is in order to overcome the problem of above-mentioned related art techniques.Therefore, the objective of the invention is avoiding foreign substance to enter the image sensing assembly.
Another object of the present invention is the image sensing encapsulation of a chip size to be provided, wherein to have a frivolous image sensor module.
One of characteristic of the present invention, provide a kind of method, may further comprise the steps: the front (a plurality of image sensor modules that include several electrode connection pads are formed on this front) that a transparency carrier is attached on a wafer at wafer level encapsulation cmos image sensor; The back side of polishing (grinding) this wafer is to remove its non-essential part; Formation one runs through the through hole of a plurality of electrode connection pads below on this front wafer surface, the back side of this wafer; On the back side of the whole surface of this through hole and this wafer, form a passivation layer (a passivation layer); Remove this passivation layer that is formed on this electrode connection pad; This through hole is filled up metal so that form a through-hole contact point on this through hole; On this through-hole contact point of this chip back surface, form a solder bump; And cut this wafer and this transparency carrier.
Another characteristic of the present invention provides a kind of wafer level encapsulation of cmos image sensor, comprising: a wafer, and the image sensor module that forms on it comprises several electrode connection pads; One transparency carrier, it is that gluing is on a front of this wafer; One through hole, it is that the back side from this wafer extends through below several electrode connection pads of this front wafer surface; One passivation layer, except the below part of the electrode connection pad of this through hole and the whole back side of this wafer, it is to form at remainder; One through-hole contact point, it is to form in this through hole; And a solder bump, it is to form on this through-hole contact point of this chip back surface.
Description of drawings
Fig. 1 is the sketch that shows a camera module, and it is to use CMOS (Complementary Metal Oxide Semiconductor) (CMOS) imageing sensor (CIS) chip of Prior Art;
Fig. 2 to Fig. 6 shows that Shellcase makes the cross section view of the processing procedure of CIS encapsulation; And
Fig. 7 to Figure 16 is the cross section view that shows a wafer level cmos image sensor method for packing, and it is to use the silicon through-hole contact point of the preferred embodiment according to the present invention.
The primary clustering symbol description
100 eyeglasses, 101 mirror head outer shells
103 flexible PCBs (FPC), 104 anisotropy conducting films
The grand point of 120A outer electrode connection pad 120B gold
200 wafer 200A fronts
The 200B back side 201 electrode connection pads
202 sensing cells, 203 epoxy resin
206 circular 207 second glass substrates
208 outer electrode 209T-joints
210 solder bumps, 211 insulating barriers
250 lines of cut, 300 wafers
301 electrode connection pads, 302 sensing cells
303 lines of cut, 304 transparency carriers
305 epoxy resin layers, 306 separators
307 through holes, 308 passivation layers
309 kinds of crystal layer 310 through-hole contact points
311 scolding tin solder bumps
Embodiment
Each characteristic of the present invention, viewpoint, and preferred embodiment will explanation in detail with reference to the accompanying drawings in following expository writing.
The cross section view of Fig. 7 to Figure 16 is the method for packing that shows the wafer level of a kind of CMOS (Complementary Metal Oxide Semiconductor) (CMOS) imageing sensor, and it is to use the silicon through-hole contact point of the preferred embodiment according to the present invention.
With reference to figure 7, via a default processing procedure, on a wafer 300, form several electrode connection pads 301, constitute a current path so that be used between the sensing cell 302 of sensing image at an external circuit and.This wafer 300 comprises several chips, and carries out cutting step after the chip manufacturing processing procedure is finished, and a plurality of chips is cut apart each other for encapsulation used.These a plurality of chips are to be separated from each other along this line of cut.
With reference to figure 8, one transparency carriers 304 be attached on this wafer 300 on thereafter.The preferably, this transparency carrier 304 is a glass substrate, its thickness is between 300 microns to 500 microns.In order to stick this transparency carrier 304, form an epoxy resin layer 305 to extend a plurality of these electrode connection pads 301 that cover these line of cut 303 both sides.In addition, a separator 306 is arranged then on this epoxy resin layer 305, with fixing space between this transparency carrier 304 and this wafer 300.This wafer 300 and this transparency carrier 304 each other sticked thereafter.Therefore, in following processing procedure, this sensing cell 302 and this electrode connection pad 310 of forming on this wafer 300 are not polluted by any foreign substance, therefore can significantly reduce the probability that defective occurs.
Secondly, with reference to figure 9, the back side of this wafer 300 is through polishing.The polishing processing procedure is in order can more easily to form a through hole in wafer 300 and carry out at following one processing procedure.By this polishing processing procedure, this wafer 300 is through polishing, can make the more durable required degree of depth of wafer 300 and form one.After the polishing processing procedure, the thickness of this wafer 300 is preferable with 50 microns to 100 microns.
Thereafter, with reference to Figure 10, a plurality of through holes 307 are the below parts that extend through these a plurality of electrode connection pads 301 from the back side of this wafer 300.This through hole 307 can directly form with reactive ion-etching (RIE) dry ecthing.In addition, this through hole 307 can be by the non-through hole that forms earlier some, remove and form with dry ecthing or wet etching remainder again wafer 300.At this moment, the diameter of this through hole 307 can be between tens of micron between thousands of microns, with 200 microns with interior preferable.Though the shape of this through hole 307 is circular basically, but this through hole 307 also can be other different shape, for example triangle, quadrangle or polygonal.In addition, the size of the through hole that forms at this wafer 300 back sides can greater than, be less than or equal to the through hole below this electrode 301.
With reference to Figure 11, through the back side of etched this through hole 307 surfaces and this wafer 300 on there be a passivation layer 308 cover to isolate a plurality of electrodes thereafter.This passivation layer 308 is preferably an oxide layer or a nitration case.Being preferably during these passivation layer 308 oxidations with salpeter solution uses low-temperature plasma enhancing chemical vapour deposition technique (PECVD) to deposit.
Secondly, with reference to Figure 12, this passivation layer 308 that is deposited on these through hole 307 bottoms (promptly below this electrode connection pad) is removed, so that a plurality of electrode connection pads 301 are exposed to the open air outside.
With reference to Figure 13 and Figure 14, use sputter process in this through hole 307, to form after a kind of crystal layer 309 in regular turn, re-use electroplating process or printing process and form a through-hole contact point 310 with tin cream.At this moment, can use any conductive material, comprise that conductive material for example: gold, silver, copper, aluminium, nickel, chromium and tungsten or its multiple alloy.
Then, with reference to Figure 15, the part that has this through-hole contact point 310 to form at these wafer 300 back sides then generates a solder bump 311.Though this solder bump 311 can adopt any conductive material, but this solder bump 311 is preferable with the alloy of the alloy of copper, gold, any nickel/gold or any tin/gold.
At last, with reference to Figure 16, this wafer of finishing 300 and this transparency carrier 304 are cut into a plurality of independent chips along this line of cut 303.
See through the processing procedure of the preferred embodiment of the invention described above, can finish an image sensing chip.Thereafter, this independently image sensing chip promptly be attached on a FPC or a printed circuit board (PCB) and be connected to an external circuit via a solder bump (forming) at a chip back surface.Then, after making up, can finish an image device (for example camera) with an eyeglass and an eyeglass shell.
Though the present invention illustrated with regard to some preferred embodiment, but under the category that does not break away from claim and defined, the personage of specially smart this skill still can implement various variations and modification.
Advantage of the present invention
By adopting the silicon through-hole contact point, have following advantages according to the image sensor package of wafer level of the present invention:
At first, being connected to the through-hole contact point of an electrode connection pad from the back side of a wafer can be at one of this wafer The front forms easily, and having a plurality of image sensing assemblies (comprising a sensing cell) to reach on this front should A plurality of electrode connection pads form;
Secondly, can avoid sensing cell to cause productive rate to reduce because foreign substance enters, this be by with One transparency carrier covers, and forms the grand point of a scolding tin at the through-hole contact point that this chip back surface one exposes, Make it be connected to an external circuit via this back side again and reach, this wherein there is no any image sensing group Part;
Thirdly, unnecessary wafer partly can be removed to reduce the thick of image sensor module finished product Degree; And
The 4th point, it is less usually that the semiconductor device of chip-scale (comprising an imageing sensor) encapsulates its volume, more feasible in practicality, and can be used in multi-chip module (MCM).
Claims (according to the modification of the 19th of treaty)
1. method at wafer level encapsulation CMOS (Complementary Metal Oxide Semiconductor) (CMOS) imageing sensor, this method comprises the following step:
Transparency carrier is attached to the front of wafer, on this front, is formed with a plurality of image sensor modules that comprise several electrode connection pads;
The polish back side of this wafer;
Use dry ecthing or wet etch method to run through and form through hole those electrode connection pad belows on this front wafer surface from this chip back surface;
On the whole surface of this through hole and this chip back surface, form passivation layer;
This passivation layer that is formed on this electrode connection pad is removed, and in this through hole, form kind of a crystal layer;
On this kind crystal layer, form through-hole contact point;
On this through-hole contact point of this chip back surface, form solder bump; And
Cut this wafer and this transparency carrier.
2. the method for claim 1 wherein before sticking this transparency carrier, more comprises the following step:
Form epoxy resin layer, it extends a plurality of electrode connection pads that cover on the line of cut both sides; And
Upper section at this epoxy resin layer forms separator.
3. the method for claim 1, wherein the step of this formation through-hole contact point more comprises the following steps:
In this through hole, form kind of a crystal layer with sputtering method; And
With paste solder printing or in this through hole with this metal plating to metal level, will fill up metal in this through hole.
4. the method for claim 1, wherein the thickness of this transparency carrier is between 300 microns to 500 microns.
5. the method for claim 1, wherein after the polishing step, the thickness of this wafer is between 50 microns to 100 microns.
6. the method for claim 1, wherein this through hole is to utilize the dry ecthing method of reactive ion etching (RIE) directly to form; Or after forming a part of non-through hole, by remove on this wafer run through without dry ecthing or wet etch method all the other partly, and form this through hole.
7. the method for claim 1, wherein this passivation layer is oxide layer or nitration case, it utilizes in salpeter solution oxidation or strengthens chemical vapour deposition (CVD) (PECVD) method and form with low-temperature plasma.
8. the method for claim 1, wherein this through-hole contact point is to make by being selected from one of following conductive metal, it comprises: gold, silver, copper, aluminium, nickel, chromium, tungsten and analog thereof or its a plurality of alloys.
9. the method for claim 1, wherein this solder bump be following one of them: the alloy of copper, gold and nickel/gold or by tin, copper and gold both formed alloys at least wherein.
10. cmos image sensor wafer level encapsulation comprises:
Wafer is formed with a plurality of image sensor modules that comprise several electrode connection pads on it;
Transparency carrier, it is a front that is attached on this wafer;
Through hole, it is to run through on this front wafer surface several electrode connection pads belows by this chip back surface and form with dry ecthing or wet etch method;
Passivation layer, it is formed in the residue position those electrode connection pad lower portion in through hole, and on the whole back side of this wafer;
Plant crystal layer and be formed on the interior through-hole contact point of this through hole; And
Solder bump, it is formed on the through-hole contact point of this chip back surface.
11. cmos image sensor wafer level encapsulation as claimed in claim 10 more comprises epoxy resin layer and separator, the position is between the front and this transparency carrier of this wafer.
12. cmos image sensor wafer level encapsulation as claimed in claim 10, wherein the thickness of this transparency carrier is between 300 microns to 500 microns.
13. cmos image sensor wafer level encapsulation as claimed in claim 10, wherein the thickness of this wafer is between 50 microns to 100 microns.
14. cmos image sensor wafer level encapsulation as claimed in claim 10, wherein this passivation layer is to belong to or the nitride layer formation with oxide.
15. cmos image sensor wafer level encapsulation as claimed in claim 10, wherein this through-hole contact point is to be made by conductive metal, and it is to be selected from gold, silver, copper, aluminium, nickel, chromium, tungsten or its a plurality of alloys.
16. cmos image sensor wafer level as claimed in claim 10 encapsulation, wherein this solder bump is copper, gold, nickel/billon one of them or tin/billon.
Claims (16)
1. method at wafer level encapsulation CMOS (Complementary Metal Oxide Semiconductor) (CMOS) imageing sensor, this method comprises the following step:
Transparency carrier is attached to the front of wafer, on this front, is formed with a plurality of image sensor modules that comprise several electrode connection pads;
The polish back side of this wafer;
Use dry ecthing or wet etch method to run through and form through hole those electrode connection pad belows on this front wafer surface from this chip back surface;
On the whole surface of this through hole and this chip back surface, form passivation layer;
This passivation layer that is formed on this electrode connection pad is removed;
In this through hole, form through-hole contact point;
On this through-hole contact point of this chip back surface, form solder bump; And
Cut this wafer and this transparency carrier.
2. the method for claim 1 wherein before sticking this transparency carrier, more comprises the following step:
Form epoxy resin layer, it extends a plurality of electrode connection pads that cover on the line of cut both sides; And
Upper section at this epoxy resin layer forms separator.
3. the method for claim 1, wherein the step of this formation through-hole contact point more comprises the following steps:
In this through hole, form kind of a crystal layer with sputtering method; And
In this through hole with paste solder printing maybe with this metal plating to metal level, will fill up metal in this through hole.
4. the method for claim 1, wherein the thickness of this transparency carrier is between 300 microns to 500 microns.
5. the method for claim 1, wherein after the polishing step, the thickness of this wafer is between 50 microns to 100 microns.
6. the method for claim 1, wherein this through hole is to utilize the dry ecthing method of reactive ion etching (RIE) directly to form; Or after forming the part non-through hole, by remove on this wafer run through without dry ecthing or wet etch method all the other partly, and form this through hole.
7. the method for claim 1, wherein this passivation layer is oxide layer or nitration case, it utilizes in salpeter solution oxidation or strengthens chemical vapour deposition (CVD) (PECVD) method and form with low-temperature plasma.
8. the method for claim 1, wherein this through-hole contact point is to make by being selected from one of following conductive metal, it comprises: gold, silver, copper, aluminium, nickel, chromium, tungsten and analog thereof or its a plurality of alloys.
9. the method for claim 1, wherein this solder bump be following one of them: the alloy of copper, gold and nickel/gold or by tin and both formed alloys of gold.
10. cmos image sensor wafer level encapsulation comprises:
Wafer is formed with a plurality of image sensor modules that comprise several electrode connection pads on it;
Transparency carrier, it is the front that is attached on this wafer;
Through hole, it is to run through this chip back surface several electrode connection pad belows on this front wafer surface;
Passivation layer, it is formed in the residue position those electrode connection pad lower portion in through hole, and on the whole back side of this wafer;
Through-hole contact point is formed in this through hole; And
Solder bump, it is formed on the through-hole contact point of this chip back surface.
11. cmos image sensor wafer level encapsulation as claimed in claim 10 more comprises epoxy resin layer and separator, the position is between the front and this transparency carrier of this wafer.
12. cmos image sensor wafer level encapsulation as claimed in claim 10, wherein the thickness of this transparency carrier is between 300 microns to 500 microns.
13. cmos image sensor wafer level encapsulation as claimed in claim 10, wherein the thickness of this wafer is between 50 microns to 100 microns.
14. cmos image sensor wafer level encapsulation as claimed in claim 10, wherein this passivation layer is to belong to or the nitride layer formation with oxide.
15. cmos image sensor wafer level encapsulation as claimed in claim 10, wherein this through-hole contact point is to be made by conductive metal, and it is to be selected from gold, silver, copper, aluminium, nickel, chromium, tungsten or its a plurality of alloys.
16. cmos image sensor wafer level as claimed in claim 10 encapsulation, wherein this solder bump is person or tin/billon one of in copper, gold, the nickel/billon.
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| CNA2005800518185A CN101356645A (en) | 2005-10-11 | 2005-10-11 | Method for encapsulating and manufacturing CMOS image sensor wafer using silicium through-hole contact point |
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| CNA2005800518185A CN101356645A (en) | 2005-10-11 | 2005-10-11 | Method for encapsulating and manufacturing CMOS image sensor wafer using silicium through-hole contact point |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101483149B (en) * | 2009-02-13 | 2010-08-04 | 华中科技大学 | Production method for through wafer interconnection construction |
| CN101807560A (en) * | 2010-03-12 | 2010-08-18 | 晶方半导体科技（苏州）有限公司 | Packaging structure of semiconductor device and manufacture method thereof |
| CN102339841A (en) * | 2011-10-08 | 2012-02-01 | 江阴长电先进封装有限公司 | High-reliability image sensor packaging structure without silicon through hole |
| CN102881666A (en) * | 2012-07-18 | 2013-01-16 | 香港应用科技研究院有限公司 | Wafer level packaging device |
| CN103400807A (en) * | 2013-08-23 | 2013-11-20 | 苏州晶方半导体科技股份有限公司 | Wafer-level packaging structure and packaging method of image sensor |
| CN103456754A (en) * | 2012-05-31 | 2013-12-18 | 意法半导体有限公司 | Wafer level optical sensor package and low profile camera module, and method of manufacture |
| CN104143557A (en) * | 2013-05-06 | 2014-11-12 | 全视科技有限公司 | Integrated circuit stack with low profile contacts |
| CN102034756B (en) * | 2009-09-29 | 2015-03-11 | 中芯国际集成电路制造(上海)有限公司 | Interconnection packaging method of image sensor |
| CN104979302A (en) * | 2014-04-09 | 2015-10-14 | 精材科技股份有限公司 | Chip package and method for manufacturing the same |
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- 2005-10-11 CN CNA2005800518185A patent/CN101356645A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101483149B (en) * | 2009-02-13 | 2010-08-04 | 华中科技大学 | Production method for through wafer interconnection construction |
| CN102034756B (en) * | 2009-09-29 | 2015-03-11 | 中芯国际集成电路制造(上海)有限公司 | Interconnection packaging method of image sensor |
| CN101807560A (en) * | 2010-03-12 | 2010-08-18 | 晶方半导体科技（苏州）有限公司 | Packaging structure of semiconductor device and manufacture method thereof |
| CN102339841A (en) * | 2011-10-08 | 2012-02-01 | 江阴长电先进封装有限公司 | High-reliability image sensor packaging structure without silicon through hole |
| CN103456754B (en) * | 2012-05-31 | 2016-04-20 | 意法半导体有限公司 | Wafer level optical sensor package and low profile camera module and manufacture method |
| CN103456754A (en) * | 2012-05-31 | 2013-12-18 | 意法半导体有限公司 | Wafer level optical sensor package and low profile camera module, and method of manufacture |
| US9117715B2 (en) | 2012-07-18 | 2015-08-25 | Hong Kong Applied Science and Technology Research Institute Company Limited | Wafer-level device packaging |
| CN102881666A (en) * | 2012-07-18 | 2013-01-16 | 香港应用科技研究院有限公司 | Wafer level packaging device |
| CN104143557A (en) * | 2013-05-06 | 2014-11-12 | 全视科技有限公司 | Integrated circuit stack with low profile contacts |
| CN104143557B (en) * | 2013-05-06 | 2017-04-12 | 豪威科技股份有限公司 | Integrated circuit stack with low profile contacts |
| CN103400807A (en) * | 2013-08-23 | 2013-11-20 | 苏州晶方半导体科技股份有限公司 | Wafer-level packaging structure and packaging method of image sensor |
| US9601531B2 (en) | 2013-08-23 | 2017-03-21 | China Wafer Level Csp Co., Ltd. | Wafer-level packaging structure for image sensors with packaging cover dike structures corresponding to scribe line regions |
| CN104979302A (en) * | 2014-04-09 | 2015-10-14 | 精材科技股份有限公司 | Chip package and method for manufacturing the same |
| CN104979302B (en) * | 2014-04-09 | 2018-09-07 | 精材科技股份有限公司 | Chip package and method for manufacturing the same |
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