Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03G—CONTROL OF AMPLIFICATION
  • H03G1/00—Details of arrangements for controlling amplification
  • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
  • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
  • H03F1/0216—Continuous control
  • H03F1/0233—Continuous control by using a signal derived from the output signal, e.g. bootstrapping the voltage supply
  • H03F1/0238—Continuous control by using a signal derived from the output signal, e.g. bootstrapping the voltage supply using supply converters

Definitions

• the disclosure relates to envelope tracking for power amplifiers.
• Envelope tracking is a technique for increasing the efficiency of power amplifiers.
• the supply voltage of a power amplifier is dynamically adjusted to keep the power amplifier operating with sufficient headroom to maintain linearity, while nevertheless minimizing DC power consumption.
• the supply voltage of the power amplifier (or "tracking supply voltage”) may be generated using a separate linear amplifier that tracks the envelope of the power amplifier output.
• the linear amplifier is itself coupled to an amplifier supply voltage generated by a boost converter, which is capable of generating a boosted supply voltage for the linear amplifier that exceeds the maximum supply voltage otherwise available to the system, e.g., from a battery of the system. In this manner, the power amplifier output can reach and even exceed the battery supply voltage when necessary.
• the tracking supply voltage may further be coupled to a switching power stage to provide greater driving capability to the power amplifier.
• the tracking supply voltage may exceed the battery supply voltage. This may lead to a condition known as "reverse current flow,” wherein current flows from the tracking supply voltage through a high-side switch of the switching power stage back to the battery supply voltage. Reverse current flow undesirably degrades system efficiency, and requires the boost converter to be significantly over-designed. Furthermore, reverse current flow may introduce distortion into the power amplifier output, causing the output waveform to potentially violate linearity and RX band noise specifications.
• FIG 1 illustrates an implementation of an envelope tracking (ET) system.
• ET envelope tracking
• FIG 2 illustrates an operating scenario showing normal operation of the ET system.
• FIG 3 illustrates an operating scenario wherein there is "reverse current” or
• FIG 4 illustrates an exemplary embodiment of an ET system according to the present disclosure.
• FIG 5 illustrates an alternative exemplary embodiment of an ET system according to the present disclosure.
• FIG 6 illustrates an alternative exemplary embodiment of an ET system according to the present disclosure, wherein a voltage sensor is provided to detect negative current flow.
• FIGs 7 and 7A illustrate alternative exemplary embodiments of the present disclosure, wherein further techniques are applied to prevent reverse current flow in an ET system.
• FIG 8 illustrates an exemplary embodiment 800 of an ET system according to the principles of the present disclosure.
• FIG 9 illustrates an exemplary embodiment of a method according to the present disclosure.
• TRUE e.g., 1
• FALSE e.g., 0
• FIG 1 illustrates an implementation of an envelope tracking (ET) system 100.
• ET envelope tracking
• FIG 1 is shown for illustrative purposes only, and is not meant to limit the scope of the present disclosure to any particular implementation of an ET system.
• the techniques described hereinbelow may readily be applied to systems incorporating alternative or additional modules not shown in FIG 1.
• a power amplifier (PA) 130 receives one or more input voltages IN and generates one or more amplified output voltages OUT.
• IN and/or OUT may each include a plurality of voltages, e.g., in-phase (I) and quadrature (Q) signal voltages, etc.
• the PA 130 may further have a digital interface (not shown in FIG 1) to change the gain settings of the PA 130.
• a voltage Vamp also denoted a "tracking supply voltage,” is provided to the PA 130 as a supply voltage. Vamp is generated at least in part by an amplifier 140.
• the amplifier 140 is supplied by a voltage VDD Amp, also denoted an “amplifier supply voltage” or a “boosted supply voltage.” In certain implementations of an ET system, to generate Vamp, the amplifier 140 may amplify a voltage Env which tracks the envelope of the PA output voltage OUT.
• amplifier 140 may generally be any type of amplifier known in the art, e.g., class A, class B, class AB, etc. Such exemplary embodiments are contemplated to be within the scope of the present disclosure.
• Vbatt which is a maximum supply voltage otherwise available to the system, e.g., a supply voltage from a battery of the system.
• Vbatt may also be denoted herein as a "battery supply voltage,” and such battery supply voltage may generally be supplied by any type of device for supplying power, e.g., lithium-ion battery, other linear or switching voltage regulators, direct AC line, etc.
• a boost converter 1 10 may be provided to generate VDD Amp.
• the boost converter 1 10 may boost VDD Amp to a higher level than Vbatt according to principles of operation not shown in FIG 1 but known in the art, e.g., using a plurality of switches alternately configured to charge and discharge a boost inductor (not shown) to generate a boosted voltage.
• the tracking supply voltage Vamp provided to the PA 130 may be maintained at a level sufficient to ensure linear operation of the PA 130, i.e., provided with sufficient "headroom," while reducing unnecessary DC power consumption.
• a switching power stage 120 is further coupled to the PA 130 at Vamp to increase the power driving capability of the PA 130.
• the switching power stage 120 includes transistor switches P I, l coupled to gate control voltages PCTRL, NCTRL respectively, wherein the switches PI, Nl are configured to alternately couple an inductor L to Vbatt or to ground.
• switches P I, Nl are shown as transistor implementations in this specification, it will be appreciated that in general, other types of switches, e.g., relays, etc., may be configured using the techniques of the present disclosure.
• P I and Nl may also be generally denoted as corresponding to a "high-side switch” and a "low-side switch,” respectively.
• the high-side switch need not be implemented using a PMOS transistor, and may instead be implemented using an NMOS transistor. Such alternative exemplary embodiments are contemplated to be within the scope of the present disclosure.
• FIGs 2 and 3 illustrate operating scenarios for the ET system 100, depicting certain principles according to the present disclosure. Note FIGs 2 and 3 are shown for illustrative purposes only, and are not meant to limit the scope of the present disclosure.
• FIG 2 illustrates an operating scenario 100A showing normal operation of the ET system 100.
• both the amplifier 140 and the switching power stage 120 may source current into the PA 130.
• current sourced to the PA 130 by the amplifier 140 from the boost converter 110 is shown by an arrow marked A
• current sourced to the PA 130 by the switching power stage 120 from Vbatt is shown by an arrow marked B.
• the operating scenario 100A may arise, e.g., when Vamp is less than Vbatt.
• FIG 3 illustrates an operating scenario 100B wherein there is "reverse current” or "reverse current flow” present in the ET system 100.
• the level of Vamp may be driven higher by amplifier 140 to provide sufficient headroom for the PA 130.
• Vbatt is low
• Vamp may eventually be driven to a level higher than Vbatt, due to the boosted amplifier supply voltage VDD_Amp provided by the boost converter 1 10.
• Vamp exceeds Vbatt
• current IL through the inductor L (whose directionality is as indicated in FIG 2) begins to decrease.
• the inductor current may reverse in direction and become negative, in which case the boost converter 1 10 effectively sources current from the amplifier 140 to Vbatt via switch PI .
• This "reverse current” is shown by the arrow marked C.
• the amount of time such "reverse current” is present in the ET system 100 may depend on factors such as the inductor current size, input voltage, tracking supply voltage, etc.
• reverse current may undesirably cause excessive loading on the amplifier 140 and boost converter 110, thereby degrading system efficiency.
• the boost converter 1 10 may need to be significantly over-designed, and/or may cause the linearity and receive (RX) band noise requirements of an output waveform to violate the device specifications.
• RX receive
• FIG 4 illustrates an exemplary embodiment 400 of an ET system according to the present disclosure. Note FIG 4 is shown for illustrative purposes only, and is not meant to limit the scope of the present disclosure. Further note that similarly labeled elements in FIGs 1 and 4 may be understood to perform similar functionality, unless otherwise noted, and their description may be omitted hereinbelow for simplicity.
• a negative current flow detection block 410 is provided in series between the inductor L and a switching node SW of a modified buck controller 420.
• Block 410 is configured to detect when IL is negative, i.e., flows from the inductor L back to the switching power stage 420, corresponding to reverse current.
• Block 410 generates a logical signal Neg_curr which indicates when IL is negative.
• switch P I is controlled by a logical condition labeled 420a. In particular, according to condition 420a, if Neg_curr is logically high, i.e., negative IL is detected by block 410, then switch P I is disabled. Otherwise, switch PI is controlled by PCTRL.
• FIG 5 illustrates an alternative exemplary embodiment 500 of an ET system according to the present disclosure. Note FIG 5 is shown for illustrative purposes only, and is not meant to limit the scope of the present disclosure. Further note that similarly labeled elements in FIGs 4 and 5 may be understood to perform similar functionality, unless otherwise noted, and their description may be omitted hereinbelow for simplicity.
• a negative current flow detection block 510 is provided in series between the switching node SW of modified buck controller 520 and Vbatt.
• Block 510 is configured to detect when IL is negative, i.e., flows from the inductor L back through the switching power stage 520 to Vbatt in a manner similar to that described with reference to block 410 in FIG 4.
• Block 510 generates a logical signal Neg_curr which indicates when IL is negative.
• switch PI is also controlled by the logical condition 420a.
• FIG 6 illustrates an alternative exemplary embodiment 600 of an ET system according to the present disclosure, wherein a voltage sensor is provided to detect negative current flow.
• FIG 6 is shown for illustrative purposes only, and is not meant to limit the scope of the present disclosure. Further note that similarly labeled elements in FIGs 5 and 6 may be understood to perform similar functionality, unless otherwise noted, and their description may be omitted hereinbelow for simplicity.
• a voltage comparator 610 of the modified switching power stage 620 includes a positive (+) input terminal coupled to the drain of PI, and a negative (-) input terminal coupled to the source of PI .
• negative current e.g., current in the direction from the drain to the source of P I
• a positive voltage drop will appear across the +, - terminals of voltage comparator 610.
• the positive voltage drop may be due to, e.g., finite on-resistance of PI .
• voltage comparator 610 Upon detecting the positive voltage drop, voltage comparator 610 will generate a high value for Neg_curr at its output. Neg_curr may be used to control the switching of PI via logical condition 420a, as earlier described hereinabove.
• FIGs 7 and 7A illustrate alternative exemplary embodiments of the present disclosure, wherein further techniques are applied to prevent reverse current flow in an ET system.
• FIGs 7 and 7A are shown for illustrative purposes only, and are not meant to limit the scope of the present disclosure to exemplary embodiments incorporating the reverse body diodes shown.
• the signal Neg_curr_b corresponds to the logical inverse of Neg_curr.
• the particular means for generating the signal Neg_curr and/or Neg_curr_b is not shown in FIGs 7 and 7A.
• an auxiliary PMOS switch SI is provided in series with Dl.
• SI is configured to be disabled when Neg_curr is high, e.g., when reverse current is detected by a negative current detection block (not shown in FIG 7).
• a negative current detection block not shown in FIG 7
• the PMOS switch SI may itself have a body diode D2, and such body diode D2 may be provided in reverse polarity from Dl . In this manner, the polarity of D2 prevents reverse current from flowing through D 1 and D2 when S 1 is disabled.
• an isolated N-well (NWELL) process may be utilized.
• a first auxiliary PMOS switch SI ' couples the NWELL of PI with the source of PI
• a second auxiliary PMOS switch S2' couples the NWELL of PI with VDD_Amp.
• the NWELL's of both SI ' and S2' are tied to the boosted voltage VDD_Amp, as illustrated by body diodes D2.1 and D3.
• the gate of SI ' is coupled to Neg_curr, as described hereinabove for the switch SI of FIG 7.
• the gate of S2' is coupled to Neg_curr_b.
• S2' is turned on to provide a path for current to flow from the node SW to the boosted voltage VDD_Amp. This prevents the voltage at SW from becoming very high, which may potentially cause either D2.1 or Nl to breakdown and be destructive to such devices.
• the gates of SI ' and S2' need not be controlled by the signals shown; rather, S2' could be always enabled during ET operation.
• S2' may always be enabled when the ET system 700A is in, e.g., an envelope tracking (ET) mode, while SI ' may always be enabled when the ET system 700A is in an average power tracking (APT) mode.
• S2' could be enabled based on negative current detection only when the boost is active, e.g., when there is a potential for a negative current event to occur.
• FIG 8 illustrates an exemplary embodiment 800 of an ET system according to the principles of the present disclosure.
• FIG 8 is shown for illustrative purposes only, and is not meant to limit the scope of the present disclosure, e.g., to any particular embodiments of a negative current flow detection block, or of blocks for implementing logical conditions.
• similarly labeled elements in FIGs 7 and 8 may correspond to elements having similar functionality, unless otherwise noted, and their descriptions may be omitted hereinbelow for simplicity.
• an exemplary embodiment 820 of the modified switching power stage includes a voltage-comparator-based negative current flow detection block 610 such as described with reference to FIG 6.
• the comparator 610 is also denoted herein as a "first comparator.”
• the signal voltage Neg_curr is coupled to a logical condition block 420a.1 implementing an enhanced version of the logical condition 420a described with reference to FIGs 4 and 5.
• block 420a.1 includes an SR latch 830.
• SR latch 830 includes an S input coupled to the output of an AND gate 840 with Neg_curr and a signal 825a as inputs, and an R input coupled to the output of an inverter 845 coupled to the signal 825a as input.
• the signal 825a is a logical signal indicating whether a condition Vamp > Vbatt is true, i.e., whether Vamp is greater than Vbatt.
• 825a is generated by a comparator 825 (also denoted herein as a "second comparator") configured to compare Vamp at its positive (+) terminal to Vbatt at its negative (-) terminal.
• the second comparator 825 Per operation of the circuitry described hereinabove, to prevent false tripping, the second comparator 825 is configured to determine if Vamp > Vbatt. If and only if Vamp > Vbatt, and the inductor current IL is negative, will PI be disabled, per the functionality of SR latch 830. In an exemplary embodiment, PI may be re-enabled once Vamp ⁇ Vbatt (regardless of the inductor current direction).
• the logical condition driving PI may configure the high-side switch PI to be re-enabled once a peak in the output voltage waveform (giving rise to the reverse current flow) has passed.
• the techniques disclosed herein advantageously allow the envelope tracking amplifier 140 to track a slow waveform, such as the 1RB LTE (1 Resource-Block Long- Term Evolution) waveform, and meet RF requirements in a low-battery configuration without necessarily over-designing the specifications of the boost amplifier.
• a slow waveform such as the 1RB LTE (1 Resource-Block Long- Term Evolution) waveform
• exemplary embodiment 800 is described showing a latch 830 and a comparator 825 for generating the signal 825a, it will be appreciated that these elements need not be present in alternative exemplary embodiments.
• an exemplary embodiment may omit the latch 830 (and associated elements) and comparator 825, and simply rely on the voltage comparator 610 to generate Neg_curr, which disables P I if Neg_curr is high.
• Such exemplary embodiments are contemplated to be within the scope of the present disclosure.
• FIG 9 illustrates an exemplary embodiment of a method 900 according to the present disclosure. Note the method 900 is shown for illustrative purposes only, and is not meant to limit the scope of the present disclosure to any particular method shown.
• a tracking supply voltage is selectively coupled to an inductor using a high-side switch, wherein the inductor is further coupled to a tracking supply voltage.
• the inductor is selectively coupled to ground using a low-side switch.
• the battery supply voltage is decoupled from the inductor using the high-side switch in response to at least one condition comprising the detecting the negative current flow.
• such reverse conduction can be eliminated by driving the gate of P I , e.g., via PCTRL, using VDD Amp rather than Vbatt, when P I is intended to be turned off.
• VSW would have to rise above Vt above VDD_Amp in order for current to flow through P I (when it is "off). It will be appreciated that by driving the gate of P I using VDD Amp ensures that P I stays off during the scenarios described hereinabove.
• control voltage PCTRL used to drive the gate of P I is configured to be as high as VDD_Amp, i.e., the output voltage of the boost converter 1 10, to turn P I off.
• VDD_Amp the output voltage of the boost converter 1 10
• Vt threshold voltage
• DSP Digital Signal Processor
• ASIC Application Specific Integrated Circuit
• FPGA Field Programmable Gate Array
• a general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
• a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
• a software module may reside in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
• An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.
• the storage medium may be integral to the processor.
• the processor and the storage medium may reside in an ASIC.
• the ASIC may reside in a user terminal.
• the processor and the storage medium may reside as discrete components in a user terminal.
• the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
• Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
• a storage media may be any available media that can be accessed by a computer.
• such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.
• any connection is properly termed a computer-readable medium.
• the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave
• DSL digital subscriber line
• wireless technologies such as infrared, radio, and microwave
• Disk and disc includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-Ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Dc-Dc Converters (AREA)
• Electronic Switches (AREA)
• Amplifiers (AREA)

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• 2013
  • 2013-01-28 US US13/752,241 patent/US9306520B2/en active Active
• 2014
  • 2014-01-21 KR KR1020157022736A patent/KR101659406B1/ko active Active
  • 2014-01-21 JP JP2015555216A patent/JP6271589B2/ja not_active Expired - Fee Related
  • 2014-01-21 WO PCT/US2014/012391 patent/WO2014116606A1/en not_active Ceased
  • 2014-01-21 CN CN201480005871.0A patent/CN104937837B/zh active Active
  • 2014-01-21 EP EP14706147.7A patent/EP2949040B1/en active Active

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