WO2014112082A1 - Dispositif logique programmable - Google Patents

Dispositif logique programmable Download PDF

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Publication number
WO2014112082A1
WO2014112082A1 PCT/JP2013/050851 JP2013050851W WO2014112082A1 WO 2014112082 A1 WO2014112082 A1 WO 2014112082A1 JP 2013050851 W JP2013050851 W JP 2013050851W WO 2014112082 A1 WO2014112082 A1 WO 2014112082A1
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WO
WIPO (PCT)
Prior art keywords
programmable logic
programmable
semiconductor chip
task
processing
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PCT/JP2013/050851
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English (en)
Japanese (ja)
Inventor
巌 杉山
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富士通株式会社
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Priority to PCT/JP2013/050851 priority Critical patent/WO2014112082A1/fr
Publication of WO2014112082A1 publication Critical patent/WO2014112082A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories

Definitions

  • the present invention relates to a programmable logic device.
  • Programmable logic device is a general term for logic devices that can programmably configure a logic operation circuit of a semiconductor integrated circuit.
  • a programmable logic device called FPGA field-programmable gate array
  • FPGA field-programmable gate array
  • CPUs Central Processing Units
  • a multiprocessor system in which a plurality of element processors are coupled in a two-dimensional grid, for example, by a coupling network to realize highly parallel processing (see, for example, Patent Document 2).
  • the multiprocessor system distributes and controls the load of the element processor.
  • Non-Patent Documents 1 and 2 a computing system using FPGA is known (for example, see Non-Patent Documents 1 and 2).
  • Multiple programmable logic units can perform hardware operations and are controlled by the CPU. However, as the number of programmable logic units increases, the load of programmable logic unit control by the CPU increases, causing a reduction in processing speed.
  • An object of the present invention is to provide a programmable logic device that can reduce the load on the CPU (offload) and improve the processing speed of the entire system.
  • the programmable logic device starts task processing when a task instruction signal is input, and outputs a task completion signal when the task processing is completed, and a plurality of programmable logic units using a lookup table according to the task completion signal
  • a plurality of programmable synchronization control cells that output task instruction signals; a programmable network that connects the plurality of programmable logic units and the plurality of programmable synchronization control units; and a processing core that performs task processing and management
  • the programmable synchronous control cell receives at least one of the task completion signal or the task instruction signal from the programmable network, and the task instruction signal via the programmable network. And outputs to the programmable logic unit.
  • FIG. 1 is a diagram illustrating a configuration example of a programmable logic device having the first semiconductor chip according to the present embodiment.
  • FIG. 2 is a graph showing the influence of the speed-up effect on the synchronization overhead of the programmable logic device.
  • FIG. 3 is a graph showing the influence of the speed-up effect on the communication overhead of the programmable logic device.
  • FIG. 4 is a diagram for explaining the wiring of the first semiconductor chip.
  • FIG. 5 is a diagram for explaining the second semiconductor chip.
  • FIG. 6 is a diagram illustrating a configuration example of a programmable logic device having a first semiconductor chip and a second semiconductor chip.
  • FIG. 7 is a diagram illustrating a configuration example of a programmable logic device including a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip.
  • FIG. 8 is a diagram illustrating a configuration example of electrodes of the second semiconductor chip.
  • FIG. 9 is a diagram illustrating a configuration example of the second semiconductor chip.
  • FIG. 10 is a diagram for explaining the operation of the second semiconductor chip.
  • FIG. 11 is a diagram illustrating an example of a logical operation of a lookup table.
  • FIG. 12 is a flowchart illustrating a processing example of the programmable logic device according to the present embodiment.
  • FIG. 13 is a diagram illustrating a processing example of the programmable logic device when there is no second semiconductor chip.
  • FIG. 14 is a diagram illustrating a processing example of the programmable logic device when there is a second semiconductor chip.
  • FIG. 15 is a diagram illustrating a program example of the processing core when there is no second semiconductor chip.
  • FIG. 16 is a timing chart illustrating a processing example of the programmable logic device in the case where the second semiconductor chip is present.
  • FIG. 17 is a diagram illustrating another configuration example of the second semiconductor chip.
  • FIG. 1 is a diagram illustrating a configuration example of a programmable logic device including the first semiconductor chip 101 according to the present embodiment.
  • the first semiconductor chip 101 has one processing core 102 and a plurality (for example, twelve) programmable logic units 103.
  • the processing core 102 is a processing unit such as a CPU, for example, and performs task processing and management.
  • the programmable logic unit 103 is a unit that develops (offloads) tasks into hardware, and can speed up the processing by hardware logic operations compared to the software processing of the CPU.
  • the plurality of programmable logic units 103 are, for example, look-up table type memories, and are connected in a programmable manner by a switch matrix.
  • the address of the lookup table corresponds to the logical input data, and the logical operation result represents the output data.
  • the output of the programmable logic unit 103 is wired through the connection box so as to be connected to any other programmable logic unit 103 by a switch box that can be switched in a programmable manner.
  • the above-mentioned lookup table data, switch box and connection box data are set in advance and then operated. This setting operation is called configuration (reconfiguration). For example, after the power is turned on, the processing core 102 first transfers the configuration data into the programmable logic unit 103 and then makes it operable. The processing core 102 can also change the configuration of some programmable logic units 103 during operation.
  • FIG. 2 is a graph showing the influence of the speed-up effect on the synchronization overhead of the programmable logic device of FIG.
  • the horizontal axis represents the processing core size r, and the vertical axis represents the speed-up effect [times].
  • the total size of all the programmable logic units 103 is the size of 12 programmable logic units 103.
  • the size of one processing core 102 is the size of one programmable logic unit 103, and 15 programmable logic units 103 are provided.
  • the size of one processing core 102 is the size of 16 programmable logic units 103, and the programmable logic unit 103 is not provided. That is, the larger the processing core size r, the smaller the number of programmable logic units 103, and the smaller the processing core size r, the larger the number of programmable logic units 103.
  • the synchronization overhead is caused by the following two factors. (1) When there is a dependency relationship between tasks allocated to the programmable logic unit 103, synchronous control is required to wait for the next task to be executed until the dependency relationship is completed.
  • FIG. 3 is a graph showing the influence of the speed-up effect on the communication overhead of the programmable logic device of FIG.
  • the horizontal axis represents the processing core size r, and the vertical axis represents the speed-up effect [times].
  • the task processing time is t
  • the communication time is tc.
  • the speed reduction due to the communication overhead in FIG. 3 is relatively small compared to the speed reduction due to the synchronization overhead in FIG.
  • the speed reduction due to the synchronization overhead of FIG. Management of tasks assigned to each programmable logic unit 103 requires two signal lines, a task instruction signal and a task completion signal.
  • the processing core 102 performs synchronization and exclusive management, all of these signal lines are connected to the processing core 102.
  • the present embodiment aims to realize a significant speed improvement by reducing the synchronization overhead.
  • FIG. 5 is a diagram for explaining the second semiconductor chip 501.
  • the second semiconductor chip 501 is connected to the first semiconductor chip 101 in FIG. As shown in FIG. 1, the plurality of programmable logic units (PU) 103 are provided in the first semiconductor chip 101, and start task processing (logic processing) when a task instruction signal Ps is input, respectively. When is completed, a task completion signal Vs is output.
  • the second semiconductor chip 501 has a programmable network 1001, outputs a task instruction signal Ps to a plurality of programmable logic units 103, and receives a task completion signal Vs.
  • FIG. 6 is a diagram illustrating a configuration example of a programmable logic device including the first semiconductor chip 101 and the second semiconductor chip 501.
  • the first semiconductor chip 101 has one processing core 102 and a plurality of programmable logic units 103.
  • the first semiconductor chip 101 and the second semiconductor chip 501 are three-dimensionally connected so as to overlap each other by an on-chip bump and a semiconductor chip through electrode.
  • FIG. 7 is a diagram illustrating a configuration example of a programmable logic device including the first semiconductor chip 101, the second semiconductor chip 501, and the third semiconductor chip 701.
  • the device of FIG. 7 is obtained by adding a third semiconductor chip 701 to the device of FIG.
  • the third semiconductor chip 701 has a plurality of programmable logic units 103.
  • the first semiconductor chip 101 and the third semiconductor chip 701 are three-dimensionally connected so as to sandwich the second semiconductor chip 501 with on-chip bumps, semiconductor chip through electrodes, and the like.
  • the programmable logic unit 103 of the third semiconductor chip 701 can be controlled by the processing core 102 of the first semiconductor chip 101.
  • the number of programmable logic units 103 can be increased.
  • FIG. 8 is a diagram illustrating a configuration example of the electrodes of the second semiconductor chip 501.
  • the through electrode (via) 801 is an electrode that penetrates the second semiconductor chip 501 and is an electrode for connecting the first semiconductor chip 101 and the third semiconductor chip 701 in FIG. Signals and data can be communicated between the chip 101 and the third semiconductor chip 701.
  • the electrode 802 is an electrode for connecting to the lower third semiconductor chip 701 in FIG. 7, and can input / output a task instruction signal Ps and a task completion signal Vs to / from the third semiconductor chip 701. it can.
  • the electrode 803 is an electrode for connecting to the first semiconductor chip 101 on the upper side in FIG.
  • the second semiconductor chip 501 is provided with electrodes 801 to 803 that can be connected in parallel to the lines of the first semiconductor chip 101 and the third semiconductor chip 701 and arranged in a three-dimensional manner, so that the load of the processing core 102 is increased. Contributes to the miniaturization of programmable logic devices as well as the reduction.
  • FIG. 4 is a diagram for explaining the wiring of the first semiconductor chip 101.
  • the first semiconductor chip 101 has a processing core 102 and a programmable logic unit 103.
  • the programmable logic unit 103 When the task instruction signal Ps is input, the programmable logic unit 103 outputs output data corresponding to the input data, and outputs a task completion signal Vs when the processing is completed.
  • Input / output data of the programmable logic unit 103 is communicated via the wiring 402 in the planar direction of the first semiconductor chip 101. Since the wiring 402 in the planar direction has a short wiring length and does not include a terminal for connecting between semiconductor chips, the delay time is short and high-speed data communication is possible.
  • the synchronization signal including the task instruction signal Ps and the task completion signal Vs of the programmable logic unit is connected to the second semiconductor chip of FIG. 7 via the wiring 401 perpendicular to the plane of the first semiconductor chip 101. 501 and the third semiconductor chip 701 are communicated.
  • the vertical wiring 401 is connected to the second semiconductor chip 501 and the third semiconductor chip 701 through the electrodes 801 to 803 in FIG. Since the number of the electrodes 801 is relatively small, it is preferable that the input / output data communication via the vertical wiring 401 is performed by inputting and outputting signals by serial communication of a packet including a header.
  • the third semiconductor chip 701 is the same as the first semiconductor chip 101 described above. Input / output data of the programmable logic unit 103 of the third semiconductor chip 701 is communicated via wiring in the planar direction of the third semiconductor chip 701. On the other hand, the synchronization signal including the task instruction signal Ps and the task completion signal Vs of the programmable logic unit 103 of the third semiconductor chip 701 is transmitted through the wiring perpendicular to the plane of the third semiconductor chip 701. The first semiconductor chip 101 and the second semiconductor chip 501 communicate with each other.
  • FIG. 9 is a diagram illustrating a configuration example of the second semiconductor chip 501.
  • the second semiconductor chip 501 includes a plurality of programmable synchronization control cells 901 in a two-dimensional matrix, a plurality of connection units (C) 902, and a plurality of switch units (S) 903.
  • the connection unit 902 and the switch unit 903 correspond to the programmable network 1001 in FIG.
  • the programmable network 1001 connects a plurality of programmable logic units 103 and a plurality of programmable synchronization control units 901.
  • the programmable synchronous control cell 901 has a lookup table 911 and flip-flops 912 and 913, and inputs and outputs a task instruction signal Ps and a task completion signal Vs.
  • lookup table 911 configuration data is set by the processing core 102 through a separately provided wiring (not shown).
  • the connection unit 902 includes a configuration memory 921 and a plurality of switches 922, and controls network connection between the upper and lower two programmable synchronization control cells 901 and the left and right switch units 903.
  • Configuration data is set in the configuration memory 921 by the processing core 102.
  • the switch 922 is controlled to be turned on / off according to configuration data in the configuration memory 921.
  • the switch unit 903 includes a configuration memory 931 and a plurality of switches 932, and controls network connection between the four connection units 902 on the upper, lower, left, and right sides.
  • Configuration data is set in the configuration memory 931 by the processing core 102.
  • the switch 932 is controlled to be turned on / off according to configuration data in the configuration memory 931.
  • FIG. 10 is a diagram for explaining the operation of the second semiconductor chip 501.
  • the second semiconductor chip 501 includes a lookup table 911, flip-flops 912 and 913, and a programmable network 1001.
  • the lookup table 911 and the flip-flops 912 and 913 are provided in the programmable synchronous control cell 901 in FIG.
  • the programmable network 1001 corresponds to the connection unit 902 and the switch unit 903 in FIG.
  • the programmable logic unit 103 is provided in the first semiconductor chip 101 or the third semiconductor chip 701.
  • the input signal IN1 is a synchronization signal input from various programmable logic units 103, various programmable synchronization control cells 901 or the processing core 102 via the programmable network 1001, and includes a task instruction signal Ps and a task completion signal Vs.
  • the programmable logic unit 103 When the processing is completed, the programmable logic unit 103 outputs a task completion signal Vs to the lookup table 911 via the programmable network 1001.
  • the lookup table 911 outputs a signal Cb corresponding to the task completion signal Vs and the input signal IN1.
  • configuration data for performing an arbitrary logical operation is written.
  • the flip-flop 912 latches the signal Cb in synchronization with the clock signal CLK, and outputs the latched signal to the programmable network 1001.
  • the flip-flop 913 latches the signal Cb in synchronization with the clock signal CLK, and outputs the latched signal to the various programmable logic units 103 via the programmable network 1001 as the task instruction signal Ps.
  • the programmable logic unit 103 starts task processing when the task instruction signal Ps is input.
  • the programmable synchronization control cell 901 controls the programmable logic unit 103 in synchronization, thereby reducing the load on the processing core 102 and reducing the synchronization overhead. Speed can be improved.
  • the flip-flops 912 and 913 are circuits necessary for timing adjustment for outputting a signal at a timing next to the clock signal CLK.
  • FIG. 11 is a diagram illustrating an example of a logical operation of the lookup table 911.
  • the programmable synchronization control cell 901a is a programmable synchronization control cell 901 that controls the task A in synchronization.
  • the programmable synchronization control cell 901b is a programmable synchronization control cell 901 that controls the task B in synchronization.
  • the lookup table 911a corresponds to the lookup table 911 and shows an example in which the task instruction signal Ps is output when two tasks A and B are completed. In this case, data such that the logical product of the task completion signals Vs is calculated is written in the lookup table 911a.
  • the look-up table 911a outputs a logical product signal Cb of the input signals A and B.
  • the programmable synchronization control cell 901a is a programmable synchronization control cell 901 that controls the task A in synchronization.
  • the programmable synchronization control cell 901b is a programmable synchronization control cell 901 that controls the task B in synchronization.
  • the lookup table 911b corresponds to the lookup table 911 and shows an example in which the task instruction signal Ps is output when one of the two tasks A and B is completed. In this case, data that calculates the logical sum of each task completion signal Vs is written in the lookup table 911b.
  • the lookup table 911b outputs a logical sum signal Cb of the input signals A and B.
  • FIG. 12 is a flowchart showing a processing example of the programmable logic device according to the present embodiment.
  • the programmable logic device is powered on.
  • the processing core 102 performs initialization processing of the programmable logic device.
  • the processing core 102 writes the configuration data to the configuration memory in the programmable logic unit (PU) 103.
  • the processing core 102 writes the configuration data to the look-up table 911 in the programmable synchronization control cell 901 and the configuration memories 921 and 931 in the programmable network 1101 (connection unit 902 and switch unit 903).
  • the processing core 102 issues a processing start command.
  • the task instruction signal Ps is input to the programmable logic unit 103 and / or the programmable synchronous control cell 901, and task processing by the programmable logic unit 103 is started.
  • steps S1206 to S1209 are performed for each task, and processing of a plurality of tasks is executed in parallel.
  • step S1206 the look-up table 911 in the programmable synchronization control cell 901 outputs a logical operation signal Cb according to the input signal.
  • step S1207 the programmable synchronization control cell 901 outputs a task instruction signal Ps.
  • step S1208 the programmable logic unit 103 inputs the task instruction signal Ps and performs task processing.
  • step S1209 when the task processing is completed, the programmable logic unit 103 outputs a task completion signal Vs.
  • step S1210 the programmable synchronization control cell 901 outputs a processing end signal to the processing core 102 when all tasks are completed. Then, the processing core 102 proceeds to the next process. Thereafter, these processes are repeated to execute a large task as a whole.
  • FIG. 13 shows a processing example of the programmable logic device when the second semiconductor chip 501 is not provided
  • FIG. 14 shows a processing example of the programmable logic device when the second semiconductor chip 501 is provided.
  • FIG. 13 is a diagram illustrating a processing example of the programmable logic device when the second semiconductor chip 501 is not provided. Since there is no second semiconductor chip 501, one processing core 102 performs all synchronization processing. Each task group includes, for example, steps S1301 to S1303 and S1311 to S1313. The processing core 102 performs processing sequentially for each task group. An example will be described in which the tasks in steps S1301 to S1303 and the tasks in steps S1311 to S1313 compete for the use of the shared resource.
  • step S1301 the processing core 102 outputs a task instruction signal Ps to a programmable logic unit 103.
  • the programmable logic unit 103 performs task processing and uses shared resources.
  • step S1303 the programmable logic unit 103 outputs a task completion signal Vs.
  • step S1311 the processing core 102 outputs a task instruction signal Ps to another programmable logic unit 103.
  • step S1312 the programmable logic unit 103 performs task processing and uses shared resources.
  • step S1313 the programmable logic unit 103 outputs a task completion signal Vs.
  • steps S1302 and S1312 competition for using the shared resource 1300 occurs due to the critical process.
  • the processing core 102 waits for one of the tasks by the synchronization process.
  • Processing core 102 performs sequential processing for each task group. When one task processing takes about 20 cycles, it takes a processing time of (about 20 cycles ⁇ number of task groups).
  • FIG. 14 is a diagram illustrating a processing example of the programmable logic device when the second semiconductor chip 501 is present.
  • the second semiconductor chip 501 performs a synchronization process.
  • the processing of three task groups 1401 to 1403 is executed in parallel.
  • Each task group 1401 to 1403 is synchronously controlled by a plurality of programmable synchronous control cells 901.
  • Configuration data is programmed in advance in the programmable synchronous control cell 901 for each task group 1401 to 1403, and a plurality of task groups 1401 to 1403 are processed in parallel.
  • the processing of the plurality of task groups 1401 to 1403 is completed in 5 to 10 clocks, so that the processing time can be shortened compared to the case of FIG.
  • FIG. 15 is a diagram showing a program example of the processing core 102 when the second semiconductor chip 501 is not present.
  • the processing core 102 performs the synchronization process by executing the program of FIG. This program corresponds to one task.
  • “MOV MEM 1” sets the initial value 1 to the variable MEM for task management.
  • “CALL A” the Ps processing routine (processing routine of the task instruction signal Ps) is called.
  • “MOV AX MEM” sets the value of the variable MEM in the register AX.
  • “CMP AX 1” compares whether or not the value of the register AX is “1”. In “JMP A”, if the value of the register AX is not 1, the process jumps to the instruction “MOV AX MEM”. If the value of the register AX is 1, the process proceeds to the next instruction. In the next instruction “DEC AX”, the value of the register AX is decremented and exclusive processing of the shared resource from other tasks is set. Next, in “MOV MEM AX”, the value of the register AX is set to the variable MEM. Thereafter, returning to the processing of the main routine, the task is executed, and when the execution is completed, “CALL B” calls the Vs processing routine (processing routine of the task completion signal Vs).
  • MOV AX MEM sets the value of the variable MEM in the register AX.
  • IRC AX the value of the register AX is incremented, and the shared resource exclusion process is canceled.
  • MOV MEM AX the value of the register AX is set to the variable MEM. Thereafter, the process returns to the main routine.
  • the number of cycles of the synchronization process of this program is 23 clocks. Since the synchronization control of the processing core 102 is performed sequentially, the exclusive control of the shared resources of all tasks requires 23 clocks ⁇ synchronization processing cycles corresponding to the number of tasks.
  • FIG. 16 is a timing chart showing a processing example of the programmable logic device when the second semiconductor chip 501 is present.
  • the programmable synchronization control cell 901 performs synchronization control.
  • a high level pulse is generated in the input signal IN1 of the lookup table 911.
  • a high level pulse is generated in the output signal Cb of the lookup table 911.
  • the programmable synchronous control cell 901 outputs a task instruction signal Ps of a pi level pulse.
  • the programmable logic unit 103 outputs a task completion signal Vs when the task processing is completed.
  • the lookup table 911 receives a task completion signal Vs of a high level pulse from the programmable logic unit 103.
  • the lookup table 911 outputs an output signal Cb of a high level pulse.
  • the programmable synchronous control cell 901 outputs a task instruction signal Ps of a pi level pulse. Thereafter, a high level pulse is generated in the input signal IN1 of the lookup table 911.
  • the synchronization process can be completed in a total of 6 clocks, and in a shorter time and in parallel than the 23 clocks in FIG. Synchronous processing can be performed. This improves the processing speed of the programmable logic device.
  • FIG. 17 is a diagram illustrating another configuration example of the second semiconductor chip 501.
  • the second semiconductor chip 501 in FIG. 17 is obtained by replacing one lookup table 911 with two lookup tables 911a and 911b and adding a selector 1701 to the second semiconductor chip 501 in FIG. It is.
  • the first lookup table 911a receives the task completion signal Vs and the input signal IN1, and outputs an output signal to the selector 1701.
  • the second lookup table 911b receives the task completion signal Vs and the input signal IN1, and outputs an output signal to the selector 1701.
  • the selector 1701 selects one of the output signals of the lookup tables 911a and 911b according to the switching signal SEL, and outputs a signal Cb.
  • the programmable synchronization control cell 901 can dynamically change the logical operation configuration of the lookup tables 911a and 911b by dynamically switching and using the plurality of lookup tables 911a and 911b.
  • connection unit 902 two configuration memories 921 of the connection unit 902 and two configuration memories 931 of the switch unit 903 in FIG. 9 can be provided.
  • control logic between tasks can be dynamically changed.

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  • Computer Hardware Design (AREA)
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Abstract

Dans la présente invention, un dispositif logique programmable comprend : une pluralité d'unités logiques (103) programmables permettant de commencer le traitement de tâches quand un signal d'instruction de tâche est entré, et de transmettre un signal d'achèvement de tâche quand le traitement de tâche s'achève; une pluralité de cellules de commande de synchronisation (911-913) programmables qui, au moyen d'une table de recherche, transmettent le signal d'instruction de tâche conformément au signal d'achèvement de tâche; un réseau (1001) programmable permettant de connecter la pluralité d'unités logiques programmables et la pluralité d'unités de commande de synchronisation programmables; et un noyau de traitement permettant d'effectuer le traitement et la gestion de tâches. Les cellules de commande de synchronisation programmable reçoivent une entrée, provenant du réseau programmable, au moins du signal d'achèvement de tâche ou du signal d'instruction de tâche, et transmettent le signal d'instruction de tâche à l'unité logique programmable via le réseau programmable.
PCT/JP2013/050851 2013-01-17 2013-01-17 Dispositif logique programmable WO2014112082A1 (fr)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001312481A (ja) * 2000-02-25 2001-11-09 Nec Corp アレイ型プロセッサ
WO2005001689A1 (fr) * 2003-06-25 2005-01-06 Nec Corporation Ordinateur electronique, circuit integre a semi-conducteurs, procede de controle, procede de creation de programme, et programme
JP2005512229A (ja) * 2001-12-05 2005-04-28 アーバー・カンパニー・リミテッド・ライアビリティ・パートナーシップ 混成の積み重ねられた集積回路ダイ要素を含む再構成可能なプロセッサモジュール
WO2009157441A1 (fr) * 2008-06-26 2009-12-30 日本電気株式会社 Dispositif de traitement de données, dispositif de traitement d’informations et procédé de traitement d’informations
WO2010087098A1 (fr) * 2009-01-30 2010-08-05 日本電気株式会社 Dispositif de calcul parallèle, système de traitement d'informations, procédé de calcul parallèle et dispositif de traitement d'informations
JP2012053778A (ja) * 2010-09-02 2012-03-15 Toshinori Sueyoshi プログラマブル論理回路のエラー訂正回路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001312481A (ja) * 2000-02-25 2001-11-09 Nec Corp アレイ型プロセッサ
JP2005512229A (ja) * 2001-12-05 2005-04-28 アーバー・カンパニー・リミテッド・ライアビリティ・パートナーシップ 混成の積み重ねられた集積回路ダイ要素を含む再構成可能なプロセッサモジュール
WO2005001689A1 (fr) * 2003-06-25 2005-01-06 Nec Corporation Ordinateur electronique, circuit integre a semi-conducteurs, procede de controle, procede de creation de programme, et programme
WO2009157441A1 (fr) * 2008-06-26 2009-12-30 日本電気株式会社 Dispositif de traitement de données, dispositif de traitement d’informations et procédé de traitement d’informations
WO2010087098A1 (fr) * 2009-01-30 2010-08-05 日本電気株式会社 Dispositif de calcul parallèle, système de traitement d'informations, procédé de calcul parallèle et dispositif de traitement d'informations
JP2012053778A (ja) * 2010-09-02 2012-03-15 Toshinori Sueyoshi プログラマブル論理回路のエラー訂正回路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SHIN'YA UENO ET AL.: "Three-Dimensional Accelerator Architecture for Image Recognition", IPSJ SIG NOTES 2011 (HEISEI 23) NENDO, vol. 2, no. 152, 15 December 2011 (2011-12-15), pages 1 - 6 *

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