WO2014108999A1 - 制御システム、マスタープログラマブルコントローラ、スレーブプログラマブルコントローラ、および、制御方法 - Google Patents

制御システム、マスタープログラマブルコントローラ、スレーブプログラマブルコントローラ、および、制御方法 Download PDF

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Publication number
WO2014108999A1
WO2014108999A1 PCT/JP2013/050121 JP2013050121W WO2014108999A1 WO 2014108999 A1 WO2014108999 A1 WO 2014108999A1 JP 2013050121 W JP2013050121 W JP 2013050121W WO 2014108999 A1 WO2014108999 A1 WO 2014108999A1
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WIPO (PCT)
Prior art keywords
programmable controller
delay time
transmission delay
slave
master
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PCT/JP2013/050121
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English (en)
French (fr)
Japanese (ja)
Inventor
幸輝 湯尾
晃 藤森
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富士電機株式会社
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Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to JP2014556241A priority Critical patent/JP5935903B2/ja
Priority to PCT/JP2013/050121 priority patent/WO2014108999A1/ja
Priority to KR1020157011274A priority patent/KR101726743B1/ko
Priority to CN201380062822.6A priority patent/CN104854523B/zh
Publication of WO2014108999A1 publication Critical patent/WO2014108999A1/ja

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/052—Linking several PLC's
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/12—Plc mp multi processor system
    • G05B2219/1215—Master slave system

Definitions

  • the present invention relates to a control system, a master programmable controller, a slave programmable controller, and a control method in which a plurality of programmable controllers that respectively control controlled devices are connected to be communicable with each other.
  • the controller has a hierarchical structure from the viewpoint of system construction and ease of maintenance, and the layers are connected by a network.
  • a plurality of programmable controllers are connected to one management device via a network, and one or a plurality of controlled devices are connected to each programmable controller. Then, the programmable controller receives a control command from the upper management device, analyzes the control command, and controls the lower-level controlled device.
  • the control process proceeds in a closed range between the programmable controller and the controlled device. Then, the programmable controller transmits only the control result to the management device. Therefore, the management device collects control results at individual timings within the programmable controller.
  • communication can be established between programmable controllers under the same management device, and control results can be transmitted and received.
  • a technique for performing scheduling for transmitting / receiving control data between programmable controllers and switching a switch provided between the programmable controllers according to the scheduling is known (for example, Patent Document 1).
  • the programmable controllers can exchange information.
  • the plurality of programmable controllers in the control system operate at independent timings according to the control command of the management device, the programmable controller and the controlled device are synchronized, but the programmable controllers are synchronized. It becomes a state that is not taken.
  • the management device collects information from a plurality of programmable controllers
  • the timing at which the information is generated differs for each programmable controller, so the context of the information is not clear and strict control is difficult.
  • the present invention provides a control system, a master programmable controller, a slave programmable controller, and a control method capable of improving portability and improving control accuracy and stability. It is an object.
  • the programmable controller is another programmable controller.
  • a communication unit that establishes communication with the controlled device, and a common memory for sharing data with other programmable controllers via the communication unit, and the programmable controller includes a master programmable controller that functions as a master, There is a slave programmable controller that functions as a slave, and the master programmable controller further has a transmission delay between the master programmable controller and the slave programmable controller.
  • the transmission delay time request frame for measuring the transmission delay time request frame is transmitted to the slave programmable controller, and when the reception completion frame that is a response to the transmission delay time request frame is received, the time when the transmission delay time request frame is transmitted and the reception completion frame
  • a delay time measurement unit that calculates a transmission delay time from a difference from the time when the signal is received and transmits a transmission delay time notification frame including the transmission delay time to the slave programmable controller.
  • the slave programmable controller further includes a transmission delay.
  • the reception completion frame is transmitted to the master programmable controller, and when the transmission delay time notification frame is received, the delay time receiving unit that acquires the transmission delay time included in the transmission delay time notification frame , Based on the transmission delay time, characterized in that it comprises a synchronization correction unit for synchronizing the slave programmable controller to the master programmable controller.
  • the master programmable controller of this invention which controls a controlled device based on a program and functions as a master is a slave programmable controller that functions as a slave, and communication that establishes communication with the controlled device And the slave programmable controller with a common memory for sharing data with the slave programmable controller via the communication unit, and a transmission delay time request frame for measuring the transmission delay time between the master programmable controller and the slave programmable controller.
  • the master programmable controller of this invention which controls a controlled device based on a program and functions as a master is a slave, and communication that establishes communication with the controlled device
  • the slave programmable controller with a common memory for sharing data with the slave programmable controller via the communication unit, and a transmission delay time request frame for measuring the transmission delay time between the master programmable controller and the slave programmable controller.
  • the slave programmable controller of this invention which controls a controlled device based on a program and functions as a slave is another programmable controller including a master programmable controller that functions as a master, and a controlled device
  • a communication unit that establishes communication with the communication unit, a common memory for sharing data with other programmable controllers via the communication unit, and a transmission delay time request for measuring the transmission delay time between the master programmable controller and the slave programmable controller
  • a reception completion frame that is a response to the transmission delay time request frame is transmitted to the master programmable controller, and a transmission delay time notification frame including the transmission delay time is received.
  • a delay time receiving unit that acquires the transmission delay time included in the transmission delay time notification frame, and a synchronization correction unit that synchronizes the slave programmable controller with the master programmable controller based on the transmission delay time, To do.
  • a programmable controller is Establish communication with other programmable controllers and controlled devices, share data with other programmable controllers using a common memory via the communication unit, and among the programmable controllers, the master programmable controller that functions as the master is the master programmable A transmission delay time request frame for measuring the transmission delay time between the controller and the slave programmable controller functioning as a slave is transmitted to the slave programmable controller, and the slave program is transmitted.
  • the grammatic controller When receiving the transmission delay time request frame, the grammatic controller sends a reception completion frame, which is a response to the transmission delay time request frame, to the master programmable controller.
  • the transmission delay time is calculated from the difference between the time when the frame is transmitted and the time when the reception completion frame is received, and the transmission delay time notification frame including the transmission delay time is transmitted to the slave programmable controller.
  • the transmission delay time notification frame When the transmission delay time notification frame is received, the transmission delay time included in the transmission delay time notification frame is acquired, and the slave programmable controller is master-programmed based on the transmission delay time. And wherein the synchronizing between logic controllers.
  • control units In a control system applied to a large-scale plant or the like, control applications are divided and controlled by a plurality of control units (also referred to as configurations) depending on the processing complexity of the entire system and the physical arrangement.
  • the control unit mainly indicates a combination of a programmable controller and a controlled device controlled by the programmable controller.
  • a plurality of such control units are prepared and connected to a management apparatus that controls the entire control system.
  • each apparatus which comprises a control system is demonstrated.
  • FIG. 1 is an explanatory diagram showing a schematic relationship between devices constituting the control system 100
  • FIG. 2 is an explanatory diagram showing a schematic configuration of the control system 100.
  • the control system 100 includes a management device 110, a plurality of programmable controllers 120, and a plurality of controlled devices 130.
  • the management device 110 and the plurality of programmable controllers 120 are connected to each other by a network wiring 140 based on Ethernet (registered trademark) such as a Giga (G) base as a controller level network.
  • the plurality of programmable controllers 120 and the plurality of controlled devices 130 are connected to each other as a device level network through, for example, a dedicated connection wiring 142.
  • the management apparatus 110 collectively controls the plurality of programmable controllers 120 so that the entire control system 100 operates in accordance with the process flow defined in the application. For example, the management apparatus 110 collects status information and control results from the individual programmable controllers 120, and outputs various control commands to the individual programmable controllers 120 according to the collected contents.
  • the programmable controller 120 is also called PLC (Programmable Logic Controller), and includes a plurality of modules such as a CPU module 122, a communication module 124, an input / output (I / O) module 126, and a power supply module 128, as shown in FIG. Consists of.
  • the CPU module 122 downloads an execution program divided for each control unit from the management apparatus 110 in order to realize an application, executes the execution program, and does not show the operation status of the control unit. Or display on other monitors.
  • the controlled device 130 is controlled based on the control command received from the management device 110, the sensor detection result of the controlled device 130 input through the input / output module 126, information held by the other programmable controller 120, and the like.
  • the CPU module 122 transmits data such as status information indicating its own state, sensor detection results, and control results to the management device 110.
  • the communication module 124 is connected to the management apparatus 110, another programmable controller 120, and other modules through, for example, Ethernet (registered trademark) such as a Giga (G) base as a controller level network, and communicates with each other. Can be established. However, data may be exchanged between the modules via a bus provided on the base board.
  • Ethernet registered trademark
  • G Giga
  • the communication module 124 is formed integrally with the CPU module 122.
  • the input / output module 126 manages input / output with respect to the controlled device 130. For example, if the controlled device 130 is a sensor, the sensor detection result is collected, and if the controlled device 130 is an electric motor, a control command represented by a discrete is transmitted and the control result is collected.
  • the power supply module 128 supplies power to each module such as the CPU module 122, the communication module 124, and the input / output module 126.
  • the controlled device 130 includes sensors that detect various states in FA (Factory Automation), and electric devices such as an electric motor and an encoder that operate according to the detection results of the sensors.
  • FA Vectory Automation
  • electric devices such as an electric motor and an encoder that operate according to the detection results of the sensors.
  • control system 100 can be applied to various control objects.
  • MES production execution system
  • production device such as a center sealer unit, a film unit, or a rolling unit as the controlled device 130.
  • the programmable controller 120 is connected.
  • the programmable controller 120 reads the operating state of the production device from the input / output module 126 and the like, and controls the rotation of the electric motor in the production device through a motor driver or the like.
  • the management device 110 collects information for each programmable controller 120 and transmits a control command. In this way, the entire control system 100 can comprehensively perform production support management such as process management, quality management, and production amount management.
  • the CPU module 122 of the programmable controller 120 will be described in detail.
  • FIG. 3 is a diagram illustrating an example of a hardware configuration of the CPU module 122.
  • the CPU module 122 illustrated in FIG. 3 includes an input unit 150, an output unit 152, a communication unit 154, a logic circuit 156, a reference signal generation unit 158, a CPU 160, a ROM 162, a RAM 164, and a common memory 166. Consists of including. Among these, the input unit 150, the output unit 152, the logic circuit 156, the CPU 160, the ROM 162, the RAM 164, and the common memory 166 are connected so that data can be moved by the common bus 168.
  • the input unit 150 includes a keyboard, a pointing device such as a mouse and a touch panel, a voice input device, and the like, and accepts various operations such as execution of a program by the user.
  • the output unit 152 includes a liquid crystal display, an organic EL (Electro Luminescence) display, and the like, and various windows, data, control program progress statuses and control results necessary for operating the CPU module 122 that performs processing in the present embodiment. Etc. are displayed.
  • the communication unit 154 functions as the communication module 124 described above, and establishes communication with the management device 110, the other programmable controller 120, and the input / output module 126 through Ethernet (registered trademark). In the present embodiment, the communication unit 154 is built in the CPU 160.
  • the logic circuit 156 is composed of an integrated circuit that can rewrite a logic circuit such as CPLD (Complex Programmable Logic Device) or FPGA (Field-Programmable Gate Array), and incorporates various logic circuits that assist the CPU 160.
  • CPLD Complex Programmable Logic Device
  • FPGA Field-Programmable Gate Array
  • the reference signal generation unit 158 is configured with a hardware counter, performs counting, and generates a reference signal for the CPU 160 when the count value reaches a preset reference value. Such a count value is periodically counted based on a reference value.
  • the reference value is preset in each CPU module 122 and can be changed from the management device 110 or the input unit 150.
  • the reference signal generation unit 158 is shown separately from the CPU 160, but the reference signal generation unit 158 may be realized using a timer counter built in the CPU 160.
  • “built-in” means that only the function units used by the CPU 160 can access the reference signal generation unit 158, for example.
  • the CPU 160 controls processing of the entire CPU module 122 such as various operations and data input / output based on a basic program such as an OS (Operating System) and an execution program. Further, the CPU 160 executes the execution program stored in the ROM 162 and uses the RAM 164 as a work area, so that the delay time measuring unit 180, the synchronization frame transmitting unit 182, the delay time receiving unit 184, and the synchronization correcting unit 186 are used. , Function unit such as an application execution unit 188, a data update unit 190, and a data transmission unit 192. In addition, the CPU 160 includes a communication unit 154, and communicates with the management device 110, the other programmable controller 120, and the input / output module 126 based on interrupt processing.
  • a basic program such as an OS (Operating System) and an execution program. Further, the CPU 160 executes the execution program stored in the ROM 162 and uses the RAM 164 as a work area, so that the delay time measuring unit 180, the synchronization frame transmit
  • the ROM 162 stores the basic program and the execution program described above. Moreover, you may have storage means, such as a hard disk, as an auxiliary storage device.
  • the RAM 164 temporarily stores a part of the basic program and the execution program and data (for example, status information, sensor detection result, control result, etc.) generated by executing the execution program.
  • the common memory 166 is a storage area for sharing information with other CPU modules 122 and may be formed as a part of the RAM 164.
  • FIG. 4 is a functional block diagram for explaining each functional unit of the CPU module 122.
  • the CPU 160 also functions as the delay time measurement unit 180, the synchronization frame transmission unit 182, the delay time reception unit 184, the synchronization correction unit 186, the application execution unit 188, the data update unit 190, and the data transmission unit 192.
  • Each of these functional units may or may not function depending on whether the programmable controller 120 operates as a master (master programmable controller) or operates as a slave (slave programmable controller).
  • the CPU module 122 in the master programmable controller is the master CPU module 122a
  • the CPU module 122 in the slave programmable controller is the slave CPU module 122b.
  • functional units that do not function depending on whether they are masters or slaves are indicated by broken lines.
  • one CPU module 122 can be a master CPU module 122a or a slave CPU module 122b.
  • the delay time measuring unit 180 transmits a transmission delay time request frame for measuring the transmission delay time between the master CPU module 122a and the slave CPU module 122b to an arbitrary slave. It transmits to CPU module 122b.
  • This transmission delay time request frame has substantially the same format as a later-described synchronization frame and has a different data in a predetermined portion (for example, a command portion) in the synchronization frame.
  • the transmission delay time request frame is transmitted in synchronization with the reference signal generated by the reference signal generation unit 158 in the master CPU module 122a.
  • the delay time measuring unit 180 when the delay time measuring unit 180 receives the reception completion frame from any slave CPU module 122b after transmitting the transmission delay time request frame, the delay time measurement unit 180 acquires the time when the reception completion frame is received. The delay time measurement unit 180 then performs round-trip transmission between the master CPU module 122a and any slave CPU module 122b based on the difference between the time when the transmission delay time request frame is transmitted and the time when the reception completion frame is received. Calculate the delay time. Then, the delay time measuring unit 180 divides the calculated round trip transmission delay time by 2, and synchronizes the transmission delay time notification frame including the transmission delay time as a result with the next reference signal, so that the arbitrary slave CPU module 122b. Send to. In this way, the transmission delay time by the network wiring 140 can be notified to an arbitrary slave CPU module 122b.
  • the synchronization frame transmission unit 182 transmits a prepared synchronization frame to the plurality of slave CPU modules 122b in synchronization with the reference signal.
  • a synchronization frame is a signal for matching the count value of the reference signal generation unit 158 of the slave CPU module 122b with the count value of the reference signal generation unit 158 of the master CPU module 122a.
  • the delay time receiving unit 184 receives the transmission delay time request frame from the master CPU module 122a, and masters the reception completion frame according to the transmission delay time request frame. It transmits to CPU module 122a. Further, when receiving the transmission delay time notification frame from the master CPU module 122a, the delay time receiving unit 184 saves the transmission delay time included in the frame in the RAM 164 or the like. In this way, the slave CPU module 122b can obtain the transmission delay time between the master CPU module 122a and the slave CPU module 122b.
  • the synchronization correction unit 186 advances the reference signal generated by the reference signal generation unit 158 in the slave CPU module 122b by the transmission delay time. Specifically, when the synchronization correction unit 186 receives the synchronization frame from the master CPU module 122a, the synchronization correction unit 186 acquires a count value from the reference signal generation unit 158, and a value corresponding to the transmission delay time (time conversion of the reference signal generation unit 158). Value) and the obtained count value, a correction amount is calculated, a correction reference value is derived by subtracting the correction amount from the reference value, and the reference signal is temporarily set using the correction reference value as a new reference value. Set in the generation unit 158. Therefore, the correction reference value is represented by reference value ⁇ (value corresponding to transmission delay time ⁇ count value of reference signal generation unit 158).
  • the correction reference value is set, and when the reference signal generation unit 158 completes counting with the correction reference value, the synchronization correction unit 186 promptly sets the original reference value in the reference signal generation unit 158. .
  • the reference value can be temporarily advanced by the transmission delay time.
  • an example is given in which correction for the transmission delay time is performed at one time.
  • the present invention is not limited to this, and the correction may be performed in multiple steps. In this embodiment, even when the synchronization correction unit 186 receives the synchronization frame without obtaining the transmission delay time from the master CPU module 122a, the above correction processing is performed with the transmission delay time set to zero (0). Good.
  • the reference signal generation unit 158 of the master CPU module 122a and the reference signal generation unit 158 of the slave CPU module 122b can be synchronized with high accuracy.
  • Such synchronization correction processing may be performed continuously or intermittently at predetermined time intervals.
  • the application execution unit 188 executes the execution program in both the master CPU module 122a and the slave CPU module 122b in accordance with the reference signal generated by the reference signal generation unit 158 (receiving the reference signal as an interrupt signal). Then, the controlled device 130 is controlled through the input / output module 126. Therefore, the execution program is periodically executed according to the reference signal.
  • the data update unit 190 uses the generated data.
  • the contents of the common memory 166 in the CPU module 122 are updated.
  • the data update unit 190 transfers the data to another CPU module 122.
  • the data update unit 190 updates the contents of the common memory 166 in its own CPU module 122 based on the data. In this way, data can be shared with other CPU modules 122.
  • the transmission timing at which the data updating unit 190 transmits data to the other CPU modules 122 is predetermined for each CPU module 122 based on the reference signal generation unit 158. Such transmission timing will be described in detail later.
  • the data transmission unit 192 collects data that is requested to be collected by the management apparatus 110 among the data generated by the application execution unit 188 executing the execution program in both the master CPU module 122a and the slave CPU module 122b. To the management device 110.
  • the transmission timing follows the transmission timing of the data update unit 190. In this embodiment, since the CPU modules 122 are synchronized with each other, data having the same generation timing is collected in the management device 110.
  • FIG. 5 is a time chart for explaining an example of the synchronization correction processing.
  • the reference value is 1000 ⁇ sec, but is not limited to this, and can be appropriately changed by the management device 110, for example.
  • ⁇ sec is expressed as ⁇ s for simplification.
  • the reference signal generator 158 of the master CPU module 122a performs counting.
  • a reference signal is output in the master CPU module 122a.
  • the application execution unit 188 executes an execution program according to the reference signal.
  • a triangular area indicated by hatching indicates the transition of the count value. The count value increases as time passes, and is reset when the count target (for example, a reference value) is reached.
  • the reference signal generation unit 158 of the slave CPU module 122b is also counting. When the count value reaches the reference value at (2) in FIG. 5, a reference signal is output. Then, the application execution unit 188 executes an execution program according to the reference signal. As described above, in the master CPU module 122a and the slave CPU module 122b, predetermined processing is performed in accordance with the independent reference signals.
  • the delay time measuring unit 180 of the master CPU module 122a transmits a transmission delay time request frame in order to calculate the transmission delay time ((3 in FIG. 5). )).
  • the delay time receiving unit 184 of the slave CPU module 122b transmits a reception completion frame to the master CPU module 122a according to the transmission delay time request frame (FIG. 5). (4)).
  • the delay time measuring unit 180 of the master CPU module 122a calculates the round trip transmission delay time between the master CPU module 122a and the slave CPU module 122b. Then, the delay time measurement unit 180 transmits a transmission delay time notification frame including a transmission delay time (200 ⁇ sec) obtained by dividing the calculated round trip transmission delay time (400 ⁇ sec) by 2 to the slave CPU module 122b ((5 in FIG. 5). )).
  • the delay time receiving unit 184 of the slave CPU module 122b saves the round-trip transmission delay time (equivalent value) included in the frame in the RAM 164 or the like ((6) in FIG. 5).
  • the synchronization frame transmission unit 182 of the master CPU module 122a transmits the synchronization frame as an interrupt signal to the slave CPU module 122b ((7) in FIG. 5).
  • the slave CPU module 122b receives the synchronization frame at the time of (8) in FIG. 5 after one-way transmission delay time (200 ⁇ s) of the network wiring 140
  • the synchronization correction unit 186 receives the synchronization signal from the reference signal generation unit 158.
  • a count value (corresponding to 190 ⁇ sec) is acquired ((9) in FIG. 5).
  • the reference signal generation unit 158 restarts because the count value reaches the temporary correction reference value 990 ⁇ s at the time point (11) in FIG.
  • the reference signal of the slave CPU module 122b is synchronized with the reference signal of the master CPU module 122a.
  • FIG. 6 is a diagram showing a schematic sequence example of the synchronization correction processing.
  • synchronization using the master CPU module 122a and the slave CPU module 122b will be described.
  • the present embodiment is not limited to this, and one master CPU module 122a is used.
  • a plurality of slave CPU modules 122b can be synchronized.
  • the reference signal generator 158 of the master CPU module 122a generates a reference signal (S11), and the reference signal generator 158 of the slave CPU module 122b is independent of the master CPU module 122a.
  • a reference signal is generated (S12). Moreover, this process is performed periodically.
  • the delay time measuring unit 180 of the master CPU module 122a transmits a transmission delay time request frame to the slave CPU module 122b in order to calculate the transmission delay time (S13).
  • the delay time receiving unit 184 of the slave CPU module 122b transmits a reception completion frame to the master CPU module 122a (S14).
  • the delay time measuring unit 180 of the master CPU module 122a calculates, for example, a transmission delay time (S15), and generates a transmission delay time notification frame including the calculated transmission delay time (S16). Then, the delay time measuring unit 180 transmits the generated transmission delay time notification frame to the slave CPU module 122b via the network wiring 140 (S17).
  • the delay time reception unit 184 of the slave CPU module 122b saves the transmission delay time (converted value) included in the transmission delay time notification frame in the RAM 164 or the like (S18).
  • the synchronization frame transmission unit 182 of the master CPU module 122a transmits the synchronization frame as an interrupt signal to the slave CPU module 122b in synchronization with the reference signal (S19).
  • the synchronization correction unit 186 acquires a count value from the reference signal generation unit 158 (S20). Then, using the transmission delay time and the reference value, the synchronization correction unit 186 calculates a reference value— (value corresponding to the transmission delay time ⁇ count value of the reference signal generation unit 158) to obtain a correction reference value (S21). . Then, the correction reference value is temporarily set in the reference signal generation unit 158 as a new reference value (S22). When the correction reference value is set and counting with the correction reference value is completed, the synchronization correction unit 186 quickly sets the original reference value in the reference signal generation unit 158 (S23).
  • Such synchronization correction processing is executed for all the slave CPU modules 122b included in the control system 100.
  • the reference signal of the slave CPU module 122b is synchronized with the reference signal of the master CPU module 122a. That is, it is possible to synchronize execution programs (applications) that operate on the CPU modules 122.
  • FIG. 7 is a time chart for explaining data transmission / reception in the CPU module 122.
  • three CPU modules (CPU module A, CPU module B, and CPU module C in FIG. 7) are listed as the plurality of CPU modules 122.
  • the synchronization correction processing has already been completed, and the three CPU modules A, B, and C are synchronized.
  • the number of CPU modules is not limited to three.
  • the application execution unit 188 periodically operates in synchronization with the reference signal. Specifically, the execution of the execution program is started at the timing when the reference signal generation unit 158 generates the reference signal, that is, the count value of the reference signal generation unit 158 is reset to 0, and the data ( The detection result of the sensor, the control result, etc.) are latched (held).
  • the execution program is started when the count value is 0 here, the processing may be started after a predetermined time in consideration of the overhead of management function processing prior to the execution program.
  • the application execution unit 188 inputs the latched data via the input / output module 126 and performs a predetermined calculation based on the execution program. Then, the common memory 166 in the CPU module A is updated with data (status information, sensor detection result, control result, etc.) to which the calculated control result is added. When the predetermined calculation is completed, abnormality monitoring of the programmable controller 120, system control processing, and the like are executed until the next reference signal.
  • the data update unit 190 refers to the count value of the reference signal generation unit 158 and measures the transmission timing assigned to the CPU module A in advance (here, 0). When the transmission timing arrives, the data update unit 190 transmits the data stored in the common memory 166 to the other CPU modules B and C, and updates the common memory 166 in the CPU modules B and C.
  • CPU modules A, B, and C are assigned different transmission timings.
  • the CPU module A is transferred to the CPU modules B and C
  • the CPU module B is transferred to the CPU modules A and C
  • the CPU module C is transferred to the CPU modules A and B with sufficient time to complete the data transmission.
  • Data is sent in order.
  • the other CPU modules receive the data and reflect the data in each common memory 166.
  • the data update unit 190 is reflected in other CPU modules.
  • the common memory 166 is synchronized in the control system 100. As long as the data of the common memory 166 is updated, the data of other CPU modules may be automatically updated.
  • the data update unit 190 refers to the count value of the reference signal generation unit 158 in each CPU module A, B, C, and sends data to the transmission timing assigned to each CPU module A, B, C. Although it is transmitted, not only the reference signal generation unit 158 but also a separate counter that starts counting according to the reference signal can be used.
  • the controlled device 130 can be easily shared by any CPU module. Can be transplanted to.
  • the data is reflected in the same memory address of the common memory 166 in the CPU module after the change.
  • An environment can be formed.
  • access to the common memory 166 by the data update unit 190 will be described in detail.
  • FIG. 8 is an explanatory diagram for explaining an arrangement change of the controlled device 130.
  • three CPU modules (CPU module A, CPU module B, and CPU module C in FIG. 8) are listed as the plurality of CPU modules 122.
  • the CPU module B when focusing on the CPU module B, as shown in FIG. 8A, the CPU module B is connected to controlled devices D and E corresponding to sensors and a controlled device F corresponding to an electric motor. Yes.
  • the control command OUTf is sent to the controlled device F corresponding to the electric motor based on the detection results INd and INe of the controlled devices D and E corresponding to the sensors.
  • the controlled devices D, E, and F are included in the same control unit, and all belong to the same CPU module B. Therefore, the control command OUTf is generated in the control unit. It's enough. That is, in the CPU module B, the application execution unit 188 acquires sensor detection results INd and INe from the controlled devices D and E via the input / output module 126, generates a control command OUTf from the detection results, The generated control command OUTf may be output to the controlled device F.
  • the arrangement of the controlled devices D and E is changed, and as shown in FIG. 8B, the controlled device F belongs to the CPU module A without changing the controlled device F, and the controlled device E is the CPU module.
  • the controlled device F belongs to the CPU module A without changing the controlled device F
  • the controlled device E is the CPU module.
  • the CPU module B can easily refer to the data of the controlled devices D and E at the same timing as before. it can.
  • FIG. 9 is an explanatory diagram showing a memory map in the common memory 166.
  • common memories 166a, 166b, and 166c are arranged in the CPU modules A, B, and C, respectively.
  • FIG. 8B it is assumed that the controlled device D belongs to the CPU module A, the controlled device F belongs to the CPU module B, and the controlled device E belongs to the CPU module C.
  • the common memory 166 since the common memory 166 is used, as shown in FIG. 9, the sensor detection result INd acquired from the controlled device D in the CPU module A is stored in the common memory 166a of its own CPU module A. At the same time, it is also stored in the common memories 166b and 166c of the other CPU modules B and C. Here, the self data is indicated by a solid line, and the replicated data is indicated by a broken line.
  • the sensor detection result INe acquired from the controlled device E in the CPU module C in the synchronized state is stored in the common memory 166c of its own CPU module C, and the common memory of the other CPU modules A and B. Also stored in 166a, 166b.
  • the application execution unit 188 of the CPU module B reads the sensor detection results INd and INe of the controlled devices D and E from the common memory 166b of the CPU module B, performs a predetermined calculation, and outputs a control command OUTf of the controlled device F. Generate. Then, the application execution unit 188 outputs a control command OUTf to the controlled device F belonging to its own CPU module B via the input / output module 126.
  • FIG. 10 is an explanatory diagram showing an application example of the common memory 166.
  • common memories 166a, 166b, and 166c are arranged in the CPU modules A, B, and C, respectively.
  • the controlled device D belongs to the CPU module A
  • the controlled device F belongs to the CPU module B
  • the controlled device E belongs to the CPU module C.
  • the CPU module B In the common memory 166 shown in FIG. 10, in addition to the sensor detection result INd acquired from the controlled device D in the CPU module A and the sensor detection result INe acquired from the controlled device E in the CPU module C, the CPU module B The control command OUTf output to the controlled device F is also stored. Therefore, the application execution unit 188 of the CPU module B reads the control command OUTf from the common memory 166b of the CPU module B, and directly controls the controlled device F belonging to the CPU module B via the input / output module 126. OUTf may be output.
  • a process of reading the sensor detection results INd and INe of the controlled devices D and E from the common memory 166b of the CPU module B, performing a predetermined calculation, and generating a control command OUTf of the controlled device F May be performed by any apparatus.
  • the processing load can be distributed.
  • FIG. 10 the example which CPU module A performs is given.
  • the data transmission unit 192 manages the data requested to be collected from the management apparatus 110 among the data generated by the application execution unit 188 executing the execution program at the data transmission timing shown in FIG. To device 110.
  • the CPU modules 122 are synchronized with each other, data having the same generation timing is collected in the management device 110.
  • the CPU modules 122 are synchronized with each other, and data can be shared among a plurality of CPU modules 122 via a broadband network. Therefore, it is possible to synchronize the application and information of the controlled device 130 between the control units, improve portability of the controlled device 130 and the like, and improve the control accuracy and stability of the entire control system 100.
  • control system 100 for example, in a system that simultaneously controls a plurality of electric motors at a high speed, such as a steel plant or a paper pulp manufacturing plant such as a rolling system, the electric motors can be synchronized with higher accuracy. As a result, product quality and yield are improved.
  • a program that causes the computer to function as a control system 100, a master programmable controller, a slave programmable controller, and a computer-readable storage medium such as a flexible disk, a magneto-optical disk, a ROM, a CD, a DVD, or a BD that records the program.
  • the program refers to data processing means described in an arbitrary language or description method.
  • each step of the control method of the present specification does not necessarily have to be processed in time series in the order described in the flowchart, and may include processing in parallel or by a subroutine.
  • the present invention can be used in a control system, a master programmable controller, a slave programmable controller, and a control method in which a plurality of programmable controllers that respectively control controlled devices are connected to be communicable with each other.

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PCT/JP2013/050121 2013-01-08 2013-01-08 制御システム、マスタープログラマブルコントローラ、スレーブプログラマブルコントローラ、および、制御方法 WO2014108999A1 (ja)

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PCT/JP2013/050121 WO2014108999A1 (ja) 2013-01-08 2013-01-08 制御システム、マスタープログラマブルコントローラ、スレーブプログラマブルコントローラ、および、制御方法
KR1020157011274A KR101726743B1 (ko) 2013-01-08 2013-01-08 제어 시스템, 마스터 프로그래머블 컨트롤러, 슬레이브 프로그래머블 컨트롤러 및 제어 방법
CN201380062822.6A CN104854523B (zh) 2013-01-08 2013-01-08 控制系统、主可编程控制器、从可编程控制器以及控制方法

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016110458A (ja) * 2014-12-08 2016-06-20 株式会社キーエンス プログラマブル・ロジック・コントローラ、基本ユニット、制御方法およびプログラム
CN110741322A (zh) * 2017-07-07 2020-01-31 欧姆龙株式会社 控制系统以及控制方法
CN110771100A (zh) * 2017-07-07 2020-02-07 欧姆龙株式会社 控制系统以及控制方法
CN112835321A (zh) * 2019-11-25 2021-05-25 富士电机株式会社 可编程控制器系统和模块
JPWO2020026363A1 (ja) * 2018-07-31 2021-07-01 株式会社島津製作所 材料試験機
JP2022028059A (ja) * 2019-03-14 2022-02-14 オムロン株式会社 制御システム
CN116685914A (zh) * 2021-06-08 2023-09-01 三菱电机株式会社 可编程逻辑控制器、动态图像管理装置、动态图像管理系统、动态图像管理方法以及程序

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108353368A (zh) * 2015-11-11 2018-07-31 华为技术有限公司 同步的方法与设备
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02179221A (ja) * 1988-12-28 1990-07-12 Meidensha Corp ループ状ディジタル保護継電装置のサンプリング同期システム
JPH04135210A (ja) * 1990-09-27 1992-05-08 Fanuc Ltd 同期信号発生装置
JP2001075932A (ja) * 1999-09-08 2001-03-23 Canon Inc ライン制御装置、ライン制御方法及びラインシステム
JP2007226492A (ja) * 2006-02-23 2007-09-06 Yaskawa Electric Corp モーションコントロールシステム
JP2009157913A (ja) * 2007-12-07 2009-07-16 Omron Corp 産業用コントローラ

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4337543B2 (ja) * 2003-12-22 2009-09-30 三菱電機株式会社 通信状態監視装置
CN100595707C (zh) * 2008-08-29 2010-03-24 华中科技大学 一种数控机床双轴同步控制装置
JP5262674B2 (ja) * 2008-12-18 2013-08-14 富士通株式会社 遅延測定方法および通信装置
JP5411835B2 (ja) 2010-11-17 2014-02-12 株式会社日立製作所 プログラマブルコントローラ、および、通信制御方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02179221A (ja) * 1988-12-28 1990-07-12 Meidensha Corp ループ状ディジタル保護継電装置のサンプリング同期システム
JPH04135210A (ja) * 1990-09-27 1992-05-08 Fanuc Ltd 同期信号発生装置
JP2001075932A (ja) * 1999-09-08 2001-03-23 Canon Inc ライン制御装置、ライン制御方法及びラインシステム
JP2007226492A (ja) * 2006-02-23 2007-09-06 Yaskawa Electric Corp モーションコントロールシステム
JP2009157913A (ja) * 2007-12-07 2009-07-16 Omron Corp 産業用コントローラ

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016110458A (ja) * 2014-12-08 2016-06-20 株式会社キーエンス プログラマブル・ロジック・コントローラ、基本ユニット、制御方法およびプログラム
CN110741322B (zh) * 2017-07-07 2022-08-12 欧姆龙株式会社 控制系统以及控制方法
CN110741322A (zh) * 2017-07-07 2020-01-31 欧姆龙株式会社 控制系统以及控制方法
CN110771100A (zh) * 2017-07-07 2020-02-07 欧姆龙株式会社 控制系统以及控制方法
JPWO2020026363A1 (ja) * 2018-07-31 2021-07-01 株式会社島津製作所 材料試験機
JP7021703B2 (ja) 2018-07-31 2022-02-17 株式会社島津製作所 材料試験機
JP7359199B2 (ja) 2019-03-14 2023-10-11 オムロン株式会社 制御システムにおいて実施される方法
JP2022028059A (ja) * 2019-03-14 2022-02-14 オムロン株式会社 制御システム
CN112835321A (zh) * 2019-11-25 2021-05-25 富士电机株式会社 可编程控制器系统和模块
JP2021086211A (ja) * 2019-11-25 2021-06-03 富士電機株式会社 プログラマブルコントローラシステムおよびモジュール
JP7439474B2 (ja) 2019-11-25 2024-02-28 富士電機株式会社 プログラマブルコントローラシステムおよびモジュール
CN112835321B (zh) * 2019-11-25 2024-05-14 富士电机株式会社 可编程控制器系统和模块
CN116685914A (zh) * 2021-06-08 2023-09-01 三菱电机株式会社 可编程逻辑控制器、动态图像管理装置、动态图像管理系统、动态图像管理方法以及程序

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