WO2014106429A1

WO2014106429A1 - Sata speed auto-negotiation method and device based on third-party phy

Info

Publication number: WO2014106429A1
Application number: PCT/CN2013/089739
Authority: WO
Inventors: 丁强; 赵远鸿; 张帆
Original assignee: 中兴通讯股份有限公司
Priority date: 2013-01-04
Filing date: 2013-12-17
Publication date: 2014-07-10
Also published as: CN103914420A; CN103914420B

Abstract

Disclosed are an SATA speed auto-negotiation method and device based on a third-party PHY and a computer storage medium. The method comprises: receiving parallel data recovered by a PHY, and performing byte alignment on the parallel data according to K codes; detecting whether the aligned parallel data contain OOB signals; when the aligned parallel data contain OOB signals, sending the OOB signals to an SATA controller; and after the SATA controller identifies the OOB signals, receiving speed selection signals sent by the SATA controller, and sending the speed selection signals to the PHY.

Description

SATA speed auto-negotiation method and device based on 笫 three-way PHY

The present invention relates to the field of computer technologies, and in particular, to a SATA (Serial Advanced Technology Attachment) speed auto-negotiation method and apparatus based on a third-party physical layer protocol (PHY). Background technique

The SATA controller has the detection capability of the OOB (Out Of Band) signal for the PHY, and can complete the entire hardware initialization according to the timing of the OOB signal, and the hardware initialization must be performed at the rate of the first generation (Genl, Generationl). After the initialization at Genl rate, for the second generation (Gen2, Generation) and above SATA controllers, it is required to complete the rate switching from Genl to Gen2, so that the controller can enter the higher rate mode that can be supported.

The parallel data recovered by the PHY usually has a 50% probability of byte shifting, that is, the data is not aligned. For the SATA controller, the byte shift of the OOB signal may cause the OOB signal detection to fail, or The controller internally detects the OOB signal only with low or high level detection, and the rate negotiation signal does not match. This may cause the controller to fail to enter low power consumption when switching the low power mode. Summary of the invention

To solve the existing technical problems, the present invention provides a SATA speed auto-negotiation method and apparatus based on a third-party PHY.

To achieve the above objective, the technical solution of the embodiment of the present invention is implemented as follows:

The embodiment of the invention provides a SATA speed auto-negotiation method based on a third-party PHY. include:

Receiving parallel data recovered by the PHY, and performing byte alignment on the parallel data;

Detecting whether the aligned parallel data includes an OOB signal;

When the aligned parallel data contains an OOB signal, the OOB signal is sent to the SATA controller;

After the SATA controller recognizes the OOB signal, it receives a speed selection signal sent by the SATA controller, and sends the speed selection signal to the PHY.

Receiving parallel data recovered by the PHY, and performing byte alignment on the parallel data includes: determining whether the SATA controller can detect a lower K code in the parallel data; if the K code is at a high level, switching to a word The logic of the section shift splicing the upper bits of the parallel data and the lower bits of the next data.

Receiving the parallel data recovered by the PHY, and performing byte alignment on the parallel data includes: taking the first eight bits of data of the start end of the parallel data, and determining whether the first eight bits of data are K codes;

If the first eight bits of data are K codes, combine the upper seven bits of the first eight bits of data with the lower one bit of the next parallel data to form new eight bits of data, and determine the new one again. Whether the eight-bit data is the K code; cyclically executing until the K code is detected; and the data after detecting the K code continues to fetch and detect the parallel data in groups of eight bits until Align each byte of the parallel data.

Before the sending the OOB signal to the SATA controller, the method further includes: initializing the OOB signal, and shaking hands with the SATA controller;

After the handshake is successful, when the OOB signal is received again, the low power state is switched to the normal working state.

Receiving the speed selection signal sent by the SATA controller, and sending the speed selection signal to the PHY includes: Receiving a speed selection signal sent by the SATA controller;

When there is a frequency-divided signal matching the speed selection signal in the PHY, the speed selection signal is directly transmitted to the PHY.

The method further includes:

When there is no frequency-divided signal matching the speed selection signal in the PHY, the speed selection signal is processed into a speed configuration signal that matches the PHY frequency-divided signal.

The embodiment of the invention further provides a SATA speed auto-negotiation device based on a third-party PHY, including:

a data alignment module configured to receive parallel data recovered by the PHY, and byte aligned the parallel data;

a logic detection module, configured to detect whether the aligned parallel data includes an out-of-band data OOB signal; when the aligned parallel data includes an OOB signal, send the OOB signal to a SATA controller;

And a rate reconfiguration module configured to: after the SATA controller recognizes the OOB signal, receive a speed selection signal sent by the SATA controller, and send the speed selection signal to the PHY.

The data alignment module is further configured to:

Determining whether the SATA controller is capable of detecting a K code or a D code in the parallel data; if the K code is at a high level, switching to a byte shift logic, lowering a high bit of the parallel data and a lower bit of a next data Splicing.

The data alignment module is further configured to:

Taking the first eight bits of data of the parallel data start end, and determining whether the first eight bits of data are K codes;

If the first eight bits of data are K codes, combining the upper seven bits of the first eight bits of data with the lower one bit of the next parallel data to form new eight bits of data, again determining Whether the new eight-bit data is the K code; cyclically executing until the weight is detected; and the data after detecting the weight continues to fetch the parallel data in groups of eight bits And detecting until the bytes of the parallel data are aligned.

The logic detection module is further configured to:

Initializing the chirp signal, and shaking hands with the SATA controller;

After the handshake is successful, when the chirp signal is received again, the low power state is switched to the normal working state.

The rate reconfiguration module is further configured to:

Receiving a speed selection signal sent by the SATA controller, and when there is a frequency-divided signal matching the speed selection signal, the speed selection signal is directly sent to the ΡΗΥ;

When there is no frequency-divided signal matching the speed selection signal in the ΡΗΥ, the speed selection signal is processed into a speed configuration signal that matches the ΡΗΥ frequency-divided signal.

The embodiment of the invention further provides a computer storage medium, the computer storage medium comprising a set of instructions, when executing the instruction, causing at least one processor to perform the third-party-based SATA speed auto-negotiation method.

The embodiment of the present invention performs byte alignment on the parallel data by receiving parallel data recovered by the PHY; detecting whether the aligned parallel data contains an OOB signal; if yes, sending the OOB signal to the SATA controller; After the SATA controller recognizes the OOB signal, receiving a speed selection signal sent by the SATA controller, and transmitting the speed selection signal to the PHY, having parallel data for restoring misalignment and enabling The successful completion of the PHY rate switching has effectively solved the problem of connection failure caused by data misalignment or failure of low power mode switching. DRAWINGS

In the drawings, which are not necessarily to scale, like reference numerals may Similar parts are described in the view. Like reference numerals with different letter suffixes may indicate different examples of similar components. The drawings generally illustrate the various embodiments discussed herein by way of example and not limitation.

1 is a schematic flow chart of an embodiment of a SATA speed auto-negotiation method based on a third-party PHY according to the present invention;

2 is a schematic structural diagram of an embodiment of a SATA speed auto-negotiation apparatus based on a third-party PHY according to the present invention;

3 is a schematic diagram showing the internal structure of a SATA speed auto-negotiation device based on an Altera PHY according to the present invention.

The implementation, functional features and advantages of the objects of the present invention will be further described in conjunction with the embodiments herein. detailed description

The technical solutions of the present invention are further described below in conjunction with the drawings and specific embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Referring to FIG. 1, FIG. 1 is a schematic flowchart of a third-party PHY-based SATA speed auto-negotiation method according to an embodiment of the present invention. As shown in FIG. 1, the SATA speed auto-negotiation method based on a third-party PHY in the embodiment of the present invention includes the following steps:

Step S01: Receive parallel data recovered by the PHY, and perform byte alignment on the parallel data. Here, when the PHY recovers the parallel data of the received SATA controller, data misalignment usually occurs.

When there is a high or low misalignment in the parallel data, the position of the K code and the D code will be placed in the high or low position that the SATA controller cannot recognize, so whether the SATA controller can detect the K code or the D code in the parallel data. Determining whether there is a high or low misalignment in the parallel data;

Specifically, if the SATA controller cannot detect the low-order K code in the parallel data, that is, if the SATA controller detects When it is detected that the K code is at the high level, it switches to the byte shift logic, and splicing the parallel data, that is, the upper bits of the current data and the lower bits of the next data. For example, the align primitives in the recovered ΟΟΒ signal should be: 4abc, 7b4a, 4abc, 7b4a, 4abc, 7b4a, and the PHY recovered parallel data appears: bc7b, 4a4a, bc7b, The data of 4a4a and bc7b indicates that the parallel data recovered by the PHY appears to be combined with the lower eight bits of the previous data and the upper eight bits of the latter data into new data when aligned, which results in all the subsequent align data. The above-mentioned misalignment occurs in the data. For parallel data with only high and low bits, it is only necessary to combine the lower bits of the previous data with the high bits of the latter data to form new parallel data, and put the K code or D code in the appropriate position;

For the relatively disordered bit-unaligned data, the alignment is adopted: taking the first eight bits of data of the parallel data start end, determining whether the first eight bits of data are K codes; if not, then the first eight Combining the upper seven bits of data in the bit data with the lower one bit data of the next parallel data to form new eight bits of data, again determining whether the new eight bit data is the K code; performing the loop until the detected Said K code; the data after detecting the K code is continued to fetch and detect the parallel data in groups of eight bits until the respective bytes of the parallel data are aligned.

For example, the data is recursively detected according to the bit (bit), and the first 8 bits of data are taken to determine whether it is a K code. If it is not a K code, the upper 7 bits of the number are combined with the next bit to form a new one. The 8 bit data, again determine whether it is a K code, and so on, until the K code appears, indicating that the edge of the byte is detected, and the subsequent data continues to be detected according to the 8-bit fetch; if non-alignment occurs, then follow this The rules are processed to ensure byte alignment of the parallel data.

Step S02, detecting whether the aligned parallel data contains an OOB signal; if yes, executing step S03; if not, returning to step S02;

Step S03: Send the OOB signal to the SATA controller.

Here, it is detected whether the aligned parallel data contains the OOB signal; if not, then continue to check If yes, the OOB signal is initialized, and the SATA controller is handshaked; after the handshake is successful, when the OOB signal is received again, the low power consumption state is switched to the normal working state.

For example, when it is detected that the aligned parallel data contains the OOB signal, the K28.5 code is extracted from the OOB signal as the COMMA signal output of the SATA controller; since the OOB signal is the K code series, if it is the OOB signal, A regular pulse signal according to the SATA protocol is generated, and after the pulse signal is transmitted to the SATA controller, it can be recognized as an OOB signal by the SATA controller.

For the SATA controller, the valid signal in the parallel data is meaningless at the beginning of the OOB signal initialization. At this time, the valid signal in the parallel data and the SATA controller are only handshaking, and the handshake is successful, and The valid OOB signal is used after the OOB signal is initialized. Therefore, the final stage of the OOB signal is detected. When the D10.2 is detected, the data after the aligned parallel data is always valid. of. At low power consumption, the OOB signal interaction is to shake hands with the SATA controller; after the handshake is successful, when the OOB signal appears again, the low power state is switched to the normal working state. In normal operation, the OOB signal is sent to the SATA controller.

Step S04: After identifying the OOB signal, the SATA controller receives a speed selection signal sent by the SATA controller, and sends the speed selection signal to the PHY.

Here, since the OOB signal is a K code series, if it is an OOB signal, a regular pulse signal according to the SATA protocol is generated, and after the pulse signal is transmitted to the SATA controller, it can be recognized as an OOB signal by the SATA controller; The SATA controller selects a signal according to the speed of the OOB signal, and when there is a frequency-divided signal matching the speed selection signal in the PHY, directly transmitting the speed selection signal to the PHY; when the PHY When there is no frequency-divided signal matching the speed selection signal, the speed selection signal is processed into a speed configuration signal that matches the PHY frequency-divided signal.

Wherein, the PHY needs to match the speed of the SATA controller according to the speed selection signal sent by the SATA controller, and the SATA controller issues a speed level negotiated with the PHY, and selects a signal with the speed. Indicated to the PHY. For example, for a SATA controller that supports only Gen2 at the highest speed, the speed selection signal is lbit, output 0 indicates that the PHY is required to operate in the Genl speed mode, and output 1 indicates that the PHY is required to operate in the Gen2 speed mode; The rate reconfiguration module corresponding to the reconfiguration step in the SATA speed auto-negotiation method of the third-party PHY reconfigures the internal frequency division coefficient, and processes the speed selection signal of the SATA controller as the corresponding reconfiguration module of the PHY. Input, reconfigures the internal partial frequency of the PHY to match the rate required by the SATA controller.

In this embodiment, the parallel data is received by the PHY, and the parallel data is byte aligned; detecting whether the aligned parallel data includes an OOB signal; if yes, sending the OOB signal to the SATA controller; After the SATA controller recognizes the OOB signal, receiving a speed selection signal sent by the SATA controller, and transmitting the speed selection signal to the PHY, has parallel data that can be restored and misaligned The beneficial effects of PHY rate switching are completed, which effectively solves the problem of connection failure caused by data misalignment or failure of low power mode switching.

Referring to FIG. 2, FIG. 2 is a schematic structural diagram of an SATA speed auto-negotiation apparatus based on a third-party PHY according to the present invention. As shown in FIG. 2, the SATA speed auto-negotiation apparatus based on the third-party PHY in the embodiment of the present invention includes: a data alignment module. 01. Logic detection module 02 and rate reconfiguration module 03.

Referring to FIG. 3, FIG. 3 is a schematic diagram showing the internal structure of a SATA speed auto-negotiation device based on a third-party PHY according to an embodiment of the present invention. Referring to FIG. 2 and FIG. 3 together, the method for the SATA speed auto-negotiation device based on the third-party PHY is: performing byte alignment on the parallel data by receiving parallel data recovered by the PHY; detecting the aligned Whether the parallel data includes an out-of-band data OOB signal; if yes, sending the OOB signal to a SATA controller; after the SATA controller identifies the OOB signal, receiving a speed selection sent by the SATA controller signal, And transmitting the speed selection signal to the PHY. Here, the signal sent by the SATA speed auto-negotiation device of the third-party PHY to the SATA controller may include: a received data signal, an OOB detection indication signal, a K-code detection signal, and a received data valid signal.

The operation of the data alignment module 01, the logic detection module 02, and the rate reconfiguration module 03 in the SATA speed auto-negotiation device based on the third-party PHY will be further described below.

The data alignment module 01 is configured to receive parallel data recovered by the PHY, and byte aligned the parallel data.

Here, when the PHY recovers the parallel data of the received SATA controller, data misalignment usually occurs.

When there is a high or low misalignment in the parallel data, the position of the K code and the D code are placed in the high or low position that the SATA controller cannot recognize, so the data alignment module 01 can detect the K code in the parallel data according to the SATA controller. Or the D code to determine whether there is a high or low misalignment in the parallel data;

Specifically, if the SATA controller does not detect the lower K code in the parallel data, that is, if it detects that the K code is at the high level, the data alignment module 01 switches to the byte shift logic, and the parallel data is the current data. The high bit is spliced with the lower bits of the next data. For example, the consecutive align primitives in the OOB signal recovered from the PHY should be: 4abc, 7b4a, 4abc, 7b4a, 4abc, 7b4a, and the parallel data of the PHY recovery appears: bc7b, 4a4a, bc7b, 4a4a, bc7b The data indicates that the parallel data recovered by the PHY appears in the alignment when the lower eight bits of the previous data and the upper eight bits of the latter data are combined into new data, which causes all the data following the continuous align data to appear. The above dislocation phenomenon. For parallel data with only high and low bits, the data alignment module 01 only needs to combine the lower bits of the previous data with the upper bits of the latter data to form new parallel data, and place the K code or D code in the appropriate position; For the relatively disordered bit-unaligned data, the data alignment module 01 adopts an alignment manner: taking the first eight bits of data of the parallel data start end, and determining that the first eight bits of data are N is a K code; if not, combining the upper seven bits of the first eight bits of data with the lower one bit of the next parallel data to form new eight bits of data, again determining the new eight bits of data Whether it is the weight; cyclically executing until the weight is detected; and the data after detecting the weight continues to fetch and detect the parallel data in groups of eight bits until the Alignment of each byte of parallel data.

For example, the data alignment module 01 performs recursive detection on the data according to the bit, and takes the first 8 bits of data at the beginning to determine whether it is a K code. If it is not a K code, the upper 7 bits of the number are combined with the next bit to form The new 8-bit data, again judge whether it is a K code, and so on, until the K code appears, it means that the edge of the byte is detected, and the subsequent data continues to be detected according to the 8-bit fetch; if non-alignment occurs, then follow This rule is processed to ensure byte alignment of parallel data.

The logic detection module 02 is configured to detect whether the aligned parallel data includes an OOB signal; if yes, send the OOB signal to the SATA controller.

Here, the logic detecting module 02 detects whether the parallel data of the data alignment module 01 is aligned with the OOB signal; if not, continues to detect; if yes, initializes the OOB signal, and performs handshake with the SATA controller; after the handshake is successful When the OOB signal is received again, the low power consumption state is switched to the normal working state.

For example, when the logic detection module 02 detects that the aligned parallel data contains the OOB signal, the K28.5 code is extracted from the OOB signal as the COMMA signal output of the SATA controller; since the OOB signal is the K code series, if it is OOB The signal, there will be a regular pulse signal according to the SATA protocol. After transmitting the pulse signal to the SATA controller, it can be recognized by the SATA controller as an OOB signal.

For the SATA controller, the valid signal in the parallel data is meaningless at the beginning of the OOB signal initialization. At this time, the valid signal in the parallel data and the SATA controller are only handshaking, and the handshake is successful and A valid OOB is used after the OOB signal is initialized. The signal, in this way, the logic detection module 02 detects the final stage D10.2 of the OOB signal. When D10.2 is detected, the data following the aligned parallel data is always valid. At low power consumption, the logic detection module 02 performs OOB signal interaction for handshake with the SATA controller. After the handshake is successful, when the OOB signal occurs again, the logic detection module 02 switches the low power consumption state to the normal working state. In normal operation, the logic detection module 02 sends an OOB signal to the SATA controller.

The rate reconfiguration module 03 is configured to receive a speed selection signal sent by the SATA controller after the SATA controller recognizes the OOB signal, and send the speed selection signal to the PHY.

Here, since the OOB signal is a K code series, if it is an OOB signal, a regular pulse signal according to the SATA protocol will appear, and the rate reconfiguration module 03 can transmit the pulse signal to the SATA controller, and then can be recognized by the SATA controller. An OOB signal; the rate reconfiguration module 03 receives a speed selection signal sent by the SATA controller according to the OOB signal, and when the frequency division signal matching the speed selection signal exists in the PHY, directly adopting the speed selection signal Transmitting to the PHY; when there is no frequency-divided signal matching the speed selection signal in the PHY, processing the speed selection signal into a speed configuration signal matching the PHY frequency-divided signal.

The PHY needs to match the speed of the SATA controller according to the speed selection signal sent by the SATA controller. The SATA controller issues a speed level negotiated with the PHY and indicates to the PHY with a speed selection signal. For example, for a SATA controller that supports only Gen2 at the highest speed, the speed selection signal is lbit, output 0 indicates that the PHY is required to operate in the Genl speed mode, output 1 indicates that the PHY is required to operate in the Gen2 speed mode, and the PHY needs to pass the rate reconfiguration module. 03 to reconfigure the internal frequency division coefficient; the rate reconfiguration module 03 processes the speed selection signal of the SATA controller, and transmits the processed speed selection signal to the PHY; the PHY selects the signal according to the speed to the PHY. The internal partial frequency is reconfigured to achieve a rate that matches the SATA controller requirements.

In actual application, the data alignment module 01, the logic detection module 02, and the rate reconfiguration module 03 can It is implemented by a central processing unit (CPU) in a SATA speed auto-negotiation device based on a third-party PHY, a digital signal processor (DSP), or a Field-Programmable Gate Array (FPGA). .

In this embodiment, the parallel data is received by the PHY, and the parallel data is byte aligned; detecting whether the aligned parallel data includes an OOB signal; if yes, sending the OOB signal to the SATA controller; After the SATA controller recognizes the OOB signal, receiving a speed selection signal sent by the SATA controller, and transmitting the speed selection signal to the PHY, having parallel data for restoring misalignment and successfully completing the PHY The beneficial effect of rate switching effectively solves the problem of connection failure caused by data misalignment or failure of low power mode switching.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware aspects. Moreover, the invention can take the form of a computer program product embodied on one or more computer usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart and/or block diagrams, and combinations of flow and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that stored in the computer readable memory The instructions in the reservoir produce an article of manufacture comprising an instruction device that implements the functions specified in one or more blocks of the flow or in a flow or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patents. The equivalent structure or equivalent process transformations made by the description of the present invention and the drawings are directly or indirectly applied to other related technical fields. The same is included in the scope of patent protection of the present invention.

Claims

claims

1. A serial advanced technology accessory SATA speed auto-negotiation method based on third-party physical layer PHY, including:

Receive the parallel data recovered by the PHY, and perform byte alignment on the parallel data;

Detect whether the aligned parallel data contains an out-of-band data OOB signal;

When the aligned parallel data contains an OOB signal, send the OOB signal to the SATA controller;

After the SATA controller recognizes the OOB signal, it receives the speed selection signal sent by the SATA controller, and sends the speed selection signal to the PHY.

2. The method of claim 1, wherein receiving the parallel data recovered by the PHY and performing byte alignment on the parallel data includes:

Determine whether the SATA controller can detect the low-bit K code in the parallel data; if the K code is in the high-bit, switch to the byte shift logic, and perform the operation between the high-bit of the parallel data and the low-bit of the next data. splicing.

3. The method of claim 1, wherein receiving the parallel data recovered by the PHY and performing byte alignment on the parallel data includes:

Get the first eight bits of data at the starting end of the parallel data and determine whether the first eight bits of data are K codes;

If the first eight bits of data are K codes, combine the upper seven bits of data in the first eight bits of data with the lower one bit of data of the next parallel data to form new eight bits of data, and determine the new bits of data again. Whether the eight-bit data is the K code; execute in a loop until the K code is detected; continue to count and detect the parallel data according to a group of eight bits after the K code is detected, until Align each byte of the parallel data.

4. The method of claim 1, wherein before sending the OOB signal to the SATA controller, the method further includes: Initialize the OOB signal and perform handshake with the SATA controller;

After the handshake is successful, when the OOB signal is received again, the low power consumption state is switched to the normal working state.

5. The method of claim 1, wherein receiving the speed selection signal sent by the SATA controller and sending the speed selection signal to the PHY includes:

Receive the speed selection signal sent by the SATA controller;

When there is a frequency division signal matching the speed selection signal in the PHY, the speed selection signal is directly sent to the PHY.

6. The method of claim 5, wherein the method further includes:

When there is no frequency division signal matching the speed selection signal in the PHY, the speed selection signal is processed into a speed configuration signal matching the frequency division signal of the PHY.

7. A SATA speed auto-negotiation device based on a third-party PHY, including:

A data alignment module configured to receive parallel data recovered by the PHY and perform byte alignment on the parallel data;

A logic detection module configured to detect whether the aligned parallel data contains an out-of-band data OOB signal; when the aligned parallel data contains an OOB signal, send the OOB signal to the SATA controller;

A rate reconfiguration module configured to receive a speed selection signal sent by the SATA controller after the SATA controller recognizes the OOB signal, and send the speed selection signal to the PHY.

8. The device of claim 7, wherein the data alignment module is further configured to: determine whether the SATA controller can detect the K code in the parallel data; if the K code is in a high position, switch to The byte shift logic splices the high bits of the parallel data and the low bits of the next data.

9. The device of claim 7, wherein the data alignment module is further configured to: Get the first eight bits of data from the starting end of the parallel data and determine whether the first eight bits of data are K codes;

If the first eight bits of data are K codes, combine the upper seven bits of data in the first eight bits of data with the lower one bit of data in the next parallel data to form new eight bits of data, and determine the new bits of data again. Whether the eight-bit data is the K code; execute in a loop until the K code is detected; continue to count and detect the parallel data according to a group of eight bits after the K code is detected, until Align each byte of the parallel data.

10. The device of claim 7, wherein the logic detection module is further configured to: initialize the OOB signal and perform handshake with the SATA controller;

11. The device of claim 7, wherein the rate reconfiguration module is further configured to: receive a speed selection signal sent by the SATA controller, when there is a speed selection signal in the PHY that matches the speed selection signal. When dividing the frequency signal, directly send the speed selection signal to the PHY;

12. A computer storage medium, the computer storage medium includes a set of instructions, which when executed, cause at least one processor to execute the third-party PHY-based method according to any one of claims 1 to 6. SATA speed auto-negotiation method.