CN103914420B - SATA speed auto-negotiation method based on third party PHY and device - Google Patents
SATA speed auto-negotiation method based on third party PHY and device Download PDFInfo
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- CN103914420B CN103914420B CN201310001430.0A CN201310001430A CN103914420B CN 103914420 B CN103914420 B CN 103914420B CN 201310001430 A CN201310001430 A CN 201310001430A CN 103914420 B CN103914420 B CN 103914420B
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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Abstract
The present invention discloses a kind of SATA speed auto-negotiation method based on third party PHY and device, and the method comprises the following steps: receives the parallel data that PHY recovers, according to K code, parallel data is carried out byte-aligned；Whether the parallel data after detection alignment contains OOB signal；The most then OOB indication signal sig_det is sent to SATA controller；At SATA controller identification OOB signal, and after completing COMRESET, COMINIT, COMWAKE process of initial phase, SATA controller transmission speed selects signal, and after speed is heavily joined, the rate selection signal after heavily joining sends to PHY；There is the beneficial effect that the parallel data recovering dislocation carries out aliging and can smoothly completing the switching of PHY speed, efficiently solve connection failure or the problem of low-power consumption mode handoff failure that data non-alignment causes.
Description
Technical field
The present invention relates to field of computer technology, particularly relate to a kind of SATA speed auto-negotiation side based on third party PHY
Method and device.
Background technology
SATA(Serial Advanced Technology Attachment, Serial Advanced Technology Attachment) controller pair
In PHY(Physical Layer, PHY) there is OOB(out of band, out of band data) power of test of signal,
And whole hardware initialization can be completed according to the sequential of OOB, hardware initialization must at Gen1(Generation1, one
Generation) speed under carry out, after completing the initialization under Gen1 speed, for secondary above SATA controller, it is desirable to can be complete
Become from Gen1 to Gen2(Generation2, secondary) speed switching, in order to controller can enter can be supported by more at a high speed
Rate MODE of operation.
The parallel data that PHY recovers, it will usually the situation of byte shift, i.e. data do not have to have the probability of 50% to occur
Alignment, and for SATA, the byte shift of OOB signal may cause the failure of OOB signal detection, or controller is internal right
The detection of OOB signal has only carried out low level or high-order detection, it may appear that the unmatched situation of rate consulation signal, the most also may be used
Controller can be caused to cannot be introduced into low-power consumption switching low-power consumption mode when.
Summary of the invention
The main object of the present invention is to provide a kind of SATA speed auto-negotiation method based on third party PHY and device, purport
The byte non-alignment occurred in data transmission between solution SATA and PHY and the unmatched problem of speed negotiation signal.
The embodiment of the invention discloses a kind of SATA speed auto-negotiation method based on third party PHY, comprise the following steps:
Receive the parallel data that physical layer PHY is recovered, described parallel data is carried out byte-aligned；
Whether the described parallel data after detection alignment contains out of band data OOB signal；
The most described OOB signal is sent to Serial Advanced Technology Attachment SATA controller；
After OOB signal described in described SATA controller identification, receive the speed selection letter that described SATA controller sends
Number, and described rate selection signal is sent to described PHY.
Preferably, the parallel data that described reception PHY recovers, described parallel data is carried out byte-aligned and includes:
Judge whether described SATA controller is able to detect that the K code of low level in described parallel data；
If K code is in a high position, then switch to the logic of byte shift, by a high position for current data and the low level of next data
Splice.
Preferably, the parallel data that described reception PHY recovers, described parallel data is carried out byte-aligned and includes:
Take described the first eight Bit data of parallel data initiating terminal, it is judged that whether the first eight Bit data described is K code；
If it is not, then by seven bit data high in described eight Bit datas and a low Bit data phase of next parallel data
In conjunction with, form eight new Bit datas, again judge whether described eight new Bit datas are described K code；Circulation performs, until
Described K code detected；
Data after described K code being detected are that described parallel data is peeked also by one group of continuation according to eight bits
Detection, until by each byte-aligned of described parallel data.
Preferably, described transmission by described OOB signal also included before the step of SATA controller:
Initialize described OOB signal, shake hands with described SATA controller；
After shaking hands successfully, when again receiving described OOB signal, switching low power consumpting state is to normal operating conditions.
Preferably, the rate selection signal that the described SATA controller of described reception sends, and by described rate selection signal
Send extremely described PHY to include:
Receive the rate selection signal that described SATA controller sends, exist in described PHY and select letter with described speed
During number fractional frequency signal matched, directly described rate selection signal is sent to described PHY；
When there is not the fractional frequency signal matched with described rate selection signal in described PHY, described speed is selected
Signal processing becomes with described PHY fractional frequency signal to the speed configuration signal mated.
The embodiment of the invention also discloses a kind of SATA speed auto-negotiation device based on third party PHY, including:
Alignment of data module, for receiving the parallel data that PHY recovers, carries out byte-aligned to described parallel data；
Whether logic detection module, contain out of band data OOB signal in the described parallel data after detecting alignment；If
It is then described OOB signal to be sent to SATA controller；
Speed heavily joins module, for after OOB signal described in described SATA controller identification, receives described SATA controller
The rate selection signal sent, and described rate selection signal is sent to described PHY.
Preferably, described alignment of data module is additionally operable to:
Judge K code or D code that whether described SATA controller be able to detect that in described parallel data；
If K code is in a high position, then switch to byte shift logic, the low level of a high position for current data and next data is entered
Row splicing.
Preferably, described alignment of data module is additionally operable to:
Take described the first eight Bit data of parallel data initiating terminal, it is judged that whether the first eight Bit data described is K code；
If it is not, then by seven bit data high in described eight Bit datas and a low Bit data phase of next parallel data
In conjunction with, form eight new Bit datas, again judge whether described eight new Bit datas are described K code；Circulation performs, until
Described K code detected；
Data after described K code being detected are that described parallel data is peeked also by one group of continuation according to eight bits
Detection, until by each byte-aligned of described parallel data.
Preferably, described logic detection module is additionally operable to:
Initialize described OOB signal, shake hands with described SATA controller；
After shaking hands successfully, when again receiving described OOB signal, switching low power consumpting state is to normal operating conditions.
Preferably, described speed is heavily joined module and is additionally operable to:
Receive the rate selection signal that described SATA controller sends, exist in described PHY and select letter with described speed
During number fractional frequency signal matched, directly described rate selection signal is sent to described PHY；
When there is not the fractional frequency signal matched with described rate selection signal in described PHY, described speed is selected
Signal processing becomes with described PHY fractional frequency signal to the speed configuration signal mated.
The present invention, by receiving the parallel data that PHY recovers, carries out byte-aligned to described parallel data；After detection alignment
Described parallel data in whether contain out of band data OOB signal；The most described OOB signal is sent to SATA controller；
After OOB signal described in described SATA controller identification, receive the rate selection signal that described SATA controller sends, and by institute
State rate selection signal to send to the method for described PHY, have and carry out the parallel data recovering dislocation aliging and can be smooth
Complete the beneficial effect of PHY speed switching, efficiently solve connection failure that data non-alignment causes or low-power consumption mode is cut
The problem changing failure.
Accompanying drawing explanation
Fig. 1 is present invention SATA based on third party PHY speed auto-negotiation method one embodiment schematic flow sheet；
Fig. 2 is present invention SATA based on third party PHY speed auto-negotiation device one example structure schematic diagram；
Fig. 3 is present invention SATA based on Altera PHY speed auto-negotiation device internal structure schematic diagram.
The realization of the object of the invention, functional characteristics and advantage will in conjunction with the embodiments, are described further referring to the drawings.
Detailed description of the invention
Technical scheme is further illustrated below in conjunction with Figure of description and specific embodiment.Should be appreciated that this
Specific embodiment described by place only in order to explain the present invention, is not intended to limit the present invention.
It is the signal of present invention SATA based on third party PHY speed auto-negotiation method one embodiment flow process with reference to Fig. 1, Fig. 1
Figure；As it is shown in figure 1, present invention SATA based on third party PHY speed auto-negotiation method comprises the following steps:
The parallel data that step S01, reception PHY recover, carries out byte-aligned to described parallel data；
When the parallel data of the SATA controller of reception is recovered by PHY, it will usually the situation that data misplace occurs.
When there is the situation of high infraversion malposition in parallel data, the position of K code and D code can be placed on SATA controller cannot know
An other high position or low level, whether the K code or the D code that are able to detect that in parallel data according to SATA controller judge parallel data
In whether there is the situation of high infraversion malposition；If SATA controller can't detect the K code of low level in parallel data, even detect
K code in a high position, then switches to byte shift logic, by the high position in described parallel data i.e. current data and next data
Low level splices.Such as, continuous print align(alignment in OOB signal PHY recovered) primitive should be: 4abc,
7b4a, 4abc, 7b4a, 4abc, 7b4a, and the parallel data that PHY recovers arises that bc7b, 4a4a, bc7b, 4a4a, bc7b
Data, then show that the parallel data that PHY recovers occurs in that previous data least-significant byte and later number alignment when
The phenomenon of new data it is combined into according to most-significant byte；This causes this continuous print align data all data below above-mentioned mistake all occur
Position phenomenon.The parallel data that only high-low-position is gone wrong, it is only necessary to by the low level of previous data and later data
High-order combination, forms new parallel data, and K code or D is piled up in place.
For the most disorderly data according to bit non-alignment, the alignment thereof of employing is, takes described parallel data and rises
The first eight Bit data of top, it is judged that whether the first eight Bit data described is K code；If it is not, then by high by seven in described eight Bit datas
A low Bit data of bit data and next parallel data combines, and forms eight new Bit datas, again judges described
Whether eight new Bit datas are described K code；Circulation performs, until described K code being detected；After described K code being detected
Data are one group according to eight bits and continue to peek described parallel data and detect, until by each word of described parallel data
Joint alignment.
Such as, according to bit(bit) data are carried out recursion detection, take incipient 8bit data, it may be judged whether for K
Code, if not being K code, combining high 7 and next bit of this number, forming new 8bit data, again determine whether
K code, the like, until there is K code, then explanation detects the edge of this byte, and data afterwards just take according to 8bit
Number proceeds detection；If non-alignment occurs, process according still further to this rule, this ensure that the byte pair of parallel data
Together.
Whether the described parallel data after step S02, detection alignment contains OOB signal；The most then perform step S03；
Step S02 is performed if it is not, then return；
Step S03, by described OOB signal send to SATA controller；
Whether the parallel data after detection alignment contains OOB signal；If it is not, then continue detection；The most then initialize institute
State OOB signal, shake hands with described SATA controller；After shaking hands successfully, when again receiving described OOB signal, switch low
Power consumption state is to normal operating conditions.
Such as, detect in the parallel data after alignment containing OOB signal time, from OOB signal, extract K28.5 code,
COMMA signal as SATA controller exports；Owing to OOB is K code series, if OOB signal, then there will be according to SATA
The regular pulses signal of protocol requirement, is sent to SATA controller by this pulse signal, just can be identified as by SATA controller
OOB signal, the useful signal in parallel data is not anticipate when OOB signal initializes and just starts for SATA controller
Justice, the two is only shaken hands, and is shaking hands successfully, and OOB signal is completed initialize after just can use effective OOB letter
Number；The D10.2 thus OOB signal completing final stage detects, and when D10.2 being detected when, alignment is also
Row data data below are continuously effectives.When low-power consumption, carrying out OOB signal is to enter with SATA controller alternately
Row is shaken hands；After shaking hands successfully, when OOB signal again occur, switching low power consumpting state is to normal operating conditions.In normal work
State, sends OOB signal to SATA controller.
Step S04, after OOB signal described in described SATA controller identification, receive described SATA controller send speed
Degree selects signal, and sends described rate selection signal to described PHY.
Owing to OOB is K code series, if OOB signal, then there will be and believe according to the regular pulses of SATA protocol requirement
Number, after this pulse signal is sent to SATA controller, just can be identified as OOB signal by SATA controller；Receive SATA control
The rate selection signal that device processed sends according to this OOB signal, in described PHY, existence and described rate selection signal match
During fractional frequency signal, directly described rate selection signal is sent to described PHY；Described PHY does not exist and selects with described speed
When selecting the fractional frequency signal that signal matches, described rate selection signal is processed into described PHY fractional frequency signal to the speed mated
Degree configuration signal.
The speed that PHY to mate with SATA controller according to the rate selection signal realization that SATA controller sends, SATA
Controller can send the speed class consulted with PHY, is indicated to PHY with rate selection signal.Such as, maximum speed is only propped up
Holding the SATA controller of Gen2, this rate selection signal is 1bit, and output 0 expression requires that PHY is operated in Gen1 velocity mode,
Output 1 expression requires that PHY is operated in Gen2 velocity mode；PHY needs by performing described SATA speed based on third party PHY
In auto-negotiation method, the divide ratio of its inside is heavily joined, by SATA controller by the corresponding module of heavily joining heavily joining step
Rate selection signal, through processing, heavily joins the input of module as PHY inside correspondence, heavily joins the inside frequency dividing of PHY, with
Reach the speed matched with SATA controller requirement.
The present embodiment, by receiving the parallel data that PHY recovers, carries out byte-aligned to described parallel data；Detection alignment
After described parallel data in whether contain out of band data OOB signal；The most described OOB signal is sent to SATA control
Device；After OOB signal described in described SATA controller identification, receive the rate selection signal that described SATA controller sends, and
Described rate selection signal is sent to the method for described PHY, has and carry out the parallel data recovering dislocation aliging and can
Smoothly complete the beneficial effect of PHY speed switching, efficiently solve connection failure or low-power consumption mould that data non-alignment causes
The problem of formula handoff failure.
It is the signal of present invention SATA based on third party PHY speed auto-negotiation device one example structure with reference to Fig. 2, Fig. 2
Figure；As in figure 2 it is shown, present invention SATA based on third party PHY speed auto-negotiation device includes: alignment of data module 01, logic
Detection module 02 and speed heavily join module 03.
The cut-away view of described SATA speed auto-negotiation device one embodiment based on third party PHY refer to Fig. 3, figure
3 is present invention SATA based on Altera PHY speed auto-negotiation device internal structure schematic diagram.Please with reference to Fig. 2 and Fig. 3,
The method that described SATA speed auto-negotiation device based on third party PHY is used is: by receiving PHY recovers and line number
According to, described parallel data is carried out byte-aligned；Whether the described parallel data after detection alignment contains out of band data OOB letter
Number；The most described OOB signal is sent to SATA controller；After OOB signal described in described SATA controller identification, connect
Receive the rate selection signal that described SATA controller sends, and described rate selection signal is sent to described PHY.
Will be further described below alignment of data module 01 in SATA speed auto-negotiation device based on third party PHY, patrol
Volume detection module 02 and speed heavily join the work process of module 03.
Alignment of data module 01, for receiving the parallel data that PHY recovers, carries out byte-aligned to described parallel data.
When the parallel data of the SATA controller of reception is recovered by PHY, it will usually the situation that data misplace occurs.
When there is the situation of high infraversion malposition in parallel data, the position of K code and D code can be placed on SATA controller cannot know
An other high position or low level, K code that whether alignment of data module 01 is able to detect that in parallel data according to SATA controller or D code
Judge whether parallel data exists the situation of high infraversion malposition；If SATA controller can't detect low level in parallel data
K code, even detects that K code then switches to byte shift logic in a high position, alignment of data module 01, by described parallel data i.e. when
The low level of the high position in front data and next data splices.Such as, continuous print in OOB signal PHY recovered
Align primitive should be: 4abc, 7b4a, 4abc, 7b4a, 4abc, 7b4a, and arises that in the parallel data that PHY recovers
The data of bc7b, 4a4a, bc7b, 4a4a, bc7b, then show that the parallel data that PHY recovers occurs in that alignment when
Previous data least-significant byte and later data most-significant byte are combined into the phenomenon of new data；After this causes this continuous print align data
All there is above-mentioned inconsistent phenomenon in all data in face.The parallel data that only high-low-position is gone wrong, alignment of data module
01 has only to the low level by previous data and the high-order combination of later data, forms new parallel data, and by K code or D
Pile up in place.
For the most disorderly data according to bit non-alignment, the alignment thereof that alignment of data module 01 uses is to take
Described the first eight Bit data of parallel data initiating terminal, it is judged that whether the first eight Bit data described is K code；If it is not, then by described eight
In Bit data, a low Bit data of high seven bit data and next parallel data combines, and forms eight new bit numbers
According to, again judge whether described eight new Bit datas are described K code；Circulation performs, until described K code being detected；Will detection
Data after described K code are one group according to eight bits and continue to peek described parallel data and detect, until by institute
State each byte-aligned of parallel data.
Such as, alignment of data module 01 carries out recursion detection according to bit to data, takes incipient 8bit data, it is judged that
Whether it is K code, if not being K code, high 7 and next bit of this number being combined, forms new 8bit data, again sentence
Whether disconnected is K code, the like, until there is K code, then explanation detects the edge of this byte, and data afterwards are just pressed
Detection is proceeded according to 8bit peek；If non-alignment occurs, process according still further to this rule, this ensure that parallel data
Byte-aligned.
Whether logic detection module 02, contain out of band data OOB signal in the described parallel data after detecting alignment；
The most described OOB signal is sent to SATA controller.
Logic detection module 02 detects in the parallel data after alignment of data module 01 is alignd whether contain OOB signal；If
No, then continue detection；The most then initialize described OOB signal, shake hands with described SATA controller；After shaking hands successfully, then
Secondary when receiving described OOB signal, switching low power consumpting state is to normal operating conditions.
Such as, logic detection module 02 detects when containing OOB signal in the parallel data after alignment, from OOB signal
Extracting K28.5 code, the COMMA signal as SATA controller exports；Owing to OOB is K code series, if OOB signal, then
There will be the regular pulses signal according to SATA protocol requirement, this pulse signal is sent to SATA controller, just can be by
SATA controller is identified as OOB signal, and the useful signal in parallel data is controlled for SATA when OOB signal initializes and just starts
Being nonsensical for device processed, the two is only shaken hands, just meeting after shaking hands successfully and completing OOB signal to initialize
Use effective OOB signal；The D10.2 thus wanting logic detection module 02 that OOB signal is completed final stage detects,
When D10.2 being detected when, the parallel data of alignment data below are continuously effectives.When low-power consumption, logic is examined
Survey module 02 carrying out OOB signal is to shake hands with SATA controller alternately；After shaking hands successfully, when again occurring that OOB believes
Number time, logic detection module 02 switches low power consumpting state to normal operating conditions.In normal operating conditions, logic detection module 02
OOB signal is sent to SATA controller.
Speed heavily joins module 03, for after OOB signal described in described SATA controller identification, receives described SATA and controls
The rate selection signal that device sends, and described rate selection signal is sent to described PHY.
Owing to OOB is K code series, if OOB signal, then there will be and believe according to the regular pulses of SATA protocol requirement
Number, speed is heavily joined after this pulse signal is sent to SATA controller by module 03, just can be identified as OOB letter by SATA controller
Number；Speed is heavily joined module 03 and is received the rate selection signal that SATA controller sends according to this OOB signal, deposits in described PHY
When the fractional frequency signal matched with described rate selection signal, directly described rate selection signal is sent to described PHY；?
When described PHY does not exist the fractional frequency signal matched with described rate selection signal, described rate selection signal is processed into
With described PHY fractional frequency signal to the speed configuration signal mated.
The speed that PHY to mate with SATA controller according to the rate selection signal realization that SATA controller sends, SATA
Controller can send the speed class consulted with PHY, is indicated to PHY with rate selection signal.Such as, maximum speed is only propped up
Holding the SATA controller of Gen2, this rate selection signal is 1bit, and output 0 expression requires that PHY is operated in Gen1 velocity mode,
Output 1 expression requires that PHY is operated in Gen2 velocity mode；PHY needs through-rate heavily to join module 03 to carry out the frequency dividing to its inside
Coefficient is heavily joined；Speed heavily joins module 03 by the rate selection signal of SATA controller after treatment, the speed after processing
Degree selects signal to be sent to PHY；The inside frequency dividing of PHY is heavily joined, to reach and SATA by PHY according to this rate selection signal
Controller requires the speed matched.
The present embodiment, by receiving the parallel data that PHY recovers, carries out byte-aligned to described parallel data；Detection alignment
After described parallel data in whether contain out of band data OOB signal；The most described OOB signal is sent to SATA control
Device；After OOB signal described in described SATA controller identification, receive the rate selection signal that described SATA controller sends, and
Described rate selection signal is sent to described PHY, has and carry out the parallel data recovering dislocation aliging and can be the completeest
Become the beneficial effect of PHY speed switching, efficiently solve connection failure or low-power consumption mode switching that data non-alignment causes
Failed problem.
The foregoing is only the preferred embodiments of the present invention, not thereby limit its scope of the claims, every utilize the present invention
Equivalent structure or equivalence flow process that description and accompanying drawing content are made convert, and are directly or indirectly used in other relevant technology necks
Territory, is the most in like manner included in the scope of patent protection of the present invention.
Claims (6)
1. a SATA speed auto-negotiation method based on third party PHY, it is characterised in that comprise the following steps:
Receive the parallel data that physical layer PHY is recovered, described parallel data is carried out byte-aligned；
Whether the described parallel data after detection alignment contains out of band data OOB signal；
The most described OOB signal is sent to Serial Advanced Technology Attachment SATA controller；
After OOB signal described in described SATA controller identification, receive the rate selection signal that described SATA controller sends, and
Described rate selection signal is sent to described PHY；
The parallel data that described reception PHY recovers, carries out byte-aligned to described parallel data and includes:
Judge whether described SATA controller is able to detect that the K code of low level in described parallel data；
If K code is in a high position, then switch to the logic of byte shift, the low level of a high position for current data and next data is carried out
Splicing；
Or, the parallel data that described reception PHY recovers, described parallel data is carried out byte-aligned and includes:
Take described the first eight Bit data of parallel data initiating terminal, it is judged that whether the first eight Bit data described is K code；
If it is not, then a low Bit data of seven bit data high in described eight Bit datas with next parallel data is tied mutually
Close, form eight new Bit datas, again judge whether described eight new Bit datas are described K code；Circulation performs, until inspection
Measure described K code；
Data after described K code being detected are one group according to eight bits and continue to peek described parallel data and examine
Survey, until by each byte-aligned of described parallel data.
2. the method for claim 1, it is characterised in that the described step by described OOB signal transmission to SATA controller
Also include before rapid:
Initialize described OOB signal, shake hands with described SATA controller；
After shaking hands successfully, when again receiving described OOB signal, switching low power consumpting state is to normal operating conditions.
3. the method for claim 1, it is characterised in that the speed that the described SATA controller of described reception sends selects letter
Number, and the transmission of described rate selection signal is included to described PHY:
Receive the rate selection signal that described SATA controller sends, exist and described rate selection signal phase in described PHY
During the fractional frequency signal mated, directly described rate selection signal is sent to described PHY；
When there is not the fractional frequency signal matched with described rate selection signal in described PHY, by described rate selection signal
It is processed into the speed configuration signal matched with described PHY fractional frequency signal.
4. a SATA speed auto-negotiation device based on third party PHY, it is characterised in that including:
Alignment of data module, for receiving the parallel data that PHY recovers, carries out byte-aligned to described parallel data；
Whether logic detection module, contain out of band data OOB signal in the described parallel data after detecting alignment；If so,
Then described OOB signal is sent to SATA controller；
Speed heavily joins module, for after OOB signal described in described SATA controller identification, receives described SATA controller and sends
Rate selection signal, and described rate selection signal is sent to described PHY；
Described alignment of data module is additionally operable to:
Judge the K code whether described SATA controller is able to detect that in described parallel data；
If K code is in a high position, then switch to byte shift logic, the low level of a high position for current data and next data is spelled
Connect；
Or, described alignment of data module is additionally operable to:
Take described the first eight Bit data of parallel data initiating terminal, it is judged that whether the first eight Bit data described is K code；
If it is not, then a low Bit data of seven bit data high in described eight Bit datas with next parallel data is tied mutually
Close, form eight new Bit datas, again judge whether described eight new Bit datas are described K code；Circulation performs, until inspection
Measure described K code；
Data after described K code being detected are one group according to eight bits and continue to peek described parallel data and examine
Survey, until by each byte-aligned of described parallel data.
5. device as claimed in claim 4, it is characterised in that described logic detection module is additionally operable to:
Initialize described OOB signal, shake hands with described SATA controller；
After shaking hands successfully, when again receiving described OOB signal, switching low power consumpting state is to normal operating conditions.
6. device as claimed in claim 4, it is characterised in that described speed is heavily joined module and is additionally operable to:
Receive the rate selection signal that described SATA controller sends, exist and described rate selection signal phase in described PHY
During the fractional frequency signal mated, directly described rate selection signal is sent to described PHY；
When there is not the fractional frequency signal matched with described rate selection signal in described PHY, by described rate selection signal
It is processed into the speed configuration signal matched with described PHY fractional frequency signal.
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| CN201310001430.0A CN103914420B (en) | 2013-01-04 | 2013-01-04 | SATA speed auto-negotiation method based on third party PHY and device |
| PCT/CN2013/089739 WO2014106429A1 (en) | 2013-01-04 | 2013-12-17 | Sata speed auto-negotiation method and device based on third-party phy |
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| CN201310001430.0A CN103914420B (en) | 2013-01-04 | 2013-01-04 | SATA speed auto-negotiation method based on third party PHY and device |
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| CN104333388A (en) * | 2014-12-01 | 2015-02-04 | 山东华芯半导体有限公司 | Serial communication protocol controller, character re-aligning circuit and 8b/10b decoder |
| CN104467865B (en) * | 2014-12-01 | 2018-08-03 | 山东华芯半导体有限公司 | Serial communication protocol controller, byte split circuit and 8b10b encoders |
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| CN101599004A (en) * | 2009-07-10 | 2009-12-09 | 中国科学院光电技术研究所 | SATA controller based on FPGA |
| US7774424B1 (en) * | 2005-09-02 | 2010-08-10 | Pmc-Sierra, Inc. | Method of rate snooping in a SAS/SATA environment |
| CN102566941A (en) * | 2011-12-22 | 2012-07-11 | 深圳市创新科信息技术有限公司 | Method for recognizing serial advanced technology attachment (SATA) hard disk through serial attached SCSI (SAS) hard disk expander |
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| US7814245B2 (en) * | 2006-10-05 | 2010-10-12 | Lsi Corporation | Apparatus and methods for improved SATA device interaction without a SAS expander |
| US8180935B2 (en) * | 2009-05-22 | 2012-05-15 | Lsi Corporation | Methods and apparatus for interconnecting SAS devices using either electrical or optical transceivers |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7774424B1 (en) * | 2005-09-02 | 2010-08-10 | Pmc-Sierra, Inc. | Method of rate snooping in a SAS/SATA environment |
| CN101599004A (en) * | 2009-07-10 | 2009-12-09 | 中国科学院光电技术研究所 | SATA controller based on FPGA |
| CN102566941A (en) * | 2011-12-22 | 2012-07-11 | 深圳市创新科信息技术有限公司 | Method for recognizing serial advanced technology attachment (SATA) hard disk through serial attached SCSI (SAS) hard disk expander |
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| WO2014106429A1 (en) | 2014-07-10 |
| CN103914420A (en) | 2014-07-09 |
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