CN113806273A - PCI express data transfer control system - Google Patents
PCI express data transfer control system Download PDFInfo
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- CN113806273A CN113806273A CN202010550739.5A CN202010550739A CN113806273A CN 113806273 A CN113806273 A CN 113806273A CN 202010550739 A CN202010550739 A CN 202010550739A CN 113806273 A CN113806273 A CN 113806273A
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- 238000005192 partition Methods 0.000 claims abstract description 65
- 230000005540 biological transmission Effects 0.000 claims abstract description 56
- 238000011144 upstream manufacturing Methods 0.000 claims description 42
- 230000002093 peripheral effect Effects 0.000 claims description 35
- 238000001514 detection method Methods 0.000 claims description 8
- 230000000694 effects Effects 0.000 abstract description 4
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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Abstract
A PCI express data transmission control system, the PCI express data device is divided into a first partition and a second partition, the first partition includes a first non-transparent bridge device, an up port device and a down port device, the second partition includes a second non-transparent bridge device, the thread node data of a CPU is transmitted to the first non-transparent bridge device, the first non-transparent bridge device transmits the thread node data to the second non-transparent bridge device through an internal line, the second non-transparent bridge device transmits the thread node data to the down port device through a physical PCI express line, the down port device transmits the thread node data to the up port device through the internal line, the up port device transmits the thread node data to the storage address of a memory through a PCI express slot and stores the data, thereby achieving the technical effect of providing the data transmission process setting of the standard PCI express device.
Description
Technical Field
The present invention relates to a data transmission control system, and more particularly, to a system for controlling data transmission of a pci express device.
Background
The detection of the peripheral component interconnect express slot is usually realized by adopting a standard peripheral component interconnect express network card, the detection of the peripheral component interconnect express slot by adopting the standard peripheral component interconnect express network card is often limited by incapability of performing autonomous test, further limited by a driving mode of the peripheral component interconnect express network card, and incapability of randomly defining the setting of a memory address and a data transmission process, and only basic power supply characteristics and the connection state of the peripheral component interconnect express slot can be detected.
In summary, it is known that there is a problem that the conventional data transmission process of the standard pci express device cannot be set for a long time in the prior art, and therefore, it is necessary to provide an improved technical means to solve the problem.
Disclosure of Invention
In view of the problem existing in the prior art that the data transmission process of the standard PCI express device cannot be set, the present invention discloses a PCI express data transmission control system, wherein:
the present invention discloses a pci express data transmission control system according to a first embodiment, comprising: the motherboard and PCI express data equipment, the PCI express data equipment further comprising: a first partition and a second partition, the first partition further comprising: a first Non-Transparent Bridge (Non-Transparent Bridge) device, an upstream port (upstream port) device, and a downstream port (downstream port) device, the second partition further comprising: a second non-transparent bridging device.
The motherboard is provided with a central processing unit, a memory and a rapid peripheral component interconnection slot, the central processing unit is electrically connected with the memory and the rapid peripheral component interconnection slot through a physical circuit, the central processing unit is provided with thread node data, the memory is provided with a storage address, and the thread node data is stored when being transmitted to the storage address.
The PCI express data device is inserted into the PCI express slot, and the first non-transparent bridge device receives thread node data from the second CPU; the uplink port equipment receives the thread node data through an internal circuit, and transmits the thread node data to a storage address of the memory through the quick peripheral component interconnection slot for storage; the downlink port equipment receives the thread node data through the entity rapid peripheral component interconnection line and transmits the thread node data to the uplink port equipment through the internal line.
The second non-transparent bridge device receives the thread node data from the first non-transparent bridge device through the internal line, and transmits the thread node data to the downstream port device through the physical PCI express line.
The present invention discloses a pci express data transmission control system according to a second embodiment, comprising: the motherboard and PCI express data equipment, the PCI express data equipment further comprising: a first partition and a second partition, the first partition further comprising: the first non-transparent bridging device, the uplink port device and the downlink port device, the second partition further includes: a second non-transparent bridging device.
The mainboard is provided with a first central processing unit, a second central processing unit, a memory and a fast peripheral component interconnection slot, the first central processing unit is respectively electrically connected with the second central processing unit, the memory and the fast peripheral component interconnection slot through a physical circuit, the second central processing unit is provided with thread node data, the memory is provided with a storage address, and the thread node data is stored when being transmitted to the storage address.
The first non-transparent bridging device receives thread node data from the second central processing unit through the first central processing unit; the uplink port equipment receives the thread node data through an internal circuit, and transmits the thread node data to a storage address of the memory through the quick peripheral component interconnection slot for storage; and the downlink port equipment receives the thread node data through the physical fast peripheral component interconnection line and transmits the thread node data to the uplink port equipment through the internal line.
The second non-transparent bridge device receives the thread node data from the first non-transparent bridge device through the internal line, and transmits the thread node data to the downstream port device through the physical PCI express line.
The present invention discloses a pci express data transmission control system according to a third embodiment, comprising: the motherboard, a first PCI express data device, and a second PCI express data device, the first PCI express data device further comprising: a first partition and a second partition, the first partition further comprising: a first non-transparent bridge device, a first uplink port device, and a first downlink port device, the second partition further comprising: a second non-transparent bridging device; the second PCI express data device further comprises: a third partition and a fourth partition, the third partition further comprising: a third non-transparent bridge device, a third upstream port device, and a third downstream port device, the fourth partition further comprising: a fourth non-transparent bridging device.
The motherboard is provided with a central processing unit, a memory, a fast peripheral component interconnection switch, a first fast peripheral component interconnection slot and a second fast peripheral component interconnection slot, the central processing unit is electrically connected with the memory and the fast peripheral component interconnection switch through a physical circuit respectively, the central processing unit is provided with thread node data, the memory is provided with a storage address, and the thread node data is stored when being transmitted to the storage address.
The first non-transparent bridging device receives the thread node data from the central processing unit through the PCI express switch; the first uplink port equipment receives the thread node data through an internal circuit and transmits the thread node data through the PCI express slots and the PCI express switches; and the first downlink port equipment receives the thread node data through the physical fast peripheral component interconnection line and transmits the thread node data to the first uplink port equipment through the internal line.
The second non-transparent bridging device receives the thread node data from the first non-transparent bridging device through the internal line, and transmits the thread node data to the first downstream port device through the physical PCI express line.
The second PCI express data device is inserted in the second PCI express slot, the third non-transparent bridge device is electrically connected with the PCI express switch through a physical line, and the third non-transparent bridge device receives the thread node data from the first uplink port device through the PCI express slot and the PCI express switch; the third uplink port equipment receives the thread node data through the internal circuit, transmits the thread node data to the storage address of the memory through the PCI express slot and the PCI express switch and stores the thread node data; and the third downlink port equipment receives the thread node data through the physical fast peripheral component interconnection line and transmits the thread node data to the third uplink port equipment through the internal line.
And a fourth nontransparent bridge device that receives the thread node data from the third nontransparent bridge device via the internal line and transmits the thread node data to the third downstream port device via the physical PCI express line.
The system disclosed herein differs from the prior art in that the PCI express data device is divided into a first partition and a second partition, the first partition including a first non-transparent bridge device, the second partition comprises a second non-transparent bridge device, the thread node data of the central processing unit is transmitted to the first non-transparent bridge device, the first non-transparent bridge device transmits the thread node data to the second non-transparent bridge device through an internal line, the second non-transparent bridge device transmits the thread node data to the downlink port device through a physical peripheral component interconnect line, the downlink port device transmits the thread node data to the uplink port device through the internal line, and the uplink port device transmits the thread node data to a storage address of the memory through a peripheral component interconnect slot and stores the thread node data.
Through the technical means, the invention can achieve the technical effect of providing the data transmission process setting of the standard PCI express device.
Drawings
FIG. 1 is a system block diagram illustrating a PCI express data transfer control system according to a first embodiment of the present invention.
FIG. 2 is a system block diagram of a PCI express data transfer control system according to a second embodiment of the present invention.
FIG. 3 is a system block diagram of a PCI express data transfer control system according to a third embodiment of the present invention.
Description of the symbols
11 central processing unit
111 the first central processing unit
112 second central processing unit
12 memory
PCI express data device
First PCI express data device 201
202 second PCI express data device
21 first partition
211 first non-transparent bridging device
212 upstream Port device
213 downstream port device
22 second partition
221 second non-transparent bridging device
231 first non-transparent bridging device
232 first upstream port device
233 first downstream port device
24 second partition
241 second non-transparent bridging device
25 third partition
251 third non-transparent bridging device
252 third upstream port device
253 third downstream Port device
26 the fourth division
261 fourth non-transparent bridging device
Detailed Description
The following detailed description of the embodiments of the present invention will be provided in conjunction with the accompanying drawings and examples, so that how to implement the technical means for solving the technical problems and achieving the technical effects of the present invention can be fully understood and implemented.
Referring to fig. 1, fig. 1 is a block diagram of a pci express data transmission control system according to a first embodiment of the present invention.
The present invention discloses a pci express data transmission control system according to a first embodiment, comprising: motherboard and PCI express data device 20, PCI express data device 20 further comprising: a first partition 21 and a second partition 22, the first partition 21 further comprising: a first Non-Transparent Bridge (Non-Transparent Bridge) device 211, an upstream port (upstream port) device 212, and a downstream port (downstream port) device 213, and the second partition 22 further includes: a second non-transparent bridging device 221.
The motherboard has a central processing unit 11, a memory 12 and a pci express slot, the central processing unit 11 is electrically connected to the memory 12 and the pci express slot by physical circuits, the central processing unit 11 has thread node data (for example, the thread node data of the SRC portion of the central processing unit 11 is only illustrated and not limited to the application scope of the present invention), the memory 12 has a storage address (for example, the storage address of the DST address in the memory 12 is only illustrated and not limited to the application scope of the present invention), and the thread node data is stored when being transmitted to the storage address.
The pci express device 20 is inserted into the pci express slot, and the data transmission process of the thread node data is as follows, the first non-transparent bridge device 211 receives the thread node data from the second cpu 11, the second non-transparent bridge device 221 receives the thread node data from the first non-transparent bridge device 211 through the internal line, the second non-transparent bridge device 221 transmits the thread node data to the downstream port device 213 through the physical pci express line, the downstream port device 213 receives the thread node data from the second non-transparent bridge device 221 through the physical pci express line, the downstream port device 213 transmits the thread node data to the upstream port device 212 through the internal line, the upstream port device 212 receives the thread node data from the downstream port device 213 through the internal line, and the upstream port device 212 transmits the thread node data to the storage address of the memory 12 through the pci express slot and transmits the thread node data to the storage address of the memory 12 through the pci express slot And storing the mixture.
The data transmission process of the thread node data is a data transmission process in a PIO mode of PCIe data (peripheral component interconnect express) transmission, where the central processing unit 11 is used as an initiator of data transmission to actively initiate data transmission to a PCIe device.
The pci express data transmission control system further comprises a pci express device electrically connected to the memory 12 and the pci express slot by physical lines, respectively, the pci express device has data, the first non-transparent bridge device 211 receives the data from the pci express device, the second non-transparent bridge device 221 receives the data from the first non-transparent bridge device 211 through an internal line, the downstream port device 213 receives the data from the second non-transparent bridge device 221 through a physical pci express line, the upstream port device 212 receives the data from the downstream port device 213 through an internal line, and the upstream port device 213 transmits the data to a storage address of the memory 12 through the pci express slot and stores the data.
The PCI express data transmission control system further comprises a detection device electrically connected with the motherboard, and respectively obtaining the thread node data or the data from the CPU 11 and the thread node data or the data stored in the storage address from the memory 12 and comparing the obtained data to verify the data of the thread node data or the data after data transmission.
Referring to fig. 2, fig. 2 is a block diagram of a system for controlling pci express data transmission according to a second embodiment of the present invention.
The present invention discloses a pci express data transmission control system according to a second embodiment, comprising: motherboard and PCI express data device 20, PCI express data device 20 further comprising: a first partition 21 and a second partition 22, the first partition 21 further comprising: the first non-transparent bridge device 211, the upstream port device 212, and the downstream port device 213, and the second partition 22 further includes: a second non-transparent bridging device 221.
The motherboard has a first cpu 111, a second cpu 112, a memory 12 and a pci express slot, the first cpu 111 is electrically connected to the second cpu 112, the memory 12 and the pci express slot by physical circuits, the second cpu 112 has thread node data (for example, the thread node data of the SRC portion of the second cpu 112 is illustrated and not limited to the application scope of the present invention), the memory 12 has a storage address (for example, the storage address of the DST address in the memory 12 is illustrated and not limited to the application scope of the present invention), and the thread node data is stored when being transmitted to the storage address.
The PCI express device 20 is inserted into the PCI express slot, and the data transmission process of the thread node data is as follows, the first non-transparent bridge device 211 receives the thread node data from the second CPU 11 through the first CPU 11, the first non-transparent bridge device 211 receives the thread node data from the second CPU 11, the second non-transparent bridge device 221 receives the thread node data from the first non-transparent bridge device 211 through the internal line, the second non-transparent bridge device 221 transmits the thread node data to the downstream port device 213 through the physical PCI express line, the downstream port device 213 receives the thread node data from the second non-transparent bridge device 221 through the physical PCI express line, the downstream port device 213 transmits the thread node data to the upstream port device 212 through the internal line, the up port device 212 receives the thread node data from the down port device 213 via the internal line, and the up port device 212 transmits the thread node data to the storage address of the memory 12 via the PCI express slot for storage.
The data transmission process of the thread node data is a data transmission process in a PIO mode of PCIe data transmission, where the central processing unit 11 is used as an initiator of data transmission to actively initiate data transmission to the PCIe device.
The PCI express data transmission control system further comprises a first PCI express device and a second PCI express device, the first PCI express device is electrically connected to the second PCI express device, the memory 12 and the PCI express slot respectively by physical lines, the second PCI express device has data, the first non-transparent bridge device 211 receives data from the second PCI express device through the first PCI express device, the second non-transparent bridge device 221 receives data from the first non-transparent bridge device 211 through internal lines, the downstream port device 213 receives data from the second non-transparent bridge device 221 through the physical PCI express line, the upstream port device 212 receives data from the downstream port device 213 through internal lines, the up port 213 transmits data to the storage address of the memory 12 through the PCI express slot for storage.
The PCI express data transmission control system further comprises a detection device electrically connected with the motherboard, and respectively obtaining the thread node data or the data from the CPU 11 and the thread node data or the data stored in the storage address from the memory 12 and comparing the obtained data to verify the data of the thread node data or the data after data transmission.
Referring to fig. 3, a system block diagram of a pci express data transmission control system according to a third embodiment of the present invention is shown in fig. 3.
The present invention discloses a pci express data transmission control system according to a third embodiment, comprising: a motherboard, a first PCI express data device 201, and a second PCI express data device 202, the first PCI express data device 201 further comprising: a first partition 23 and a second partition 24, the first partition 23 further comprising: a first non-transparent bridge device 231, a first upstream port device 232, and a first downstream port device 233, and the second partition 24 further includes: a second non-transparent bridging device 241; the second PCI express data device 202 further comprises: a third partition 25 and a fourth partition 26, the third partition 25 further comprising: a third non-transparent bridge device 251, a third upstream port device 252, and a third downstream port device 253, and the fourth partition 26 further includes: a fourth non-transparent bridging device 261.
The motherboard has a central processing unit 11, a memory 12, a pci switch 14, a first pci slot and a second pci slot, the central processing unit 11 is electrically connected to the memory 12 and the pci switch 14 by physical lines, the central processing unit 11 has thread node data (for example, the thread node data of the SRC portion of the central processing unit 11 is illustrated and not limited to the application range of the present invention), the memory 12 has a storage address (for example, the storage address of the DST address of the memory 12 is illustrated and not limited to the application range of the present invention), and the thread node data is stored when being transmitted to the storage address.
The first PCI express device 20 is inserted into the first PCI express slot, the data transmission process of the thread node data is as follows, the first non-transparent bridge device 231 is electrically connected to the PCI express switch 14 by a physical line, the first non-transparent bridge device 231 receives the thread node data from the CPU 11 through the PCI express switch 14, the second non-transparent bridge device 241 receives the thread node data from the first non-transparent bridge device 231 through an internal line, the second non-transparent bridge device 241 transmits the thread node data to the first downstream port device 233 through the PCI express line, the first downstream port device 233 receives the thread node data from the second non-transparent bridge device 241 through the PCI express line, the first downstream port device 233 transmits the thread node data to the first upstream port device 232 through the internal line, the first upstream port device 232 receives thread node data from the first downstream port device 233 via the internal lines, and the first upstream port device 232 transmits the thread node data to the third non-transparent bridge device 251 via the PCI express slot and the PCI express switch 14.
The fourth non-transparent bridge device 261 receives thread node data from the third non-transparent bridge device 251 through an internal line, the fourth non-transparent bridge device 261 transmits thread node data to the third downstream port device 253 through a physical PCI express line, the third downstream port device 253 receives thread node data from the fourth non-transparent bridge device 261 through a physical PCI express line, the third downstream port device 253 transmits thread node data to the third upstream port device 252 through an internal line, the third upstream port device 252 receives thread node data from the third downstream port device 253 through an internal line, and the third upstream port device 252 transmits thread node data to a storage address of the memory 12 through a PCI express slot and the PCI express switch 14 and stores the thread node data.
The data transmission process of the thread node data is a data transmission process in a PIO mode of PCIe data transmission, where the central processing unit 11 is used as an initiator of data transmission to actively initiate data transmission to the PCIe device.
The PCI express data transmission control system further comprises a PCI express device electrically connected to the memory 12 and the PCI express switch 14 by physical lines, respectively, the PCI express device having data, the first non-transparent bridge device 231 receiving data from the PCI express device through the PCI express switch 14, the second non-transparent bridge device 241 receiving data from the first non-transparent bridge device 231 through internal lines, the first downstream port device 233 receiving data from the second non-transparent bridge device 241 through the PCI express line, the first upstream port device 232 receiving data from the first downstream port device 233 through internal lines, the first upstream port device 232 transmitting data to the third non-transparent bridge device 251 through the PCI express slot and the PCI express switch 14, the fourth non-transparent bridge device 261 receives data from the third non-transparent bridge device 251 through an internal line, the third downstream port device 253 receives data from the fourth non-transparent bridge device 261 through a physical PCI express line, the third upstream port device 252 receives data from the third downstream port device 253 through an internal line, and the third upstream port device 252 transmits data to the storage address of the memory 12 through the PCI express slot and the PCI express switch 14 for storage.
The PCI express data transmission control system further comprises a detection device electrically connected with the motherboard, and respectively obtaining the thread node data or the data from the CPU 11 and the thread node data or the data stored in the storage address from the memory 12 and comparing the obtained data to verify the data of the thread node data or the data after data transmission.
In summary, it can be seen that the difference between the present invention and the prior art is that the PCI express data device is divided into a first partition and a second partition, the first partition includes a first non-transparent bridge device, the second partition comprises a second non-transparent bridge device, the thread node data of the central processing unit is transmitted to the first non-transparent bridge device, the first non-transparent bridge device transmits the thread node data to the second non-transparent bridge device through an internal line, the second non-transparent bridge device transmits the thread node data to the downlink port device through a physical peripheral component interconnect line, the downlink port device transmits the thread node data to the uplink port device through the internal line, and the uplink port device transmits the thread node data to a storage address of the memory through a peripheral component interconnect slot and stores the thread node data.
The technical means can solve the problem that the existing data transmission process of the standard PCI express device cannot be set in the prior art, and further achieve the technical effect of providing data transmission process setting of the standard PCI express device.
Although the embodiments of the present invention have been described, the description is not intended to limit the scope of the invention. Workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the disclosure. The scope of the present invention is defined by the appended claims.
Claims (9)
1. A pci express data transmission control system, comprising:
the computer system comprises a mainboard, a memory and a PCI express slot, wherein the mainboard is provided with a central processing unit, the memory and the PCI express slot which are electrically connected by a physical circuit respectively, the central processing unit is provided with thread node data, the memory is provided with a storage address, and the thread node data is stored when being transmitted to the storage address; and
a PCI express data device, said PCI express data device inserted into said PCI express slot, said PCI express data device further comprising:
a first partition, the first partition further comprising:
a first non-transparent bridging device receiving the thread node data from the second central processing unit;
an upstream port device for receiving the thread node data through an internal circuit, and transmitting the thread node data to the storage address of the memory through the PCI express slot for storage; and
the downlink port equipment receives the thread node data through an entity rapid peripheral component interconnection line and transmits the thread node data to the uplink port equipment through an internal line; and
a second partition, the second partition further comprising:
and a second non-transparent bridge device receiving the thread node data from the first non-transparent bridge device through an internal line, and transmitting the thread node data to the downstream port device through an entity express peripheral component interconnect line.
2. The PCI express data transmission control system of claim 1, further comprising a PCI express device electrically connected to the memory and the PCI express slot respectively by physical lines, the PCI express device having data, the first non-transparent bridge device receiving the data from the PCI express device, the second non-transparent bridge device receiving the data from the first non-transparent bridge device via internal lines, the downstream port device receiving the data from the second non-transparent bridge device via physical PCI express lines, the upstream port device receiving the data from the downstream port device via internal lines, the up port device transmits the data to the storage address of the memory through the PCI express slot and stores the data.
3. The system of claim 1, further comprising a detection device electrically connected to the motherboard for obtaining the thread node data from the CPU and the thread node data stored in the storage address from the memory and comparing the thread node data with the storage address to verify the data of the thread node data after data transmission.
4. A pci express data transmission control system, comprising:
the computer system comprises a mainboard, a first computer, a second computer, a memory and a quick peripheral component interconnection slot, wherein the mainboard is provided with the first computer, the second computer, the memory and the quick peripheral component interconnection slot which are electrically connected through a physical circuit respectively; and
a PCI express data device, said PCI express data device inserted into said PCI express slot, said PCI express data device further comprising:
a first partition, the first partition further comprising:
a first non-transparent bridging device that receives the thread node data from the second central processor through the first central processor;
an upstream port device for receiving the thread node data through an internal circuit, and transmitting the thread node data to the storage address of the memory through the PCI express slot for storage; and
the downlink port equipment receives the thread node data through an entity rapid peripheral component interconnection line and transmits the thread node data to the uplink port equipment through an internal line; and
a second partition, the second partition further comprising:
and a second non-transparent bridge device receiving the thread node data from the first non-transparent bridge device through an internal line, and transmitting the thread node data to the downstream port device through an entity express peripheral component interconnect line.
5. The PCI express data transmission control system of claim 1, further comprising a first PCI express device and a second PCI express device, wherein said first PCI express device is electrically connected to said second PCI express device, said memory and said PCI express slot by physical lines, respectively, said second PCI express device has data, said first non-transparent bridge device receives said data from said second PCI express device through said first PCI express device, said second non-transparent bridge device receives said data from said first non-transparent bridge device through internal lines, said downstream port device receives said data from said second non-transparent bridge device through physical PCI express lines And receiving the data, receiving the data from the downstream port device by the upstream port device through an internal line, and transmitting the data to the storage address of the memory and storing the data by the upstream port device through the PCI express slot.
6. The system of claim 1, further comprising a detection device electrically connected to the motherboard for obtaining the thread node data from the second cpu and the thread node data stored in the storage address from the memory and comparing the thread node data with the storage address to verify the data of the thread node data after data transmission.
7. A pci express data transmission control system, comprising:
the computer system comprises a mainboard, a memory, a PCI express switch, a first PCI express slot and a second PCI express slot, wherein the mainboard is provided with a Central Processing Unit (CPU), the memory, the PCI express switch, the first PCI express slot and the second PCI express slot, the CPU is respectively electrically connected with the memory and the PCI express switch through a physical circuit, the CPU is provided with a thread node data, the memory is provided with a storage address, and the thread node data is stored when being transmitted to the storage address;
a first PCI express data device, said first PCI express data device being inserted into said first PCI express slot, said first PCI express data device further comprising:
a first partition, the first partition further comprising:
a first non-transparent bridge device electrically connected to the PCI express switch by a physical line, the first non-transparent bridge device receiving the thread node data from the CPU through the PCI express switch;
a first upstream port device that receives the thread node data through an internal line and transmits the thread node data through the PCI express slot and the PCI express switch; and
a first downstream port device that receives the thread node data via an entity express peripheral component interconnect line and transmits the thread node data to the first upstream port device via an internal line; and
a second partition, the second partition further comprising:
a second non-transparent bridge device receiving the thread node data from the first non-transparent bridge device through an internal line, and transmitting the thread node data to the first downstream port device through an entity express peripheral component interconnect line; and
a second PCI express data device, said second PCI express data device inserted into said second PCI express slot, said second PCI express data device further comprising:
a third partition, the third partition further comprising:
a third non-transparent bridge device electrically connected to the PCI express switch by a physical line, the third non-transparent bridge device receiving the thread node data from the first upstream port device through the PCI express slot and the PCI express switch;
a third upstream port device for receiving the thread node data through an internal circuit, transmitting the thread node data to the storage address of the memory through the PCI express slot and the PCI express switch, and storing the thread node data; and
a third downstream port device that receives the thread node data via an entity express Peripheral Component Interconnect (PCI) line and transmits the thread node data to the third upstream port device via an internal line; and
a fourth partition, the fourth partition further comprising:
and a fourth non-transparent bridge device configured to receive the thread node data from the third non-transparent bridge device through an internal line, and transmit the thread node data to the third downstream port device through an entity express peripheral component interconnect line.
8. The PCI express data transmission control system of claim 7, further comprising a PCI express device electrically connected to the memory and the PCI express switch respectively by physical lines, the PCI express device having data, the first non-transparent bridge device receiving the data from the PCI express device through the PCI express switch, the second non-transparent bridge device receiving the data from the first non-transparent bridge device through internal lines, the first downstream port device receiving the data from the second non-transparent bridge device through the PCI express line, the first upstream port device receives the data from the first downstream port device via an internal line, the first upstream port device transmits the data to the third non-transparent bridge device through the PCI express slot and the PCI express switch, the fourth nontransparent bridge device receives the data from the third nontransparent bridge device through an internal line, the third downstream port device receives the data from the fourth non-transparent bridge device via physical PCI express lines, the third upstream port device receives the data from the third downstream port device via an internal line, the third upstream port device transmits the data to the storage address of the memory through the PCI express slot and the PCI express switch for storage.
9. The system of claim 7, further comprising a detection device electrically connected to the motherboard for obtaining the thread node data from the CPU and the thread node data stored in the storage address from the memory and comparing the thread node data with the storage address to verify the data of the thread node data after data transmission.
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