CN113806273B - Fast peripheral component interconnect data transfer control system - Google Patents
Fast peripheral component interconnect data transfer control system Download PDFInfo
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- CN113806273B CN113806273B CN202010550739.5A CN202010550739A CN113806273B CN 113806273 B CN113806273 B CN 113806273B CN 202010550739 A CN202010550739 A CN 202010550739A CN 113806273 B CN113806273 B CN 113806273B
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- 230000002093 peripheral effect Effects 0.000 title claims description 27
- 230000005540 biological transmission Effects 0.000 claims abstract description 74
- 238000005192 partition Methods 0.000 claims abstract description 66
- 238000011144 upstream manufacturing Methods 0.000 claims description 39
- 238000001514 detection method Methods 0.000 claims description 14
- 230000000694 effects Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 230000000977 initiatory effect Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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Abstract
The PCI express data device is divided into a first partition and a second partition, the first partition comprises a first non-transparent bridging device, an uplink port device and a downlink port device, the second partition comprises a second non-transparent bridging device, the thread node data of the CPU is transmitted to the first non-transparent bridging device, the first non-transparent bridging device transmits the thread node data to the second non-transparent bridging device through an internal circuit, the second non-transparent bridging device transmits the thread node data to the downlink port device through an entity PCI express line, the downlink port device transmits the thread node data to the uplink port device through the internal circuit, and the uplink port device transmits the thread node data to a storage address of a memory through a PCI express slot and stores the thread node data, so that the technical effect of providing a data transmission process setting of the PCI express device can be achieved.
Description
Technical Field
The present invention relates to a data transmission control system, and more particularly, to a system for performing data transmission control on a peripheral component interconnect express device.
Background
The current PCI express slot detection is usually implemented by using a standard PCI express network card, and the detection of the standard PCI express slot by using the standard PCI express network card is often limited by the inability to perform autonomous test, further limited by the driving mode of the standard PCI express network card, and unable to define the memory address and the setting of the data transmission process at will, and only the basic power supply characteristic and the connection state of the standard PCI express slot can be detected.
In view of the foregoing, it is known that there is a long-felt need in the art to solve the problem that the conventional data transmission process of the standard PCI express device cannot be set.
Disclosure of Invention
In view of the problem that the existing data transmission process of the standard PCI express device cannot be set in the prior art, the present invention discloses a PCI express data transmission control system, wherein:
the PCI express data transmission control system according to the first embodiment of the present invention comprises: motherboard and PCI express data device, the PCI express data device further comprises: the first partition and the second partition, the first partition still contains: a first Non-transparent bridging (Non-Transparent Bridge) device, an upstream port device, and a downstream port device, the second partition further comprising: and a second non-transparent bridging device.
The motherboard is provided with a central processing unit, a memory and a rapid peripheral component interconnection slot, wherein the central processing unit is respectively and electrically connected with the memory and the rapid peripheral component interconnection slot through physical lines, the central processing unit is provided with thread node data, the memory is provided with a storage address, and the thread node data is stored when being transmitted to the storage address.
The rapid peripheral component interconnection data equipment is inserted into the rapid peripheral component interconnection slot, and the first non-transparent bridging equipment receives thread node data from the second central processing unit; the uplink port equipment receives thread node data through an internal line, and transmits the thread node data to a storage address of a memory through a rapid peripheral component interconnect slot and stores the thread node data; the downstream port device receives the thread node data through the physical PCI express link and transmits the thread node data to the upstream port device through the internal link.
The second non-transparent bridging device receives the thread node data from the first non-transparent bridging device through the internal line and transmits the thread node data to the downstream port device through the physical PCI express link.
The PCI express data transmission control system according to the second embodiment of the present invention comprises: motherboard and PCI express data device, the PCI express data device further comprises: the first partition and the second partition, the first partition still contains: the first non-transparent bridge device, the uplink port device and the downlink port device, and the second partition further comprises: and a second non-transparent bridging device.
The motherboard is provided with a first CPU, a second CPU, a memory and a PCI express slot, wherein the first CPU is electrically connected with the second CPU, the memory and the PCI express slot through physical lines respectively, the second CPU is provided with thread node data, the memory is provided with a storage address, and the thread node data is stored when being transmitted to the storage address.
The rapid peripheral component interconnection data equipment is inserted into the rapid peripheral component interconnection slot, and the first non-transparent bridging equipment receives thread node data from the second central processing unit through the first central processing unit; the uplink port equipment receives thread node data through an internal line, and transmits the thread node data to a storage address of a memory through a rapid peripheral component interconnect slot and stores the thread node data; and the downlink port equipment receives the thread node data through the physical PCI express component interconnecting line and transmits the thread node data to the uplink port equipment through the internal line.
The second non-transparent bridging device receives the thread node data from the first non-transparent bridging device through the internal line and transmits the thread node data to the downstream port device through the physical PCI express link.
The PCI express data transmission control system according to the third embodiment of the present invention comprises: motherboard, first PCI express data device and second PCI express data device, the first PCI express data device further comprises: the first partition and the second partition, the first partition still contains: the first non-transparent bridge device, the first uplink port device, and the first downlink port device, and the second partition further includes: a second non-transparent bridging device; the second PCI express data device further includes: a third partition and a fourth partition, the third partition further comprising: the third non-transparent bridge device, the third uplink port device and the third downlink port device, and the fourth partition further includes: and a fourth non-transparent bridging device.
The motherboard is provided with a central processing unit, a memory, a PCI express switch, a first PCI express slot and a second PCI express slot, wherein the central processing unit is respectively and electrically connected with the memory and the PCI express switch through physical lines, the central processing unit is provided with thread node data, the memory is provided with a storage address, and the thread node data is stored when being transmitted to the storage address.
The first PCI express data device is inserted in the first PCI express slot, the first non-transparent bridge device and the PCI express switch are electrically connected by a physical circuit, and the first non-transparent bridge device receives thread node data from the CPU through the PCI express switch; the first uplink port equipment receives thread node data through an internal line and transmits the thread node data through the PCI express slot and the PCI express switch; and the first downstream port device receives the thread node data through the physical PCI express link and transmits the thread node data to the first upstream port device through the internal link.
The second non-transparent bridging device receives the thread node data from the first non-transparent bridging device through the internal line and transmits the thread node data to the first downlink port device through the physical PCI express device interconnect line.
The second PCI express data device is inserted in the second PCI express slot, the third non-transparent bridge device and the PCI express switch are electrically connected by a physical circuit, and the third non-transparent bridge device receives thread node data from the first uplink port device through the PCI express slot and the PCI express switch; the third uplink port equipment receives thread node data through an internal line, and transmits the thread node data to a storage address of a memory through a quick peripheral component interconnection slot and a quick peripheral component interconnection switch and stores the thread node data; and the third downstream port device receives the thread node data through the physical PCI express link and transmits the thread node data to the third upstream port device through the internal link.
And the fourth non-transparent bridging device receives the thread node data from the third non-transparent bridging device through the internal line and transmits the thread node data to the third downlink port device through the physical PCI express device interconnecting line.
The system disclosed in the present invention is different from the prior art in that the PCI express device is divided into a first partition and a second partition, the first partition includes a first non-transparent bridge device, an uplink port device and a downlink port device, the second partition includes a second non-transparent bridge device, the thread node data of the CPU is transferred to the first non-transparent bridge device, the first non-transparent bridge device transfers the thread node data to the second non-transparent bridge device through an internal line, the second non-transparent bridge device transfers the thread node data to the downlink port device through an physical PCI express line, the downlink port device transfers the thread node data to the uplink port device through an internal line, and the uplink port device transfers the thread node data to a storage address of the memory through a PCI express slot and stores the thread node data.
By the technical means, the invention can achieve the technical effect of providing the data transmission process setting of the standard PCI express device.
Drawings
Fig. 1 is a system block diagram of a pci express data transmission control system according to a first embodiment of the present invention.
Fig. 2 is a system block diagram of a pci express data transmission control system according to a second embodiment of the present invention.
Fig. 3 is a system block diagram of a pci express data transmission control system according to a third embodiment of the invention.
Symbol description
11 CPU
111 first CPU
112, second CPU
12 memory
Fast peripheral component interconnect data device
201 first PCI express data device
202 second PCI express data device
21 first partition
211 first non-transparent bridging device
212 upstream port device
213 downstream Port device
22 second partition
221 second non-transparent bridging device
23 first partition
231 first non-transparent bridging device
232 first upstream Port device
233 first downstream Port device
24 second partition
241 second non-transparent bridging device
25 third partition
251 third non-transparent bridging device
252 third upstream Port device
253 third downstream Port device
26 fourth partition
261 fourth non-transparent bridge device
Detailed Description
The following detailed description of embodiments of the present invention will be given with reference to the accompanying drawings and examples, so that the implementation process of how the present invention can be applied to solve the technical problems and achieve the technical effects can be fully understood and implemented.
The following first describes a pci express data transmission control system according to a first embodiment of the present invention, and referring to fig. 1, fig. 1 is a system block diagram of a pci express data transmission control system according to a first embodiment of the present invention.
The PCI express data transmission control system according to the first embodiment of the present invention comprises: motherboard and PCI express data device 20, PCI express data device 20 further comprises: a first partition 21 and a second partition 22, the first partition 21 further comprising: the first Non-transparent bridging (Non-Transparent Bridge) device 211, upstream port (upstream port) device 212, and downstream port (downstream port) device 213, and the second partition 22 further includes: a second non-transparent bridging device 221.
The motherboard has a cpu 11, a memory 12, and a pci express slot, the cpu 11 is electrically connected to the memory 12 and the pci express slot by physical lines, the cpu 11 has thread node data (for example, the thread node data of the SRC portion of the cpu 11 is only illustrated herein and is not limited to the application scope of the present invention), the memory 12 has a storage address (for example, the storage address of the DST address of the memory 12 is only illustrated herein and is not limited to the application scope of the present invention), and the thread node data is stored when transmitted to the storage address.
The pci data device 20 is inserted into the pci slot, the process of transferring thread node data is as follows, the first non-transparent bridge device 211 receives thread node data from the second cpu 11, the second non-transparent bridge device 221 receives thread node data from the first non-transparent bridge device 211 through the internal line, the second non-transparent bridge device 221 transfers thread node data to the downstream port device 213 through the physical pci slot, the downstream port device 213 receives thread node data from the second non-transparent bridge device 221 through the physical pci slot, the downstream port device 213 transfers thread node data to the upstream port device 212 through the internal line, the upstream port device 212 receives thread node data from the downstream port device 213 through the internal line, and the upstream port device 212 transfers thread node data to the storage address of the memory 12 through the pci slot and stores the thread node data.
The data transmission process of the thread node data is a data transmission process in a PIO mode of PCIe data (peripheral component interconnect express) transmission, the central processing unit 11 is used as an initiating terminal of data transmission to actively initiate data transmission to the PCIe device, a data transmission process in a DMA mode of PCIe data transmission will be described below, and the PCIe device is used as an initiating terminal of data transmission to actively initiate data transmission to the memory.
The PCI express data transmission control system further includes PCI express devices electrically connected to the memory 12 and PCI express slots by physical lines, respectively, the PCI express devices have data, the first non-transparent bridge device 211 receives data from the PCI express devices, the second non-transparent bridge device 221 receives data from the first non-transparent bridge device 211 through internal lines, the downstream port device 213 receives data from the second non-transparent bridge device 221 through the physical PCI express lines, the upstream port device 212 receives data from the downstream port device 213 through internal lines, and the upstream port device 213 transmits data to the storage address of the memory 12 through the PCI express slots and stores the data.
The PCI express data transmission control system further comprises a detection device, wherein the detection device is electrically connected with the host board, and respectively obtains thread node data or data from the CPU 11 and obtains thread node data or data stored in the storage address from the memory 12 for comparison so as to verify the thread node data or data after data transmission.
The following first describes a PCI express data transmission control system according to a second embodiment of the present invention, and referring to FIG. 2, FIG. 2 is a system block diagram of a PCI express data transmission control system according to a second embodiment of the present invention.
The PCI express data transmission control system according to the second embodiment of the present invention comprises: motherboard and PCI express data device 20, PCI express data device 20 further comprises: a first partition 21 and a second partition 22, the first partition 21 further comprising: the first non-transparent bridge device 211, the upstream port device 212, and the downstream port device 213, and the second partition 22 further includes: a second non-transparent bridging device 221.
The motherboard has a first cpu 111, a second cpu 112, a memory 12, and a pci slot, where the first cpu 111 is electrically connected to the second cpu 112, the memory 12, and the pci slot by physical lines, respectively, the second cpu 112 has thread node data (for example, thread node data of the SRC portion of the second cpu 112 is only illustrated herein and is not limited in scope by the present invention), the memory 12 has a storage address (for example, a storage address of the DST address of the memory 12 is only illustrated herein and is not limited in scope by the present invention), and the thread node data is stored when transferred to the storage address.
The pci data device 20 is inserted into the pci slot, and the data transmission process of the thread node data is as follows, where the first non-transparent bridge device 211 receives the thread node data from the second cpu 11 through the first cpu 11, the first non-transparent bridge device 211 receives the thread node data from the second cpu 11, the second non-transparent bridge device 221 receives the thread node data from the first non-transparent bridge device 211 through the internal line, the second non-transparent bridge device 221 transmits the thread node data to the downstream port device 213 through the physical pci link, the downstream port device 213 receives the thread node data from the second non-transparent bridge device 221 through the physical pci link, the downstream port device 213 transmits the thread node data to the upstream port device 212 through the internal line, the upstream port device 212 receives the thread node data from the downstream port device 213 through the internal line, and the upstream port device 212 transmits the thread node data to the storage address of the memory 12 through the pci slot and stores the thread node data.
The data transmission process of the thread node data is a data transmission process in a PIO mode of PCIe data transmission, the central processing unit 11 is used as an initiating terminal of data transmission to actively initiate data transmission to the PCIe device, the data transmission process in a DMA mode of PCIe data transmission will be described below, and the PCIe device is used as an initiating terminal of data transmission to actively initiate data transmission to the memory.
The PCI express data transmission control system further comprises a first PCI express device and a second PCI express device, wherein the first PCI express device is electrically connected with the second PCI express device, the memory 12 and the PCI express slot respectively in a physical circuit, the second PCI express device is provided with data, the first non-transparent bridge device 211 receives the data from the second PCI express device through the first PCI express device, the second non-transparent bridge device 221 receives the data from the first non-transparent bridge device 211 through an internal circuit, the downstream port device 213 receives the data from the second non-transparent bridge device 221 through the physical PCI express device, the upstream port device 212 receives the data from the downstream port device 213 through an internal circuit, and the upstream port device 213 transmits the data to a storage address of the memory 12 through the PCI express slot and stores the data.
The PCI express data transmission control system further comprises a detection device, wherein the detection device is electrically connected with the host board, and respectively obtains thread node data or data from the CPU 11 and obtains thread node data or data stored in the storage address from the memory 12 for comparison so as to verify the thread node data or data after data transmission.
The following first describes a PCI express data transmission control system according to a third embodiment of the present invention, and referring to FIG. 3, FIG. 3 is a system block diagram of a PCI express data transmission control system according to a third embodiment of the present invention.
The PCI express data transmission control system according to the third embodiment of the present invention comprises: motherboard, first PCI express data device 201, and second PCI express data device 202, first PCI express data device 201 further comprises: a first partition 23 and a second partition 24, the first partition 23 further comprising: the first non-transparent bridge device 231, the first upstream port device 232, and the first downstream port device 233, and the second partition 24 further includes: a second non-transparent bridging device 241; the second PCI express data device 202 further includes: third partition 25 and fourth partition 26, third partition 25 further comprises: the third non-transparent bridge device 251, the third upstream port device 252, and the third downstream port device 253, and the fourth partition 26 further includes: fourth non-transparent bridging device 261.
The motherboard has a cpu 11, a memory 12, a pci express switch 14, a first pci express switch 14, and a second pci express switch 14, wherein the cpu 11 is electrically connected to the memory 12 and the pci express switch 14 by physical lines, respectively, the cpu 11 has thread node data (for example, the thread node data of the SRC portion of the cpu 11 is only illustrated herein and not limited to the application scope of the present invention), the memory 12 has a storage address (for example, the storage address of the DST address of the memory 12 is only illustrated herein and not limited to the application scope of the present invention), and the thread node data is stored when transmitted to the storage address.
The first pci express data device 20 is inserted into the first pci express slot, the data transmission process of the thread node data is as follows, the first non-transparent bridge device 231 is electrically connected with the pci express switch 14 by a physical line, the first non-transparent bridge device 231 receives the thread node data from the cpu 11 through the pci express switch 14, the second non-transparent bridge device 241 receives the thread node data from the first non-transparent bridge device 231 through an internal line, the second non-transparent bridge device 241 transmits the thread node data to the first downlink port device 233 through the physical pci express interconnect line, the first downlink port device 233 receives the thread node data from the second non-transparent bridge device 241 through the physical pci express interconnect line, the first downlink port device 233 transmits the thread node data to the first uplink port device 232 through the internal line, the first uplink port device 232 receives the thread node data from the first downlink port device 233 through the internal line, and the first uplink port device 232 transmits the thread node data to the third non-transparent bridge device 251 through the pci express slot and the pci express switch 14.
The fourth non-transparent bridge device 261 receives the thread node data from the third non-transparent bridge device 251 through the internal line, the fourth non-transparent bridge device 261 transmits the thread node data to the third downstream port device 253 through the physical PCI express line, the third downstream port device 253 receives the thread node data from the fourth non-transparent bridge device 261 through the physical PCI express line, the third downstream port device 253 transmits the thread node data to the third upstream port device 252 through the internal line, the third upstream port device 252 receives the thread node data from the third downstream port device 253 through the internal line, and the third upstream port device 252 transmits the thread node data to the storage address of the memory 12 through the PCI express slot and the PCI express switch 14 and stores the thread node data.
The data transmission process of the thread node data is a data transmission process in a PIO mode of PCIe data transmission, the central processing unit 11 is used as an initiating terminal of data transmission to actively initiate data transmission to the PCIe device, the data transmission process in a DMA mode of PCIe data transmission will be described below, and the PCIe device is used as an initiating terminal of data transmission to actively initiate data transmission to the memory.
The PCI express data transfer control system further includes PCI express devices electrically connected to the memory 12 and the PCI express switch 14 by physical lines, respectively, the PCI express devices having data, the first non-transparent bridge device 231 receiving data from the PCI express devices through the PCI express switch 14, the second non-transparent bridge device 241 receiving data from the first non-transparent bridge device 231 by internal lines, the first downstream port device 233 receiving data from the second non-transparent bridge device 241 by the PCI express lines, the first upstream port device 232 receiving data from the first downstream port device 233 by internal lines, the first upstream port device 232 transmitting data to the third non-transparent bridge device 251 by the PCI express slots and the PCI express switch 14, the fourth non-transparent bridge device 261 receiving data from the third non-transparent bridge device 251 by internal lines, the third downstream port device receiving data from the fourth non-transparent bridge device 231 by the PCI express lines, the third downstream port device 253 receiving data from the third downstream port device 252 by the internal lines, and storing data from the third downstream port device 253 to the peripheral device through the PCI express switch 14 and storing the data to the peripheral device 12.
The PCI express data transmission control system further comprises a detection device, wherein the detection device is electrically connected with the host board, and respectively obtains thread node data or data from the CPU 11 and obtains thread node data or data stored in the storage address from the memory 12 for comparison so as to verify the thread node data or data after data transmission.
In summary, the difference between the present invention and the prior art is that the pci express device is divided into a first partition and a second partition, the first partition includes a first non-transparent bridging device, an uplink port device and a downlink port device, the second partition includes a second non-transparent bridging device, the cpu thread node data is transferred to the first non-transparent bridging device, the first non-transparent bridging device transfers the thread node data to the second non-transparent bridging device through an internal circuit, the second non-transparent bridging device transfers the thread node data to the downlink port device through an physical pci express device interconnect circuit, the downlink port device transfers the thread node data to the uplink port device through an internal circuit, and the uplink port device transfers the thread node data to a storage address of the memory through a pci express device interconnect slot and stores the thread node data.
The technical means can solve the problem that the prior art cannot set the data transmission process of the standard PCI express device, thereby achieving the technical effect of providing the data transmission process setting of the standard PCI express device.
Although the embodiments of the present invention are described above, the disclosure is not intended to limit the scope of the present invention. Workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. The scope of the invention is to be defined only by the appended claims.
Claims (9)
1. A PCI express data transmission control system, comprising:
the system comprises a motherboard, a memory and a PCI express slot, wherein the motherboard is provided with a central processing unit, a memory and a PCI express slot, the central processing unit is respectively and electrically connected with the memory and the PCI express slot through physical lines, the central processing unit is provided with thread node data, the memory is provided with a storage address, and the thread node data is stored when being transmitted to the storage address; and
A PCI express data device that is inserted into the PCI express slot, the PCI express data device further comprising:
a first partition, the first partition further comprising:
the first non-transparent bridging device receives the thread node data from the second central processing unit;
an upstream port device for receiving the thread node data via an internal line, transmitting the thread node data to the storage address of the memory via the PCI express slot, and storing the thread node data; and
The downlink port equipment receives the thread node data through an entity rapid peripheral component interconnection line and transmits the thread node data to the uplink port equipment through an internal line; and
A second partition, the second partition further comprising:
and the second non-transparent bridging device receives the thread node data from the first non-transparent bridging device through an internal line and transmits the thread node data to the downlink port device through an entity rapid peripheral component interconnection line.
2. The PCI express data transmission control system of claim 1 further comprising a PCI express device electrically connected to the memory and the PCI express slot, respectively, the PCI express device having data, the first non-transparent bridge device receiving the data from the PCI express device, the second non-transparent bridge device receiving the data from the first non-transparent bridge device over an internal line, the downstream port device receiving the data from the second non-transparent bridge device over an internal line, the upstream port device receiving the data from the downstream port device over an internal line, the upstream port device transmitting the data to the storage address of the memory and storing the data.
3. The PCI express data transmission control system of claim 1, further comprising a detection device electrically connected to the host board, wherein the detection device obtains the thread node data from the CPU and obtains the thread node data stored in the storage address from the memory and compares the thread node data to verify the thread node data after data transmission.
4. A PCI express data transmission control system, comprising:
the system comprises a motherboard, a first CPU, a second CPU, a memory and a PCI express slot, wherein the first CPU is electrically connected with the second CPU, the memory and the PCI express slot through physical lines respectively, the second CPU is provided with thread node data, the memory is provided with a storage address, and the thread node data is stored when being transmitted to the storage address; and
A PCI express data device that is inserted into the PCI express slot, the PCI express data device further comprising:
a first partition, the first partition further comprising:
a first non-transparent bridging device that receives the thread node data from the second central processor through the first central processor;
an upstream port device for receiving the thread node data via an internal line, transmitting the thread node data to the storage address of the memory via the PCI express slot, and storing the thread node data; and
The downlink port equipment receives the thread node data through an entity rapid peripheral component interconnection line and transmits the thread node data to the uplink port equipment through an internal line; and
A second partition, the second partition further comprising:
and the second non-transparent bridging device receives the thread node data from the first non-transparent bridging device through an internal line and transmits the thread node data to the downlink port device through an entity rapid peripheral component interconnection line.
5. The PCI express data transmission control system of claim 4, further comprising a first PCI express device and a second PCI express device, wherein the first PCI express device is electrically connected to the second PCI express device, the memory, and the PCI express slots, respectively, by physical lines, the second PCI express device has data, the first PCI express device receives the data from the second PCI express device via the first PCI express device, the second PCI express device receives the data from the first PCI express device via an internal line, the downstream port device receives the data from the second PCI express device via a physical PCI express line, the upstream port device receives the data from the downstream port device via an internal line, and the upstream port device transmits the data to the memory via the PCI express slot for storage.
6. The PCI express data transmission control system of claim 4, further comprising a detection device electrically connected to the motherboard, wherein the detection device obtains the thread node data from the second CPU and obtains the thread node data stored in the storage address from the memory and compares the thread node data to verify the thread node data after data transmission.
7. A PCI express data transmission control system, comprising:
the system comprises a motherboard, a first PCI express device and a second PCI express device, wherein the motherboard is provided with a central processing unit, a memory, a PCI express device interconnection switch, a first PCI express device interconnection slot and a second PCI express device interconnection slot, the central processing unit is respectively and electrically connected with the memory and the PCI express device interconnection switch through physical lines, the central processing unit is provided with thread node data, the memory is provided with a storage address, and the thread node data is stored when being transmitted to the storage address;
a first PCI express data device that is inserted into the first PCI express slot, the first PCI express data device further comprising:
a first partition, the first partition further comprising:
the first non-transparent bridging device is electrically connected with the rapid peripheral component interconnection switch through a physical circuit, and receives the thread node data from the central processing unit through the rapid peripheral component interconnection switch;
the first uplink port equipment receives the thread node data through an internal line and transmits the thread node data through the PCI express slot and the PCI express switch; and
The first downlink port equipment receives the thread node data through an entity rapid peripheral component interconnection line and transmits the thread node data to the first uplink port equipment through an internal line; and
A second partition, the second partition further comprising:
the second non-transparent bridging device receives the thread node data from the first non-transparent bridging device through an internal line and transmits the thread node data to the first downlink port device through an entity rapid peripheral component interconnect line; and
A second PCI express data device that is inserted into the second PCI express slot, the second PCI express data device further comprising:
a third partition, the third partition further comprising:
a third non-transparent bridge device electrically connected to the PCI express switch by a physical line, the third non-transparent bridge device receiving the thread node data from the first upstream port device through the PCI express slot and the PCI express switch;
a third upstream port device for receiving the thread node data via an internal line, and transmitting the thread node data to the storage address of the memory via the PCI express slot and the PCI express switch, and storing the thread node data; and
The third downlink port device receives the thread node data through an entity rapid peripheral component interconnection line and transmits the thread node data to the third uplink port device through an internal line; and
A fourth partition, the fourth partition further comprising:
and the fourth non-transparent bridging device receives the thread node data from the third non-transparent bridging device through an internal line and transmits the thread node data to the third downlink port device through an entity rapid peripheral component interconnection line.
8. The PCI express data transmission control system of claim 7, further comprising a PCI express device electrically connected to the memory and the PCI express switch in physical lines, respectively, the PCI express device having data, the first non-transparent bridge device receiving the data from the PCI express device through the PCI express switch, the second non-transparent bridge device receiving the data from the first non-transparent bridge device through an internal line, the first downstream port device receiving the data from the second non-transparent bridge device through an physical PCI express line, the first upstream port device receiving the data from the first downstream port device through an internal line, the first upstream port device transmitting the data to the third non-transparent bridge device through the PCI express switch, the second non-transparent bridge device receiving the data from the third non-transparent bridge device through an internal line, the third downstream port device receiving the data from the third non-transparent bridge device through an internal line, the third upstream port device receiving the data from the third non-transparent bridge device through the third non-transparent bridge device, the third upstream port device transmits the data to the storage address of the memory through the PCI express slot and the PCI express switch and stores the data.
9. The PCI express data transmission control system of claim 7, further comprising a detection device electrically connected to the motherboard, wherein the detection device obtains the thread node data from the CPU and obtains the thread node data stored in the storage address from the memory and compares the thread node data to verify the thread node data after data transmission.
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