WO2014094417A1 - 阻变存储器及其制备方法 - Google Patents
阻变存储器及其制备方法 Download PDFInfo
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- WO2014094417A1 WO2014094417A1 PCT/CN2013/079020 CN2013079020W WO2014094417A1 WO 2014094417 A1 WO2014094417 A1 WO 2014094417A1 CN 2013079020 W CN2013079020 W CN 2013079020W WO 2014094417 A1 WO2014094417 A1 WO 2014094417A1
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- Prior art keywords
- conductive
- bottom electrode
- resistive
- layer
- forming
- Prior art date
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- 238000002360 preparation method Methods 0.000 title abstract description 7
- 230000015654 memory Effects 0.000 claims description 54
- 239000000463 material Substances 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 26
- 239000004020 conductor Substances 0.000 claims description 23
- 238000002955 isolation Methods 0.000 claims description 22
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 238000005498 polishing Methods 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000003518 caustics Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000003487 electrochemical reaction Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
- H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8416—Electrodes adapted for supplying ionic species
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8418—Electrodes adapted for focusing electric field or current, e.g. tip-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
Definitions
- resistive memory With the charge-type non-volatile memory represented by Flash gradually approaching the physical limit, resistive memory has been widely studied as a technology that is very likely to replace the charge-type non-volatile memory in the past decade. Compared to other types of non-volatile memories, resistive memory has the following advantages: simple structure, high speed, compatibility with existing field effect transistor fabrication techniques, greater potential for further scaling down, and multi-value storage.
- Conductive filament theory has been widely recognized in the academic community as a conductive mechanism for resistive memory. This theory holds that the resistance change of a resistive memory is due to the formation and fracture of conductive filaments connecting the electrodes at both ends of the resistive material. To: Under the action of an external electric field, oxygen vacancies or metal ions in the resistive material migrate and electrochemical reactions occur to form conductive filaments. When the conductive filaments are formed and connected to the electrodes at both ends, the resistive memory enters a low resistance. State; under the action of heat or reverse electric field, the filament part is even completely broken, so that the resistive memory enters a high resistance state.
- Embodiments of the present invention provide a resistive memory and a method for fabricating the same.
- a conductive bump on a bottom electrode of a resistive memory By providing a conductive bump on a bottom electrode of a resistive memory, a "lightning rod" effect is generated, which greatly improves the stability of formation and fracture of the conductive filament.
- an embodiment of the present invention provides a resistive memory including a bottom electrode, a resistive layer, and a top electrode, wherein the resistive layer is located above the bottom electrode; and the top electrode is located in the resistive layer a conductive protrusion is disposed on the bottom electrode, the conductive protrusion is embedded in the resistive layer, and a top width of the conductive protrusion is smaller than a bottom Part width.
- an embodiment of the present invention further provides a method for fabricating a resistive memory, comprising: forming a bottom electrode on a substrate; forming a conductive protrusion having a top width smaller than a bottom width on the bottom electrode; A resistive layer is formed on the electrode and the conductive protrusion, and the conductive protrusion is embedded inside the resistive layer; a top electrode is formed on the resistive layer.
- the resistive memory provided by the embodiment of the present invention can generate a "lightning rod" effect by providing conductive protrusions on the bottom electrode, so that the electric field in the resistive layer is concentrated in the vicinity of the conductive protrusions, which is extremely large.
- the probability of the conductive filaments being generated at the conductive protrusions is increased, so that the generation of the conductive filaments is no longer random, ensuring the stability of various parameters in the resistive memory, thereby greatly improving the reliability and stability of the work of the resistive memory. Sex.
- FIG. 1 is a schematic structural diagram of a resistive memory according to an embodiment of the present invention.
- FIG. 2 is another schematic structural diagram of a resistive memory according to an embodiment of the present invention.
- FIG. 3 is a flow chart of a method for preparing a resistive memory provided by an embodiment of the present invention.
- FIG. 4 is a flow chart of another method for preparing a resistive memory provided by an embodiment of the present invention.
- 5 to 10 are schematic diagrams of preparing a resistive memory provided by an embodiment of the present invention.
- FIG. 11 is another schematic diagram of the resistive memory provided by the embodiment of the present invention. detailed description
- FIG. 1 is a schematic structural diagram of a resistive memory according to an embodiment of the present invention.
- the resistive memory includes a bottom electrode 11, a resistive layer 12, and a top electrode 14.
- the resistive layer 12 is located above the bottom electrode 11; the top electrode 14 is located above the resistive layer 12.
- a conductive protrusion 13 is disposed on the bottom electrode 11, and the conductive protrusion 13 is embedded in the resistive layer 12, and the top width of the conductive protrusion 13 is smaller than the bottom width. It should be noted that the top of the conductive protrusion is The portion near the top electrode and the bottom portion are located at the bottom electrode.
- the width of the top of the conductive protrusion 13 ranges from lOnm to 30.
- the width range is close to the diameter range of the conductive filament, and the growth path of the conductive filament can be better controlled.
- the conductive protrusions 13 may have a growth thickness ranging from 40 nm to 60 nm.
- the material forming the conductive protrusions 13 is any known or imminently active metal conductive material, and may be, for example, any of Cu Al Ti TiN Ag and M.
- the material forming the bottom electrode 11 is any known or imminent inert metal conductive material, and may be, for example, Pt or Au. It should be noted that in order to form the conductive protrusions during etching, the bottom electrode is not etched, and a more active conductive material is selected as the material of the conductive protrusions with respect to the material of the bottom electrode, and at the same time, such an arrangement is advantageous for resisting
- the memory can form conductive filaments more quickly and more stably under the action of an external electric field.
- the bottom electrode 11 may have a thickness ranging from 50 nm to 200 nm; the top electrode 14 may have a thickness ranging from 50 nm to 200 nm; and the material forming the top electrode 14 is any known or upcoming.
- Metal conductive material for example, may be Pt or Au
- the growth thickness of the top electrode and the growth thickness of the bottom electrode may be the same or different, and the material forming the top electrode and the material forming the bottom electrode may be the same or different, and are not limited herein. .
- the resistive layer 12 may have a thickness ranging from 70 nm to 100 nm, wherein the resistive layer
- the thickness of the layer 12 is greater than the thickness of the conductive protrusions 13. Specifically, the thickness difference between the resistive layer 12 and the conductive protrusions 13 can be determined according to specific conditions, which is not limited in the present invention.
- the present invention also provides another structure of a resistive memory as shown in FIG.
- the resistive memory of the embodiment includes a bottom electrode 21, a resistive layer 23, a top electrode 25 and a conductive protrusion 24, and is disposed on both sides of the conductive protrusion 24 on the bottom electrode 21.
- the bottom electrode 21, the resistive layer 23, the top electrode 25, and the conductive protrusions 24 are similar to the bottom electrode, the resistive layer, the top electrode, and the conductive protrusions in the above embodiments, and are not described herein again.
- the material forming the isolation layer may be silicon nitride.
- the isolation layer can function as an electrical isolation between adjacent resistive memories; meanwhile, in the process of preparing the resistive memory, performing chemical mechanical polishing on the resistive layer
- the separator can also be used as a stop layer during the process steps.
- the resistive memory provided by the embodiment of the present invention can generate a "lightning rod" effect by providing conductive protrusions on the bottom electrode, so that the electric field in the resistive layer is concentrated in the vicinity of the conductive protrusions, which is extremely large.
- the probability of the conductive filaments being generated at the conductive protrusions is increased, so that the generation of the conductive filaments is no longer random, ensuring the stability of various parameters in the resistive memory, thereby greatly improving the reliability and stability of the work of the resistive memory. Sex.
- the embodiment of the invention further provides a method for preparing a resistive memory.
- FIG. 3 it is a flowchart of a method for preparing a resistive memory in an embodiment of the present invention, and the method may include the following steps.
- Step 101 forming a bottom electrode on the substrate.
- the substrate may be a polysilicon substrate or other semiconductor substrate; the bottom electrode may be deposited by chemical vapor deposition or physical vapor deposition.
- the thickness of the bottom electrode ranges from 50 nm to 200 nm, and the specific thickness may be determined according to different conditions, and is not limited herein.
- the material forming the bottom electrode may be any known or upcoming material, for example, may be Pt or Au.
- Step 102 forming a conductive protrusion having a top width smaller than a bottom width on the bottom electrode.
- One of the methods of forming the conductive bumps may include the following steps.
- a layer of active conductive material (the active conductive material refers to a conductive material which is more active than the bottom electrode material) is deposited on the bottom electrode 31 by chemical vapor deposition or physical vapor deposition; As shown in FIG. 6, the active conductive material is etched by wet etching using an anisotropy of a conductive material to form conductive bumps 32 having a top width smaller than a bottom width.
- the top surface of the conductive protrusion 32 has a width ranging from 10 nm to 30 nm, and the conductive protrusion 32 has a thickness ranging from 40 nm to 60 nm.
- the material forming the conductive protrusion 32 is any known or upcoming metal conductive.
- the material for example, may be any of Cu, Al, Ti, TiN, Ag, and M.
- the choice of etchant is related to the specific conductive material, and the etchant is not required to be opposite to the bottom electrode. Should be or very slow reaction, the concentration of corrosive agent is low, the rate of corrosive corresponding active conductive material is controlled at 5-30 ang/sec, and attention should be paid to the corrosion during corrosion to ensure the stability and anisotropy of the concentration of the corrosive agent.
- Step 103 forming a resistive layer on the bottom electrode and the conductive protrusion, and embedding the conductive protrusion inside the resistive layer.
- One of the methods of forming the resistive layer may include the following steps.
- a resistive material is deposited by chemical vapor deposition or physical vapor deposition, and since the conductive bumps 32 protrude on the bottom electrode 31, the deposition resistance is caused.
- the upper end surface of the material is not flat; as shown in FIG. 8, the conductive protrusion 32 is used as a stop layer, and the resistive material is chemically mechanically polished to form a first resistive layer 331 whose upper end surface is flat; as shown in FIG.
- a resistive material is again deposited on the first resistive layer 331 to form a second resistive layer 332 (the dotted line is shown for clarity, clearly indicating the range represented by the first resistive layer and the second resistive layer,
- the first resistive layer 331 and the second resistive layer 332 together form the resistive layer 33, which is not included in the embodiment of the present invention and does not impose any limitation on the present invention.
- the first resistive layer is formed and the material forming the second resistive layer is the same.
- the resistive layer has a thickness ranging from 70 nm to 100 nm.
- Step 104 forming a top electrode on the resistive layer.
- a top electrode 34 is deposited by chemical vapor deposition or physical vapor deposition.
- the thickness of the top electrode 34 may range from 50 nm to 200 nm; the material forming the top electrode 34 is any known or upcoming metal conductive material, for example, may be Pt or Au.
- the growth thickness of the top electrode 34 and the growth thickness of the bottom electrode 31 may be the same or different, and the material forming the top electrode 34 and the material forming the bottom electrode 31 may be the same or different. There are no restrictions here.
- the method for preparing the resistive memory provided by the embodiment by using the conventional preparation method, by providing conductive protrusions on the bottom electrode, can generate a "lightning rod" effect, so that the electric field in the resistive layer is concentrated in the vicinity of the conductive protrusions,
- the large increase in the probability of the conductive filaments being generated at the conductive protrusions makes the generation of the conductive filaments no longer random, ensuring the stability of various parameters in the resistive memory, thereby greatly improving the reliability of the work of the resistive memory. And stability.
- FIG. 4 it is a flowchart of another method for preparing a resistive memory according to an embodiment of the present invention. The method includes the following steps.
- Step 201 forming a bottom electrode on the substrate.
- a 150 nm Pt bottom electrode was deposited on the polycrystalline silicon substrate by chemical vapor deposition.
- Step 202 forming an isolation layer over the bottom electrode.
- a 50 nm thick silicon nitride was deposited as a spacer layer 42 by chemical vapor deposition on the Pt bottom electrode 41.
- Step 203 etching a window for forming a conductive protrusion on the bottom electrode on the isolation layer.
- the step specifically includes: applying a photoresist on the silicon nitride isolation layer 42; forming a square window of a lattice w m *w m in a middle portion of the silicon nitride; and photolithography layering the silicon nitride layer at the window portion from the bottom.
- the electrodes are all removed, and as shown in Fig. 12, a window (or a hole) for forming a conductive protrusion with the bottom electrode 41 as a base is formed.
- Step 204 depositing a living conductive material at a window of the conductive protrusion.
- the step may be to first thermally evaporate a layer of copper seed crystals, and then electrochemically deposit a layer of 100 nm thick copper on the bottom electrode 41 and the isolation layer 42.
- Step 205 Perform chemical mechanical polishing treatment on the active conductive material with the isolation layer as a stopping layer.
- the silicon nitride isolation layer 42 is used as a stop layer, and the active conductive material copper is subjected to a chemical mechanical polishing treatment such that the active conductive material copper and the silicon nitride isolation layer 42 are at the bottom electrode 41.
- the thickness is the same, both are 50 nm.
- Step 206 wet etching the active conductive material to form the conductive protrusion.
- the active conductive material copper is etched by wet etching to form conductive bumps 43 having a top width greater than the bottom width.
- the pt bottom electrode 41 is overetched.
- Step 207 forming a first resistive layer on the bottom electrode and the conductive protrusion and the isolation layer.
- a 00 nm thick resistive material yttria is grown as a first resistive layer 441 on the Pt bottom electrode 41 and the copper conductive bumps 43 and the silicon nitride spacer 42 by chemical vapor deposition.
- Step 208 performing chemical mechanical polishing treatment on the first resistive layer with the isolation layer as a stop layer.
- the silicon nitride spacer 42 is used as a stop layer, and the ruthenium oxide layer is treated by chemical mechanical polishing to smooth the upper end surface while making the thickness of the first resistive layer 441 and the conductive bumps and
- the spacer layer 42 has the same thickness and is 50 nm.
- Step 209 forming a second resistive layer on the first resistive layer after the chemical mechanical polishing treatment.
- the first resistance after chemical mechanical polishing is also used by chemical vapor deposition.
- a 30 nm thick resistive material yttrium oxide is grown on the variable layer 441 as the second resistive layer 442 (the dotted line is shown for clarity, clearly showing the first resistive layer and the second resistive layer)
- the range of the representation is not included in the embodiment of the present invention, nor does it impose any limitation on the present invention.
- the first resistive layer 441 and the second resistive layer 442 together form the resistive layer 44.
- Step 210 forming a top electrode on the second resistive layer.
- a 200 nm metal Pt was vapor-deposited on the resistive layer 44 by electron beam evaporation as the top electrode 45.
- the resistive layer is formed by the first resistive layer 441 and the second resistive layer 442 located above the first resistive layer 441, so the top electrode 45 is grown on the resistive layer 44.
- the top electrode 45 is grown on the second resistive layer 442.
- the present embodiment is only an example.
- the forming material, the growth method, and the thickness of each portion of the bottom electrode, the conductive protrusion, the resistive layer, the isolation layer, and the top electrode in the resistive memory provided by the present invention are not limited to the embodiment.
- Other suitable forming materials, growth methods, and thicknesses may also be listed, and are not described herein.
- the resistive memory and the preparation method thereof provided by the embodiments of the present invention can generate a "lightning rod" effect by providing conductive protrusions on the bottom electrode, so that the electric field in the resistive layer is concentratedly distributed in the vicinity of the conductive protrusions, which greatly increases The probability that the conductive filaments are generated at the conductive protrusions makes the generation of the conductive filaments no longer random, ensuring the stability of various parameters in the resistive memory, thereby greatly improving the reliability and stability of the work of the resistive memory.
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US14/354,919 US9281476B2 (en) | 2012-12-19 | 2013-07-08 | Resistive memory and method for fabricating the same |
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CN2012105553736A CN103035840A (zh) | 2012-12-19 | 2012-12-19 | 阻变存储器及其制备方法 |
CN201210555373.6 | 2012-12-19 |
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CN (1) | CN103035840A (zh) |
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Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
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CN103035840A (zh) * | 2012-12-19 | 2013-04-10 | 北京大学 | 阻变存储器及其制备方法 |
US9444040B2 (en) * | 2013-03-13 | 2016-09-13 | Microchip Technology Incorporated | Sidewall type memory cell |
CN103594622B (zh) * | 2013-11-28 | 2016-10-05 | 北京大学 | 高一致性的阻变存储器结构及其制备方法 |
US10003021B2 (en) | 2014-02-19 | 2018-06-19 | Microchip Technology Incorporated | Resistive memory cell with sloped bottom electrode |
US9318702B2 (en) | 2014-02-19 | 2016-04-19 | Microchip Technology Incorporated | Resistive memory cell having a reduced conductive path area |
US9385313B2 (en) | 2014-02-19 | 2016-07-05 | Microchip Technology Incorporated | Resistive memory cell having a reduced conductive path area |
CN107004766A (zh) | 2014-11-26 | 2017-08-01 | 密克罗奇普技术公司 | 具有用于经减少的导电路径区域/经增强的电场的间隔物区域的电阻式存储器单元 |
CN106299108B (zh) * | 2015-05-25 | 2019-08-23 | 中国科学院苏州纳米技术与纳米仿生研究所 | 阻变存储器及其制备方法 |
GB2561168B (en) * | 2017-03-31 | 2019-08-07 | Ucl Business Plc | A switching resistor and method of making such a device |
CN108565338A (zh) * | 2018-05-21 | 2018-09-21 | 华中科技大学 | 一种局域电场增强忆阻器及其制备方法 |
CN109920911B (zh) * | 2019-03-06 | 2023-04-25 | 中国科学院微电子研究所 | 阻变存储器的制备方法 |
CN111987217A (zh) * | 2020-08-25 | 2020-11-24 | 上海华力微电子有限公司 | Rram单元结构及其制造方法 |
US11502252B2 (en) * | 2020-11-19 | 2022-11-15 | International Business Machines Corporation | Resistive switching memory cell |
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US8023302B2 (en) * | 2005-01-31 | 2011-09-20 | Semiconductor Energy Laboratory Co., Ltd. | Memory device and semiconductor device |
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CN101488555A (zh) * | 2009-02-10 | 2009-07-22 | 中国科学院上海微系统与信息技术研究所 | 一种低功耗相变存储器的制备方法 |
CN102738386A (zh) * | 2011-03-31 | 2012-10-17 | 中国科学院微电子研究所 | 阻变存储器及其制造方法 |
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2012
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2013
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Patent Citations (4)
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US20110227045A1 (en) * | 2009-01-28 | 2011-09-22 | Julien Borghetti | Voltage-Controlled Switches |
CN102157688B (zh) * | 2011-03-23 | 2012-07-18 | 北京大学 | 一种阻变存储器及其制备方法 |
CN102708919A (zh) * | 2011-03-28 | 2012-10-03 | 中国科学院微电子研究所 | 阻变存储器及其制造方法 |
CN103035840A (zh) * | 2012-12-19 | 2013-04-10 | 北京大学 | 阻变存储器及其制备方法 |
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