WO2014086105A1

WO2014086105A1 - Method for manufacturing net-shaped array structure of mono-crystalline silicon nano-wires

Info

Publication number: WO2014086105A1
Application number: PCT/CN2013/070357
Authority: WO
Inventors: 俞骁; 李铁; 王跃林
Original assignee: 中国科学院上海微系统与信息技术研究所
Priority date: 2012-12-04
Filing date: 2013-01-11
Publication date: 2014-06-12
Also published as: CN102963862A; CN102963862B

Abstract

Disclosed is a method for manufacturing a net-shaped array structure of mono-crystalline silicon nano-wires, comprising the following steps: 1) providing a mono-crystalline silicon substrate with a crystal face (111) and manufacturing an anti-oxidation mask on the surface thereof; 2) forming a plurality of mask windows having a pre-set shape according to a pre-set arrangement rule in the anti-oxidation mask by using a photo-etching process; 3) etching the mono-crystalline silicon under each mask window to a pre-set depth using an ICP etching method; 4) performing anisotropic wet corrosion on the mono-crystalline silicon under each mask window, thus forming a plurality of corrosion grooves with the upper and lower surfaces thereof being hexagonal and forming a thin wall of mono-crystalline silicon between the side walls of two adjacent corrosion grooves; 5) performing heat oxidization on the obtained structure above by a self-limiting oxidation process so as to gradually oxidize the thin walls of mono-crystalline silicon, and finally forming mono-crystalline silicon nano-wires extending along the length direction of the thin walls of mono-crystalline silicon in the central regions at the top of the thin walls of mono-crystalline silicon; and 6) removing the anti-oxidation mask and the silicon oxide formed during the oxidation, thereby forming the net-shaped array structure of mono-crystalline silicon nano-wires. The method is simple and highly efficient, the core steps thereof only involving conventional photo-etching, corrosion process, anti-oxidization mask and anisotropic corrosion, and under the conditions for conventional mask preparation and photo-etching, the method can be used for manufacturing combined patterns of mono-crystalline silicon nano-wires on a large scale on silicon chips using the crystal face distribution characteristic in the silicon chip with a crystal face (111).

Description

Single crystal silicon nanowire mesh array structure manufacturing method

Technical field

The present invention relates to a method of fabricating a silicon nanowire, and more particularly to a method of fabricating a monocrystalline silicon nanowire mesh array structure. Background technique

With the development of nanoscience and technology, the nanostructure of materials is more and more valued by researchers because they often exhibit different characteristics from their macroscopic state. It is hoped that through the development of nanostructures such as electrical, thermal, optical and mechanical properties. Research, in order to better understand the various effects at the nanoscale, to achieve a deeper understanding of the relationship between the microstructure of the material and its properties, and thus design and manufacture applications with better performance. As a standard material for CMOS technology and MEMS technology, research on monocrystalline silicon nanostructures and nanodevices is particularly popular. Studies have shown that monocrystalline silicon exhibits a variety of valuable physical properties under a (quasi) one-dimensional nanowire structure. For example, the piezoresistive coefficient of silicon nanowires is increased by more than 50% compared with bulk silicon materials; the thermoelectric figure of merit ZT decreases even with the diameter of silicon nanowires at room temperature; The line realizes photoluminescence characteristics at a wavelength of 1.54 um at room temperature and the like. In addition, as the specific surface area increases, the electrical properties of the monocrystalline silicon nanowires become very sensitive to changes in surface states such as charge and mass, making them well suited as sensing components for a variety of highly sensitive sensors. Because of these new physical properties, silicon nanowires are considered to be an integral part of future nanoelectronic devices, nanophotonic devices, and nano energy conversion devices.

At present, the top-down method for fabricating single crystal silicon nanostructure lines is performed by top-down, that is, the undesired portions of the material are removed by positioning, leaving a nanostructure conforming to the design, including electron beam direct writing, deep ultraviolet lithography. Nano-etching technology such as nanoimprinting, although the process principle is relatively simple, the preparation process is expensive and time-consuming, and is not suitable for general nano research work. In recent years, it has been found that when the single crystal silicon nanostructure is oxidized, the outer layer of the nanostructure is pressed against the unoxidized region of the inner layer due to the volume expansion after oxidation, thereby generating a large stress in the inner layer of the nanostructure. Due to the presence of this stress, the oxidation rate of the inner silicon atoms is significantly lower than that of the outer silicon atoms. This phenomenon is called "self-limiting oxidation" and is often used as a low-cost size reduction technique for single crystal silicon nanowires. Structure preparation. Therefore, some of the researches have been carried out on a single-layer silicon wafer or a SOI-structured multilayer silicon wafer of (100) crystal plane type, (110) crystal plane type, (111) crystal plane type, according to the corresponding single crystal silicon. The crystal plane distribution characteristics of the sheet are reduced in size by a method based on anisotropic wet etching and self-limiting oxidation to prepare single or multiple single crystal silicon nanowires along a specific crystal orientation. Such a method for preparing single crystal silicon nanowires based on anisotropic wet etching and oxidation processes has a low manufacturing cost and is suitable for mass production. However, the single crystal silicon nanowires prepared by these methods tend to be parallel structures that are parallel to each other, and no complicated combination is formed. Structure, thus limiting its potential applications in the field of nanotechnology. Summary of the invention

In view of the above disadvantages of the prior art, an object of the present invention is to provide a method for fabricating a single crystal silicon nanowire mesh array structure, which is used to solve the discrete structure in which the single crystal silicon nanowires are often parallel to each other in the prior art. It is difficult to form a complicated combination structure problem.

To achieve the above and other related objects, the present invention provides a method for fabricating a single crystal silicon nanowire mesh array structure, the method comprising at least the following steps:

1) providing a (111) crystal plane single crystal silicon substrate, and forming an oxidation mask on the surface of the single crystal silicon substrate;

2) forming a plurality of mask windows having a preset arrangement rule of a preset shape in the oxidation resistant mask by a photolithography process

P ;

3) etching the single crystal silicon under the mask window to a predetermined depth by using ICP etching;

4) performing anisotropic wet etching on the single crystal silicon under the mask window to form a plurality of etching grooves having a hexagonal shape on the upper and lower surfaces, and forming a thin wall of single crystal silicon between the sidewalls of the adjacent two etching grooves;

5) thermally oxidizing the structure obtained by a self-limiting oxidation process to gradually oxidize the thin wall of the single crystal silicon, and finally forming a single sheet extending along the length of the thin wall of the single crystal silicon in the central portion of the thin wall of the single crystal silicon thin wall Crystalline silicon nanowires;

6) removing the oxidation mask and the silicon oxide formed during the oxidation to form a single crystal silicon nanowire mesh array structure.

As a preferred embodiment of the method for fabricating the single crystal silicon nanowire mesh array structure of the present embodiment, the oxidation resistant mask is a silicon nitride film having a thickness of 10 ηηη 2 ηηι or a silicon oxide having a thickness of 100 ηηι to 5 μηι. .

As a preferred embodiment of the method for fabricating the monocrystalline silicon nanowire mesh array structure of the present embodiment, the minimum distance between two adjacent mask windows is 1 μηι 10 10 μm.

As a preferred embodiment of the method for fabricating the single crystal silicon nanowire mesh array structure of the present embodiment, the preset depth is 100 ηηι 100 100 ηι.

As a preferred embodiment of the method for fabricating the single crystal silicon nanowire mesh array structure in the present embodiment, in step 4), the anisotropic wet etching time is from 10 minutes to 100 hours.

As a preferred embodiment of the method for fabricating the single crystal silicon nanowire mesh array structure in the embodiment, each inner angle of the hexagon is 120°, and each side is along the <110> crystal orientation, and each of the sides The sidewalls of the etched trench are all within the {111} crystal plane family.

As a preferred embodiment of the method for fabricating the single crystal silicon nanowire mesh array structure of the present embodiment, the angle between each of the thin walls of the single crystal silicon and the upper surface of the single crystal silicon substrate is 69.5° to 71.5°. As a preferred embodiment of the method for fabricating the single crystal silicon nanowire mesh array structure in the embodiment, each of the thin walls of the single crystal silicon has a width of 1 nm to 999 nm, a length of 100 nm to 1 mm, and any two single crystal silicon. The width of the thin walls does not differ by more than 500 nm.

As a preferred embodiment of the method for fabricating the single crystal silicon nanowire mesh array structure in the embodiment, the plurality of single crystal silicon thin walls form a hexagonal mesh array having an angle of 120°, and the plurality of single The crystalline silicon nanowires form a hexagonal mesh array with an angle of 120°.

As a preferred embodiment of the method for fabricating the single crystal silicon nanowire mesh array structure in the embodiment, the end points of the adjacent three single crystal silicon nanowires are connected to a single crystal silicon support structure, and between any two ends The distance is 10ηηι~20μηι.

As described above, the present invention provides a method for fabricating a single crystal silicon nanowire mesh array structure, which first forms an oxidation mask on a (111) crystal face wafer and forms a mask window; The method comprises: etching the single crystal silicon to a predetermined depth; then performing anisotropic wet etching on the single crystal silicon under each of the mask windows to form a plurality of etching grooves having hexagons on the upper and lower surfaces, adjacent to the two Forming a thin wall of single crystal silicon between the sidewalls of the etching trench; then performing thermal oxidation by a self-limiting oxidation process to form a single crystal silicon nanowire in a central portion of the thin wall of the single crystal silicon; finally removing the oxidation mask and silicon oxide Forming a monocrystalline silicon nanowire mesh array structure. The process of the invention is simple and efficient, and the core steps only involve conventional photolithography, etching process, oxidation mask and anisotropic etching, and (111) crystal face wafer is used under conventional mask preparation conditions and photolithography conditions. The characteristics of the crystal plane distribution inside can be used to fabricate large-scale monocrystalline silicon nanowire combination patterns on silicon wafers. DRAWINGS

1 shows a method for fabricating a single crystal silicon nanowire mesh array structure according to the present invention, and anisotropic etching of single crystal silicon under a grooved etching window of a certain depth and arbitrary shape of a (111) crystal plane single crystal silicon substrate. The schematic diagram of the etched groove is formed. The upper and lower surfaces of the etched groove are hexagonal with an internal angle of 120°. Each side of the hexagon is along the <110> crystal orientation group, and the hexagonal sidewalls are all in the {111} crystal. Inside the family.

2 is a schematic view showing a method for fabricating a single crystal silicon nanowire mesh array structure according to the present invention, and a plurality of anisotropic etching grooves adjacent to each other on a (111) crystal plane single crystal silicon substrate, adjacent to the etching groove side The wall forms a thin wall of single crystal silicon single crystal silicon, and at least two adjacent side walls of each etching groove respectively form a thin wall of single crystal silicon with the side walls of the adjacent etching grooves.

3a to 3b are views showing a method for fabricating a single crystal silicon nanowire mesh array structure according to the present invention, and a thin-wall oxidation process of single crystal silicon having an upper surface covered with an oxidation mask. When an anti-oxidation mask is formed on the upper surface of the thin wall of the single crystal silicon, after a certain degree of oxidation, on the thin walls of the single crystal silicon, due to volume expansion during oxidation, internal stresses of uneven size are generated, at the maximum stress. (The area located near the center of the thin wall near the oxidation mask) Since the oxidation rate is the slowest, when the other parts of the thin wall are completely oxidized to silicon oxide, the area still leaves a single crystal silicon structure with a small cross section. 4 is a view showing a method for fabricating a single crystal silicon nanowire mesh array structure according to the present invention, wherein a plurality of single crystal silicon thin walls are oxidized, and the oxidation resistant mask and the silicon oxide obtained by the silicon oxide grown during the oxidation process are removed. The schematic diagram of the nanowire mesh array structure, only the smallest mesh array unit is shown, that is, the structure of three single crystal silicon nanowires connected.

5 to FIG. 10 are schematic diagrams showing the steps of the steps 1) to 6) of the method for fabricating the single crystal silicon nanowire mesh array structure of the present invention. Component label description

101 single crystal silicon substrate

102 Antioxidant Mask

103 mask window

104 trough corrosion window

105 corrosion tank

106 single crystal silicon thin wall

107 monocrystalline silicon nanowires

108 silicon oxide

109 Support structure Specific implementation

The embodiments of the present invention are described below by way of specific specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The invention may be practiced or applied in various other specific embodiments, and the details of the invention may be variously modified or changed without departing from the spirit and scope of the invention.

Please refer to Figure 1 to Figure 10. It should be noted that the illustrations provided in this embodiment merely illustrate the basic concept of the present invention in a schematic manner, and only the components related to the present invention are shown in the drawings, instead of the number and shape of components in actual implementation. Dimensional drawing, the actual type of implementation of each component's type, number and proportion can be a random change, and its component layout can be more complicated.

The embodiment provides a method for fabricating a single crystal silicon nanowire mesh array structure according to the length of the single crystal silicon nanowire 107 in the target single crystal silicon nanowire network structure array and the distance from the bottom of the etching trench 105. Calculating a shape parameter of the preset etching mask window 103, an arrangement rule, and a depth of ICP etching of the single crystal silicon in the window, thereby controlling corresponding process parameters, and realizing a target shape of the single crystal silicon nanowire network structure array .

Figure 1 shows the anisotropic etching principle of single crystal silicon of (111) crystal plane, as shown in the figure, in the (111) crystal plane On the surface of the single crystal silicon substrate 101, when there is a groove-shaped etching window 104 of any shape and a certain depth, after the anisotropic etching of the single crystal silicon, an etching groove 105 having a hexagonal shape on the upper and lower surfaces will be formed, each of which has six sides. All internal angles of the shape are 120°. Wherein, the AB side, the BC side, the CD side, the DE side, the EF side, and the FA side constitute the upper surface hexagon of the etching groove 105, the A'B' side, the B'C' side, the C'D' side, and the D' The E' edge, the E'F' edge, and the F'A' constitute the lower surface hexagon of the etching groove 105, and the twelve sides are all along the <110> crystal orientation group. Wherein, the hexagonal sides of the AB side, the B'C' side, the CD side, the D'E' side, the EF side, and the F'A' side are vertically projected, and the inner angle of the predetermined arbitrary shape etching groove 105 is 120°. The smallest external hexagon. The six sidewalls of the etching bath 105 are all within the {111} crystal plane, and the angle S with the upper surface is 70.5 ° ± 1 °. AB side and A'B' side, BC side and B'C' side, CD side and C'D' side, DE side and D'E' side, EF side and E'F' side, FA side and F' The projection distance 4 on the upper surface between the edges of A' is the same and can be calculated as:

d _l = T - ctg0

Where r is the preset corrosion window depth.

When a plurality of groove-shaped etching windows 104 are preset to be close to each other, after the single-crystal silicon anisotropic wet etching, the adjacent etching grooves 105 are formed by mutually parallel sidewalls to form a single crystal silicon thin wall 106, as shown in FIG. As shown, the width w of the monocrystalline silicon thin wall 106 can be calculated as:

w = d ₀ - d _l

Wherein, the adjacent corrosion window is perpendicular to the minimum distance in the longitudinal direction of the thin wall in the plane.

At least two adjacent sidewalls of the etching trench 105 simultaneously form a thin wall 106 of single crystal silicon having a width difference within 500 nm between the other two etching trenches 105 adjacent to the etching trench 105. When the anti-oxidation mask 102 is provided on the upper surface of the thin wall of the single crystal silicon 106, according to the principle of self-limiting oxidation, in the region where the single crystal silicon thin wall 106 is located at the top center near the oxidation resistant mask 102, the oxidation rate is the slowest, in the thin When the other parts of the wall are completely oxidized to the silicon oxide 108, this region still leaves a single crystal silicon structure having a small cross section, as shown in Figs. 3a to 3b. Extending along the length of the thin wall, these remaining single crystal silicon structures form single crystal silicon nanowires 107, and the angle between the adjacent nanowires along the length direction is 120°, as shown in FIG. If a large number of the etching grooves 105 are densely arranged in the same pattern, a monocrystalline silicon nanowire mesh array structure will eventually be obtained.

According to the above design, as shown in FIG. 1 to FIG. 10, the embodiment provides a method for fabricating a single crystal silicon nanowire mesh array structure, and the manufacturing method includes at least the following steps:

As shown in Fig. 5, step 1) is first performed to provide a (111) crystal plane single crystal silicon substrate 101, and an oxidation mask 102 is formed on the surface of the single crystal silicon substrate 101.

In the present embodiment, the oxidation-resistant mask 102 is a silicon nitride film having a thickness of 10 ηηι to 2 μηι or a silicon oxide having a thickness of 100 ηηι to 5 μηι. In a specific implementation, a low stress silicon nitride film grown by LPCVD is used, and the silicon nitride film has a thickness of 1 μm. As shown in Fig. 1 and Fig. 6 to Fig. 8, steps 2) to 4) are then performed. Step 2), using a photolithography process to form a plurality of mask windows 103 having a preset arrangement rule of a predetermined shape in the oxidation preventing mask 102; Step 3), using the ICP etching method, each of the masks The single crystal silicon under the window 103 is etched to a predetermined depth to form a trench etching window 104; in step 4), the single crystal silicon under each of the mask windows 103 is anisotropically wet etched to form a top and bottom surface of six a plurality of etched trenches 105, a thin wall 106 of single crystal silicon is formed between sidewalls of adjacent etched trenches 105;

In the step 2) of the embodiment, the minimum distance between the adjacent two mask windows 103 is 1 μηι 10 10 μm. In step 3) of the embodiment, the preset depth is 100 ηηι to 100 μηι.

In the step 4) of the present embodiment, the anisotropic wet etching is performed using an anisotropic etching solution of a single crystal silicon such as ruthenium or iridium as an etching solution, and the etching time is 10 minutes to 100 hours. The sides of the hexagon obtained after the etching are all along the <110> crystal orientation, and the sidewalls of each of the etching grooves 105 are all within the {111} crystal plane group. The angle between each of the single crystal silicon thin walls 106 and the upper surface of the single crystal silicon substrate 101 is 69.5° to 71.5°.

Step 4) Each of the obtained single crystal silicon thin walls 106 has a width of from 1 nm to 999 nm and a length of from 100 nm to 1 mm, and any two of the single crystal silicon thin walls 106 have a width not exceeding 500 nm.

In step 4), a plurality of single crystal silicon thin walls 106 form a hexagonal mesh array having an angle of 120°.

In a specific implementation process, the shape parameters of the target single crystal silicon nanowire mesh array structure are first set as follows: All the single crystal silicon nanowires 107 are equal in length and have a length of ΙΟΟμηι, and the single crystal silicon nanowires 107 are away from the etching trench. The distance at the bottom of 105 is 10μηι. Referring to FIG. 1, to meet the goal, the upper surface of each of the etching grooves 105 should be hexagonal, that is, the edge, the BC side, the CD side, the DE side, the EF side, and the FA side are hexagonal, and Side lengths are ΙΟΟμηι; ΑΒ edge and A'B' edge, BC edge and B'C' edge, CD edge and C'D' edge, DE edge and D'E' edge, EF edge and E'F' edge The projection distance between the FA side and the FA' side on the upper surface can be calculated as:

d _l = T - ctg0 = 10 / . g70.5° = 3.54 /m,

Thereby, the projection shape and parameters of the lower surface of the etching groove 105 on the plane can be determined. The intersection of the projection of the hexagon ABCDEF and the hexagon A'B'C'D'E'F' on the plane is a hexagonal abcdef (not shown), so that the preset etching mask window 103 is made. The minimum mating hexagon whose shape satisfies the inner angle of 120° is a hexagonal abcdef.

In this embodiment, the plurality of mask windows 103 are arrayed in the same shape and size, and after the shape of the mask window 103 and the predetermined depth of the etching groove 105 are determined, the shape of the hexagonal ABCDEF will also be It is determined that the positions of the plurality of mask windows 103 are adjusted to satisfy: at least two adjacent sides of the hexagon ABCDEF associated with any one of the mask windows 103 and one of the other two adjacent hexagons ABCDEF The sides are parallel and the plane projection distance w is in the range of 10 nm to 999 nm, and accordingly, the distance of each mask window 103 in the direction perpendicular to the sides can be calculated. d ₀ = w + 3.45 /m.

As shown in Fig. 9 to Fig. 10, steps 5) to 6) are then performed. Step 5), thermally oxidizing the structure obtained by using a self-limiting oxidation process to gradually oxidize the thin-walled silicon oxide wall 106, and finally forming a thin wall 106 along the central portion of the monocrystalline silicon thin wall 106. The single-crystal silicon nanowires 107 extending in the longitudinal direction; Step 6), removing the oxidation-resistant mask 102 and the silicon oxide 108 formed during the oxidation process to form a monocrystalline silicon nanowire network array structure.

When the anti-oxidation mask 102 is provided on the upper surface of the thin wall of the single crystal silicon 106, according to the principle of self-limiting oxidation, in the region where the single crystal silicon thin wall 106 is located at the top center near the oxidation resistant mask 102, the oxidation rate is the slowest, in the thin When the other portions of the wall are completely oxidized to the silicon oxide 108, the region still leaves a single crystal silicon structure having a small cross section, and the single crystal silicon structure extends along the length direction of the single crystal silicon thin wall 106 into the single crystal silicon nanowires 107. It should be noted that the single crystal silicon located at the central portion of the intersection of the single crystal silicon thin walls 106 is also slow in oxidation rate, so after the silicon oxide 108 is removed, the single crystal silicon nanowires 107 are The junction will have a single crystal silicon support structure 109, as shown in FIG.

In this embodiment, the plurality of single crystal silicon nanowires 107 form a hexagonal mesh array having an angle of 120°, and the end points of the adjacent three single crystal silicon nanowires 107 are connected to a single crystal silicon support. Structure 109, and the distance between any two ends is 10 ηη~20μη.

In summary, the present invention provides a method for fabricating a monocrystalline silicon nanowire mesh array structure, which first forms an oxidation mask on a (111) crystal face wafer and forms a mask window; Etching method, etching the single crystal silicon to a predetermined depth; then performing anisotropic wet etching on the single crystal silicon under the mask window to form a plurality of etching grooves having hexagons on the upper and lower surfaces, adjacent Forming a thin wall of single crystal silicon between the sidewalls of the two etching trenches; then performing thermal oxidation by a self-limiting oxidation process to form a single crystal silicon nanowire in a central portion of the thin wall of the single crystal silicon; finally removing the oxidation mask and oxidizing Silicon forms a monocrystalline silicon nanowire network array structure. The process of the invention is simple and efficient, and the core steps only involve conventional photolithography, etching process, oxidation mask and anisotropic etching, and (111) crystal face wafer is used under conventional mask preparation conditions and photolithography conditions. The characteristics of the crystal plane distribution inside can be used to fabricate large-scale monocrystalline silicon nanowire combination patterns on silicon wafers. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-described embodiments are merely illustrative of the principles of the invention and its advantages, and are not intended to limit the invention. Modifications or variations of the above-described embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and scope of the inventions are still to be covered by the appended claims.

Claims

The invention provides a method for fabricating a monocrystalline silicon nanowire mesh array structure, characterized in that the manufacturing method comprises at least the following steps:

2) forming, by using a photolithography process, a plurality of mask windows having a preset arrangement rule of a preset shape in the oxidation resistant mask;

6) removing the anti-oxidation mask and the silicon oxide formed during the oxidation to form a monocrystalline silicon nanowire mesh array structure. The method for fabricating a single crystal silicon nanowire mesh array structure according to claim 1, wherein: the oxidation resistant mask is a silicon nitride film having a thickness of 10 ηηι to 2 μηι or an oxidation of a thickness of 100 ηηι to 5 μηι silicon. The method for fabricating a single crystal silicon nanowire mesh array structure according to claim 1, wherein the minimum distance between two adjacent mask windows is 1 μm to 10 μm. The method for fabricating a single crystal silicon nanowire mesh array structure according to claim 1, wherein: the predetermined depth is 100 ηηι to 100 μηι. The method for fabricating a single crystal silicon nanowire mesh array structure according to claim 1, wherein: in step 4), the anisotropic wet etching time is from 10 minutes to 100 hours. The method for fabricating a single crystal silicon nanowire mesh array structure according to claim 1, wherein: each of the hexagons has an internal angle of 120°, and each side is along a <110> crystal orientation, each of which The sidewalls of the etched trench are all within the {111} crystal plane family. The method for fabricating a single crystal silicon nanowire mesh array structure according to claim 1, wherein: each of the single crystals The angle between the thin silicon wall and the upper surface of the single crystal silicon substrate is 69.5° to 71.5°. The method for fabricating a single crystal silicon nanowire mesh array structure according to claim 1, wherein: each of the thin walls of the single crystal silicon has a width of 1 nm to 999 nm, a length of 100 nm to 1 mm, and any two single crystals. The width of the thin silicon walls does not differ by more than 500 nm. The method for fabricating a single crystal silicon nanowire mesh array structure according to claim 1, wherein: the plurality of single crystal silicon thin walls form a hexagonal mesh array having an angle of 120°, and a plurality of The single crystal silicon nanowires form a hexagonal mesh array with an angle of 120°. 0. The method for fabricating a single crystal silicon nanowire mesh array structure according to claim 9, wherein: the end points of the adjacent three single crystal silicon nanowires are connected to a single crystal silicon support structure, and any two ends are connected. The distance between them is 10ηη~20μη.