KR102035505B1 - Manufacturing method of single silicon nanowire device based-on standard photolithography - Google Patents

Abstract

The present invention relates to a method for manufacturing a single silicon nanowire device based on a standard exposure process. According to the present invention, an insulating layer is stacked on a substrate and a device layer is stacked on the insulating layer. An etching mask layer is stacked on the device layer. A photoresist pattern including a region aligned in a direction (110) and a region non-aligned in the direction (110) is formed on the etching mask layer. The etching mask layer is formed as a pattern layer having a shape corresponding to the photoresist pattern by using the photoresist pattern to expose a part of the device layer and to remove the photoresist pattern. An exposed part of the device layer is removed to form a structure in which first and second inclined surfaces are formed on both sides thereof, separately. An oxide film is formed on each of the first and second inclined surfaces of the structure. Also, the pattern layer is removed and a part of the structure is removed to form a single silicon nanowire.

Description

MANUFACTURING METHOD OF SINGLE SILICON NANOWIRE DEVICE BASED-ON STANDARD PHOTOLITHOGRAPHY}

The present invention relates to a method for fabricating a single silicon nanowire device, and more particularly, exhibits superior physical and chemical properties as compared to conventional microdevices, such as single electronic devices, quantum devices, nanoelectronic devices, nanophotoelectric devices, and nanobiotechnology. The present invention relates to a method for fabricating a single silicon nanowire device based on a standard exposure process for manufacturing a short channel nanowire device applied to a sensor and a chemical sensor.

Recently, due to the excellent electrical, optical, and physical properties of silicon nanowires having a one-dimensional structure, studies have been actively conducted to apply them to various fields such as lasers, transistors, memories, and chemical sensing sensors. Furthermore, many methods have been studied for fabricating high quality, low dimensional structured ultrafine silicon nanowires in large quantities and in large areas.

In general, the silicon nanowire fabrication process can be roughly divided into a bottom-up process and a top-down process.

The bottom-up process includes a method of growing silicon nanowires by using a vapor-liquid-solid (VLS) method using gold particles as a catalyst, a catalyst assisted self-assembly chemical synthesis method in nanopores, and the like. This bottom-up process has the advantage of producing large quantities of single crystal nanowires with diameters of several tens of nanometers or less at a very high quality level, but subsequent fabrication of a device having one function using nanowires is possible. The process is very complicated and difficult.

As a representative example, in order to fabricate a device such as a field effect transistor, a grown silicon nanowire must be placed between a specific position, a source and a drain electrode. This requires a highly aligned process between the nanowires and the electrode pattern.

In addition, there are many challenges to overcome to establish reliable electrical contact between the nanowires and the electrodes. In other words, even if it is possible to manufacture a large amount of high-quality nanowires of several tens of nanoscale or less, there is a limit to the mass production of functional semiconductor devices at the wafer level.

Meanwhile, the top-down process includes electron beam lithography, scanning prove lithography, focused ion-beam lithography, nano imprinting, and the like. have. Among these, electron beam exposure and focused ion beam exposure are one of the representative techniques used for fabricating silicon nanowires.

However, the nanowires produced by the top-down process are inferior in quality to the nanowires produced by the bottom-up process and the width of the nanowires does not reach the level. In particular, the direct writing electron beam exposure and the focused ion beam exposure are not suitable for mass production at the wafer level because a large process time is required to draw a large area of the pattern.

Meanwhile, the standard exposure process technology, which is one of the top-down processes, can transfer hundreds of nanoscale micro-patterns onto the substrate at one time, which is suitable for mass production of semiconductor devices at the wafer level. It is currently widely used in semiconductor processes. Therefore, many methods for fabricating silicon nanowires using existing standard photolithography processes are being studied.

In US Patent Publication No. 2012-0202325, a high-quality single-crystal silicon nanowire of 10-20 nm level is manufactured using two-step microlithography and micro fabrication process. Here's how.

However, when using this method, at least two strands of silicon nanowires are formed in one device pattern. Therefore, when the field effect transistor device is manufactured using the present method, a pair channel device is formed instead of a single channel device.

United States Patent Application Publication No. 2012-0202325

Therefore, the technical problem of the present invention was conceived in this respect, and the object of the present invention is to manufacture a single channel device instead of a pair channel device by changing only a force mask design in a conventional standard exposure process, and through this, the pair channel silicon The present invention relates to a method of fabricating a single silicon nanowire device based on a standard exposure process, which can manufacture a single channel nanowire device using the same process as before, without an additional exposure process for making the nanowire into a single channel.

In the method of manufacturing a single silicon nanowire device based on a standard exposure process according to an embodiment for realizing the object of the present invention described above, an insulating layer is laminated on a substrate and a device layer is laminated on the insulating layer. An etching mask layer is stacked on the device layer. A photoresist pattern including a region aligned in the [110] direction and a region not aligned in the [110] direction is formed on the etching mask layer. The etch mask layer is formed as a pattern layer having a shape corresponding to the photoresist pattern by using the photoresist pattern to expose a portion of the device layer and then remove the photoresist pattern. The exposed portions of the device layer are removed to form structures having first and second inclined surfaces on both sides thereof, respectively. An oxide film is formed on a surface of each of the first and second oblique surfaces of the structure. After removing the pattern layer, a portion of the structure is removed to form a single silicon nanowire.

In one embodiment, the photoresist pattern extends along the [110] direction to have a predetermined width, and is disposed between the A and B regions and the A and B regions that are disposed to face each other with a longitudinal gap therebetween. May include a C region having a width smaller than those of the A and B regions, and including a region aligned in the [110] direction and an unaligned region in the [110] direction.

In one embodiment, the first corner portion of the region aligned in the [110] direction in the region C extends in the [110] direction, and the second corner portion of the region unaligned in the [110] direction is the It may extend in a direction other than the [110] direction.

In one embodiment, the second corner portion extends in a direction oblique to the [110] direction, extends in a zigzag direction along the [110] direction, or a first direction in which a central portion is perpendicular to the [110] direction. Along the convex portion, or the central portion of the first side may be convex along the first direction, and the central portion of the second side may be concave along the first direction.

In an embodiment, in the removing of the exposed portion of the device layer, an anisotropic etching solution may be used to remove the exposed part of the device layer.

In an embodiment, in the forming of the structure, the cross section of the structure and the first and second inclined surfaces may be formed in a trapezoidal shape.

In one embodiment, the first and second slopes may be (111) planes.

In an embodiment, in the removing of a part of the structure, the region including the second slope may be removed and only the region including the first slope may remain.

In one embodiment, an anisotropic etching solution may be used to remove a portion of the structure.

In an embodiment, in the forming of the single silicon nanowire, a region including the first slope may be formed of the single silicon nanowire.

According to the embodiments of the present invention as described above, it is possible to manufacture a short-channel nanowire device having a high potential for use in manufacturing a nanodevice having a superior performance as compared to a pair channel nanowire device.

In particular, the short channel nanowire device may be utilized in the development of single electronic devices, quantum devices, nanoelectronic devices such as nano memories, nano LEDs, nano photoelectric devices such as nano lasers, nano biosensors having high sensitivity, and chemical sensors. Big.

1 is a flowchart illustrating a method of manufacturing a single silicon nanowire device based on a standard exposure process according to an embodiment of the present invention.
2A to 2H are flowcharts illustrating a method of fabricating a single silicon nanowire device based on the standard exposure process of FIG. 1.
FIG. 3A is a plan view illustrating a photoresist pattern formed using the photolithography of FIG. 2A.
3B to 3D are plan views illustrating other examples of the photoresist pattern of FIG. 3A.
4A to 4D are images illustrating short channel nanowire devices fabricated by the method of fabricating a single silicon nanowire device based on the standard exposure process of FIG. 1.

As the inventive concept allows for various changes and numerous modifications, the embodiments will be described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements. Terms such as first and second may be used to describe various components, but the components should not be limited by the terms.

The terms are used only for the purpose of distinguishing one component from another. The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise.

In this application, the terms "comprise" or "consist of" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a flowchart illustrating a method of manufacturing a single silicon nanowire device based on a standard exposure process according to an embodiment of the present invention. 2A to 2H are flowcharts illustrating a method of fabricating a single silicon nanowire device based on the standard exposure process of FIG. 1. FIG. 3A is a plan view illustrating a photoresist pattern formed using the photolithography of FIG. 2A. 3B to 3D are plan views illustrating other examples of the photoresist pattern of FIG. 3A.

1 and 2A, in the method for fabricating a single silicon nanowire based on a standard exposure process according to the present embodiment, as shown in the drawing, an insulating layer 200 and an element layer 300 are formed on a first substrate 100. The stack is sequentially performed (step S100), and the etch mask layer 400 is stacked on the device layer 300 (step S200).

In this case, the first substrate 100 may be formed of silicon (Si) as a stacking material, the insulating layer 200 may be formed of silicon oxide (SiO) as a stacking material, and the device layer 300 may be Single crystal silicon (Si) can be used as the lamination material.

However, the stacking of the insulating layer 200 and the device layer 300 on the first substrate 100 has been described above, but the first substrate 100, the insulating layer 200, and the device layer have been described. A Si-On-Insulator (SOI) wafer, which is a substrate including 300, may be used. In this case, the etch mask layer 400 may be stacked on the SOI wafer.

The device layer 300 is finally formed as a short channel nanowire through a process to be described later, and may be formed as a short channel nanowire doped with an n-type dopant or a p-type dopant.

The etching mask layer 400 may be formed of an oxide or nitride-based material, and may include, for example, silicon oxide (SiO) or silicon nitride (SiN). In addition, the etching mask layer 400 may include any one or more materials selected from metal oxides such as alumina (Al ₂ O ₃ ) and hafnium dioxide (HfO ₂ ), an organic layer such as SAM (Self-Assembled Monolayer), or a photoresist. can do. However, considering the etching selectivity of the oxide layer formed on the bevel and the insulating layer 200 after the oxide film process described later, silicon nitride (SiN) is highly compatible with the process.

The etching mask layer 400 may be deposited on the device layer 300 through a deposition process such as low pressure chemical vapor deposition (LCPVD) or plasma chemical vapor deposition (PECVD).

Next, a photomask (not shown) is arranged on the etching mask layer 400 to form a photoresist pattern 500 (step S200). In this case, the photomask is arranged such that the photoresist pattern 500 is generally aligned along the [110] direction.

Generally, the pattern or notch formed on the substrate is located in the [110] direction. This is because there are relatively strong and weak mechanical properties in terms of physical properties depending on the relationship between the slice direction of the substrate and the crystal orientation of the surface, and based on the direction with the highest mechanical strength. For example, when cutting into a crystal plane, it is known to have the best mechanical strength in the portion corresponding to the [110] direction of the surface, and the weakest in the portion corresponding to the [001] direction or the [010] direction.

1, 2B and 3A, the photoresist pattern 500 as described above is formed through a standard exposure process using the photomask, that is, a photolithography process.

Since the photoresist pattern 500 is formed by using a photolithography process through the arrangement of the photomasks, although not shown, the photomask is preferably formed in the same shape as the photoresist pattern 500.

More specifically, referring to FIG. 3A, the photoresist pattern 500 includes an A region 510, a B region 520, and a C region 530, as shown in FIG. 3A.

Here, the A and B regions 510 and 520 are disposed to face each other at intervals in the longitudinal direction and extend along the [110] direction to have a predetermined width.

The C region 530 extends in the [110] direction as a whole between the A and B regions 510 and 520 and has a smaller width than the A and B regions 510 and 520.

In this case, the region extends between the A and B regions 510 and 520 of the C region 530, and includes a region aligned in the [110] direction and an unaligned region in the [110] direction.

The first corner portion 531 of the region aligned in the [110] direction extends in the [110] direction but is misaligned in the [110] direction on the opposite side of the first corner portion 531. The second corner portion 532 may not extend in the [110] direction but may extend in a direction oblique to the [110] direction.

That is, the second corner portion 532 may extend in a direction closer to the first corner portion 531 extending in the [110] direction along the region B from the region A 510. Thus, the C region may be formed in a trapezoidal shape.

In contrast, the C region 530 of the photoresist pattern 500 may be formed in a shape as shown in FIGS. 3B to 3D.

That is, in this case, the second corner portion 532 in the C region 530 may extend in the zigzag direction along the [110] direction as shown in FIG. 3B, and as shown in FIG. 3C. May extend so as to be convex along the first direction 1 perpendicular to the [110] direction, and as shown in FIG. 3C, a central portion of the first side 2 is convex along the first direction 1. And a central portion of the second side 3 may be concave along the first direction.

Further, the second corner portion 532 may extend in any direction unless it extends only in the [110] direction.

1 and 2B, the etch mask layer 400 is formed of a pattern layer 400 having a shape corresponding to the photoresist pattern 500 using the photoresist pattern 500 as described above. Thereafter, the photoresist pattern 500 is removed (step S400).

That is, the pattern layer 401 has a shape corresponding to that of the mask 500 and is transferred onto the device layer 300. Like the photoresist pattern 500, the pattern layer 401 and the region A 410 and B ( 420 and region C 430, wherein region C 430 includes a first corner portion 431 aligned in the [110] direction and a second corner portion 432 unaligned in the [110] direction. ).

Since the etch mask layer 400 is formed of the pattern layer 401 having such a shape, a portion of the device layer 300 disposed under the etch mask layer 400 is exposed.

Next, referring to FIGS. 1 and 2D, the exposed portion of the device layer 300 is removed to form a structure 301 having first and second inclined surfaces 310 and 320 formed on both sides, respectively. (Step S500).

The (110) plane is a plane orthogonal to the [110] crystal direction, and the (111) plane is defined as a plane orthogonal to the [111] crystal direction (see FIG. 2D).

Here, the use of square brackets '[]' and round brackets '()' corresponds to the direction and plane of the crystal lattice, respectively, and when used with the numbers 110 and 111, follows the standard crystallographic nomenclature known in the art. Indicates.

In general, the (110) plane is etched at a speed of 5 to 10 times faster than the (111) plane, so that the exposed portion of the device layer 300 is formed in a trapezoidal shape as it is shown. The first inclined surface 310 and the second inclined surface 320 may be formed at both sides of the trapezoid. In this case, the first and second oblique surfaces 310 and 320 may be a (111) plane formed in a trapezoidal shape.

On the other hand, when removing the exposed portion of the device layer 300, an anisotropic wet etching (etching) process is used, in this case as an etching solution, tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH) Solutions including aqueous solutions and the like can be used.

However, the present disclosure is not limited thereto, and an anisotropic etching solution may be sufficient to minimize damage to the first and second inclined surfaces 310 and 320 formed while the device layer 300 is removed.

Through the first anisotropic wet process as described above, the structure 301 having trapezoidal cross sections is formed.

Meanwhile, in fabricating the structure 301, an etching rate and an etching velocity may be variously controlled according to a process temperature, a process time, etc., and the width and height of the structure 301 may be adjusted. .

Thereafter, referring to FIGS. 1 and 2E, the first and second oblique surfaces 310 and 320 are oxidized (step S600). For example, the first and second inclined surfaces 310 and 320 may be thermally oxidized for 15 minutes in a dry environment of 950 degrees Celsius.

Thus, the surface of the first oblique surface 310 is formed of the first oxide film 311, the surface of the second oblique surface 320 is oxidized to form the second oxide film 321, and the first and second oxide films are formed. The fields 311 and 321 may act as an etching mask during the second anisotropic wet etching, which will be described later, to protect the first and second inclined surfaces 310 and 320 from the anisotropic etching solution.

Next, referring to FIGS. 1, 2F and 2G, after removing the pattern layer 401 located on the structure 301, a portion of the structure 301, that is, the region C of FIG. 2B ( A part of the portion corresponding to 430 is removed (step S700).

In this case, when a portion of the portion corresponding to the C region 430 of the structure 301 is removed as shown by using a second anisotropic wet etching process, the second as shown in FIG. 2G. The area including the oblique surface 320 is removed and only the area including the first oblique surface 310 remains.

As described above, the first corner portion 531 extends in the [110] direction, and the second corner portion 532 has the [110] direction as in the diagonal direction to the [110] direction described above. This is because it is exposed to the etching solution so that the etching speed is extended in a non-directional direction so that the etching speed is very fast.

Accordingly, as the second corner portion 532 is etched relatively faster than the first corner portion 531, that is, anisotropic etching is performed, the second corner portion not aligned in the [110] direction ( 532 is not made of nanowires and is naturally etched away.

As only a portion of the structure including the first oblique surface 310 remains in the process of etching a portion of the structure 301, the region including the first oblique surface 310 is formed as a short channel nanowire 700. Can be formed.

Thus, as shown in FIG. 2H, the short channel nanowire 700 is positioned between the A and B regions 410 and 420, and the short channel nanowire device in which the short channel nanowire 700 is formed is provided. Is produced.

4A through 4D are images illustrating a short channel nanowire device manufactured by a method of fabricating a single silicon nanowire device based on the standard exposure process of FIG. 1.

FIG. 4A illustrates the fabricated nanostructure pattern of the device layer, FIG. 4B is an enlarged view of region 'A' of FIG. 4A, FIG. 4 is an enlarged view of region 'B' of FIG. 4B, and FIG. 4D is a view of FIG. An enlarged view of region 'C' of 4b.

Referring to FIG. 4D, it can be seen that a single strand of nanowire pattern is formed only at an edge portion (the first edge portion) aligned in the [110] direction of both edge portions in the region C of the device layer.

That is, it can be seen that the nanowire pattern of the corner portion (the second corner portion) unaligned in the [110] direction is etched away and is only used for the step due to the multi-step process (cleaning, natural oxide etching, etc.). You can see that only the shading pattern exists.

According to the embodiments of the present invention as described above, it is possible to manufacture short channel nanowires that are highly applicable to fabricate nanodevices having even better performance than pair channel nanowire devices.

In particular, the short channel nanowire device may be utilized in the development of single electronic devices, quantum devices, nanoelectronic devices such as nano memories, nano LEDs, nano photoelectric devices such as nano lasers, nano biosensors having high sensitivity, and chemical sensors. Big.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

100: first substrate 200: insulating layer
300 element layer 301 structure
310: first sloped surface 320: second sloped surface
400: etching mask layer 401: pattern layer
410: A area 420: B area
430: C region 500: photoresist pattern

Claims (10)

Stacking an insulating layer on a substrate and stacking an element layer on the insulating layer;
Stacking an etch mask layer on the device layer;
Forming a photoresist pattern on the etch mask layer, the photoresist pattern including a region aligned in a [110] direction and an region aligned in the [110] direction;
Removing the photoresist pattern after exposing a portion of the device layer by forming the etching mask layer as a pattern layer having the same shape as the photoresist pattern by using the photoresist pattern;
Removing the exposed portions of the device layer on which the pattern layer is not formed to form structures having first and second inclined surfaces on both sides thereof;
Forming an oxide film on a surface of each of the first and second inclined surfaces of the structure; And
Removing a portion of the structure after removing the pattern layer to form a single silicon nanowire;
The photoresist pattern is
A and B regions extending in the [110] direction to have a predetermined width and disposed to face each other at intervals in the longitudinal direction; And
A region C between the regions A and B and having a width smaller than those of the regions A and B and including a region aligned in the [110] direction and an region unaligned in the [110] direction,
In the C region,
The first corner portion of the region aligned in the [110] direction extends in the [110] direction, and the second corner portion of the region unaligned in the [110] direction extends in the diagonal direction with the [110] direction. ,
The pattern layer is integrally formed to have the same corner portions as the first corner portion and the second corner portion, and the pattern layer formed by the second corner portion is the same as the extending direction of the second corner portion. Method for producing a single silicon nanowire, characterized in that extending in the [110] direction and the diagonal direction. delete delete delete The method of claim 1, wherein in the step of removing the exposed portion of the device layer,
A method of manufacturing a single silicon nanowire, characterized in that to remove the exposed portion of the device layer using an anisotropic etching solution. The method of claim 5,
A cross section of the structure, and the first and second oblique surfaces are formed in a trapezoidal shape, characterized in that the manufacturing method of a single silicon nanowire. The method of claim 6, wherein the first and second slopes,
Method for producing a single silicon nanowire, characterized in that the (111) plane. The method of claim 1, wherein in the step of removing a portion of the structure,
And the region including the second slope is removed and only the region including the first slope is left. The method of claim 8,
Method of manufacturing a single silicon nanowire, characterized in that by removing an portion of the structure using an anisotropic etching solution. The method of claim 8, wherein in the forming of the single silicon nanowire,
And a region including the first sloped surface is formed of the single silicon nanowire.

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