WO2014084215A1 - フォトダイオードアレイ - Google Patents

フォトダイオードアレイ Download PDF

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Publication number
WO2014084215A1
WO2014084215A1 PCT/JP2013/081801 JP2013081801W WO2014084215A1 WO 2014084215 A1 WO2014084215 A1 WO 2014084215A1 JP 2013081801 W JP2013081801 W JP 2013081801W WO 2014084215 A1 WO2014084215 A1 WO 2014084215A1
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Prior art keywords
semiconductor region
semiconductor
region
hole
photodiode array
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Ceased
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PCT/JP2013/081801
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English (en)
French (fr)
Japanese (ja)
Inventor
辰己 山中
明 坂本
暢郎 細川
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Hamamatsu Photonics KK
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Hamamatsu Photonics KK
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Priority to CN201380050908.7A priority Critical patent/CN104685631B/zh
Priority to DE112013005685.2T priority patent/DE112013005685T5/de
Priority to US14/646,406 priority patent/US10461115B2/en
Publication of WO2014084215A1 publication Critical patent/WO2014084215A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H10F39/189—X-ray, gamma-ray or corpuscular radiation imagers
    • H10F39/1898—Indirect radiation image sensors, e.g. using luminescent members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
    • H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
    • H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
    • H10F30/21—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
    • H10F30/22—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes
    • H10F30/221—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier being a PN homojunction
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/811—Interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes

Definitions

  • the present invention relates to a photodiode array.
  • Patent Document 1 describes a photodiode array used in a CT (Computed Tomography) apparatus or the like.
  • P + -type semiconductor regions constituting a light detection region are two-dimensionally arranged on the incident surface side of an n-type semiconductor substrate.
  • An electrode is connected to each P + type semiconductor region.
  • Each electrode is drawn out to the back surface side opposite to the incident surface through a through hole provided corresponding to each P + type semiconductor region.
  • the P + -type semiconductor regions and the through holes are alternately arranged on the semiconductor substrate along a predetermined direction.
  • An object of the present invention is to provide a photodiode array capable of improving the aperture ratio and reliability.
  • a photodiode array is a photodiode array including a plurality of photodiodes formed on a semiconductor substrate, each of the photodiodes being a first semiconductor of a first conductivity type provided on the semiconductor substrate.
  • a second semiconductor region of a second conductivity type provided on one surface side of the semiconductor substrate with respect to the first semiconductor region so as to surround the predetermined region and constituting a photodetection region together with the first semiconductor region;
  • a through-electrode provided in a through-hole penetrating between one surface and the other surface of the semiconductor substrate so as to pass through one semiconductor region and a predetermined region, and electrically connected to the second semiconductor region;
  • the through hole includes a portion that expands from one surface to the other surface.
  • the through hole passes through the first semiconductor region and the predetermined region, and the predetermined region is surrounded by the second semiconductor region.
  • the second semiconductor region constitutes a light detection region together with the first semiconductor region.
  • the through hole is surrounded by the light detection region. Accordingly, the interval between adjacent photodiodes can be reduced. Therefore, the aperture ratio can be improved.
  • a leak current generated due to damage to the inner wall of the through hole easily enters the light detection region. Therefore, when the through hole is surrounded by the light detection region, it is preferable to reduce damage to the inner wall of the through hole.
  • the through hole includes a portion that expands from the front surface to the back surface.
  • the expanded portion can be formed by anisotropic etching, for example.
  • anisotropic etching the inner wall of the through hole is hardly damaged. Therefore, in this photodiode array, leakage current from the through hole can be reduced.
  • the predetermined region may include a third semiconductor region of the first conductivity type having an impurity concentration higher than the impurity concentration of the first semiconductor region through the through hole.
  • the second semiconductor region, the third semiconductor region May be separated from each other, and a part of the first semiconductor region may exist between the second semiconductor region and the third semiconductor region so as to surround the third semiconductor region.
  • the through hole passes through the third semiconductor region having an impurity concentration higher than that of the first semiconductor region. Therefore, the surface leakage current that is generated in the inner wall of the through hole and goes to the light detection region can be reduced by the second semiconductor region. Therefore, electrical characteristics can be improved.
  • the third semiconductor region through which the through hole passes has an impurity concentration higher than that of the first semiconductor region, various stresses generated in the through hole can be buffered. Therefore, the strength can be improved.
  • the second semiconductor region and the third semiconductor region are separated from each other, and a part of the first semiconductor region exists between the second semiconductor region and the third semiconductor region. Therefore, a short circuit between the second semiconductor region and the third semiconductor region can be suppressed, and electrical characteristics can be improved.
  • the distance between the inner edge and the outer edge of the third semiconductor region may be larger than the distance between the outer edge of the third semiconductor region and the inner edge of the second semiconductor region. According to this configuration, various stresses generated in the through hole can be further buffered by the third semiconductor region.
  • the inner edge of the second semiconductor region may surround the opening of the through hole on the other surface side when viewed from the thickness direction of the semiconductor substrate. According to this configuration, the second semiconductor region is provided in a range outside the through hole when viewed from the thickness direction of the semiconductor substrate. Therefore, for example, when a bump electrode is formed in the through hole, the stress applied to the second semiconductor region constituting the light detection region can be reduced.
  • Each of the photodiodes may include a contact electrode that is formed on one surface and electrically connects the second semiconductor region and the through electrode, and the outer edge of the contact electrode extends from the thickness direction of the semiconductor substrate.
  • the opening of the through hole on the other surface side may be surrounded. According to this configuration, when viewed from the thickness direction of the semiconductor substrate, the contact electrode is provided across the inner and outer ranges of the through hole. Therefore, the strength around the through hole can be improved.
  • the opening of the through hole on one surface side may have a circular shape. According to this configuration, for example, when a bump electrode is formed in the through hole, it is possible to prevent stress concentration from occurring in the through hole.
  • FIG. 6 is a cross-sectional view showing a process of the method for manufacturing the photodiode array in FIG. 1.
  • FIG. 6 is a cross-sectional view showing a process of the method for manufacturing the photodiode array in FIG. 1.
  • FIG. 6 is a cross-sectional view showing a process of the method for manufacturing the photodiode array in FIG. 1.
  • FIG. 6 is a cross-sectional view showing a process of the method for manufacturing the photodiode array in FIG. 1.
  • FIG. 6 is a cross-sectional view showing a process of the method for manufacturing the photodiode array in FIG. 1.
  • FIG. 6 is a cross-sectional view showing a process of the method for manufacturing the photodiode array in FIG. 1.
  • FIG. 6 is a cross-sectional view showing a process of the method for manufacturing the photodiode array in FIG. 1.
  • FIG. 6 is a cross-sectional view showing a process of the method for manufacturing the photodiode array in FIG. 1.
  • FIG. 6 is a cross-sectional view showing a process of the method for manufacturing the photodiode array in FIG. 1.
  • FIG. 6 is a cross-sectional view showing a process of the method for manufacturing the photodiode array in FIG. 1.
  • FIG. 2 is a partial cross-sectional view of a CT apparatus to which the photodiode array of FIG. 1 is applied. It is a top view of the photodiode of the photodiode array of other embodiment of this invention. It is a top view of the photodiode of the photodiode array of other embodiment of this invention.
  • the photodiode array 1 is used in, for example, a CT apparatus.
  • the photodiode array 1 includes a plurality of photodiodes PD1 formed on a semiconductor substrate 2.
  • the semiconductor substrate 2 has a rectangular shape in plan view. As shown in FIG. 3, the semiconductor substrate 2 has a front surface (one surface) 21 and a back surface (other surface) 22 that face each other. On the surface 21, an insulating film f1 and an insulating film f3 are formed in this order from the surface 21. On the back surface 22, an insulating film f4 and an insulating film f5 are formed in this order from the back surface 22. As each insulating film, a SiO 2 film or a SiN film is formed.
  • the photodiodes PD1 are two-dimensionally arranged on the semiconductor substrate 2. Each of the photodiodes PD1 functions as one pixel. As shown in FIG. 3, the photodiode PD1 includes a first semiconductor region 3, a third semiconductor region 4, a second semiconductor region 5, a fourth semiconductor region 6, a fifth semiconductor region 7, and a through electrode. 81a, a contact electrode 82a, and a terminal electrode 83a.
  • the first semiconductor region 3 includes a central portion in the thickness direction of the semiconductor substrate 2.
  • the first semiconductor region 3 has a rectangular shape when viewed from the thickness direction of the semiconductor substrate 2.
  • the first semiconductor region 3 is provided over the entire area of the photodiode PD1 in the central portion of the semiconductor substrate 2 in the thickness direction.
  • the first semiconductor regions 3 and 3 of the adjacent photodiodes PD1 and PD1 are integrally formed.
  • the first semiconductor region 3 is an n ⁇ type semiconductor region.
  • the first semiconductor region 3 is made of, for example, Si.
  • a substrate electrode (not shown) is connected to the first semiconductor region 3.
  • the third semiconductor region 4 is provided on the surface 21 side of the semiconductor substrate 2 with respect to the first semiconductor region 3.
  • the third semiconductor region 4 has a circular outer edge and a rectangular shape (in detail, a square shape) at the inner edge.
  • the third semiconductor region 4 may have another ring shape (for example, a polygonal ring such as a square ring or an annular ring). That is, an annular shape is an integral shape surrounding an arbitrary region so as to be closed.
  • the inner edge of the third semiconductor region 4 forms an opening of a through hole 9A (described later) on the surface 21 side.
  • the third semiconductor region 4 is an n + type semiconductor region, and has an impurity concentration higher than that of the first semiconductor region 3.
  • the third semiconductor region 4 is formed, for example, by diffusing an n-type impurity in Si.
  • the second semiconductor region 5 is provided on the surface 21 side of the semiconductor substrate 2 with respect to the first semiconductor region 3.
  • the second semiconductor region 5 surrounds a region (predetermined region) including the third semiconductor region 4 and a first portion 31 described later.
  • the second semiconductor region 5 is separated from the third semiconductor region 4.
  • the second semiconductor region 5 When viewed from the thickness direction of the semiconductor substrate 2, the second semiconductor region 5 has a rectangular shape at the outer edge and a circular shape at the inner edge.
  • the second semiconductor region 5 may have another ring shape.
  • the second semiconductor region 5 is a p + type semiconductor region.
  • the second semiconductor region 5 and the first semiconductor region 3 form a pn junction and constitute a light detection region of the photodiode PD1.
  • the second semiconductor region 5 is formed, for example, by diffusing p-type impurities into Si.
  • the third semiconductor region 4 is formed deeper than the second semiconductor region 5.
  • the first portion 31 that is a part of the first semiconductor region 3.
  • the first portion 31 surrounds the third semiconductor region 4 and is surrounded by the second semiconductor region 5 when viewed from the thickness direction of the semiconductor substrate 2.
  • the first portion 31 has an annular shape when viewed from the thickness direction of the semiconductor substrate 2.
  • the first portion 31 may have another ring shape.
  • the fourth semiconductor region 6 is provided on the surface 21 side of the semiconductor substrate 2 with respect to the first semiconductor region 3.
  • the fourth semiconductor region 6 When viewed from the thickness direction of the semiconductor substrate 2, the fourth semiconductor region 6 has a rectangular ring shape larger than the second semiconductor region 5 and surrounds the second semiconductor region 5.
  • the fourth semiconductor region 6 may have another ring shape.
  • the fourth semiconductor region 6 is separated from the second semiconductor region 5.
  • a second portion 32 that is a part of the first semiconductor region 3 exists.
  • the second portion 32 has a rectangular ring shape when viewed from the thickness direction of the semiconductor substrate 2.
  • the second portion 32 may have another annular shape.
  • the fourth semiconductor regions 6 and 6 of the adjacent photodiodes PD1 and PD1 are integrally formed.
  • the fourth semiconductor region 6 is an n + type semiconductor region and has an impurity concentration higher than that of the first semiconductor region 3.
  • the fourth semiconductor region 6 is formed, for example, by diffusing an n-type impurity in Si.
  • the fourth semiconductor region 6 functions as a channel stopper that separates adjacent photodiodes PD1 and PD1.
  • the fourth semiconductor region 6 is grounded via an electrode (not shown).
  • the fifth semiconductor region 7 is provided on the back surface 22 side of the semiconductor substrate 2 with respect to the first semiconductor region 3.
  • the fifth semiconductor region 7 is formed over the entire area of the photodiode PD1 on the back surface 22 side.
  • the fifth semiconductor regions 7 and 7 of the adjacent photodiodes PD1 and PD1 are integrally formed.
  • the fifth semiconductor region 7 is an n + type semiconductor region, and has an impurity concentration higher than that of the first semiconductor region 3.
  • the fifth semiconductor region 7 is formed, for example, by diffusing an n-type impurity in Si.
  • the first semiconductor region 3 and the fifth semiconductor region 7 may be formed, for example, by growing an n ⁇ type epitaxial layer having an impurity concentration lower than that of Si on the n + type Si.
  • the semiconductor substrate 2 is provided with a through hole 9 ⁇ / b> A that penetrates between the front surface 21 and the back surface 22.
  • the through hole 9 ⁇ / b> A passes through the first semiconductor region 3, the third semiconductor region 4, and the fifth semiconductor region 7.
  • 9 A of through-holes contain the part expanded toward the back surface 22 side from the surface 21 side.
  • the through-hole 9A includes a small hole portion 91a located on the front surface 21 side and a large hole portion 92a located on the back surface 22 side.
  • the small hole portion 91a penetrates the insulating film f1.
  • the small hole portion 91a has a cylindrical shape.
  • the opening of the through hole 9A on the surface 21 side has a circular shape.
  • the large hole portion 92 a penetrates the first semiconductor region 3 and the third semiconductor region 4.
  • the large hole portion 92a extends from the front surface 21 side toward the back surface 22 side, and has a tapered shape. Specifically, the large hole portion 92a has a quadrangular pyramid shape.
  • the opening of the through hole 9A on the back surface 22 side has a rectangular shape (in detail, a square shape).
  • the inner wall of the large hole portion 92a and the surface 21 form an angle of approximately 55 °.
  • the inner wall of the large hole portion 92a and the back surface 22 form an angle of approximately 125 °.
  • the upper side of the large hole portion 92a is larger than the diameter of the small hole portion 91a.
  • the small hole portion 91a and the large hole portion 92a are arranged coaxially.
  • An insulating film f6 is formed on the inner wall of the large hole portion 92a.
  • the insulating film f6 is formed continuously with the insulating film f4 on the back surface 22 side.
  • the distance d1 between the inner edge and the outer edge of the third semiconductor region 4 is larger than the distance d2 between the outer edge of the third semiconductor region 4 and the inner edge of the second semiconductor region 5 (the distance between the inner edge and the outer edge of the first portion 31). large.
  • the inner edge of the second semiconductor region 5 surrounds the opening of the through hole 9A on the back surface 22 side when viewed from the thickness direction of the semiconductor substrate 2. That is, the second semiconductor region 5 is provided in a range outside the through hole 9 ⁇ / b> A when viewed from the thickness direction of the semiconductor substrate 2.
  • the thickness / impurity concentration of each region is, for example, as follows.
  • First semiconductor region 3 thickness 50 to 625 ⁇ m / impurity concentration 5 ⁇ 10 11 to 5 ⁇ 10 15 cm ⁇ 3
  • Third semiconductor region 4 thickness 1.0 to 10 ⁇ m / impurity concentration 1 ⁇ 10 18 to 1 ⁇ 10 20 cm ⁇ 3
  • Second semiconductor region 5 thickness 0.01 to 3.0 ⁇ m / impurity concentration 1 ⁇ 10 18 to 1 ⁇ 10 20 cm ⁇ 3
  • Fourth semiconductor region 6 thickness 1.0 to 10 ⁇ m / impurity concentration 1 ⁇ 10 18 to 1 ⁇ 10 20 cm ⁇ 3
  • Fifth semiconductor region 7 thickness 1.0 to 620 ⁇ m / impurity concentration 1 ⁇ 10 18 to 1 ⁇ 10 20 cm ⁇ 3
  • the through electrode 81a is provided in the through hole 9A.
  • the through electrode 81a has a hollow quadrangular truncated pyramid shape whose bottom surface is fully opened.
  • the through electrode 81a is formed on the inner wall of the small hole portion 91a and on the insulating film f6 in the large hole portion 92a.
  • the through electrode 81a closes the opening of the through hole 9A on the surface 21 side.
  • the contact electrode 82a is formed on the surface 21.
  • the contact electrode 82a electrically connects the second semiconductor region 5 and the through electrode 81a.
  • the contact electrode 82a includes a disk-shaped part and an annular part.
  • the disk-shaped part is formed on the insulating film f1.
  • the disk-shaped part covers the opening on the surface 21 side of the through hole 9A.
  • the disk-shaped portion is connected to the through electrode 81a.
  • the annular portion extends from the outer edge of one surface (the surface on the insulating film f1 side) of the disk-shaped portion toward the radially outer side.
  • the annular portion penetrates the insulating film f ⁇ b> 1 and is in contact with the second semiconductor region 5.
  • the outer edge of the contact electrode 82a surrounds the opening of the through hole 9A on the back surface 22 side when viewed from the thickness direction of the semiconductor substrate 2. That is, the contact electrode 82 a is provided across the range of the inside and outside of the through hole 9 ⁇ / b> A when viewed from the thickness direction of the semiconductor substrate 2.
  • the terminal electrode 83 a is formed on the back surface 22.
  • the terminal electrode 83a is formed on the insulating film f4.
  • the terminal electrode 83a has an annular shape with a circular outer edge and a square inner edge. The inner edge of the terminal electrode 83a is connected to the through electrode 81a.
  • the contact electrode 82a, the through electrode 81a, and the terminal electrode 83a are made of, for example, aluminum.
  • an n ⁇ -type Si substrate S having a crystal plane (100) is prepared.
  • the substrate S includes the first semiconductor region 3.
  • an insulating film f1 is formed on the surface 21 by, for example, thermal oxidation.
  • the insulating film f1 on the position where the third semiconductor region 4 and the fourth semiconductor region 6 are to be formed is removed by photoetching to form an opening.
  • Phosphorus is thermally diffused into the substrate S through the opening.
  • phosphorus is also thermally diffused on the back surface 22.
  • the third semiconductor region 4, the fourth semiconductor region 6, and the fifth semiconductor region 7 are formed.
  • the opening is closed by thermal oxidation.
  • the insulating film f1 on the position where the second semiconductor region 5 is to be formed is removed by photoetching to form an opening. Boron is thermally diffused in the substrate S through the opening. Thereby, the second semiconductor region 5 is formed. Subsequently, the opening is closed by thermal oxidation.
  • the insulating film f1 at the position where the annular portion of the contact electrode 82a is to be formed is removed by photoetching to form an opening (contact hole).
  • the contact electrode 82a is formed by sputtering.
  • an insulating film f3 is formed on the insulating film f1 and the contact electrode 82a by, for example, plasma CVD or LP-CVD. Subsequently, in order to adjust the thickness of the portion through which light is transmitted, the surface 21 side (specifically, the insulating film f3) is subjected to chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • the back surface 22 is anisotropically etched by alkali etching (using potassium hydroxide solution, TMAH, human radine, EDP, or the like).
  • alkali etching using potassium hydroxide solution, TMAH, human radine, EDP, or the like.
  • TMAH potassium hydroxide solution
  • EDP human radine
  • a large hole portion 92a in which the inner wall and the surface 21 form an angle of approximately 55 ° is formed.
  • the anisotropic etching is performed until the large hole portion 92a reaches the insulating film f1.
  • the small hole portion 91a is formed by dry etching.
  • the insulating films f4 and f6 are formed on the back surface 22, on the inner wall of the large hole portion 92a, and on the inner wall of the small hole portion 91a by plasma CVD or LP-CVD, for example.
  • the insulating film f6 on the inner wall of the small hole portion 91a is removed by photoetching to form an opening (contact hole), and a part of the contact electrode 82a is exposed to the back surface 22 side.
  • the through electrode 81a and the terminal electrode 83a are formed by sputtering.
  • an insulating film f5 is formed on the insulating film f4, the terminal electrode 83a, and the through electrode 81a by, for example, plasma CVD or LP-CVD. Subsequently, the inner edge side on the terminal electrode 83a and the insulating film f5 on the through electrode 81a are removed by photoetching. Thus, the configuration shown in FIG. 3 is obtained.
  • the CT apparatus 100 includes the photodiode array 1 described above, a scintillator 101, and a mounting substrate 102.
  • the scintillator 101 is in contact with the insulating film f3.
  • the scintillator 101 has a rectangular parallelepiped shape. When viewed from the thickness direction of the semiconductor substrate 2, the scintillator 101 is approximately the same size as the second semiconductor region 5 constituting the light detection region and overlaps the second semiconductor region 5.
  • the scintillator 101 is a solid scintillator (crystalline material such as CsI, NaI, LaBr3, or GAGG) having a crystallinity, a ceramic scintillator (such as a sintered body of an inorganic phosphor), or a plastic scintillator (such as PET). It is a scintillator.
  • a reflective film 103 is provided on the surface of the scintillator 101 other than the contact surface with the insulating film f3.
  • the reflective film 103 is made of, for example, aluminum or titanium oxide.
  • the mounting substrate 102 has an electrode 104.
  • the electrode 104 is electrically connected to the through electrode 81a via a bump electrode 105 formed in the through electrode 81a.
  • the bump electrode 105 is formed of a conductive material such as solder, gold, nickel, copper, or a conductive adhesive resin.
  • the scintillator 101 when X-rays enter the scintillator 101, the scintillator 101 emits scintillation light.
  • the scintillation light is directly incident on the second semiconductor region 5, or is incident on the second semiconductor region 5 after being reflected by the contact electrode 82a, the reflective film 103, and the like.
  • Information on the charges generated in the light detection region by the incidence of the scintillation light is input to the mounting substrate 102 via the contact electrode 82a, the through electrode 81a, the terminal electrode 83a, and the bump electrode 105.
  • each photodiode PD1 in each photodiode PD1, the through hole 9A passes through the first semiconductor region 3 and the third semiconductor region 4, and the third semiconductor region 4 becomes the second semiconductor region 5. Surrounded by The second semiconductor region 5 constitutes a light detection region together with the first semiconductor region 3.
  • the through hole 9A in each photodiode PD1 which is one pixel, the through hole 9A is surrounded by the light detection region. Thereby, the space
  • the through-hole 9 ⁇ / b> A includes a tapered large hole portion 92 a that expands from the front surface 21 toward the back surface 22.
  • the large hole portion 92a is formed by anisotropic etching. In the anisotropic etching, the inner wall of the through hole 9A is hardly damaged. Therefore, in the photodiode array 1, it is possible to reduce the leakage current from the through hole 9A generated due to damage. Therefore, electrical characteristics can be improved.
  • the inner wall of the large hole portion 92a and the back surface 22 form an obtuse angle (approximately 125 °). Accordingly, when the insulating films f4 and f6 are formed, the insulating film at the opening edge of the through hole 9A on the back surface 22 side is compared with the case where the inner wall of the large hole portion 92a and the back surface 22 form a right angle or an acute angle.
  • the film thicknesses f4 and f6 are easily formed thick. Therefore, electrical characteristics can be improved.
  • the through hole 9 ⁇ / b> A passes through the third semiconductor region 4 having an impurity concentration higher than that of the first semiconductor region 3. Accordingly, the third semiconductor region 4 can reduce the surface leakage current that is generated on the inner wall of the through hole 9A and travels toward the light detection region. Further, damage caused by etching can be reduced by the third semiconductor region 4. Therefore, electrical characteristics can be improved. These effects are more preferably exhibited when the third semiconductor region 4 is formed deeper than the second semiconductor region 5.
  • the insulating film f6 and the semiconductor substrate 2 are made of different materials, it is considered that stress is generated at the interface between the insulating film f6 and the through hole 9A.
  • the third semiconductor region 4 through which the through hole 9A passes has an impurity concentration higher than the impurity concentration of the first semiconductor region 3, and thus occurs at the interface between the through hole 9A and the insulating film f6.
  • the stress can be buffered in the third semiconductor region 4. Therefore, the strength can be improved.
  • the semiconductor substrate 2 Since the area of the front surface 21 and the back surface 22 of the semiconductor substrate 2 is larger than the thickness, it is considered that the semiconductor substrate 2 is distorted. In the photodiode array 1, the stress generated in the through hole 9A due to the distortion of the semiconductor substrate 2 can be buffered in the third semiconductor region 4 through which the through hole 9A passes. Therefore, the strength can be improved.
  • the bump electrode 105 When the bump electrode 105 is formed in the through hole 9A, it is conceivable that stress is generated in the through hole 9A due to thermal contraction of the bump electrode 105 or the like. In the photodiode array 1, stress generated when the bump electrode 105 is formed can be buffered in the third semiconductor region 4 through which the through hole 9 ⁇ / b> A passes. Therefore, the strength can be improved.
  • the second semiconductor region 5 and the third semiconductor region 4 are separated from each other. Between the second semiconductor region 5 and the third semiconductor region 4, a first portion 31 that is a part of the first semiconductor region 3 exists so as to surround the third semiconductor region 4. Therefore, a short circuit between the second semiconductor region 5 and the third semiconductor region 4 can be suppressed. Therefore, electrical characteristics can be improved.
  • the distance d1 between the inner edge and the outer edge of the third semiconductor region 4 is larger than the distance d2 between the outer edge of the third semiconductor region 4 and the inner edge of the second semiconductor region 5. Therefore, the third semiconductor region 4 can further buffer the various stresses generated in the through hole 9A.
  • the inner edge of the second semiconductor region 5 surrounds the opening of the through hole 9A on the back surface 22 side when viewed from the thickness direction of the semiconductor substrate 2. That is, the second semiconductor region 5 is provided in a range outside the through hole 9 ⁇ / b> A when viewed from the thickness direction of the semiconductor substrate 2. Therefore, when the bump electrode 105 is formed in the through hole 9A, the stress applied to the second semiconductor region 5 constituting the light detection region can be reduced.
  • Each of the photodiodes PD1 includes a contact electrode 82a that is formed on the surface 21 and connects the second semiconductor region 5 and the through electrode 81a.
  • the outer edge of the contact electrode 82a extends from the thickness direction of the semiconductor substrate 2. When viewed, it surrounds the opening of the through hole 9A on the back surface 22 side. That is, when viewed from the thickness direction of the semiconductor substrate 2, the contact electrode 82 a is provided across the inner and outer ranges of the through hole 9 ⁇ / b> A. Therefore, the strength around the through hole 9A can be improved.
  • the opening of the through hole 9A on the surface 21 side has a circular shape. For this reason, for example, when the bump electrode 105 is formed in the through hole 9A, it is possible to prevent stress concentration from occurring in the through hole 9A.
  • the outer edge of the third semiconductor region 4 has a circular shape. Therefore, the concentration of the electric field can be suppressed as compared with the case where the outer edge of the third semiconductor region 4 has a polygonal shape or the like.
  • the photodiode array of this embodiment includes a photodiode PD2 instead of the photodiode PD1 (see FIG. 2).
  • the photodiode PD2 is different from the photodiode PD1 in that the photodetection region is divided into a plurality (four).
  • the photodiode PD2 includes a plurality of (four) second semiconductor regions 51 having a shape different from that of the second semiconductor region 5 instead of the second semiconductor region 5.
  • the photodiode PD2 has a plurality of (four) third portions 33 that are part of the first semiconductor region 3 in place of the first and second portions 31 and 32.
  • the photodiode PD2 has a plurality of sixth semiconductor regions 10.
  • the plurality of second semiconductor regions 51 are provided apart from each other.
  • the plurality of second semiconductor regions 51 surround the third semiconductor region 4 when viewed from the thickness direction of the semiconductor substrate 2.
  • Each of the second semiconductor regions 51 is separated from the third semiconductor region 4.
  • Each of the second semiconductor regions 51 has a shape in which one corner is cut out in a fan shape from a rectangle when viewed from the thickness direction of the semiconductor substrate 2.
  • the distance d1 between the inner edge and the outer edge of the third semiconductor region 4 is the distance between the outer edge of the third semiconductor region 4 and the inner edge of the second semiconductor region 51 (the distance between the inner edge and the outer edge in each of the third portions 33) d3. Bigger than.
  • the inner edges of the plurality of second semiconductor regions 51 surround the opening of the through hole 9A on the back surface 22 side when viewed from the thickness direction of the semiconductor substrate 2. That is, the plurality of second semiconductor regions 51 are provided outside the through hole 9 ⁇ / b> A when viewed from the thickness direction of the semiconductor substrate 2.
  • Each of the second semiconductor regions 51 is connected to the contact electrode 82a. Information obtained in the plurality of second semiconductor regions 51 is output as one piece of information from the through electrode 81a. That is, the PD 2 including the plurality of second semiconductor regions 51 functions as one pixel.
  • Each of the third portions 33 has an annular shape. Each of the third portions 33 surrounds the second semiconductor region 51 when viewed from the thickness direction of the semiconductor substrate 2. The plurality of third portions 33 are provided to be separated from each other. The plurality of third portions 33 surround the third semiconductor region 4 when viewed from the thickness direction of the semiconductor substrate 2.
  • the sixth semiconductor region 10 is provided on the surface 21 side of the semiconductor substrate 2 with respect to the first semiconductor region 3.
  • the sixth semiconductor region 10 is formed between the adjacent third portions 33 and 33 when viewed from the thickness direction of the semiconductor substrate 2.
  • the sixth semiconductor region 10 has a substantially rectangular shape when viewed from the thickness direction of the semiconductor substrate 2.
  • the sixth semiconductor region 10 is an n + type semiconductor region, and has an impurity concentration higher than that of the first semiconductor region 3.
  • the sixth semiconductor region 10 is provided continuously with the third semiconductor region 4 and the fourth semiconductor region 6 which are n + type semiconductor regions.
  • the sixth semiconductor region 10 has the same thickness and impurity concentration as the third semiconductor region 4 and the fourth semiconductor region 6.
  • the third semiconductor region 4 is formed, for example, by diffusing an n-type impurity in Si.
  • the third semiconductor region 4 is formed simultaneously with the third semiconductor region 4 and the fourth semiconductor region 6 in the manufacturing method described above.
  • a photodiode array including a plurality of photodiodes PD2 as described above has the same effect as the photodiode array 1 described above.
  • the through hole 9A passes through the first semiconductor region 3 and the third semiconductor region 4, and the third semiconductor region 4 includes a plurality of second semiconductor regions 51. Surrounded by The plurality of second semiconductor regions 51 together with the first semiconductor region 3 constitutes a light detection region.
  • the through hole 9A is surrounded by the light detection region. Thereby, the space
  • the third semiconductor region 4 is formed continuously with the grounded fourth semiconductor region 6 via the sixth semiconductor region 10. For this reason, in the photodiode PD2, the electrical stability can be improved as compared with the photodiode PD1 described above.
  • the number of divisions of the photodetection region is different from that of the photodiode PD2 (see FIG. 14) described above.
  • the photodiode PD3 has a plurality (eight) second semiconductor regions 52 instead of the plurality (four) second semiconductor regions 51.
  • the second semiconductor region 52 has a substantially rectangular shape when viewed from the thickness direction of the semiconductor substrate 2.
  • the photodiode PD3 includes a plurality (eight) third portions 34 instead of the plurality (four) third portions 33.
  • the third portion 34 has a substantially square ring shape when viewed from the thickness direction of the semiconductor substrate 2.
  • the photodiode PD3 includes a plurality (eight) sixth semiconductor regions 11 instead of the plurality (four) sixth semiconductor regions 10.
  • the sixth semiconductor region 11 has a substantially rectangular shape when viewed from the thickness direction of the semiconductor substrate 2.
  • Such a photodiode array including a plurality of photodiodes PD3 has the same effect as the photodiode array including a plurality of photodiodes PD2 described above.
  • the photodetection region is divided, the number of divisions is not limited to four and eight, and can be changed to various numbers.
  • the material and shape of each component of the photodiode array are not limited to the materials and shapes described above, and can be changed to various materials and shapes.
  • the p-type and n-type conductivity types in the photodiode array may be opposite to those described above.
  • the photodiode array is not limited to the one in which the photodiodes PD1 to PD3 are two-dimensionally arranged, and may be one-dimensionally arranged.
  • the photodiode array is not limited to the CT apparatus, and can be applied to various apparatuses.

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Light Receiving Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
PCT/JP2013/081801 2012-11-28 2013-11-26 フォトダイオードアレイ Ceased WO2014084215A1 (ja)

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US20150340402A1 (en) 2015-11-26
US10461115B2 (en) 2019-10-29
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JP2014107446A (ja) 2014-06-09
JP6068955B2 (ja) 2017-01-25

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