WO2014071663A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2014071663A1
WO2014071663A1 PCT/CN2012/085624 CN2012085624W WO2014071663A1 WO 2014071663 A1 WO2014071663 A1 WO 2014071663A1 CN 2012085624 W CN2012085624 W CN 2012085624W WO 2014071663 A1 WO2014071663 A1 WO 2014071663A1
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Prior art keywords
gate
mosfet
layer
semiconductor substrate
forming
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French (fr)
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朱慧珑
梁擎擎
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US14/144,275 priority Critical patent/US9117926B2/en
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
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    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H10D64/0133—Aspects related to lithography, isolation or planarisation of the conductor at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall
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    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/0142—Manufacturing their gate conductors the gate conductors having different shapes or dimensions
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/014—Manufacturing their gate conductors the gate conductors having different materials or different implants
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers

Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly to semiconductor devices for integrating metal oxide semiconductor field effect transistors (MOSFETs) having different gate lengths and methods of fabricating the same.
  • MOSFETs metal oxide semiconductor field effect transistors
  • a gate stack comprising a high K gate dielectric and a metal gate conductor.
  • semiconductor devices including such gate stacks are typically fabricated using a replacement gate process.
  • the replacement gate process involves forming a high ⁇ gate dielectric and a metal gate conductor in the aperture defined between the gate spacers.
  • due to the shrinking device size it has become increasingly difficult to form high ⁇ gate dielectrics and metal conductors in such small gate openings.
  • a method of fabricating a semiconductor device comprising: forming a first MOSFET having a first gate length in a semiconductor substrate; and forming a second MOSFET having a second gate length in the semiconductor substrate, Wherein the second gate length is less than the first gate length, wherein the second MOSFET has a gate stack in the form of a sidewall, the gate stack including a gate conductor and a gate dielectric, the gate dielectric separating the gate conductor from the semiconductor substrate.
  • a semiconductor device including: a semiconductor substrate; a first MOSFET having a first gate length in the semiconductor substrate; and a second gate length in the semiconductor substrate a second MOSFET, wherein the second gate length is smaller than the first gate length, wherein the second MOSFET has a gate stack in the form of a sidewall, the gate stack includes a gate conductor and a gate dielectric, and the gate dielectric is located on the gate conductor and the semiconductor substrate between.
  • the present disclosure forms a gate stack of a different structure for a first MOSFET and a second MOSFET, wherein the first MOSFET Including a conventional gate stack, the second MOSFET includes a gate stack in the form of a sidewall. Therefore, the gate length of the second MOSFET can be much smaller than the gate length of the first MOSFET.
  • the present disclosure provides a method of integrating MOSFETs of different gate lengths on one semiconductor substrate. In a preferred embodiment of the present disclosure, the sacrificial sidewalls are first formed and then the sacrificial sidewalls are replaced with gate stacks, which can reduce the use of masks and the need for complex lithography processes, thereby reducing manufacturing costs.
  • 1 to 11 are schematic views showing a flow of manufacturing a semiconductor device in accordance with a first embodiment of the present disclosure.
  • 12-19 are schematic views showing a part of steps of a process of fabricating a semiconductor device in accordance with a second embodiment of the present disclosure.
  • 20-27 are schematic views showing a part of steps of a process of fabricating a semiconductor device in accordance with a third embodiment of the present disclosure. detailed description
  • semiconductor structure refers to a general term for the entire semiconductor structure formed in the various steps of fabricating a semiconductor device, including all layers or regions that have been formed.
  • semiconductor material includes, for example, a group III-V semiconductor such as GaAs, InP, GaN, SiC, and a Group IV semiconductor such as Si, Ge.
  • the gate conductor may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials such as TaC, TiN, TaTbN. , TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni 3 Si, Pt, Ru, Ir, Mo, HfRu, Ru0x
  • the gate dielectric may be composed of 510 2 or a material having a dielectric constant greater than SiO 2 , and includes, for example, an oxide, a nitride, an oxynitride, a silicate, an aluminate, a titanate, wherein the oxide includes, for example, Si0 2 . , Hf0 2, Zr0 2, A1 2 0 3, Ti0 2, L3 ⁇ 40 3, e.g. nitrides include Si, silicates such as including Hf Si0x, e.g. aluminates including LaA10 3, titanates include, for example SrTi0 3, oxynitride
  • the compound includes, for example, SiON.
  • the gate dielectric may be formed not only by materials well known to those skilled in the art, but also materials developed for the gate dielectric in the future.
  • a conventional process after the "pseudo" gate stack and the sidewalls on both sides of the dummy gate stack are used to fabricate the source and drain regions in the substrate, the sidewalls on both sides are retained to define apertures between the sidewalls Form a true gate stack by filling the pores.
  • an "alternative side wall” process is proposed. After forming the source and drain regions, a layer of material on one side of the source and drain regions is retained, and a gate stack is formed in the sidewall of the remaining material layer as a sidewall (in particular, a gate conductor) ). Thereby, the gate stack can be formed in a larger space (specifically, substantially the gate region + the other of the source region and the drain region), and the gate stack is formed only in the small gate opening between the sidewall spacers The conventional process can make the process easier.
  • FIGS. 1-11 A flow of manufacturing a semiconductor device in accordance with a first embodiment of the present disclosure will be described with reference to FIGS. 1-11.
  • a substrate 101 is provided.
  • the substrate 101 may be a substrate of various forms such as, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (S0I) substrate, a SiGe substrate, or the like.
  • a bulk Si substrate will be described as an example for convenience of explanation.
  • STI shallow trench isolation
  • STI 102 can include, for example, an oxide (e.g., silicon oxide).
  • the first MOSFET 100 has been formed on the semiconductor substrate 101 by a conventional process.
  • the first active region of the first MOSFET 100 is the left region defined by the STI 102 in FIG.
  • the first MOSFET 100 is included in the semiconductor A gate stack formed on the substrate, the gate stack including a gate dielectric 102 on the semiconductor substrate 101 and a gate conductor 103 on the gate dielectric 102.
  • Gate dielectric 102 separates gate conductor 103 from semiconductor substrate 101.
  • the side wall 105 is formed around the gate conductor 103.
  • the first MOSFET 100 further includes source/drain regions (not shown) formed in the semiconductor substrate 101, an extension region (not shown), and an optional halo region (not shown).
  • the first MOSFET 100 can be fabricated using a variety of processes, such as the known "gate-first process” or "alternative gate process.”
  • a first masking layer 106 having a thickness of about 100 to 200 nm is formed on the surface of the semiconductor structure by a known deposition process such as CVD (Chemical Vapor Deposition), atomic layer deposition, sputtering, or the like.
  • the first masking layer 106 may be composed of an oxide (e.g., silicon oxide).
  • a photoresist layer (not shown) is formed on the first masking layer 106 by spin coating, and the photoresist layer is patterned by a photolithography process including exposure and development.
  • the first masking layer 106 is removed by dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, or by wet etching using an etchant solution, using the photoresist layer as a mask.
  • dry etching such as ion milling, plasma etching, reactive ion etching, laser ablation, or by wet etching using an etchant solution, using the photoresist layer as a mask.
  • the portion in the right region of Figure 1 i.e., the second active region surrounded by STI 102).
  • the photoresist layer is removed by dissolving or ashing in a solvent.
  • the first masking layer 106 covers only the first active region of the first MOSFET 100, as shown in FIG.
  • a second masking layer 107 having a thickness of about 100 to 200 nm is formed on the surface of the semiconductor structure by the above-described known deposition process.
  • the second masking layer 107 may be composed of a nitride (e.g., silicon nitride).
  • the second masking layer 107 may include a nitride layer and an oxide layer, the oxide layer being over the nitride layer.
  • the second masking layer 107 is planarized, for example, by chemical mechanical polishing (CMP) to obtain a flat semiconductor structure surface.
  • CMP chemical mechanical polishing
  • the first masking layer 106 and the second masking layer 107 are adjacent, and the first masking layer 106 covers the first active region of the first MOSFET 100, and the second masking layer 107 covers the second MOSFET of the second MOSFET to be formed. Source area.
  • An opening is formed in the second masking layer 107 by a patterning step, for example, using a photoresist mask, the opening exposing a surface of a portion of the semiconductor substrate 101 in the second active region.
  • the opening is adjacent to the first masking layer 106 and exposes a portion of the STI 102 between the first active region and the second active region, as shown in FIG.
  • the opening exposes a portion of the semiconductor substrate 101 where one of the source and drain regions is to be formed.
  • a first ion implantation is performed through the opening in a direction perpendicular to the main surface of the semiconductor substrate 101 to form the extension region 108a.
  • a p-type impurity such as In, BF 2 or B may be implanted;
  • an extension region may be formed by implanting an n-type impurity such as As or P.
  • a second ion implantation is performed in a direction oblique to the main surface of the semiconductor substrate 101 to form one of the source and drain regions 108b.
  • the direction of the second ion implantation is clockwise offset from the direction of the first ion implantation by an angle (less than 90 °, for example, 15 °) such that the second masking layer 107 blocks a portion of the ions during the second ion implantation.
  • the implanted ions enter the semiconductor substrate 101 only at a position close to the STI 102 to form one of the source and drain regions.
  • the depth of the second ion implantation is greater than the depth of the first ion implantation.
  • the above-described P-type impurity may be employed for the P-type device; for the n-type device, the above-described n-type impurity may be employed.
  • the extension 108a and one of the source and drain regions 108b are superimposed on one another without a clear boundary, as shown in FIG.
  • additional ion implantation may be performed through the opening to form a halo (not shown) prior to the first ion implantation.
  • the direction of the additional ion implantation is offset counterclockwise from the direction of the first ion implantation by an angle (less than 90 °, for example 15 °) such that during the additional ion implantation, the first masking layer 106 blocks a portion of the ions.
  • the implanted ions enter the semiconductor substrate 101 only at a position away from the STI 102 to form a halo.
  • the depth of the additional ion implantation is greater than the depth of the first ion implantation and the depth of the second ion implantation.
  • the above-described n-type impurity can be used for the P-type device, and the above-described P-type impurity can be used for the n-type device.
  • an annealing treatment such as spike annealing, laser annealing, rapid annealing, or the like may be performed to activate the implanted impurities.
  • a third masking layer 109 (e.g., oxide) is formed over the semiconductor structure by the above-described known deposition process, and the material of the third masking layer 109 fills the opening.
  • a planarization process such as CMP, is used to obtain a flat surface of the semiconductor structure, as shown in FIG.
  • the material of the third masking layer 109 for filling the opening may be the same as the first masking layer 106. If the second masking layer 107 includes a nitride layer and an oxide layer, the CMP step only needs to be stopped at the nitride layer.
  • the second masking layer 107 is selectively removed with respect to the first masking layer 106 and the third masking layer 109 by a dry etching or a wet etching as described above using a suitable etchant, as shown in FIG.
  • This etching stops on the surface of the semiconductor substrate 101.
  • an additional oxide layer (not shown) may be provided on the surface of the semiconductor substrate 101 to provide etch selectivity.
  • a nitride layer of, for example, 8-30 nm is deposited on the surface of the semiconductor structure by the above-described known deposition process, and then the sacrificial spacer 110 is formed on the sidewall of the first masking layer 106 by anisotropic etching. As shown in Figure 7.
  • the sacrificial sidewall 110 is formed and material the same as a conventional gate spacer. As will be described below, the sacrificial sidewalls 110 are eventually removed and replaced by gate stacks.
  • the extension region 111a and the source and drain regions are formed in the semiconductor substrate 101 by the third ion implantation and the fourth ion implantation in accordance with the method already described in connection with FIG. Another ll lb, as shown in Figure 8.
  • additional ion implantation may be performed to form a halo (not shown) prior to the third ion implantation.
  • an annealing treatment such as spike annealing, laser annealing, rapid annealing, or the like may be performed to activate the implanted impurities.
  • the sacrificial spacer 110 is selectively removed with respect to the first masking layer 106 and the third masking layer 109 by a dry etching or a wet etching as described above using a suitable etchant.
  • a super-steep back well (SSRW) 112 may be formed by a fifth ion implantation (indicated by the arrows in the figure), as shown in FIG.
  • SSRW super-steep back well
  • an n-type impurity such as As or P or Sb
  • an SSRW can be formed by implanting a p-type impurity such as In, BF 2 or B, thereby effectively improving the leakage current between the strips.
  • the SSRW 112 in Fig. 9 is only shown as a regular rectangular shape for convenience of illustration. In fact, the shape of the SSRW 112 is determined by the implantation process and may not have clear boundaries.
  • a conformal dielectric layer e.g., Hf0 2
  • a gate conductor layer e.g., polysilicon
  • the conductor layer is anisotropically etched to remove a portion of the conductor layer extending in parallel with the main surface of the semiconductor substrate 101.
  • the vertically extending portion of the gate conductor layer on the sidewall of the third masking layer 109 remains, forming a gate conductor 113 in the form of a sidewall spacer.
  • the gate stack includes a gate dielectric 114 and a gate conductor 113, wherein the gate dielectric 114 separates the gate conductor 113 from the semiconductor substrate 101, as shown in FIG.
  • the dielectric layer has a thickness of about 2-4 nm.
  • the gate conductor layer has a thickness of about 9-30 nm.
  • a success function adjustment layer (not shown) may be formed between the gate conductor 113 and the gate dielectric 114.
  • the work function adjusting layer may include, for example, TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa, NiTa, MoN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi, Ni 3 Si, Pt, Ru, Ir Mo, HfRu, RuO x and combinations thereof may have a thickness of about 2-10 nm.
  • the work function adjusting layer is a preferred layer, and a gate stack including a work function adjusting layer (such as Hf0 2 /TiN/poly Si) can advantageously obtain a reduced gate leakage current.
  • a work function adjusting layer such as Hf0 2 /TiN/poly Si
  • the second MOSFET 12 including the extension regions 108a, 111a, the source/drain regions 108b, 111b, the SSRW 112, the gate conductor 113, and the gate dielectric 114 is formed in the second active region.
  • a dielectric layer 115 is formed over the semiconductor structure by the above-described known deposition process.
  • the dielectric layer 115 is planarized, for example, by chemical mechanical polishing (CMP) to obtain a flat surface of the semiconductor structure, as shown in FIG. Only the portion of the dielectric layer 115 covering the second MOSFET is shown in the figure. Alternatively, the dielectric layer 115 may cover both the first MOSFET and the second MOSFET.
  • the first masking layer 106, the third masking layer 109, and the dielectric layer 115 serve as an interlayer dielectric (ILD).
  • ILD interlayer dielectric
  • a first masking layer 106 is formed on the surface of the semiconductor structure, and the first masking layer 106 is patterned. After the patterning step, the first masking layer 106 covers not only the first active region of the first MOSFET 100 but also a portion of the second active region of the second MOSFET to be formed.
  • a sacrificial spacer 110' is formed on a sidewall of the first masking layer 106 exposed through the opening, as shown in Fig. 12.
  • the extension region 111a is formed in the semiconductor substrate 101 by the first ion implantation and the second ion implantation.
  • a second masking layer 107' is formed on the surface of the semiconductor structure.
  • the first masking layer 106 and the second masking layer 107' are planarized such that the second masking layer 107' is flush with the first masking layer 106 and exposes the top surface of the sacrificial sidewall 110', as shown in FIG. .
  • a first active region of the first MOSFET 100 is blocked with a photoresist mask, relative to the second masking layer 107' (eg, silicon oxide) and the sacrificial sidewall 110' (eg, polysilicon or amorphous Silicon), a portion of the first masking layer 106 (eg, silicon nitride) is selectively etched to form an opening that exposes a surface of a portion of the semiconductor substrate 101 in the second active region, as shown in FIG.
  • This selective etching can be carried out, for example, by hot phosphoric acid.
  • the spacer 110' serves as a hard mask, and the extension region 108a and the other of the source and drain regions 108b are formed in the semiconductor substrate 101 by the third ion implantation and the fourth ion implantation, as shown in FIG.
  • the sacrificial spacer 110' is selectively removed with respect to the first masking layer 106 and the second masking layer 107' by etching.
  • an ultra-steep back-off trap (SSRW) 112 is formed through the opening by the fifth ion implantation, as shown in FIG.
  • a gate stack is formed on one sidewall of the second masking layer 107' exposed through the opening, the gate stack including the gate conductor 118 and the gate conductor 118 and the semiconductor substrate 101 Between the gate dielectric 113, as shown in FIG. Alternatively, a success function adjustment layer (not shown) may be formed between the gate conductor 113 and the gate dielectric 114.
  • a third masking layer 109' is formed on the semiconductor structure to fill the opening as shown in FIG.
  • FIGS. 20-27 A flow of manufacturing a semiconductor device in accordance with a third embodiment of the present disclosure will be described with reference to FIGS. 20-27.
  • elements corresponding to those of the first embodiment are denoted by like reference numerals, and detailed descriptions of materials, structures, and manufacturing processes are omitted.
  • a second masking layer 107" covering the second active region of the second MOSFET to be formed is formed.
  • An opening is formed in the second masking layer 107".
  • the difference from the step shown in FIG. 3 is that the opening exposes a portion of the semiconductor substrate 101 where one of the source and drain regions is to be formed, and a semiconductor liner adjacent to one of the source and drain regions.
  • the bottom 101 will be used as part of the channel region.
  • a first ion implantation is performed via the opening, and an ultra-steep back well (RRSW) 112 is formed in the semiconductor substrate 101, as shown in Fig. 20.
  • RRSW ultra-steep back well
  • a sacrificial spacer 110" is formed on a sidewall of the second masking layer 107 "exposed through the opening, as shown in FIG.
  • a second ion implantation is performed through the opening to form the extension region 108a with the sacrificial spacer 110" as a hard mask, and then, along the main surface of the semiconductor substrate 101 A third ion implantation is performed to form one of the source and drain regions 108b, as shown in Figure 22.
  • additional ion implantation is performed to form a halo, or further optionally Annealing is performed to activate the implanted impurities.
  • the sacrificial spacer 110" is selectively removed with respect to the first masking layer 106 and the second masking layer 107 by a dry etching or a wet etching as described above using a suitable etchant. Then, similar to the steps shown in FIG. 10, A gate stack is formed on a sidewall of the second masking layer 107 that is exposed through the opening, the gate stack including a gate conductor 118 and a gate dielectric 113 between the gate conductor 118 and the semiconductor substrate 101, as shown in FIG. Alternatively, a success function adjustment layer (not shown) may be formed between the gate conductor 113 and the gate dielectric 114.
  • a third masking layer 109" is formed over the semiconductor structure to fill the opening in the second masking layer 107" as shown in FIG.
  • the second masking layer 107 is selectively removed with respect to the first masking layer 106 and the third masking layer 109 by a dry etching or wet etching as described above using a suitable etchant. " , as shown in Figure 25.
  • the extension region 111a and the source and drain regions are formed in the semiconductor substrate 101 by the fourth ion implantation and the fifth ion implantation with the sacrificial spacer 110" as a hard mask.
  • a dielectric layer 115" covering at least the second MOSFET is formed, as shown in Fig. 27.
  • first, second, and third embodiments according to the present disclosure describe the step of further forming the second MOSFET after forming the conventional first MOSFET.
  • a gate stack of the second MOSFET is formed on the sidewall of the masking layer. Therefore, the gate length of the second MOSFET can be significantly smaller than the gate length of the first MOSFET, for example, the gate length of the second MOSFET is about 5-20 nm.
  • an interlayer insulating layer, a via hole in the interlayer insulating layer, a wiring or an electrode on the upper surface of the interlayer insulating layer may be formed on the obtained semiconductor structure. , thus completing the rest of the MOSFET.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

公开了一种半导体器件和一种制造半导体器件的方法。该方法包括：在半导体衬底（101）中形成具有第一栅长的第一MOSFET（100）；以及在半导体衬底（101）中形成具有第二栅长的第二MOSFET，其中第二栅长小于第一栅长，其中，第二MOSFET具有侧墙形式的栅堆叠，该栅堆叠包括栅极导体（113）和栅极电介质（114），栅极电介质（114）将栅极导体（113）与半导体衬底（101）隔开。

Description

半导体器件及其制造方法 本申请要求了 2012年 11月 12日提交的、 申请号为 201210451050. 2、 发明名称 为 "半导体器件及其制造方法"的中国专利申请的优先权， 其全部内容通过引用结合 在本申请中。 技术领域
本公开涉及半导体领域， 更具体地， 涉及用于集成具有不同栅长的金属氧化物半 导体场效应晶体管 （M0SFET ) 的半导体器件及其制造方法。 背景技术
随着半导体器件的尺寸越来越小， 短沟道效应愈加明显。 为此， 提出了使用包括 高 K栅介质和金属栅极导体的栅堆叠。 为避免栅堆叠的性能退化， 包括这种栅堆叠的 半导体器件通常利用替代栅工艺来制造。替代栅工艺涉及在栅侧墙之间限定的孔隙中 形成高 κ栅介质和金属栅极导体。 然而， 由于器件尺寸的缩小， 要在如此小的栅极开 口中形成高 κ栅介质和金属导体越来越困难。
因此， 仍然期望制造和集成小栅极尺寸的 M0SFET的方法。 尤其期望在一个半导 体衬底集成不同栅长的 M0SFET的方法。 发明内容
本公开的目的至少部分地在于提供一种集成具有不同栅长的 M0SFET的方法。 根据本公开的方法， 提供一种制造半导体器件的方法， 包括： 在半导体衬底中形 成具有第一栅长的第一 M0SFET ; 以及在半导体衬底中形成具有第二栅长的第二 M0SFET, 其中第二栅长小于第一栅长， 其中， 第二 M0SFET具有侧墙形式的栅堆叠， 该栅堆叠包括栅极导体和栅极电介质， 栅极电介质将栅极导体与半导体衬底隔开。
根据本公开的另一方面， 提供一种半导体器件， 包括： 半导体衬底； 位于半导体 衬底中的具有第一栅长的第一 M0SFET;以及位于半导体衬底中的具有第二栅长的第二 M0SFET, 其中第二栅长小于第一栅长， 其中， 第二 M0SFET具有侧墙形式的栅堆叠， 该栅堆叠包括栅极导体和栅极电介质， 栅极电介质位于栅极导体与半导体衬底之间。
本公开针对第一 M0SFET和第二 M0SFET形成不同结构的栅堆叠，其中第一 M0SFET 包括常规的栅堆叠， 第二 MOSFET包括侧墙形式的栅堆叠。 因此， 第二 MOSFET的栅长 可以比第一 MOSFET的栅长小很多。 本公开提供了在一个半导体衬底上集成不同栅长 的 MOSFET的方法。 在本公开的优选实施例中， 首先形成牺牲侧墙， 然后采用栅堆叠 替代牺牲侧墙， 这可以减少掩模的使用以及对复杂的光刻工艺的需求， 从而降低制造 成本。 附图说明
通过以下参照附图对本公开实施例的描述， 本公开的上述以及其他目的、特征和 优点将更为清楚， 在附图中：
图 1-11是示出了根据本公开的第一实施例的制造半导体器件流程的示意图。 图 12-19是示出了根据本公开的第二实施例的制造半导体器件流程的一部分步骤 的示意图。
图 20-27是示出了根据本公开的第三实施例的制造半导体器件流程的一部分步骤 的示意图。 具体实施方式
以下将参照附图更详细地描述本公开。在各个附图中， 相同的元件采用类似的附 图标记来表示。 为了清楚起见， 附图中的各个部分没有按比例绘制。
为了简明起见， 可以在一幅图中描述经过数个步骤后获得的半导体结构。
应当理解， 在描述器件的结构时， 当将一层、 一个区域称为位于另一层、 另一个 区域 "上面"或 "上方" 时， 可以指直接位于另一层、 另一个区域上面， 或者在其与 另一层、 另一个区域之间还包含其它的层或区域。 并且， 如果将器件翻转， 该一层、 一个区域将位于另一层、 另一个区域 "下面"或 "下方" 。
如果为了描述直接位于另一层、 另一个区域上面的情形， 本文将采用 "直接 在……上面"或 "在……上面并与之邻接" 的表述方式。
在本申请中，术语 "半导体结构"指在制造半导体器件的各个步骤中形成的整个 半导体结构的统称， 包括已经形成的所有层或区域。在下文中描述了本公开的许多特 定的细节， 例如器件的结构、 材料、 尺寸、 处理工艺和技术， 以便更清楚地理解本公 开。但正如本领域的技术人员能够理解的那样， 可以不按照这些特定的细节来实现本 公开。 除非在下文中特别指出， MOSFET的各个部分可以由本领域的技术人员公知的材料 构成。 半导体材料例如包括 III-V族半导体， 如 GaAs、 InP、 GaN、 SiC， 以及 IV族半 导体， 如 Si、 Ge。 栅极导体可以由能够导电的各种材料形成， 例如金属层、 掺杂多晶 硅层、 或包括金属层和掺杂多晶硅层的叠层栅极导体或者是其他导电材料， 例如为 TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax, MoNx、 TiSiN、 TiCN、 TaAlC、 TiAlN、 TaN、 PtSix、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 HfRu、 Ru0x |和所述各 种导电材料的组合。栅极电介质可以由 5102或介电常数大于 Si02的材料构成，例如包 括氧化物、氮化物、氧氮化物、硅酸盐、铝酸盐、钛酸盐，其中，氧化物例如包括 Si02、 Hf02、 Zr02、 A1203、 Ti02、 L¾03, 氮化物例如包括 Si ， 硅酸盐例如包括 Hf Si0x， 铝酸 盐例如包括 LaA103， 钛酸盐例如包括 SrTi03， 氧氮化物例如包括 SiON。 并且， 栅极电 介质不仅可以由本领域的技术人员公知的材料形成，也可以采用将来开发的用于栅极 电介质的材料。
在常规工艺中， 在利用 "伪"栅堆叠以及该伪栅堆叠两侧的侧墙在衬底中制造出 源区和漏区之后， 保留两侧的侧墙而在侧墙之间限定出孔隙， 通过填充孔隙来形成真 正的栅堆叠。 与此不同， 在本公开中， 提出了一种 "替代侧墙"工艺。 在形成源区和 漏区之后， 保留位于源区和漏区之一一侧的材料层， 并在该保留的材料层的侧壁上以 侧墙的形式形成栅堆叠 （特别是， 栅极导体）。 从而可以在较大的空间 （具体地， 大 致为栅区 +源区和漏区中另一个的区域） 上来形成栅堆叠， 相比于仅在侧墙之间的小 栅极开口中形成栅堆叠的常规工艺， 可以使得工艺更加容易进行。
本公开可以各种形式呈现， 以下将描述其中一些示例。
参照图 1-11描述根据本公开的第一实施例的制造半导体器件的流程。
如图 1所示， 提供衬底 101。 该衬底 101可以是各种形式的衬底， 例如但不限于 体半导体材料衬底如体 Si衬底、 绝缘体上半导体（S0I )衬底、 SiGe衬底等。 在以下 的描述中， 为方便说明， 以体 Si衬底为例进行描述。 在衬底 101上， 可以形成有浅 沟槽隔离（STI ) 102， 用以隔离单独器件的有源区。 STI 102例如可以包括氧化物（例 如， 氧化硅）。 这里需要指出的是， 在以下描述的示例中， 为方便说明， 仅形成两个 半导体器件的情况， 其中 STI 102在图 1中的左侧和右侧限定两个半导体器件的有源 区。 但是本公开不局限于此， 而是可以应用于形成更多个半导体器件的情况。
在半导体衬底 101上已经采用常规的工艺形成第一 MOSFET 100。第一 MOSFET 100 的第一有源区是图 1中由 STI 102限定的左侧区域。 第一 MOSFET 100包括在半导体 衬底上形成的栅堆叠，该栅堆叠包括位于半导体衬底 101上的栅极电介质 102以及位 于栅极电介质 102上的栅极导体 103。 栅极电介质 102将栅极导体 103与半导体衬底 101隔开。侧墙 105围绕栅极导体 103而形成。第一 M0SFET 100还包括在半导体衬底 101中形成的源 /漏区 （未示出）、 延伸区 （未示出） 和可选的暈圈区 （未示出）。
正如本领域的技术人员可以理解的那样， 可以采用各种工艺制造第一 M0SFET 100， 例如采用已知的 "先栅工艺"或 "替代栅工艺"。
接下来， 通过已知的沉积工艺， 如 CVD (化学气相沉积）、 原子层沉积、 溅射等， 在半导体结构的表面上形成厚度约为 100-200nm的第一掩蔽层 106。 第一掩蔽层 106 可以由氧化物 （例如， 氧化硅） 组成。
然后， 通过旋涂在第一掩蔽层 106上形成光致抗蚀剂层 （未示出）， 并通过其中 包括曝光和显影的光刻工艺将光致抗蚀剂层形成图案。 利用光致抗蚀剂层作为掩模， 通过干法蚀刻， 如离子铣蚀刻、 等离子蚀刻、 反应离子蚀刻、 激光烧蚀， 或者通过其 中使用蚀刻剂溶液的湿法蚀刻，去除第一掩蔽层 106位于图 1的右侧区域（即 STI 102 围绕的第二有源区） 中的部分。 通过在溶剂中溶解或灰化去除光致抗蚀剂层。
在上述图案化步骤之后， 第一掩蔽层 106仅覆盖第一 M0SFET 100的第一有源区， 如图 2所示。
接下来， 通过上述的已知的沉积工艺， 在半导体结构的表面上形成厚度约为 100-200nm的第二掩蔽层 107。 第二掩蔽层 107可以由氮化物 （例如， 氮化硅）组成。 优选地，第二掩蔽层 107可以包括氮化物层和氧化物层，氧化物层位于氮化物层上方。 采用第一掩蔽层 106作为停止层， 对第二掩蔽层 107进行平面化处理， 例如采用化学 机械抛光 （CMP)， 获得平整的半导体结构的表面。 结果， 第一掩蔽层 106和第二掩蔽 层 107邻接， 并且第一掩蔽层 106覆盖第一 M0SFET 100的第一有源区， 而第二掩蔽 层 107覆盖将要形成的第二 M0SFET的第二有源区。
例如采用光致抗蚀剂掩模，通过上述的图案化步骤在第二掩蔽层 107中形成开口， 开口暴露第二有源区中半导体衬底 101的一部分的表面。优选地， 开口与第一掩蔽层 106相邻并且暴露第一有源区和第二有源区之间的 STI 102的一部分， 如图 3所示。 开口暴露半导体衬底 101中将要形成源区和漏区中的一个的部分。
接下来， 穿过开口， 沿着垂直于半导体衬底 101的主表面的方向进行第一离子注 入以形成延伸区 108a。在第一离子注入中， 对于 p型器件， 可以通过注入 p型杂质如 In、 BF2或 B; 对于 n型器件， 可以通过注入 n型杂质如 As或 P， 来形成延伸区。 然后， 仍然穿过开口， 沿着与半导体衬底 101的主表面倾斜的方向进行第二离子 注入以形成源区和漏区中的一个 108b。第二离子注入的方向相对于第一离子注入的方 向顺时针地偏离某一角度 （小于 90 ° ， 例如为 15 ° )， 使得在第二离子注入期间， 第 二掩蔽层 107阻挡一部分离子。 结果， 注入的离子仅在靠近 STI 102的位置进入半导 体衬底 101中而形成源区和漏区中的一个。第二离子注入的深度比第一离子注入的深 度大。在第二离子注入中， 对于 P型器件， 可以采用上述的 P型杂质； 对于 n型器件， 可以采用上述的 n型杂质。 正如本领域的技术人员可以理解的那样， 延伸区 108a和 源区和漏区中的一个 108b彼此叠加， 两者没有清晰的边界， 如图 4所示。
可选地， 在第一离子注入之前， 还可以穿过开口进行附加的离子注入以形成暈圈 (未示出）。 该附加的离子注入的方向相对于第一离子注入的方向逆时针偏离某一角 度 （小于 90 ° ， 例如为 15 ° )， 使得在该附加的离子注入期间， 第一掩蔽层 106阻挡 一部分离子。 结果， 注入的离子仅在远离 STI 102的位置进入半导体衬底 101中而形 成暈圈。 该附加的离子注入的深度比第一离子注入的深度和第二离子注入的深度均 大。 在该附加的离子注入中， 对于 P型器件， 可以采用上述的 n型杂质； 对于 n型器 件， 可以采用上述的 P型杂质。
可选地， 在第二离子注入之后， 可以进行退火处理例如尖峰退火、 激光退火、 快 速退火等， 以激活注入的杂质。
接下来， 通过上述已知的沉积工艺， 在半导体结构上形成第三掩蔽层 109 (例如， 氧化物）， 第三掩蔽层 109的材料填充开口。进行平面化处理， 例如采用 CMP， 获得平 整的半导体结构的表面， 如图 5所示。用于填充开口的第三掩蔽层 109的材料可以与 第一掩蔽层 106相同。 如果第二掩蔽层 107包括氮化物层和氧化物层， 则 CMP步骤只 需停止于氮化物层即可。
接下来， 采用合适的蚀刻剂， 通过上述的干法蚀刻或湿法蚀刻， 相对于第一掩蔽 层 106、 第三掩蔽层 109选择性去除第二掩蔽层 107， 如图 6所示。 该蚀刻停止在半 导体衬底 101的表面上。优选地， 可以在半导体衬底 101的表面上设置附加的氧化物 层 （未示出）， 以提供蚀刻的选择性。
接下来， 通过上述已知的沉积工艺， 在半导体结构的表面上沉积例如 8-30纳米 的氮化物层， 然后通过各向异性蚀刻在第一掩蔽层 106的侧壁上形成牺牲侧墙 110， 如图 7所示。 该牺牲侧墙 110的形成和材料与常规的栅极侧墙相同。 如下文将要描述 的那样， 该牺牲侧墙 110最终去除并由栅极堆叠代替。 接下来， 以牺牲侧墙 110作为硬掩模， 按照结合图 4已经描述的方法， 通过第三 离子注入和第四离子注入在半导体衬底 101中形成延伸区 111a和源区和漏区中的另 一个 l l lb， 如图 8所示。
可选地，在第三离子注入之前，还可以进行附加的离子注入以形成暈圈（未示出）。 可选地， 在第四离子注入之后， 可以进行退火处理例如尖峰退火、 激光退火、 快 速退火等， 以激活注入的杂质。
接下来， 采用合适的蚀刻剂， 通过上述的干法蚀刻或湿法蚀刻， 相对于第一掩蔽 层 106、 第三掩蔽层 109选择性去除牺牲侧墙 110。
可选地，为更好地控制短沟道效应以及抑制带间泄露，可以通过第五离子注入（图 中箭头所示）， 形成超陡后退阱 （SSRW) 112， 如图 9所示。 例如， 对于 p型器件， 可 以通过注入 n型杂质如 As或 P或 Sb; 对于 n型器件， 可以通过注入 p型杂质如 In、 BF2或 B， 来形成 SSRW, 从而有效改善带间泄露电流。 这里需要指出的是， 图 9中的 SSRW 112仅仅是为了图示方便而示出为规则的矩形形状。 实际上， SSRW 112的形状 由注入工艺决定， 并且可能没有清晰的边界。
接下来， 通过已知的沉积工艺， 在半导体结构的表面上依次形成共形的电介质层 (例如 Hf02) 以及栅极导体层 （例如多晶硅）。 对导体层进行各向异性蚀刻， 以去除 导体层与半导体衬底 101的主表面平行延伸的部分。 栅极导体层位于第三掩蔽层 109 的侧壁上的垂直延伸的部分保留， 形成侧墙形式的栅极导体 113。 进一步地， 采用栅 极导体 113作为硬掩模并采用合适的蚀刻剂， 相对于栅极导体 113和第三掩蔽层 109 选择性地去除电介质层的暴露部分， 以形成栅极电介质 114。 栅堆叠包括栅极电介质 114和栅极导体 113， 其中栅极电介质 114将栅极导体 113与半导体衬底 101隔开， 如图 10所示。
电介质层的厚度约为 2-4纳米。 栅极导体层的厚度约为 9-30纳米。 结果， 通过 控制栅极导体层的厚度，所形成的栅极导体 113与图 7所示的牺牲侧墙 110大致对准， 进而使得所形成的栅极导体 113与延伸区 111a和源区和漏区中的另一个 111b大致对 准。
可选地， 在栅极导体 113和栅极电介质 114之间还可以形成功函数调节层（未示 出）。 功函数调节层例如可以包括 TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTa、 NiTa、 MoN、 TiSiN、 TiCN、 TaAlC、 TiAlN、 TaN、 PtSi、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 HfRu、 RuOx及其组合， 厚度可以约为 2_10nm。 正如本领域的技术人员已知的 那样， 功函数调节层是优选的层， 包含功函数调节层的栅堆叠（如 Hf02/TiN/多晶 Si ) 可以有利地获得减小的栅极漏电流。
结果， 在第二有源区中形成包括延伸区 108a、 111a, 源 /漏区 108b、 111b, SSRW 112、 包括栅极导体 113和栅极电介质 114的第二 MOSFET 12。
接下来， 通过上述已知的沉积工艺， 在半导体结构上形成电介质层 115。 对电介 质层 115进行平面化处理， 例如采用化学机械抛光（CMP)， 获得平整的半导体结构的 表面， 如图 10所示。 在图中示出仅保留电介质层 115覆盖第二 MOSFET的部分。 替代 地， 电介质层 115可以覆盖第一 MOSFET和第二 MOSFET二者。 第一掩蔽层 106、 第三 掩蔽层 109和电介质层 115—起作为层间电介质 （ILD)。 参照图 12-19描述根据本公开的第二实施例的制造半导体器件的流程。在第二实 施例中， 与第一实施例对应的元件采用类似的附图标记表示， 并且省略对其材料、 结 构和制造工艺的详细描述。
接着图 1所示的步骤， 与图 2所示的步骤类似， 在半导体结构的表面上形成第 一掩蔽层 106， 并且图案化第一掩蔽层 106。 在图案化步骤之后， 第一掩蔽层 106不 仅覆盖第一 MOSFET 100的第一有源区， 而且覆盖将要形成的第二 MOSFET的第二有源 区的一部分。 接着， 与图 7所示的步骤类似， 在第一掩蔽层 106经由开口暴露的一个 侧壁上形成牺牲侧墙 110 ' ， 如图 12所示。
接下来， 与图 8所示的步骤类似， 以第一掩蔽层 106和牺牲侧墙 110 ' 作为硬掩 模， 通过第一离子注入和第二离子注入在半导体衬底 101中形成延伸区 111a和源区 和漏区中的一个 l l lb， 如图 13所示。
接下来， 在半导体结构的表面上形成第二掩蔽层 107 ' 。 对第一掩蔽层 106和第 二掩蔽层 107 ' 进行平面化处理， 使得第二掩蔽层 107 ' 与第一掩蔽层 106齐平， 并 且暴露牺牲侧墙 110 ' 的顶部表面， 如图 14所示。
接下来， 采用光致抗蚀剂掩模遮挡第一 MOSFET 100的第一有源区， 相对于第二 掩蔽层 107 ' (例如， 氧化硅） 以及牺牲侧墙 110 ' (例如， 多晶硅或非晶硅）， 选择 性刻蚀第一掩蔽层 106 (例如， 氮化硅） 的一部分， 以形成暴露第二有源区中半导体 衬底 101的一部分的表面的开口， 如图 15所示。 这种选择性刻蚀例如可以通过热磷 酸来进行。
接下来， 与图 8所示的步骤类似， 以第一掩蔽层 106、 第二掩蔽层 107 ' 和牺牲 侧墙 110 ' 作为硬掩模， 通过第三离子注入和第四离子注入在半导体衬底 101中形成 延伸区 108a和源区和漏区中的另一个 108b， 如图 16所示。
接下来， 与图 9所示的步骤类似， 通过蚀刻， 相对于第一掩蔽层 106、 第二掩蔽 层 107 ' 选择性去除牺牲侧墙 110 ' 。 可选地， 通过第五离子注入， 经由开口形成超 陡后退阱 （SSRW) 112， 如图 17所示。
接下来，与图 10所示的步骤类似，在第二掩蔽层 107 ' 经由开口暴露的一个侧壁 上形成栅堆叠，该栅堆叠包括栅极导体 118和位于栅极导体 118和半导体衬底 101之 间的栅介质 113， 如图 18所示。可选地， 在栅极导体 113和栅极电介质 114之间还可 以形成功函数调节层 （未示出）。
接下来， 与图 5所示的步骤类似， 在半导体结构上形成第三掩蔽层 109 ' 以填充 开口， 如图 19所示。
参照图 20-27描述根据本公开的第三实施例的制造半导体器件的流程。在第三实 施例中， 与第一实施例对应的元件采用类似的附图标记表示， 并且省略对其材料、 结 构和制造工艺的详细描述。
接着图 2所示的步骤， 在形成第一掩蔽层 106之后， 与图 3所示的步骤类似， 形 成覆盖将要形成的第二 M0SFET 的第二有源区的第二掩蔽层 107 " 。 在第二掩蔽层 107 " 中形成开口。然而，与图 3所示的步骤不同之处在于该开口暴露半导体衬底 101 中将要形成源区和漏区中的一个的部分， 以及与该源区和漏区中的一个相邻的半导体 衬底 101中将要用作沟道区的部分。 接着， 与图 9所示的步骤类似， 可选地， 经由该 开口进行第一离子注入， 在半导体衬底 101中形成超陡后阱阱 （RRSW) 112， 如图 20 所示。
然后， 与图 7所示的步骤类似， 在第二掩蔽层 107 "经由开口暴露的一个侧壁上 形成牺牲侧墙 110 " ， 如图 21所示。
然后， 与图 4所示的步骤类似， 以牺牲侧墙 110 "作为硬掩模， 穿过开口进行第 二离子注入以形成延伸区 108a，接着，沿着与半导体衬底 101的主表面倾斜的方向进 行第三离子注入以形成源区和漏区中的一个 108b， 如图 22所示。 在第三离子注入之 后， 可选地， 执行附加的离子注入以形成暈圈， 或者进一步可选地， 进行退火处理以 激活注入的杂质。
然后， 采用合适的蚀刻剂， 通过上述的干法蚀刻或湿法蚀刻， 相对于第一掩蔽层 106、 第二掩蔽层 107 "选择性去除牺牲侧墙 110 " 。 接着， 与图 10所示的步骤类似， 在第二掩蔽层 107 "经由开口暴露的一个侧壁上形成栅堆叠， 该栅堆叠包括栅极导体 118和位于栅极导体 118和半导体衬底 101之间的栅介质 113，如图 23所示。可选地， 在栅极导体 113和栅极电介质 114之间还可以形成功函数调节层 （未示出）。
然后， 与图 5所示的步骤类似， 在半导体结构上形成第三掩蔽层 109 " 以填充第 二掩蔽层 107 " 中的开口， 如图 24所示。
然后， 与图 6所示的步骤类似， 采用合适的蚀刻剂， 通过上述的干法蚀刻或湿法 蚀刻， 相对于第一掩蔽层 106、第三掩蔽层 109 "选择性去除第二掩蔽层 107 " ， 如图 25所示。
然后， 与图 8所示的步骤类似， 以牺牲侧墙 110 "作为硬掩模， 通过第四离子注 入和第五离子注入在半导体衬底 101 中形成延伸区 111a和源区和漏区中的另一个 111b, 如图 26所示。
然后， 与图 11所示的步骤类似， 形成至少覆盖第二 M0SFET的电介质层 115 " ， 如图 27所示。
上述根据本公开的第一实施例、第二实施例和第三实施例描述了在形成常规的第 一 M0SFET之后进一步形成第二 M0SFET的步骤。 第二 M0SFET的栅堆叠形成在掩蔽层 的侧壁上。 因此， 第二 M0SFET的栅长可以显著小于第一 M0SFET的栅长， 例如， 第二 M0SFET的栅长约为 5-20nm。
在图 11、图 19和图 27所示的步骤之后，可以在所得到的半导体结构上形成层间 绝缘层、 位于层间绝缘层中的通孔、 位于层间绝缘层上表面的布线或电极， 从而完成 M0SFET的其他部分。
在以上的描述中， 对于各层的构图、 蚀刻等技术细节并没有做出详细的说明。 但 是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。 另外， 为了形成同一结构， 本领域技术人员还可以设计出与以上描述的方法并不完全 相同的方法。 另外， 尽管在以上分别描述了各实施例， 但是这并不意味着各个实施例 中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。 但是， 这些实施例仅仅是为了说明的目的， 而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。 不脱 离本公开的范围， 本领域技术人员可以做出多种替代和修改， 这些替代和修改都应落 在本公开的范围之内。

Claims

权 利 要 求
1、 一种制造半导体器件的方法， 包括：
在半导体衬底中形成具有第一栅长的第一 M0SFET; 以及
在半导体衬底中形成具有第二栅长的第二 M0SFET, 其中第二栅长小于第一栅长， 其中， 第二 MOSFET具有侧墙形式的栅堆叠， 该栅堆叠包括栅极导体和栅极电介 质， 栅极电介质将栅极导体与半导体衬底隔开。
2、 根据权利要求 1所述的方法， 其中形成第二 M0SFFET包括：
以掩蔽层作为掩模形成第二 MOSFET的源区和漏区之一；
以牺牲侧墙作为掩模形成第二 MOSFET的源区和漏区中另一个； 以及
采用栅堆叠替代牺牲侧墙。
3、 根据权利要求 1所述的方法， 其中形成第二 MOSFET包括：
以牺牲侧墙作为掩模形成第二 MOSFET的源区和漏区之一；
以牺牲侧墙作为掩模形成第二 MOSFET的源区和漏区中另一个； 以及
采用栅堆叠替代牺牲侧墙。
4、 根据权利要求 1所述的方法， 其中形成第二 M0SFFET包括：
以牺牲侧墙作为掩模形成第二 MOSFET的源区和漏区之一；
采用栅堆叠替代牺牲侧墙； 以及
以掩蔽层作为掩模形成第二 MOSFET的源区和漏区中另一个。
5、根据权利要求 2至 4中任一项所述的方法， 其中采用以下步骤形成牺牲侧墙: 形成具有一个暴露的侧壁的另一个掩蔽层； 以及
在该另一个掩蔽层的侧壁上形成牺牲侧墙。
6、 根据权利要求 5所述的方法， 其中采用栅堆叠替代牺牲侧墙包括： 去除牺牲侧墙；
形成共形的电介质层， 电介质层至少覆盖该另一个掩蔽层的侧壁和半导体衬底的 表面；
在电介质层上形成共形的导体层；
将导体层图案化为栅极导体； 以及
以栅极导体作为掩模， 将电介质层图案化为栅极电介质。
7、 根据权利要求 6所述的方法， 其中栅极导体的厚度与牺牲侧墙的厚度大致相
8、 一种半导体器件， 包括：
半导体衬底；
位于半导体衬底中的具有第一栅长的第一 MOSFET; 以及
位于半导体衬底中的具有第二栅长的第二 MOSFET, 其中第二栅长小于第一栅长， 其中， 第二 MOSFET具有侧墙形式的栅堆叠， 该栅堆叠包括栅极导体和栅极电介 栅极电介质位于栅极导体与半导体衬底之间。
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