WO2014044095A1 - 充电控制电路和充电装置以及充电控制方法和充电方法 - Google Patents

充电控制电路和充电装置以及充电控制方法和充电方法 Download PDF

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Publication number
WO2014044095A1
WO2014044095A1 PCT/CN2013/081343 CN2013081343W WO2014044095A1 WO 2014044095 A1 WO2014044095 A1 WO 2014044095A1 CN 2013081343 W CN2013081343 W CN 2013081343W WO 2014044095 A1 WO2014044095 A1 WO 2014044095A1
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WIPO (PCT)
Prior art keywords
current
voltage
charging
signal
threshold
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PCT/CN2013/081343
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English (en)
French (fr)
Inventor
江力
戴加良
熊江
Original Assignee
炬力集成电路设计有限公司
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Application filed by 炬力集成电路设计有限公司 filed Critical 炬力集成电路设计有限公司
Priority to EP13839677.5A priority Critical patent/EP2899838B1/en
Priority to US14/415,077 priority patent/US9455590B2/en
Publication of WO2014044095A1 publication Critical patent/WO2014044095A1/zh

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Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007Regulation of charging or discharging current or voltage
    • H02J7/00712Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters
    • H02J7/007182Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters in response to battery voltage
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/00302Overcharge protection

Definitions

  • the present invention relates to a charging technique, and more particularly to a charging control circuit and a charging device suitable for a charging mode in which an output voltage and an output current are adjustable, and a charging control method and a charging method.
  • FIG. 1 is a schematic structural diagram of a charging device in the prior art. As shown in Fig. 1, the charging device 1 is for charging a battery 100, and the charging device 1 includes a charging execution circuit 11, a charging protection circuit 12, and a charging control circuit 13.
  • the charging execution circuit 11 is configured to generate an output voltage Vout and an output current lout from its charging output terminal during charging, and adjust the generated output voltage Vout and the output current lout.
  • the charge execution circuit 11 includes differential amplifiers 111 and 112, a voltage selector 113, and an adjustable switch 114 (herein, only a PMOS is used as the adjustable switch 114); a negative input terminal of the differential amplifier 111 serves as a charge execution circuit.
  • a current reference input terminal of 11 and a negative input terminal of the differential amplifier 112 serve as a voltage reference input terminal of the charge performing circuit 11, and a drain D of the PMOS 114 serves as the above-described charge output terminal of the charge performing circuit 11.
  • a negative input terminal of the differential amplifier 111 receives the input calibration current reference Iref_s, and the other positive input terminal of the differential amplifier 111 receives the output current lout fed back from the charging output terminal of the charging execution circuit 11, and the output terminal of the differential amplifier 111 has an output.
  • a control signal Ctrl_I of the positive voltage value, the positive voltage value of the control signal Ctrl_I represents the current difference amplitude of the output current lout compared to the calibration current reference Iref_s;
  • a negative input terminal of the differential amplifier 112 receives the input calibration voltage reference Vref_s, and the other positive input terminal of the differential amplifier 112 receives the charge output terminal of the charge execution circuit 11.
  • the output voltage Vout, the output of the differential amplifier 112 outputs a control signal Ctrl-V having a positive voltage value, and the positive voltage value of the control signal Ctrl-V represents the voltage of the output voltage Vout compared to the calibration voltage reference Vref_s Difference
  • the voltage selector 113 receives the above-mentioned control signal Ctrl-1 and the control signal Ctrl-V, and the voltage selector 113 also receives the charge protection circuit 12 according to the state of charge signal S (for example, the state for indicating the power source VccO, the internal temperature of the charging device 1) a control signal Ctrl_P of the signal of the internal temperature of the battery 100, the positive voltage value of the control signal Ctrl_P indicates whether the abnormality is abnormal, and the positive voltage value of the control signal Ctrl_P is abnormal.
  • the state of charge signal S for example, the state for indicating the power source VccO, the internal temperature of the charging device 1
  • a control signal Ctrl_P of the signal of the internal temperature of the battery 100 the positive voltage value of the control signal Ctrl_P indicates whether the abnormality is abnormal, and the positive voltage value of the control signal Ctrl_P is abnormal.
  • the voltage selector 113 selects the largest one from the positive voltage values of the control signal Ctrl_I, the control signal Ctrl_V, and the control signal Ctrl-P (this article only takes the maximum selection as an example, but the practical application It is also possible to select the smallest case for different component characteristics), and set the gate G of the PMOS 114 to the selected maximum positive voltage value;
  • the source S of the PMOS 114 is connected to the input power source VccO, the drain D of the PMOS 114 is connected to the battery 100, and is used to generate the output current lout and the output voltage Vout; as the positive voltage value of the gate G of the PMOS 114 changes, the PMOS 114
  • the degree of conduction between the source S and the drain D can be adjusted accordingly to achieve adjustment of the output current lout; accordingly, since the output voltage Vout is equal to the core voltage V0 of the battery 100 and the internal resistance R0 of the battery 100
  • the sum of the voltage drops, and the voltage drop generated by the core voltage V0 and the internal resistance R0 are both related to the output current lout. Therefore, the adjustment of the output voltage Vout can also be achieved by adjusting the output current lout.
  • the charging control circuit 13 is configured to control the termination of charging according to whether the output current lout is less than the calibration current reference Iref_s.
  • the charge control circuit 13 includes a comparator 130.
  • a negative input terminal of the comparator 130 receives the output current lout fed back by the charging output terminal of the charging execution circuit 11, and the other positive input terminal of the comparator 130 receives the calibration current reference Iref s', and the output terminal of the comparator 130 A charge termination signal Fin_a is generated; when the output current lout is less than the calibration voltage reference Iref_s, the charge termination signal Fin_a is set to an active high level to trigger the charge termination of the charge execution circuit 11.
  • the calibration current reference Iref_s is a recognized current reference for constant current charging
  • the calibration current reference Iref_s is a recognized current reference for charging termination
  • the calibration current reference Iref_s is greater than the calibration current reference Iref_s
  • the above-mentioned calibration voltage reference Vref_s is a recognized voltage reference for charging termination.
  • the basic working principle of the charging device 1 shown in Fig. 1 will be described in detail in combination with the above-mentioned meanings of the calibration current reference Iref_s, the calibration current reference Iref_s, and the calibration voltage reference Vref_s. Since the charge protection circuit 12 is optional, not necessary, in the following detailed description, it is assumed that the control signal Ctrl_P_ outputted by the charge protection circuit 12 is held at a relatively low positive voltage value indicating no abnormality.
  • the output current lout is much smaller than the calibration current reference Iref_s, and the output voltage Vout is much smaller than the calibration voltage reference Vref_s.
  • the control signal Ctrl_I and the control signal Ctrl-V both have a lower positive voltage value, thereby making the voltage
  • the selector 112 also sets the gate G of the PMOS 114 to a lower positive voltage value; then, since the source S of the PMOS 114 is pulled high by the input power source VccO, the gate-source voltage difference VGS of the PMOS 114 is made negative. And less than the cutoff voltage of the PMOS 114, thereby maximizing the turn-on of the PMOS 114 and increasing the output current lout;
  • the positive voltage value of the control signal Ctrl_I will be higher than the control signal Ctrl-V, and accordingly, the gate G of the PMOS 114 is set to the control signal Ctrl-I by the voltage selector 112.
  • the positive voltage value and the conduction degree of the PMOS 114 are also controlled by the positive voltage value of Ctrl_I;
  • the internal voltage V0 of the battery 100 will gradually increase, and accordingly, the output voltage Vout will gradually increase from a lower voltage value which is much smaller than the calibration voltage reference Vref_s; since the positive voltage value of the control signal Ctrl-I will remain The positive voltage value indicating that the output current lout reaches the calibration current reference Iref_s, therefore, the positive voltage value of the control signal Ctrl_V is still lower than the control signal Ctrl-I as long as the output voltage Vout has not reached the calibration voltage reference Vref_s Positive voltage value;
  • the positive voltage value of the control signal Ctrl_V is higher than the positive voltage value of the control signal Ctrl_I, then at this time, the gate G of the PMOS 114
  • the voltage selector 112 is set to a higher positive value of the control signal Ctrl-V, so that the gate-source voltage difference VGS of the PMOS 114 is smaller than the off-voltage, so that the PMOS 114 is turned on and the output current is made. Lout is reduced, after which the constant voltage charging phase begins.
  • the output voltage Vout will be equal to the voltage reference Vref_s due to the negative feedback
  • the charge termination signal Fin_a becomes an active high level, thereby triggering the termination of charging (how to trigger the termination of charging is not of interest here, and those skilled in the art have mastered A variety of specific implementations, so I will not repeat them in this article.
  • the existing charging device 1 can realize the charging mode in which the output voltage Vout and the output current lout can be adjusted by using the charging execution circuit 11, and realize the control of the charging termination by using the charging control circuit 13, but, due to the existing charging device
  • the charging control circuit 13 in 1 is unreasonable in controlling the termination of charging, and lacks adjustment of the output voltage Vout to the charging execution circuit 11.
  • the control of the output current lout thus causing the following defects:
  • the output current lout is in the charging start phase, and the output current lout will instantaneously surge.
  • the control signal Ctrl_P of the charging protection circuit 12 triggers the charging restart phase after the charging suspension, or the battery 100 and the charging output terminal.
  • the output current lout is also likely to instantaneously surge, so that it is easy to cause an impact on the input power source VccO and the battery 100, resulting in a defect of low charging reliability.
  • the present invention provides a charging control circuit and a charging device, and a charging control method and a charging method.
  • a charging control circuit for controlling an adjustment of an output voltage and an output current generated by a charging execution circuit to a charging output thereof, and triggering charging of the charging execution circuit Terminating, the charging control circuit includes a current adjustment module and a detection control module;
  • the current adjustment module is configured to adjust a first current reference of the external input, and output the adjusted second current reference to a current reference input of the charge execution circuit to control the charge execution circuit to Adjusting an output voltage and the output current; wherein a minimum current value of the second current reference is less than the first current reference, and a maximum current value is equal to the first current reference;
  • the detection control module is configured to periodically trigger an interruption of charging, and control the current adjustment module, and generate a charge termination signal; wherein the second current is controlled by the current adjustment module during an interruption period a reference is limited to the minimum current value; the control of the current regulation module is cancelled by a control of the current regulation module during a charge period separated by the interruption; when the interruption period ends When it is detected that the voltage difference of the output voltage lower than the externally input first voltage reference is less than a preset first voltage threshold, the charging termination signal is asserted to trigger the charging termination.
  • the second current reference when it is detected that the current difference of the output current is lower than the second current reference is less than the first current threshold during the charging period, if the second current reference has not reached the maximum current value And the second current reference whose limit is cancelled is adjusted by the current adjustment module;
  • the second current reference When the current difference is detected to be greater than or equal to the third current threshold during the charging period, if the second current reference has not reached the minimum current value, the second is cancelled
  • the current reference is reset by the current regulation module to the minimum current value; wherein the first current threshold is less than the second current threshold, and the second current threshold is less than the third current threshold.
  • the charge control circuit further includes a voltage adjustment module, the voltage adjustment module is configured to adjust the first voltage reference, and output the adjusted second voltage reference to a voltage of the charge execution circuit a reference input terminal for controlling the adjustment of the output voltage and the output current by the charging execution circuit; wherein, a maximum voltage value of the second voltage reference is greater than the first voltage reference, and a minimum voltage value is equal to the a first voltage reference; and the detection control module is further configured to control the voltage adjustment module, wherein: when the end of the interruption period, detecting that the voltage difference is greater than or equal to the first voltage threshold, and less than the second At the voltage threshold, if the second voltage reference has not reached the minimum voltage value, the second voltage reference is turned down by the voltage regulation module;
  • the second voltage reference When the voltage difference is detected to be greater than the third voltage threshold at the end of the interruption period, if the second voltage reference has not reached the maximum voltage value, the second voltage reference is raised by the voltage regulation module ;
  • the first voltage threshold is smaller than the second voltage threshold, and the second voltage threshold is smaller than the third voltage threshold.
  • a charging device comprising a charging control circuit as described above.
  • a charging control method for controlling an output voltage and an output current generated during charging and triggering a charging end includes:
  • Al adjusting the input first current reference, and outputting the adjusted second current reference to control the adjustment of the output voltage and the output current; wherein, the minimum current value of the second current reference is less than The first current reference, the maximum current value is equal to the first current reference;
  • the second current reference is limited to the minimum a current value; the limit of the second current reference is cancelled by control of the current regulation module during a charge period separated by the interruption; the output voltage is detected to be low when the interruption period ends And when the voltage difference amplitude of the externally input first voltage reference is less than a preset first voltage threshold, the charging termination signal is asserted to trigger the charging termination.
  • the second current reference when it is detected that the current difference of the output current is lower than the second current reference is less than the first current threshold during the charging period, if the second current reference has not reached the maximum current value And then the second current reference that is canceled by the limit is raised by the a1;
  • the charging control method further includes: a2, adjusting the first voltage reference, and outputting the adjusted second voltage reference to control adjustment of the output voltage and the output current;
  • the maximum voltage value of the second voltage reference is greater than the first voltage reference, and the minimum voltage value is equal to the first voltage reference;
  • the second voltage reference When the voltage difference is detected to be greater than or equal to the first voltage threshold and less than the second voltage threshold at the end of the interruption period, if the second voltage reference has not reached the minimum voltage value, the second The voltage reference is lowered by the a2;
  • the second voltage reference When the voltage difference is detected to be greater than the third voltage threshold at the end of the interruption period, if the second voltage reference has not reached the maximum voltage value, the second voltage reference is raised by the a2;
  • the first voltage threshold is smaller than the second voltage threshold, and the second voltage threshold is smaller than the third voltage threshold.
  • a charging method comprising the steps of the control method as described above.
  • the present invention can provide a second current reference that can be adjusted within a range less than or equal to the calibrated first current reference, and by limiting the second current reference to a minimum current value during the periodically triggered interruption period.
  • the output voltage is closer to the core voltage of the battery, so if the output voltage is detected to be close to the calibrated first voltage reference at the end of the interruption period, it can be approximately determined that the core voltage of the battery approaches the first voltage that is calibrated.
  • the reference thus, the present invention triggers the termination of charging on the condition that the output voltage approaches the nominal first voltage reference, and the defect of insufficient charging can be improved. Further better:
  • the present invention can also provide a second voltage reference that can be adjusted within a range of greater than or equal to the calibrated first voltage reference; if the output voltage is detected to be close to the calibrated first voltage reference at the end of the interruption period, Approximately determine that the core voltage of the battery will be close to To the calibrated first voltage reference, and can lower the output voltage during the charging period by lowering the second voltage reference to prevent overcharging; if the output voltage is detected to be far below the calibrated first voltage reference at the end of the interruption period And then determining that the core voltage of the battery is far from reaching the calibrated first voltage reference, and allowing the output voltage to exceed the calibrated first voltage reference during the charging period by increasing the second voltage reference to increase the charging speed;
  • the present invention is also capable of limiting the instantaneous overshoot of the output current by adjusting the second current reference during charging.
  • FIG. 1 is a schematic structural view of a charging device in the prior art
  • FIG. 2 is a schematic structural diagram of a charging device according to Embodiment 1 of the present invention
  • FIG. 3 is a schematic diagram of a preferred structure of a current regulating module included in a charging control circuit in a charging device according to Embodiment 1 of the present invention
  • FIG. 4 is a schematic diagram showing a preferred structure of a detection control module included in a charging control circuit in a charging device according to Embodiment 1 of the present invention
  • FIG. 5 is a schematic diagram of a specific example of a voltage detector in the detection control module shown in FIG. 4.
  • FIG. 6 is a schematic diagram of a specific example of a logic controller in the detection control module shown in FIG. 2 is a schematic structural diagram of a charging device of the second embodiment;
  • FIG. 8 is a schematic diagram showing a preferred structure of a detecting control module included in the charging control circuit in the charging device of the second embodiment of the present invention;
  • FIG. 9 is a schematic diagram of a specific example of a current detector in the detection control module shown in FIG. 8;
  • FIG. 10 is a schematic diagram showing a specific example of a logic controller in the detection control module shown in FIG.
  • FIG. 11 is a schematic diagram of a waveform of an output current generated by a charging device according to Embodiment 2 of the apparatus of the present invention
  • 12 is a schematic structural diagram of a charging device according to a third embodiment of the present invention
  • FIG. 13 is a schematic diagram of a preferred structure of a voltage regulating module included in a charging control circuit in a charging device according to Embodiment 3 of the present invention
  • FIG. 14 is a schematic diagram showing a preferred structure of a detection control module included in a charging control circuit in a charging device according to a third embodiment of the present invention.
  • Figure 15 is a schematic view showing a specific example of a voltage detector in the detection control module shown in Figure 14;
  • FIG. 16 is a schematic diagram showing a specific example of a logic controller in the detection control module shown in FIG. 14;
  • FIG. 17 is a schematic diagram showing waveforms of output voltages and corresponding output currents generated by a charging device according to Embodiment 3 of the apparatus of the present invention.
  • FIG. 18 is a schematic structural diagram of a charging device according to a fourth embodiment of the present invention.
  • FIG. 19 is a schematic diagram of a preferred structure of a detecting control module included in a charging control circuit in a charging device according to Embodiment 4 of the present invention;
  • Figure 20 is a schematic diagram showing a specific example of a logic controller in the detection control module shown in Figure 19. Mode for carrying out the invention
  • FIG. 2 is a schematic structural diagram of a charging apparatus according to Embodiment 1 of the apparatus of the present invention.
  • the charging device 2 is for charging a battery 100.
  • the charging device 2 includes a charging execution circuit 11, a charging protection circuit 12, and a charging control circuit 23.
  • the structure and working principle of the charging execution circuit 11 and the charging protection circuit 12 are the same as those in the prior art, and are not described in detail in this embodiment, and the charging protection circuit 12 is optional, not required; the charging control circuit 23 is used for
  • the charge execution circuit 11 is controlled to adjust the output voltage Vout and the output current lout generated at its charge output terminal, and to control the charge termination of the charge execution circuit 11.
  • the charging control circuit 23 included in the charging device 2 in this embodiment includes: a current regulation module 231 and a detection control module 230.
  • the current adjustment module 231 is configured to adjust the externally input calibration current reference Iref_s, and output the adjusted variable current reference Iref-g to the current reference input of the charge execution circuit 11 (ie, the negative input of the differential amplifier 111). End), to control the adjustment of the output voltage Vout and the output current lout by the charging execution circuit 11; wherein, the minimum current value of the variable current reference Iref-g is smaller than the calibration current reference Iref_s, and the maximum value of the variable current reference Iref-g The current value is equal to the calibration current reference Iref_s;
  • the detection control module 230 is configured to periodically trigger an interruption of charging, and control the current adjustment module 231, and generate a charge termination signal Fin-b; wherein, by controlling the current adjustment module 231 during the interruption period, the variable current reference Iref- g is limited to the above minimum current value; the above limitation of the variable current reference Iref-g is canceled by the control of the current adjustment module 231 during the charging period separated during the interruption; and, when the interruption period is detected, the detection is terminated
  • the output voltage Vout is lower than the voltage difference of the externally input calibration voltage reference Vref_s by less than a preset voltage threshold Th_vl (approximately indicating that the core voltage V0 of the battery 100 approaches the calibration voltage reference Vref_s)
  • the charge termination signal Fin-b is asserted to trigger charging termination.
  • a deviation allowable range may be set in advance to ensure the deviation of the output voltage Vout from the battery core voltage V0 (ie, the battery 100).
  • the pressure drop generated by the internal resistance R0 is within the allowable range of the deviation Inside is the constraint for setting the minimum current value.
  • the size of the predetermined deviation allowable range will vary according to various requirements. Accordingly, the specific value of the minimum current value will be different; and, even if the size of the predetermined deviation is determined, the difference is different.
  • the "cancelling the above limitation of the variable current reference Iref-g" means that: the arbitrary current value of the variable current reference Iref-g can be arbitrarily adjusted between the minimum current value and the maximum current value, For example, the variable current reference Iref-g is adjusted to the maximum current value (ie, the calibration current reference Iref_s) and is stably maintained at the maximum current value during the charging period, or the variable current reference Iref-g is adjusted to be greater than the minimum current. The value is less than or equal to the maximum current value, a pre-selected default current value, and is stably maintained at the default current value during the charging period, which is no longer listed here.
  • the current reference input terminal of the charging execution circuit 11 receives the variable current reference Iref-g instead of the fixed calibration current reference Iref_s; in addition, in the present embodiment, the charging is performed.
  • the voltage reference input of circuit 11 i.e., the negative input of differential amplifier 112 still receives the input nominal voltage reference Vref_s.
  • variable current reference Iref-g is limited to the above minimum current value during each interruption period, the output current lout is greater than, or even much larger than, the variable to the minimum current value whenever the interruption period starts.
  • the current reference Iref-g correspondingly, the positive voltage value of the control signal Ctrl-1 is high regardless of whether the output voltage Vout has not reached the calibration voltage reference Vref_s or has reached or is slightly higher than the calibration voltage reference Vref_s.
  • the PMOS 114 is still controlled by the control signal Ctrl-1, and remains in a closed or weakly conducting state;
  • the positive voltage value of the control signal Ctrl_V may be temporarily higher than the positive voltage value of the control signal Ctrl-I, then even
  • the control signal Ctrl_V controls the PMOS 114 to increase the conduction level, increase the output current lout and slightly higher than the variable current reference Iref-g limited to the minimum current value, and the positive voltage value of the control signal Ctrl-I will again Higher than the positive voltage value of the control signal Ctrl-V, and re-controlling the PMOS 114 to reduce the conduction level;
  • the substantially flat state can be maintained during the interruption period.
  • the smaller the minimum current value the smaller the voltage drop generated by the internal resistance R0 of the battery 100, that is, the output voltage Vout is smaller than the core voltage V0 of the battery 100, and accordingly, after the interruption period, the output voltage Vout The closer to the true core voltage V0, the lower the voltage difference of the voltage at which the output voltage Vout is lower than the voltage of the calibration voltage reference Vref_s is detected at the end of the interruption period.
  • the above-mentioned voltage difference detected at the end of the interruption period of the present embodiment can approximately reflect whether the battery 100 is fully charged or not, and correspondingly, whether the output current lout is sufficient as a trigger charging termination condition. In the present embodiment, it is more accurate to determine whether it is necessary to trigger the termination of charging by using the above voltage difference amplitude, thereby further improving the defect of insufficient charging.
  • the voltage reference input terminal of the charge execution circuit 11 ie, the negative input terminal of the differential amplifier 112 receives the calibration voltage reference Vref_s in this embodiment, it is based on the subsequent device embodiment III and the device.
  • those skilled in the art can determine whether the input of the calibration voltage reference Vref_s by the voltage reference input terminal of the charging execution circuit 11 does not substantially affect the defect of improving the undercharge.
  • FIG. 3 is a schematic diagram showing a preferred structure of a current adjustment module included in a charging control circuit in a charging device according to Embodiment 1 of the present invention.
  • the current adjustment module 231 is implemented in a variable gain current mirror structure and has 2m adjustment gear positions.
  • the current adjustment module 231 includes a current mirror trunk 2311 and a m current mirror branch. 2312-l ⁇ 2312-m, and an m-bit decoder 2313, m is a positive integer greater than or equal to 1.
  • the current mirror trunk 2311 includes an NMOS0.
  • the drain D of the NMOS0 serves as an input terminal of the current mirror trunk 2311 and is connected to the input terminal of the current regulating module 231 for receiving the calibration current reference Iref_s; the source S of the NMOS0 is used as the output of the current mirror trunk 2311.
  • the gate G of the NMOS0 is connected to the drain D of the NMOS0 and is pulled high, so that a gate-to-source voltage difference VGS greater than the NMOS0 is generated between the gate G and the source S.
  • the cutoff voltage that is, the NMOS0 is in the normally open state, so that the input terminal of the current mirror trunk 2311 receives the calibration current reference Iref_s from the input terminal of the current regulating module 231 and can be output from the output terminal of the current mirror trunk 2311. .
  • each current mirror branch 2312-i (i is a positive integer greater than or equal to 1 and less than or equal to m) includes three NMOSiO ⁇ NMOSi2 and one inverter Revi, where:
  • the source S of the NMOSiO serves as the input terminal of the current mirror branch 2312-i, and the drain D serves as the output terminal of the current mirror branch 2312-i;
  • the source S of the NMOSil is connected to the gate G of the NMOSiO, the drain D is connected to the drain D of the NMOS0 (pull-up), and the gate G is connected to the output terminal of the i-th bit of the decoder 2313;
  • the source S of NMOSi2 is connected to the source S (ground) of NMOS0, the drain G is connected to the gate G of NMOSiO, and the gate G is connected to the output of the ith bit of the decoder 2313 via the inverter Revi.
  • the input of the decoder 2313 is received from the detection control module via a current control bus
  • the gate G of the NMOSil is pulled high, and the NMOSil is turned on, and the gate G of the NMOSi2 is inverted by the inverter Revi and then pulled low, and The NMOSi2 is turned off; the turned-on NMOSil turns on the gate G of the NMOSiO and the gate G of the NMOS0, thereby forming a current mirror having a ratio of 1/m to the current mirror trunk 2311 in the current mirror branch 2312-i.
  • 1/m of the calibration current reference Iref_s is concentrated to the output of the current regulation module 231 via the output of the current mirror branch 2312-i.
  • the gate G of the NMOSi2 is pulled low, and the NMOSil is turned off, and the gate G of the NMOSi2 is inverted by the inverter Revi and pulled up, and NMOSi2 is turned on; the turned-on NMOSi2 pulls the gate G of the NMOSiO low, and turns off the NMOSiO, so that the 1/m of the calibration current reference Iref_s received by the input terminal of the current mirror branch 2312-i is not It will converge to the output of the current regulation module 231.
  • the current reference Iref_s of each current mirror branch 2312-i can be concentrated to the current adjustment module.
  • the output of the 231, correspondingly, the variable current reference Iref-g generated by the output of the current regulating module 231 is equal to the calibration current reference Iref_s, that is, the maximum current value.
  • the calibration current reference Iref_s is at least 1/m unable to converge to the output of the current adjustment module 231, and correspondingly, the output of the current adjustment module 231 is generated.
  • the variable current reference Iref-g is less than the calibration current reference Iref_s. Then, according to the foregoing description of the action of the minimum current value of the variable current reference Iref-g, it is possible to use these current values 0m-1) Iref_s/m from the calibration current reference Iref_s as needed. Select one as the minimum current value.
  • the current regulating module 231 can also be implemented by other structures, for example, a structure based on a variable resistor, etc., which is not described herein. Accordingly, in addition to the current coded signal Icode, other signal forms can be used to control the current regulation module 231.
  • the detection control module 230 includes a clock timer 2301, a logic controller 2302, a current counter 2304, and a voltage detector 2305.
  • the clock timer 2301 is configured to count the reference clock signal CLK_s and generate an interrupt clock signal CLK_t according to the counting result; wherein, when the interrupt clock signal CLK_t is valid, it indicates an interrupt period, and when it is invalid, it indicates a charging period.
  • the logic controller 2302 is configured to generate a current reset signal I_res according to the interrupt clock signal CLK_t; wherein, when the interrupt clock signal CLK_t is valid, the current reset signal I res is asserted.
  • the current counter 2304 is configured to perform a counting operation according to the reference clock signal and the current reset signal I_res, and output the obtained current counting result to the current adjusting module 231, so that the current adjusting module 231 adjusts according to the current counting result (for current).
  • the adjustment module 231 adopts a preferred structure as shown in FIG. 3, and the current counting result can be a current encoded signal.
  • the Icode mode is output to the current regulation module 231 for reception by the input of the decoder 2313); wherein, whenever the reference clock signal CLK_s comes from an invalid jump to a valid clock edge (at the end of the interrupt period):
  • variable current reference Iref_g ie, the calibration current reference Iref_s
  • the default current count value corresponding to the pre-selected default current value mentioned above; that is, the current counter 2304 is required to "cancel the pair"
  • the variable current reference Iref-g is quickly adjusted to the maximum current value by continuous counting and stably maintained at the maximum current value during the charging period, or the variable current reference Iref is The -g is adjusted to be greater than the minimum current value and less than or equal to the maximum current value by a pre-selected default current value and is stably maintained at the default current value during the charging period.
  • the voltage detector 2305 is configured to detect a magnitude of a voltage difference amplitude of the output voltage Vout lower than the calibration voltage reference Vref_s, and generate a voltage detection signal V-tl according to the magnitude of the voltage difference amplitude; wherein the voltage detection signal V-tl is The voltage difference amplitude is less than the voltage threshold Th-vl, that is, when the voltage detection signal V-tl is active, the output voltage Vout is close to reaching the calibration voltage reference Vref_s.
  • the logic controller 2302 is further configured to generate a charge termination signal Fin-b according to the interrupt clock signal CLK_t and the voltage detection signal V-tl; wherein, when the interrupt clock signal CLK-t changes from a valid jump to an invalid clock edge Upon arrival, if the voltage detection signal V-t is active (at the end of the interruption period, approximately indicating that the core voltage V0 of the battery 100 approaches the nominal voltage reference Vrefs), the charge termination signal Finb is asserted.
  • the detection control module 230 can implement its corresponding function.
  • the clock timer 2301 and the current counter 2304 substantially implement the counter function that can be mastered by those skilled in the art, and thus the clock timer 2301 and the current counter 2304 are implemented, and will not be described herein;
  • the detector 2305 and the logic controller 2302 although various implementations can be combined by various components, those skilled in the art will further exemplify the following.
  • the detection output voltage Vout is lower than the voltage difference of the calibration voltage reference Vref_s, in order to detect the closeness of the output voltage Vout to the calibration voltage reference Vref_s. Then, in a specific implementation, the specific voltage value of the voltage difference amplitude may be detected first, and the specific voltage value of the voltage difference amplitude is compared with the voltage threshold Th_vl, or may be extracted from the calibration voltage reference Vref_s first. The difference voltage equivalent to the voltage threshold Th_vl is lost, and the output voltage Vout is compared with the extracted difference voltage.
  • FIG. 5 is a schematic diagram of a specific example of a voltage detector in the detection control module shown in FIG. 4.
  • the difference voltage equivalent to the voltage threshold Th_vl is extracted from the calibration voltage reference Vref_s, and the output voltage Vout is compared with the difference voltage.
  • the voltage detector 2305 includes a comparator Comp-vtl, a negative input terminal of the comparator Compvt1 receives the output voltage Vout, and the other positive input terminal receives the calibration voltage reference Vref_s and the voltage threshold Th.
  • the output of the comparator Comp - vtl produces a voltage detection signal V - tl. among them:
  • the output voltage Vout is less than or equal to the difference voltage Vref_s-Th-vl, it means that the output voltage Vout is lower than the calibration voltage reference Vref_s, and the voltage difference is greater than or equal to the voltage threshold Th-vl (the output voltage Vout is not yet close to The calibration voltage reference Vref_s is reached, so that the voltage detection signal V-tl at this time is at a high level;
  • the output voltage Vout is greater than the difference voltage Vref_s-Th-vl, it means that the output voltage Vout is lower than the calibration voltage reference Vref_s, and the voltage difference is smaller than the voltage threshold Th-vl (the output voltage Vout has approached The voltage reference Vref_s is calibrated, so that the voltage detection signal Vtl at this time is active at a low level.
  • FIG. 6 is a schematic diagram of a specific example of a logic controller in the detection control module shown in FIG. 4. An easy-to-implement logic decision and triggering approach is used in Figure 6. As shown in FIG. 6, the logic controller 2302 includes inverters Rev- cl and Rev_c2, a resistor Rf and a capacitor Cf, and a D flip-flop DFF1 and an inverter Rev-vl.
  • the reference clock signal CLK-t sequentially passes through the delay of the inverter Rev- cl, the delay of the resistor Rf and the capacitor Cf, and the reverse of the inverter Rev-c2 to generate the current reset signal I_res, thereby
  • the current reset signal I_res is asserted to be active high, and is slightly delayed compared to the reference clock signal CLKt.
  • the reference clock signal CLK_t is inactive at the low level indicating the charging period
  • the current reset signal I_res is set to a low level and is slightly delayed compared to the reference clock signal CLK_t.
  • the D flip-flop DFF1 is controlled by the reference clock signal CLK-t passing the reverse signal of the inverter Rev- cl and triggering the charging according to the level state of the voltage detection signal V-tl reversed by the inverter Rev-vl.
  • the level state of the termination signal Fin_b is inverted, so that the rising edge of the reference clock signal CLK_t, that is, the falling of the reference clock signal CLK_t from the active high level to the low level is invalid.
  • the charge termination signal Fin-b is turned from the low level to the high level according to the active voltage detection signal V_tl at the low level.
  • the charging device 3 is for charging a battery 100.
  • the charging device 3 includes a charging execution circuit 11, a charging protection circuit 12, and a charging control circuit 33.
  • the structure and working principle of the charging execution circuit 11 and the charging protection circuit 12 are the same as those in the prior art, and are not described in detail in this embodiment, and the charging protection circuit 12 is optional, not required; the charging control circuit 33 is used for The charge execution circuit 11 is controlled to adjust the output voltage Vout and the output current lout generated at its charge output terminal, and to control the charge termination of the charge execution circuit 11.
  • the charging control circuit 33 included in the charging device 3 in the present embodiment includes a current adjustment module 231 and a detection control module 330.
  • the detection control module 330 is configured to periodically trigger an interruption of charging, and control the current adjustment module 231, and generate a charge termination signal Fin-b; wherein, by controlling the current adjustment module 231 during the interruption period, the variable current reference Iref- g is limited to the above minimum current value; the above limitation of the variable current reference Iref-g is canceled by the control of the current adjustment module 231 during the charging period separated during the interruption; and, when the interruption period is detected, the detection is terminated When the output voltage Vout is lower than the voltage input of the externally input calibration voltage reference Vref_s by less than the voltage threshold Th-vl (approximately indicating that the core voltage V0 of the battery 100 approaches the calibration voltage reference Vref_s), the charging is terminated.
  • the signal Fin-b is asserted to trigger the termination of charging; moreover, based on the control of the current regulating module 231 by the detection control module 330, the variable current reference Iref-g with the above-mentioned limitation is removed to have the following changes:
  • variable current reference Iref-g When the output current lout is detected during the charging period is lower than the variable current reference Iref-g, the current difference is smaller than the preset current threshold Th il (indicating that the output current lout is very close) In the current variable current reference Iref-g), if the variable current reference Iref_g has not reached its maximum current value (ie, the calibration current reference Iref_s), the variable current reference Iref-g is adjusted by the current adjustment module 231. high;
  • the current difference is greater than or equal to the preset current threshold Th_i2, and is smaller than the current threshold Th_i3 (indicating that the output current lout is significantly lower than When the current variable current reference Iref_g), if the variable current reference Iref_g has not reached the aforementioned minimum current value, the variable current reference Iref_g is lowered by the current adjustment module 231;
  • variable current reference Iref_g When the output current lout is detected during the charging period is lower than the variable current reference Iref-g, the current difference is greater than or equal to the preset current threshold Th_i3 (indicating that the output current lout is far lower than the current variable current reference Iref)
  • Th_i3 the preset current threshold
  • the current threshold Th_i 1 is smaller than the current threshold Th_i2, and the current threshold Th_i2 is smaller than the current threshold Th_i3.
  • the current reference input terminal of the charging execution circuit 11 receives the variable current reference Iref-g instead of the fixed calibration current reference Iref_s; in addition, in the present embodiment, the charging is performed.
  • the voltage reference input of circuit 11 i.e., the negative input of differential amplifier 112 still receives the input nominal voltage reference Vref_s.
  • variable current reference Iref-g is limited to the above minimum current value during each interruption period, the present embodiment can improve the defect of insufficient charging as in the first embodiment of the apparatus.
  • variable current reference Iref-g can be adaptively adjusted in accordance with the change of the output current lout, that is, the "cancel the variable current reference” as described in the first embodiment.
  • Iref-g “Adjusts the variable power in an adaptive manner
  • this embodiment can be constructed. Due to the adoption of this adaptive adjustment, therefore:
  • the output current lout When the output current lout has been significantly lower than the current variable current reference Iref-g, the output current lout is adapted to decrease by reducing the variable current reference Iref-g, and the instantaneous overshoot is avoided when the output current lout rebounds;
  • the present embodiment can further limit the instantaneous overshoot of the output current lout by adjusting the variable current reference Iref-g during charging.
  • the detection control module 330 is further configured to reset the variable current reference Iref g to the aforementioned minimum current value by controlling the current adjustment module 231 when the charge termination signal Fin-b is asserted to Avoid the instantaneous overshoot of the output current lout after the start of the next charge.
  • the voltage reference input terminal of the charge execution circuit 11 receives the calibration voltage reference Vref_s in this embodiment, it is based on the description of the subsequent device embodiment 4. Those skilled in the art can determine whether the input of the calibration voltage reference Vref_s by the voltage reference input of the charging execution circuit 11 does not substantially affect the limiting instantaneous overshoot.
  • FIG. 8 is a schematic diagram of a preferred structure of a detection control module included in a charging control circuit in a charging apparatus according to Embodiment 2 of the apparatus of the present invention.
  • the detection control module 330 includes a clock timer 2301, a logic controller 3302, a current detector 3303, a current counter 3304, and a voltage detector 2305.
  • the clock timer 2301 has been described in the first embodiment of the apparatus.
  • the manner in which the CLK _ t periodically triggers the charging interruption is not the same as the logic controller 2302 in the first embodiment of the apparatus. No longer.
  • the current detector 3303 is configured to detect a magnitude of a current difference amplitude of the output current lout that is lower than the variable current reference Iref-g, and generate a current detection signal I-11, a current detection signal I-12, and according to the magnitude of the current difference amplitude.
  • the current detecting signal I-13 is effective when the current difference is smaller than the current threshold Th-il, and the current detecting signal I 12 is effective when the current difference is smaller than the current threshold Th_i2, current The detection signal I-13 is effective when the current difference is smaller than the current threshold Th_i3.
  • Table 1 shows the meanings of various combinations of levels of the current detection signal I-tl, the current detection signal I-12, and the current detection signal I-t3.
  • indicates that the output current lout is lower than the current difference of the variable current reference Iref-g, and the logic controller 2302 is used to generate an interrupt according to the clock counter 2301.
  • the current counter 3304 is configured to perform a counting operation according to the reference clock signal CLK_s, the current increasing signal I_up, the current decreasing signal I_down, and the current reset signal I_res, and output the obtained current counting result to the current.
  • the adjustment module 231 is configured to adjust the current adjustment module 231 according to the current counting result (for the current adjustment module 231 adopting a preferred structure as shown in FIG. 3, the current counting result may be output to the current adjustment module 231 in the manner of the current encoding signal Icode.
  • each current adjustment step size, etc. can be set. Long, that is, set the number of adjustment gears corresponding to each current adjustment step is the same; of course, you can also set the current adjustment step to be unequal, that is, set the current adjustment step each time compared to the previous time. Or the counting operation of increasing or decreasing at least one adjustment gear by the subsequent current adjustment step;
  • the voltage detector 2305 has been described in the first embodiment of the apparatus. In this embodiment, the method and device implementation of the charging termination signal Fin_b by the voltage detecting signal V-tl generated by the voltage signal detector 2305 are no longer used.
  • the logic controller 2302 in the first example is the same, and will not be described in detail in this embodiment.
  • the logic controller 3302 can further set the current reset signal I_res to be active when the charge termination signal Fin_b is active. In this case, when the current detection signal I-13 is invalid, the charge termination signal Fin_b is inactive, and the delayed reference clock signal CLK-1 is inactive indicating the charging period, the current reset signal I_res is set to low. Flat is invalid.
  • the detection control module 330 can implement its corresponding function.
  • the current counter 3304 substantially implements the counter function that can be mastered by those skilled in the art, and thus the implementation of the current counter 3304 will not be described here; for the current detector 3303 and the logic controller 3302, , although it can also be Those skilled in the art can use a variety of components to combine various implementations, but further examples are further illustrated below.
  • the detection output current lout is lower than the magnitude of the current difference of the variable current reference Iref-g, in fact, in order to detect the approach of the output current lout to the constantly changing variable current reference Iref-g degree.
  • the specific current value of the current difference amplitude may be detected first, and the specific current value of the current difference amplitude is respectively compared with the current threshold value Th-il ⁇ Th_i3, or may be from the current
  • the variable current reference Iref-g extracts a difference current equivalent to the loss of the current threshold Th_il ⁇ Th_i3, and compares the output current lout with the extracted difference currents.
  • FIG. 9 is a schematic diagram of a specific example of a current detector in the detection control module shown in FIG. 8.
  • the differential current corresponding to the lost current threshold Th_i 1 ⁇ Th_i3 is extracted from the current variable current reference Iref-g, and then the output current lout and the extracted each are extracted.
  • the difference current is compared and compared by converting the output current lout to each differential current to a corresponding voltage.
  • the current detector 3304 includes resistors Ra, Rb, Rc, Rd, Rout, and also includes a comparator Comp-itl ⁇ Comp-it3.
  • the resistors Ra, Rb, Rc, and Rd are sequentially connected in series to form a resistor string.
  • the resistor string is located at one end of the resistor Ra and receives the variable current reference Iref-g, and the other end of the side where Rd is located is grounded.
  • the resistor string is located at one end of the side of the resistor Ra to generate a voltage corresponding to the variable current reference Iref-g; the connection end of the resistors Ra and Rb, the connection end of Rb and Rc, and the connection end of Rc and Rd are in turn An incremental voltage drop is generated, and the magnitude of the incremental voltage drop corresponds to the current threshold Th_il ⁇ Th_i3.
  • One end of the resistor Rout receives the output current Iout and the other end is grounded.
  • the resistor Rout receives one end of the output current lout to generate a voltage corresponding to the output current lout.
  • the voltage at one end of the resistor Rout receiving the output current lout is compared with the voltage at the connection end of the resistors Ra and Rb, the connection end of Rb and Rc, and the connection end of Rc and Rd, and the output current lout can be known.
  • the magnitude of the current difference below the variable current reference Iref-g is compared to the magnitude relationship of the current thresholds Th_i1 to Th_i3. Therefore:
  • a negative input terminal of the comparator Comp-itl is connected to Rout to receive one end of the output voltage Vout, and the other positive input terminal is connected to the connection end of Ra and Rb, and the output end of the comparator Comp-itl generates a current detection signal I-tl;
  • Rout receives the voltage of one end of the output voltage Vout less than or equal to the voltage of the connection terminal of Ra and Rb, it means that the current difference of the output current lout is lower than the variable current reference Iref-g is greater than or equal to the current threshold Th-il, thus
  • the current detection signal I_tl is inactive at a high level; and when the voltage at one end of the Rout receiving output voltage Vout is greater than the voltage of the connection terminal of Ra and Rb, it means that the output current lout is lower than the variable current reference Iref-g
  • the current difference is smaller than the current threshold Th—il , and thus the current detection signal I tl at this time is inactive;
  • One comparator of the comparator Comp-it2 is connected to Rout to receive one end of the output voltage Vout, and the other positive input is connected to the connection of Rb and Rc.
  • the output of the comparator Comp-it2 is the same as the comparator Comp-it
  • the principle generates a current detection signal I-12; one negative input of the Compar-Comp3 is connected to one end of the output voltage Vout, and the other positive input is connected to the connection end of Rc and Rd, the comparator Comp-it3
  • the output generates a current detection signal I-13 in accordance with the same principle as the comparator Comp-it.
  • FIG. 10 is a schematic diagram showing a specific example of a logic controller in the detection control module shown in FIG. Figure. An easy-to-implement logic decision and triggering approach is used in Figure 10.
  • the logic controller 2302 includes inverters Rev-il and Rev-i2, AND gate ANDi, OR gate OR, and also includes Rev-c1 and Rev-c2, resistor Rf and capacitor Cf, and D-trigger. DFF 1 and inverter Rev-vl.
  • the current detection signal I_tl is reversed by the inverter Rev-il to generate a current increase signal I_up; when the current detection signal I-t is active low, the current increase signal I_up is It becomes effective to become a high level; conversely, the current increase signal I_up becomes inactive.
  • the current detection signal I-12 is input to the AND gate ANDi, and the current detection signal I-13 is also input to the AND gate ANDi after being inverted by the inverter Rev_i2; when the current detection signal I-12 is high, the current detection is When the signal I-12 is active low, the current decrease signal I_down outputted by the AND gate ANDi becomes active high; on the contrary, the current decrease signal I_down outputted by the AND gate ANDi becomes Low level is invalid.
  • the current detection signal I-13 is output to the OR gate OR; when the current detection signal I-13 is at a high level, the current reset signal I_res of the OR gate OR becomes active high.
  • the reference clock signal CLK-t is sequentially delayed by the delay of the inverter Rev- cl, the delay of the resistor Rf and the capacitor Cf, and the reverse of the inverter Rev-c2, and is delayed to the reference clock signal CLK-1. And output to the OR gate OR.
  • the delayed reference clock signal CLK-1 is active at the high level indicating the interruption period, the current reset signal I_res of the OR gate OR becomes active high.
  • the D flip-flop DFF1 is controlled by the reference clock signal CLK-t passing the reverse signal of the inverter Rev- cl and triggering the charging according to the level state of the voltage detection signal V-tl reversed by the inverter Rev-vl.
  • the level state of the termination signal Fin_b is inverted, so that the rising edge of the reference clock signal CLK_t, that is, the falling of the reference clock signal CLK_t from the active high level to the low level is invalid.
  • the charge termination signal Fin_b is inverted from the low level according to the effective voltage detection signal V_tl at the low level. It is valid for high level.
  • the variable current reference I ref — g is reset to the minimum current value by controlling the current adjustment module 231 , and then charging
  • the termination signal Fin-b is output to the OR gate OR (indicated by a broken line in Fig. 10) in addition to being outputted to the outside of the charge control circuit 33; when the charge termination signal Fin-b is active high, the OR gate
  • the current reset signal I_res of the OR output becomes active high.
  • Figure 11 is a waveform diagram showing the output current generated by the charging device of the second embodiment of the apparatus of the present invention.
  • the waveform of the output current lout during the charging period and the waveform of the output current lout' when the embodiment mode is not employed in the embodiment of the present embodiment are shown in FIG. 11; and the present embodiment on which FIG. 11 is based
  • the solution is that the current adjustment module 231 adopts the structure shown in FIG. 3, and the m in the structure shown in FIG.
  • the current counting result represented by the current encoding signal Icode gradually increases as the output current lout increases, or The output current lout is gradually decreased, thereby avoiding the instantaneous overshoot of the output current lout;
  • FIG. 12 is a schematic structural diagram of a charging apparatus according to Embodiment 3 of the apparatus of the present invention.
  • the charging device 4 is for charging the battery 100.
  • the charging device 4 includes a charging execution circuit 11, a charging protection circuit 12, and a charging control circuit 43.
  • the structure and working principle of the charging execution circuit 11 and the charging protection circuit 12 are the same as those in the prior art, and are not described in detail in this embodiment, and the charging protection circuit 12 is optional, not required; the charging control circuit 43 is used for
  • the charge execution circuit 11 is controlled to adjust the output voltage Vout and the output current lout generated at its charge output terminal, and to control the charge termination of the charge execution circuit 11.
  • the charging control circuit 43 included in the charging device 4 of the present embodiment includes: a current regulating module 231, a voltage adjusting module 432, and a detecting control module 430.
  • the voltage adjustment module 432 is configured to adjust the calibration voltage reference Vref_s, and output the adjusted variable voltage reference Vref-g to the voltage reference input terminal of the charge execution circuit 11 (ie, one negative input terminal of the differential amplifier 112). To control the adjustment of the output voltage Vout and the output current lout by the charging execution circuit 11; wherein, the maximum voltage value of the variable voltage reference Vref-g is greater than the calibration voltage reference Vref_s, and the minimum voltage value of the variable voltage reference Vref-g Equal to the calibration voltage reference Vref_s;
  • the detection control module 430 is configured to periodically trigger an interruption of charging, and control the current adjustment module 231, and generate a charge termination signal Fin-b; wherein, by controlling the current adjustment module 231 during the interruption period, the variable current reference Iref- g is limited to the above minimum current value; the above limitation of the variable current reference Iref-g is canceled by the control of the current adjustment module 231 during the charging period separated during the interruption; and, when the interruption period is detected, the detection is terminated When the output voltage Vout is lower than the voltage input of the externally input calibration voltage reference Vref_s by less than the voltage threshold Th-vl (approximately indicating that the core voltage V0 of the battery 100 approaches the calibration voltage reference Vref_s), the charging is terminated.
  • the signal Fin-b is asserted to trigger the charging termination; the detection control module 430 is further configured to control the voltage adjustment module 432. Based on the control of the voltage adjustment module 432 by the detection control module 430, the variable voltage reference Vref-g has the following Change status:
  • the above voltage difference is greater than or equal to the aforementioned voltage threshold.
  • variable voltage reference Vref g has not reached the above minimum voltage a value, the variable voltage reference Vref-g is lowered by the voltage regulation module 432;
  • variable voltage reference Vref g When the voltage difference is detected to be greater than the preset voltage threshold Th_v3 at the end of the interruption period (indicating that the output voltage Vout at the end of the interruption period is far from the calibration voltage reference Vref s ), if the variable voltage reference Vref g has not been reached The maximum voltage value, the variable voltage reference Vref-g is adjusted by the voltage adjustment module 432;
  • the voltage threshold Th vl is smaller than the voltage threshold Th_v2, and the voltage threshold Th_v2 is smaller than the voltage threshold Th_v3.
  • variable current reference Iref-g for the setting of the minimum current value of the variable current reference Iref-g and the implementation of "cancelling the above limitation of the variable current reference Iref-g", reference may be made to the description in the first embodiment of the apparatus. , I will not go into details here.
  • the current reference input of the charging execution circuit 11 receives the variable current reference Iref-g instead of the fixed calibration current reference Iref_s; the voltage reference input of the charging execution circuit 11.
  • the variable voltage reference Vref-g rather than the fixed calibration voltage reference Vref_s.
  • variable current reference Iref-g is limited to the above minimum current value during each interruption period, the output current lout is greater than, or even much larger than, the variable to the minimum current value whenever the interruption period starts.
  • the current reference Iref_g correspondingly, whether the output voltage Vout has not reached the variable voltage reference Vref-g at this time, or has reached or is slightly higher than the variable voltage reference Vref-g, the positive voltage value of the control signal Ctrl-1 Will be higher than the positive voltage value of the control signal Ctrl-V, and control the PMOS 114 (ie, the adjustable switch) to turn off, or weakly turn on, from The output current lout is lowered to be substantially equal to the variable current reference Iref-g limited to the minimum current value.
  • the PMOS 114 is still controlled by the control signal Ctrl-1, and remains in a closed or weakly conducting state;
  • the positive voltage value of the control signal Ctrl_V may be temporarily higher than the positive voltage value of the control signal Ctrl-1, then, Even if the control signal Ctrl-V controls the PMOS 114 to increase the conduction level, the output current lout is increased and slightly higher than the variable current reference Iref_g limited to the minimum current value, the positive voltage value of the control signal Ctrl-1 Again higher than the positive voltage value of the control signal Ctrl-V, and re-control the PMOS 114 to reduce the conduction level;
  • the present embodiment replaces the calibration voltage reference Vref_s received by the reference voltage input terminal of the charging execution circuit 11 with the variable voltage reference Vref g , the output current lout and the limit are minimized. After the variable current reference Iref-g of the current value remains substantially flat, the present embodiment can still ensure that the substantially flat state can be maintained during the interruption period as in the first embodiment of the apparatus.
  • the present embodiment can improve the defect of insufficient charging as in the first embodiment and the second embodiment of the apparatus.
  • variable voltage reference Vref can be adaptively adjusted in accordance with the degree of the output voltage Vout (approximating the core voltage V0 of the battery 100) approaching the calibration voltage reference Vref_s. — g, therefore:
  • the output voltage Vout at the end of the interruption period is to approach the nominal voltage reference Vref s
  • the core voltage V0 of the battery 100 is to approach the calibration voltage reference Vref_s
  • by reducing Varying the voltage reference Vref-g and reducing the output voltage Vout within the beginning of the charging cycle it is possible to prevent the battery voltage V0 from approaching the calibration voltage reference Vref_s due to the excessive output voltage Vout.
  • the embodiment can further speed up the charging speed by adjusting the variable voltage reference Vref-g at the end of the interruption period.
  • the detection control module 430 is further operable to reset the variable voltage reference Vref-g to the aforementioned minimum voltage value by controlling the voltage adjustment module 432 when the charge termination signal Fin-b is asserted.
  • Fig. 13 is a view showing a preferred configuration of a voltage regulating module included in a charging control circuit in the charging device of the third embodiment of the apparatus of the present invention.
  • the voltage regulation module 432 includes a resistance tunable circuit 4321 having n gear positions, and an n-bit decoder 4322, n being a positive integer greater than two.
  • the resistance adjustable circuit 4321 includes resistors R1 to Rn and NMOS1 to NMOSn.
  • the resistors R1 R Rn are sequentially connected in series to form a resistor string.
  • the resistor string is located at one end of the resistor R1 and receives a calibration voltage reference Vref_s.
  • the resistor string is connected to a power source Vccl at the other end of the Rn side and is used to generate a variable voltage reference. Vref — g.
  • the source S of the NMOS1 is connected to one end of the resistor string receiving the calibration voltage reference Vref_s, the drain D is connected to the other end of the resistor string on the side where Rn is located (ie, connected to the power source Vccl), and the gate G is connected to the decoder.
  • the source S of the NMOSj is connected to one end of the resistor Rj-1 connected to the resistor Rj-1, the drain D is connected to the other end of the resistor string on the side where Rn is located (ie, connected to the power source Vccl), and the gate G is connected to the decoder 4322.
  • j is a positive integer greater than one and less than or equal to n.
  • the input of the decoder 4322 receives the voltage coded signal Vcode from the detection control module 430 via a voltage control bus, and controls the level state of the n outputs according to the voltage coded signal Vcode.
  • the NMOSj When the output of the jth bit of the decoder 4322 is at a high level, the NMOSj is turned off; and when the output of the jth bit of the decoder 4322 is at a high level, the NMOSj is turned on, and the resistors Rj ⁇ Rn are short-circuited, thereby When NMOS1 ⁇ NMOSj are turned off, the variable voltage reference Vref_g is generated in a certain increment compared to the nominal voltage reference Vref_s due to the unshort-circuited resistors R1 to Rj-1;
  • variable voltage reference Vref-g will be compared to the calibration voltage due to the unshort-circuited resistors R1 ⁇ Rn.
  • the reference Vref s produces the largest increment, ie the maximum as described above Voltage value.
  • different adjustment gear positions can be realized by short-circuiting different numbers of resistors R1 to Rn. And by setting the resistance of the resistors R1 to Rn, the adjustment positions can be the same or different.
  • the voltage adjustment module 432 can also be implemented by other structures, for example, based on the calibration voltage reference Vref_s, and simultaneously providing a plurality of voltage values greater than or equal to the calibration voltage reference Vref_s, and from the plurality of voltages according to the decoder 4322.
  • One of the values is chosen as the variable voltage reference Vref-g.
  • other signal forms can be used to control the voltage regulation module 432.
  • Fig. 14 is a view showing a preferred configuration of a detection control module included in a charging control circuit in the charging device of the third embodiment of the apparatus of the present invention.
  • the detection control module 430 includes a clock timer 2301, a logic controller 4302, a current counter 2304, and a voltage detector 4305 and a voltage counter 4306.
  • the clock timer 2301 has been described in the first embodiment of the apparatus.
  • the manner in which the CLK _ t periodically triggers the charging interruption is not the same as the logic controller 2302 in the first embodiment of the apparatus. No longer.
  • the current counter 2304 has been described in the first embodiment of the apparatus, and will not be described again in this embodiment.
  • the manner in which the logic controller 4302 controls the current counter 2304 by using the current reset signal I-res is the same as the logic controller 2302 in the first embodiment of the apparatus, and will not be further described in this embodiment.
  • the voltage detector 4305 is configured to detect a magnitude of a voltage difference amplitude of the output voltage Vout lower than the variable voltage reference Vref-g, and generate a voltage detection signal V-t1, a voltage detection signal V-12, and according to the magnitude of the voltage difference amplitude.
  • Voltage detection signal V-13 wherein, the voltage detection signal V-tl is valid when the voltage difference is smaller than the voltage threshold Th vl, and the voltage detection signal V t2 is on When the voltage difference amplitude is smaller than the voltage threshold Th-v2, the voltage detection signal V-13 is effective when the voltage difference is smaller than the voltage threshold Th-v3.
  • Table 2 shows the meanings of various combinations of levels of the voltage detection signal V-tl, the voltage detection signal V-12, and the voltage detection signal V-t3.
  • AV indicates that the output voltage Vout is lower than the voltage difference of the variable voltage reference Vref-g.
  • the logic controller 4302 is configured to generate the adjusted clock signal CLK_g according to the interrupt clock signal CLK_t generated by the clock counter 2301, and according to the interrupt clock signal CLK-1, and the voltage detecting signal V generated by the voltage detector 4305 Tl ⁇ V-13, generating a charge termination signal Fin-b, a voltage decrease signal V_down, and a voltage increase signal V_up; wherein, the adjustment clock signal CLK_g is a reverse of the interrupt clock signal CLK_t Signal; and, based on the meaning of the various level combinations shown in Table 2, the charging terminal generated by the logic controller 4302 Stop signal Fin — b, voltage reduction signal V — down, voltage increase signal V — up level change: 3 ⁇ 4 port:
  • the voltage reduction signal V_down is set. Is valid; otherwise, the voltage reduction signal V_down remains inactive; when the interrupt clock signal CLK_t comes from the valid transition to the invalid clock edge (end of the interrupt period), if the voltage detection signal V-13 is invalid, the voltage The increase signal V_up is asserted; otherwise, the voltage increase signal V_up remains inactive.
  • the voltage counter 4306 is configured to perform a counting operation according to the adjusted clock signal CLK_g, the voltage increasing signal V_up, and the voltage decreasing signal V_down, and output the obtained voltage counting result to the voltage adjusting module 432 to adjust the voltage.
  • the module 432 adjusts according to the voltage counting result (for the voltage adjusting module 432, a preferred structure as shown in FIG. 13 is adopted, and the voltage counting result may be output to the voltage adjusting module 432 in the manner of the voltage encoding signal Vcode for the decoder.
  • the input of the 4311 is received); wherein, whenever the clock signal CLK-g is changed from an invalid transition to a valid clock edge (starting during the interruption period):
  • each voltage adjustment can be set.
  • the step length is equal, that is, the adjustment range of each adjustment gear is set to be the same, and the number of adjustment gears corresponding to each voltage adjustment step is the same; of course, the voltage adjustment step can also be set to be unequal, that is, Set the adjustment range of each adjustment gear to be different, and the number of adjustment gears corresponding to each voltage adjustment step is the same, or set the adjustment range of each adjustment gear to be the same, but each time the voltage adjustment step is Than before or after One time the voltage adjustment step increases or decreases at least one adjustment gear);
  • the logic controller 4302 may further generate a voltage reset signal V_res according to the charge termination signal Fin-b, wherein when the charge termination signal Fin_b is valid, the voltage reset signal V_res is asserted, when the charge termination signal Fin-b is invalid, The voltage reset signal V_res is invalid; accordingly, the voltage counter 4306 is further configured to perform a counting operation according to the voltage reset signal V_res, and when the voltage reset signal V_res is valid, the voltage counting result is reset to the minimum voltage count value once.
  • the counting operation corresponds to the aforementioned minimum voltage value, that is, the calibration voltage reference Vref_s.
  • the detection control module 330 can implement its corresponding function.
  • the voltage counter 4306 substantially implements the counter function that can be mastered by those skilled in the art, and thus the implementation of the voltage counter 4306 will not be described here; for the voltage detector 4305 and the logic controller 4302, Although various implementations can be combined by various components using those skilled in the art, the following further exemplifies further examples.
  • the detection output voltage Vout is lower than the voltage difference of the calibration voltage reference Vref_s, in fact, in order to detect the closeness of the output voltage Vout to the calibration voltage reference Vref_s.
  • the specific voltage value of the voltage difference amplitude may be detected first, and the specific voltage value of the voltage difference amplitude is respectively compared with the voltage threshold value Th_vl ⁇ Th-v3, or the calibration voltage reference may be firstly used.
  • the difference voltages respectively corresponding to the voltage thresholds Th_vl ⁇ Th-v3 are extracted in Vref_s, and the output voltages Vout are respectively compared with the extracted difference voltages.
  • FIG. 15 is a schematic diagram of a specific example of a voltage detector in the detection control module shown in FIG. 14.
  • the difference voltages respectively corresponding to the voltage thresholds Th_vl ⁇ Th-v3 are extracted from the calibration voltage reference Vref_s, and the output voltages Vout are respectively compared with the difference voltages. the way.
  • voltage detector 4305 contains three comparators Comp-vtl ⁇ Comp-vt3.
  • comparator Comp-vtl receives the output voltage Vout, and the other positive input receives the difference voltage Vref s-Th vl of the calibration voltage reference Vref_s and the voltage threshold Th-vl, the comparator Comp-vtl The output generates a voltage detection signal V-tl. among them:
  • the output voltage Vout is less than or equal to the difference voltage Vref_s-Th-vl, it means that the output voltage Vout is lower than the calibration voltage reference Vref_s, and the voltage difference is greater than or equal to the voltage threshold Th-vl (the output voltage Vout is not yet close to The calibration voltage reference Vref_s is reached, so that the voltage detection signal V-tl at this time is at a high level;
  • the output voltage Vout is greater than the difference voltage Vref_s-Th-vl, it means that the output voltage Vout is lower than the calibration voltage reference Vref_s, and the voltage difference is smaller than the voltage threshold Th-vl (the output voltage Vout has approached The voltage reference Vref_s is calibrated, so that the voltage detection signal Vtl at this time is active at a low level.
  • One negative input of the comparator Comp-vt2 receives the output voltage Vout, and the other positive input receives the difference voltage Vref_s-Th-v2 of the calibration voltage reference Vref_s and the voltage threshold Th-v2, the comparator Comp- The output of vt2 produces a voltage detection signal V-12. among them:
  • One negative input of the comparator Comp-vt3 receives the output voltage Vout, and the other positive input receives the difference voltage Vref_s-Th_ ⁇ 3 of the calibration voltage reference Vref_s and the voltage threshold Th-v3, the comparator Comp- The output of vt3 produces a voltage detection signal V-13. among them:
  • Figure 16 is a schematic diagram showing a specific example of a logic controller in the detection control module shown in Figure 14. An easy-to-implement logic decision and triggering approach is used in Figure 16.
  • the logic controller 4302 includes inverters Rev_ cl ⁇ Rev_c3, resistor Rf and capacitor Cf, D flip-flops DFF1 ⁇ DFF3, AND gate AND-v, and inverter Rev-vl and Rev. — v2.
  • the structure of the current reset signal I_res is generated by the inverters Rev_cl and Rev_c2, the resistor Rf and the capacitor Cf, and the termination of charging is performed by using the inverter Rev-vl and the D flip-flop DFF1.
  • the structure of the signal Fin b and the phase shown in FIG. 6 in the first embodiment of the apparatus The structure should be the same, and the details are not described in this embodiment.
  • the reference clock signal CLK-t is sequentially inverted by the inverter Rev- cl, the delay of the delay circuit composed of the resistor Rf and the capacitor Cf, and the reverse of the inverter Rev-c2, and then inverted by the inverter Rev-c3.
  • an adjusted clock signal CLK_g which is inverted from the reference clock signal CLK-t and has a certain delay is generated.
  • the D flip-flop DFF2 is controlled by the inverted signal of the reference clock signal CLK-t passing through the inverter Rev- cl, and is flipped according to the level state of the AND gate V_? And one of the inputs AND-V of the gate receives the voltage detection signal V-tl, and the other input receives the voltage detection signal V-12 reversed by the inverter Rev-v2; thus, the reference clock signal CLK- The rising edge after the reverse direction, that is, the falling of the reference clock signal CLK_t from the active high level to the low level, the falling edge of the low frequency (at the end of the interrupt period), according to the voltage detection signal V which is inactive at the high level —tl, and the low-level effective voltage detection signal V—12, so that the voltage-decreasing signal V_down is inverted from the low-level inactive to the high-level.
  • the D flip-flop DFF3 is controlled by the reference clock signal CLK_t passing through the reverse signal of the inverter Rev- cl, and triggering the level state of the voltage increase signal V_up according to the level state of the voltage detection signal V-13 Therefore, when the rising edge of the reference clock signal CLK_t is reversed, that is, when the reference clock signal CLK_t transitions from the active high level to the low level, the falling edge of the low level is invalid (at the end of the interrupt period), It is effective to invert the voltage increase signal V_up from the low level to the high level in accordance with the high level invalid voltage detection signal V-13.
  • the variable voltage reference Vref-g is reset to the aforementioned minimum voltage value by the control of the voltage adjustment module 432, and then the charging is performed.
  • the termination signal Fin-b is outputted to the outside of the charge control circuit 43, and sequentially generates voltage reset signals V_res by inverters Rev-v3 and Rev-v4 (indicated by broken lines in Fig. 16); when the charge termination signal Fin—b is high When it is valid, the voltage reset signal V_res becomes active high.
  • Figure 17 is a waveform diagram showing the output voltage and corresponding output current generated by the charging device of the third embodiment of the apparatus of the present invention.
  • the waveforms of the output voltage Vout and the output current lout during the charging period and the output voltage Vout' and the output current lout' when the mode of the present embodiment is not employed are shown in FIG. 17;
  • the scheme of the embodiment based on FIG. 17 is based on the voltage adjustment module 432 adopting the structure shown in FIG. 13 and the n taking 4 in the structure shown in FIG.
  • the output voltage Vout is restored to a state approximately equal to the core voltage V0 of the battery 100, and then detected by the detection output Vout at the end of each interruption period.
  • the voltage count result represented by the voltage coded signal Vcode will increase accordingly, thereby allowing the output voltage Vout to be higher than the calibration voltage reference Vref_s, and the output current lout is at the output voltage.
  • Vout does not decrease after reaching the calibration voltage reference Vref_s, thereby increasing the charging speed.
  • the output voltage Vout' must not be higher than the calibration voltage reference Vref_s, so that the output current lout' is after the output voltage Vout reaches the calibration voltage reference Vref_s. That is, the reduction starts, resulting in a low charging speed.
  • FIG. 18 is a schematic structural diagram of a charging apparatus according to Embodiment 4 of the apparatus of the present invention.
  • the charging device 5 is for charging the battery 100.
  • the charging device 4 includes a charge execution circuit 11, a charge protection circuit 12, and a charge control circuit 53.
  • the structure and working principle of the charging execution circuit 11 and the charging protection circuit 12 are the same as those in the prior art, and are not described in detail in this embodiment, and the charging protection circuit 12 is optional, not required; the charging control circuit 53 is used for
  • the charge execution circuit 11 is controlled to adjust the output voltage Vout and the output current lout generated at its charge output terminal, and to control the charge termination of the charge execution circuit 11.
  • the charging control circuit 53 included in the charging device 5 in this embodiment includes: a current regulating module 231, a voltage adjusting module 432, and a detecting control module 530.
  • the function and specific implementation of the current regulation module 231 have been described in the device embodiment 1.
  • the function and specific implementation of the voltage regulation module 432 have been described in the device embodiment 3. Therefore, the current regulation module 231 and the voltage are used in this embodiment.
  • the adjustment module 432 is not described again;
  • the detection control module 530 is configured to periodically trigger the interruption of charging, and control the current adjustment module 231 and the voltage adjustment module 432, and generate a charge termination signal Fin-b; wherein, during the interruption period, The control of the current regulation module 231 causes the variable current reference Iref-g to be limited to the minimum current value described above; during the charging period separated during the interruption, the variable current reference is cancelled by the control of the current regulation module 231
  • the above limitation of Iref-g and, when the output voltage Vout is detected to be lower than the voltage threshold Th-vl of the calibration voltage reference Vref_s at the end of the interruption period, the charge termination signal Fin-b is asserted To control the termination of charging;
  • variable current reference Iref-g that is canceled by the above limitation has a change state as described in the second embodiment of the apparatus; and the voltage adjustment module 432 is based on the detection control module 530.
  • the control, variable voltage reference Vref-g has a varying state as described in apparatus embodiment three.
  • the current reference input of the charging execution circuit 11 receives the variable current reference Iref-g instead of the fixed calibration current reference Iref_s; the voltage reference input of the charging execution circuit 11 Is the variable voltage reference Vref-g, not Is a fixed calibration voltage reference Vref_s.
  • variable current reference Iref-g is limited to the minimum current value during each interruption period, the present embodiment can still improve the charging shortage as in the first embodiment, the second embodiment of the apparatus, and the third embodiment of the apparatus. Defects.
  • variable voltage reference Vref can be adaptively adjusted in accordance with the degree of the output voltage V0Ut (approximating the core voltage V0 of the battery 100) close to the calibration voltage reference Vref_s. - g, thus, compared to the device embodiment 1 and the device embodiment 2, the embodiment can further speed up the charging speed as in the device embodiment 3.
  • variable current reference Iref-g can be adaptively adjusted according to the change of the output current lout, and thus the embodiment is compared with the device embodiment 1 and the device embodiment 3. It is also possible to further limit the instantaneous overshoot of the output current lout as in the second embodiment of the apparatus.
  • the detection control module 530 is further configured to reset the variable current reference Iref-g to the aforementioned minimum current value by controlling the current adjustment module 231 when the charge termination signal Fin-b is asserted,
  • the variable voltage reference Vref-g is reset to the aforementioned minimum voltage value by control of the voltage regulation module 432.
  • Fig. 19 is a view showing a preferred configuration of a detection control module included in a charging control circuit in the charging device of the fourth embodiment of the apparatus of the present invention.
  • the detection control module 530 includes a clock timer 2301, a logic controller 5302, a current detector 3303, a current counter 3304, and a voltage detector 4305 and a voltage counter 4306.
  • the clock timer 2301 has been described in the first embodiment of the apparatus.
  • the manner in which the CLK _ t periodically triggers the charging interruption is not the same as the logic controller 2302 in the first embodiment of the apparatus. No longer.
  • the current detector 3303 and the current counter 3304 have been described in the second embodiment of the device, and will not be described in detail in this embodiment.
  • the logic controller 5302 controls the current counter 3304 according to the current increase signal I_up, the current decrease signal I_down, and the current reset signal I_res generated by the current detector 3303, and the device in the second embodiment.
  • the logic controller 3302 is the same, and will not be described in detail in this embodiment.
  • the voltage detector 4305 and the voltage counter 4306 have been described in the third embodiment of the device, and will not be described in detail in this embodiment.
  • the logic controller 5302 controls the voltage counter according to the charge termination signal Fin-b, the voltage increase signal V_up, the voltage decrease signal V_down, and the optional voltage reset signal V_res generated by the voltage detector 4305.
  • the mode of the 3304 is the same as that of the logic controller 4302 in the third embodiment of the device, and details are not described in this embodiment.
  • Figure 20 is a schematic diagram showing a specific example of a logic controller in the detection control module shown in Figure 19.
  • the logic controller 5302 includes inverters Rev- cl ⁇ Rev-c3, resistor Rf and capacitor Cf, inverters Rev-il and Rev-i2, AND gate AND-i, OR gates OR, D.
  • Figure 20 shows the structure of the current reset signal I_res using the inverters Rev-c1 and Rev-c2, the resistor Rf and the capacitor Cf, and the OR gate OR, and the inverters Rev-il and Rev_i2, and
  • the structure of the gate AND-i generating the current increasing signal I_up and the current reducing signal I_down is the same as the corresponding structure shown in FIG. 10 in the second embodiment of the apparatus, and will not be described in detail in this embodiment;
  • the structure of the adjustment clock signal CLK_g is generated by the inverters Rev_ cl ⁇ Rev_c3, the resistor Rf and the capacitor Cf, and the D flip-flops DFF1 ⁇ DFF3, the AND gate AND-v, and the inverter Rev- are used.
  • the structure of the charging termination signal Fin_b, the voltage reduction signal V_down, and the voltage increasing signal V_up is the same as the corresponding structure shown in FIG. 16 in the third embodiment of the apparatus, and this embodiment does not Let me repeat.
  • the inverters Rev-v3 and Rev-v3 are further included in FIG.
  • the structure of the voltage reset signal V_res is generated by the inverters Rev-v3 and Rev-v3 (indicated by a broken line in FIG. 20).
  • the corresponding structure is the same as that shown in FIG. 16 in the third embodiment of the device, and details are not described in this embodiment.
  • the waveform of the output voltage Vout and the corresponding output current lout generated in this embodiment can be seen in Fig. 17, and the waveform of each rising edge of the output current lout shown in Fig. 17 is as shown in Fig. 11.
  • Step a1 adjusting the input calibration current reference Iref_s, and outputting the adjusted variable current reference Iref-g to control the adjustment of the output voltage Vout and the output current lout generated during charging; wherein, the variable current The minimum current value of the reference Iref-g is smaller than the calibration current reference Iref_s, and the maximum current value of the variable current reference Iref-g is equal to the calibration current reference Iref_s; step b0, periodically interrupting the charging, and controlling the step a1 And generating a charge termination signal Fin-b; wherein, by controlling the current regulation module 231 during the interruption period, the variable current reference Iref-g is limited to the minimum current value; by the charging period separated during the interruption period The control of the current adjustment module 231, the above limitation of the variable current reference Iref-g is canceled; and, when the end of the interruption period, the detected output voltage Vout is lower than the externally input calibration voltage reference Vref_s, the voltage difference is smaller than the advance
  • the charging method of the present embodiment Based on the charging control method in the present embodiment, the charging method of the present embodiment generates the output voltage Vout and the output current Iout while charging, and uses the variable current reference Iref-g and the calibration voltage according to the same principle as the charging execution circuit 11.
  • the reference Vref_s controls the regulation of the output voltage Vout and the output current lout.
  • variable current reference Iref-g is limited to the above minimum current value during each interruption period, the charging control method and the charging method in this embodiment can improve the defect of insufficient charging, similarly to the device embodiment. .
  • the interrupt that periodically triggers charging in step b0 may include: counting the reference clock signal CLK_s, and generating an interrupt clock signal CLK_t according to the counting result; wherein, when the interrupt clock signal CLK_t is valid, indicating that the interrupt period is invalid, Indicates the charging period.
  • the detecting of the current difference amplitude and the controlling of the step a1 in the step b0 may include: bi ll, generating a current reset signal I_res according to the interrupt clock signal CLK-t; wherein, when the interrupt clock signal CLK_t is valid, the current The reset signal I_res is asserted.
  • the counting operation of the flow adjustment step is performed until the maximum current count value or a preset default current count value corresponding to the maximum current value of the variable current reference Iref-g (ie, the calibration current reference Iref) is reached.
  • the default current count value corresponds to the pre-selected default current value mentioned above; that is, when it is required to "cancel the above limitation of the variable current reference Iref-g", it can be variable by continuous counting
  • the current reference Iref-g is quickly adjusted to the maximum current value and stably maintained at the maximum current value during the charging period, or the variable current reference Iref-g is adjusted to be greater than the minimum current value and less than or equal to the maximum current value.
  • the current value is saved and is maintained at the default current value during the charging period.
  • the process of detecting the above voltage difference amplitude in the step b0 and generating the charge termination signal Fin_b may include:
  • the charging control method in this embodiment still includes the steps a1 and b0 in the first embodiment of the method, but the "restriction of the above limitation on the variable current reference Iref-g" described in the step b0 is adopted in this embodiment.
  • the adaptive manner such that the variable current reference Iref-g, which is canceled as described above, has a varying state as described in apparatus embodiment 2.
  • the charging method of the present embodiment Based on the charging control method in the present embodiment, the charging method of the present embodiment generates the output voltage Vout and the output current Iout while charging, and uses the variable current reference Iref-g and the calibration voltage according to the same principle as the charging execution circuit 11.
  • the reference Vref_s controls the regulation of the output voltage Vout and the output current lout.
  • variable current reference Iref-g is limited to the above minimum current value during each interruption period, the charging control method and the charging method in this embodiment can improve the defect of insufficient charging as in the first embodiment.
  • the variable current reference Iref-g can be adaptively adjusted in accordance with the change of the output current lout, and therefore, in the same manner as the device embodiment 2, the present embodiment is compared with the method.
  • Embodiment 1 can further limit the instantaneous overshoot of the output current lout during the charging period.
  • step b0 may further reset the variable current reference Iref-g to the aforementioned minimum current value by controlling the step a1 when the charge termination signal Fin_b is asserted, To avoid instantaneous overshoot of the output current lout after the start of the next charge.
  • the manner of periodically triggering the interruption of the charging in the step b0 may be the same as the method embodiment 1 and will not be described here.
  • the detecting of the current difference amplitude and the controlling of the step a1 in the step b0 may include: b211, detecting that the output current lout is lower than the magnitude of the current difference of the variable current reference Iref-g, and generating according to the magnitude of the current difference The current detection signal I-tl, the current detection signal I-12, and the current detection signal I-13; wherein, the current detection signal I-t is effective when the current difference is smaller than the current threshold Th-il, and the current detection signal I-12 When the current difference is smaller than the current threshold Th_i2, the current detection signal I-13 is effective when the current difference is smaller than the current threshold Th_i3 B212, the interrupt clock signal CLK-1 generated by the clock counter 2301, the current detection signal I_tl ⁇ generated by the current detector 3303: [- t3, generating a current increase signal I_up, a current decrease signal I_down, And a current reset signal I_res; wherein the current increase signal I_up, the current decrease signal I_down,
  • the step a is adjusted according to the current counting result; wherein, whenever the reference clock signal CLK_s changes from an invalid jump to a valid clock edge:
  • the current increase signal I_up is valid, the current count result is incremented by one current adjustment step (the length of each current adjustment step can be set, and the current adjustment step length can be set to be equal). operating; If the current reduction signal I_down is valid, performing a counting operation of reducing the current counting result by one current adjustment step;
  • the process of detecting the above-mentioned voltage difference and generating the charging termination signal Fin_b in the step b0 may be the same as the method embodiment 1 and will not be repeated here.
  • step b0 is required to further enable the charge termination signal Fin-b to be asserted
  • the variable current reference Iref-g is reset to the aforementioned minimum current value by controlling the step a1, and b211 may further be at the charge termination signal.
  • the current reset signal I_res is asserted.
  • the current detection signal I-13 is invalid
  • the charge termination signal Fin_b is inactive
  • the delayed reference clock signal CLK_t is inactive indicating the charging period
  • the current reset signal I_res is set to low. Flat is invalid.
  • the charging control method in this embodiment includes the step al and the step b0 in the method. However, the charging control method in this embodiment further includes:
  • Step a2 adjusting the calibration voltage reference Vref_s, and outputting the adjusted variable voltage reference Vref-g to control the adjustment of the output voltage Vout and the output current lout generated during charging; wherein, the variable voltage reference Vref The maximum voltage value of g is greater than the calibration voltage reference Vref_s, and the minimum voltage value of the variable voltage reference Vref-g is equal to the calibration voltage reference Vref_s; accordingly, step b0 needs to be further used for controlling step a2, and, based on Step bO controls the step a2, and the variable voltage reference Vref-g has a change state as described in the third embodiment of the apparatus.
  • the charging method of the present embodiment Based on the charging control method in the present embodiment, the charging method of the present embodiment generates the output voltage Vout and the output current Iout during charging according to the same principle as the charging execution circuit 11,
  • the variable current reference Iref-g and the variable voltage reference Vref-g are used to control the adjustment of the output voltage Vout and the output current lout.
  • variable current reference Iref-g is limited to the minimum current value during each interruption period
  • the charging control method and the charging method in this embodiment can be improved as in the first embodiment and the second embodiment. Defects in insufficient charging.
  • variable voltage reference Vref at the end of each interruption period, can be adaptively adjusted in accordance with the degree of the output voltage Vout (approximating the core voltage V0 of the battery 100) approaching the calibration voltage reference Vref_s. - g, therefore, in the same manner as the third embodiment of the apparatus, the embodiment can further speed up the charging by adjusting the variable voltage reference Vref-g at the end of the interruption period as compared with the method embodiment 1 and the method embodiment 2. .
  • step b0 is further operable to reset the variable voltage reference Vref-g to the aforementioned minimum voltage value by controlling the step a2 when the charge termination signal Fin-b is asserted.
  • the manner of periodically triggering the interruption of the charging in the step b0 may be the same as the method embodiment 1 and will not be described here.
  • the detection of the current difference amplitude and the control of the step al in the step b0 may be the same as the method embodiment 1, and will not be described herein.
  • the detecting of the voltage difference amplitude, the generation of the charging termination signal Fin_b, and the controlling of the step a2 in the step b0 may include:
  • the voltage detection signal V-tl is valid when the voltage difference is smaller than the voltage threshold Th-vl
  • the voltage detection signal V-12 is valid when the voltage difference is smaller than the voltage threshold Th v2
  • the voltage detection signal V t3 is The above voltage difference is smaller than The voltage threshold is valid when Th_v3;
  • step a2 is counted according to the voltage The result is adjusted; whereever, whenever the clock signal CLKg is adjusted from an invalid transition to a valid clock edge (starting during the interruption):
  • the voltage increase signal V_up If the voltage increase signal V_up is valid, perform a counting operation of increasing the voltage counting result by one voltage counting step (you can set each voltage adjusting step to be equal in length, or you can set the voltage adjusting step length to be unequal. );
  • step b0 is required to further enable the charge termination signal Fin-b to be asserted
  • the variable voltage reference Vref-g is reset to the aforementioned minimum voltage value by the control of step a2
  • b322 may further be based on the charge termination signal.
  • Fin- b generates a voltage reset signal V_res, wherein, when the charge termination signal Fin_b is valid, the voltage reset signal V_res is asserted, and when the charge termination signal Fin_b is invalid, the voltage reset signal V_res is invalid.
  • b323 further performs a counting operation according to the voltage reset signal V_res, and when the voltage reset signal V_res is valid, performing a counting operation of resetting the voltage counting result to the minimum voltage counting value, the minimum voltage counting value corresponding to the foregoing
  • the minimum voltage value that is, the calibration voltage reference Vref_s.
  • the charging control method in this embodiment includes the step a1 in the first embodiment of the method, and the step a2 and the step b0 in the third embodiment of the method, and the canceling of the variable current reference Iref-g for the step b0
  • the above limitation is adopted.
  • This embodiment adopts the adaptive mode in the second embodiment of the method.
  • the charging method of the present embodiment Based on the charging control method in the present embodiment, the charging method of the present embodiment generates the output voltage Vout and the output current Iout at the time of charging, and uses the variable current reference Iref-g and the variable according to the same principle as the charging execution circuit 11.
  • the voltage reference Vref-g controls the regulation of the output voltage Vout and the output current lout.
  • the charging control method and the charging method in this embodiment can be like the method embodiment 1 and the method embodiment 2 and the method.
  • the defect of insufficient charging is improved as in the third embodiment.
  • variable voltage reference Vref can be adaptively adjusted in accordance with the degree of the output voltage Vout (approximating the core voltage V0 of the battery 100) approaching the calibration voltage reference Vref_s. - g, therefore, this embodiment is compared to the method Embodiment 1 and Method Embodiment 2 can further speed up the charging speed by adjusting the variable voltage reference Vref-g at the end of the interruption period.
  • variable current reference Iref-g can be adaptively adjusted according to the change of the output current lout. Therefore, the embodiment is compared with the method embodiment 1 and the method embodiment. Third, it is possible to further limit the instantaneous overshoot of the output current lout during the charging period.
  • step b0 may further reset the variable current reference Iref-g to the aforementioned minimum current value by controlling the step a1 when the charge termination signal Fin_b is asserted,
  • the variable voltage reference Vref-g is reset to the aforementioned minimum voltage value by the control of step a2.
  • the manner of periodically triggering the interruption of the charging in the step b0 may be the same as the method embodiment 1 and will not be described here.
  • the detection of the current difference amplitude and the control of the step al in the step b0 may be the same as the method embodiment 2, and will not be described herein.
  • the technical solution of the present invention can be embodied in the form of hardware or in the form of a software product, either in essence or in a contribution to the prior art.
  • a system or device equipped with a storage medium readable by a machine, on which the charging control device and the charging control method are implemented may be provided.
  • a functional software program code that causes the computer (or CPU or MPU) of the system or device to read and execute the program code stored in the storage medium.
  • the program code itself read from the storage medium can implement the functions of the above-described charging control device and the charging control method, and thus the program code and the storage medium storing the program code constitute the implementation of the above-described charging control device and charging control method.
  • Storage medium embodiments for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), Tape, non-volatile memory card and ROM.
  • the program code can be downloaded from the server computer by the communication network.
  • the program code read out from the storage medium is written into a memory set in an expansion board inserted into the computer or written in a memory set in an expansion unit connected to the computer, and then based on the program code.
  • the command causes the CPU or the like mounted on the expansion board or the expansion unit to perform part and all of the actual operations, thereby realizing the functions of the above-described charging control device and charging control method.

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Abstract

充电控制电路(23、33、43、53)及包含该充电控制电路(23、33、43、53)的充电装置(2),以及充电控制方法和包含该充电控制方法中各步骤的充电方法。充电控制电路(23、33、43、53)以及充电控制方法能够提供一可变电流基准(Iref_g)、并在周期性触发的中断期间内将可变电流基准(Iref_g)限制在最小电流值、以使输出电压(Vout)在中断期间结束时更接近电池内核电压(V0),因此,以中断期间结束时的输出电压(Vout)是否趋近于达到标定电压基准(Vref_s)为条件来触发充电终止,从而能够改善充电不足的缺陷,并且还能够通过在充电期间利用可变电流基准(Iref_g)来限制输出电流(lout)的瞬时上冲。此外,充电控制电路(23、33、43、53)以及充电控制方法还能够提供一可变电压基准(Vref_g),并在中断期间结束时检测到输出电压(Vout)远未达到标定电压基准(Vref_s)时,通过提高可变电压基准(Vref_g)来允许输出电压(Vout)在充电期间内超过标定电压基准(Vref_s),从而能够提高充电速度。

Description

充电控制电路和充电装置以及充电控制方法和充电方法 技术领域
本发明涉及充电技术, 特别涉及适用于输出电压和输出电流可调节 的充电方式的充电控制电路和充电装置、 以及充电控制方法和充电方 法。 发明背景
图 1为现有技术中的一种充电装置的示例性结构示意图。 如图 1所 示, 该充电装置 1用于对电池 100充电, 该充电装置 1包括充电执行电 路 11、 充电保护电路 12、 以及充电控制电路 13。
其中,充电执行电路 11用于在充电时从其充电输出端产生输出电压 Vout和输出电流 lout、 并调节产生的输出电压 Vout和输出电流 lout。
具体说, 充电执行电路 11包括差分放大器 111和 112、 电压选择器 113、 以及可调节开关 114 (本文仅以 PMOS作为可调节开关 114为例); 差分放大器 111 的一路负输入端作为充电执行电路 11 的电流基准输入 端、差分放大器 112的一路负输入端作为充电执行电路 11的电压基准输 入端、 PMOS 114的漏极 D作为充电执行电路 11的上述充电输出端。
差分放大器 111的一路负输入端接收输入的标定电流基准 Iref— s,差 分放大器 111的另一路正输入端接收充电执行电路 11的充电输出端反馈 的输出电流 lout, 差分放大器 111的输出端输出具有正电压值的一控制 信号 Ctrl— I, 该控制信号 Ctrl— I的正电压值表示输出电流 lout相比于标 定电流基准 Iref— s的电流差幅;
差分放大器 112的一路负输入端接收输入的标定电压基准 Vref— s, 差分放大器 112的另一路正输入端接收充电执行电路 11的充电输出端输 出的输出电压 Vout, 差分放大器 112的输出端输出具有正电压值的一控 制信号 Ctrl— V, 该控制信号 Ctrl— V的正电压值表示输出电压 Vout相比 于标定电压基准 Vref— s的电压差幅;
电压选择器 113接收上述的控制信号 Ctrl— I和控制信号 Ctrl— V, 电 压选择器 113还接收充电保护电路 12依据充电状态信号 S (例如用于表 示电源 VccO的状态、 充电装置 1的内部温度、 电池 100的内部温度等 状态的信号)输出的一控制信号 Ctrl— P, 该控制信号 Ctrl— P的正电压值 表示是否异常, 通常情况下该控制信号 Ctrl— P的正电压值会在异常时升 高; 并且, 电压选择器 113从控制信号 Ctrl— I、 控制信号 Ctrl— V、 以及 控制信号 Ctrl— P的正电压值中选取最大的一个(本文仅以选取最大为例、 但实际应用中也可能针对不同的元器件特性而存在选取最小的情况), 并将 PMOS 114的栅极 G置为所选取的最大的正电压值;
PMOS 114的源极 S连接输入电源 VccO, PMOS 114的漏极 D连接 电池 100、 并用于产生输出电流 lout和输出电压 Vout; 随着 PMOS 114 的栅极 G的正电压值的变化, PMOS 114的源极 S和漏极 D之间的导通 程度可以随之调节, 从而实现对输出电流 lout的调节; 相应地, 由于输 出电压 Vout等于电池 100的内核电压 V0与电池 100的内阻 R0所产生 的压降之和,而内核电压 V0与内阻 R0所产生的压降均与输出电流 lout 相关, 因此, 通过对输出电流 lout 的调节还能够实现对输出电压 Vout 的调节。
充电控制电路 13 用于依据输出电流 lout是否小于标定电流基准 Iref— s,控制充电的终止。
具体说, 充电控制电路 13包括一比较器 130。 比较器 130的一路负 输入端接收充电执行电路 11的充电输出端反馈的输出电流 lout,比较器 130的另一路正输入端接收标定电流基准 Iref s', 比较器 130的输出端 产生一充电终止信号 Fin— a; 当输出电流 lout小于标定电压基准 Iref— s, 时, 充电终止信号 Fin— a置为有效的高电平、 用以触发充电执行电路 11 的充电终止。
其中, 标定电流基准 Iref— s为公认的恒流充电的电流基准, 标定电 流基准 Iref— s,为公认的充电终止的电流基准, 标定电流基准 Iref— s大于 标定电流基准 Iref— s,; 而上述的标定电压基准 Vref— s则为公认的充电终 止的电压基准。
下面, 结合标定电流基准 Iref— s、 标定电流基准 Iref— s,、 以及标定电 压基准 Vref— s的上述含义,对现有如图 1所示充电装置 1的基本工作原 理进行详细说明。 由于充电保护电路 12是可选的、 而非必需, 因此, 在下文的详细说明中, 假设充电保护电路 12输出的控制信号 Ctrl— P— 直保持在表示无异常的较低正电压值。
在充电启动阶段:
输出电流 lout远小于标定电流基准 Iref— s、 输出电压 Vout远小于标 定电压基准 Vref— s, 此时, 控制信号 Ctrl— I和控制信号 Ctrl— V均具有较 低的正电压值, 从而使得电压选择器 112会将 PMOS 114的栅极 G也置 为较低的正电压值; 那么, 由于 PMOS 114的源极 S被输入电源 VccO 拉高, 因而使 PMOS 114的栅源电压差 VGS为负值、 并小于 PMOS 114 的截止电压, 从而使 PMOS 114最大程度地导通、 并使输出电流 lout增 大;
当输出电流 lout增大后, 控制信号 Ctrl— I的正电压值会高于控制信 号 Ctrl— V, 相应地, PMOS 114的栅极 G就会被电压选择器 112置为控 制信号 Ctrl— I的正电压值、 PMOS 114的导通程度也就受控于 Ctrl— I的 正电压值;
经过一定的稳定时间后, 在控制信号 Ctrl I 的正电压值控制下的 PMOS 114的导通程度就会使输出电流 lout保持在标定电流基准 Iref— s, 此后, 即开始了恒流充电阶段。
在恒流充电阶段:
电池 100的内压 V0会逐渐提升, 相应地, 输出电压 Vout也会从远 小于标定电压基准 Vref— s的较低电压值而逐渐升高;由于控制信号 Ctrl— I 的正电压值会一直保持在表示输出电流 lout达到标定电流基准 Iref— s的 正电压值, 因此, 只要输出电压 Vout尚未达到标定电压基准 Vref— s, 控 制信号 Ctrl— V的正电压值仍会低于控制信号 Ctrl— I的正电压值;
当输出电压 Vout达到并略高于标定电压基准 Vref— s时, 控制信号 Ctrl— V 的正电压值就会高于控制信号 Ctrl— I 的正电压值, 那么此时, PMOS 114的栅极 G就会被电压选择器 112置为更高的控制信号 Ctrl— V 的正电压值,使 PMOS 114小于截止电压的栅源电压差 VGS增大,从而 使 PMOS 114的导通程度、 并使输出电流 lout减小, 此后, 即开始恒压 充电阶段。
在恒压充电阶段:
输出电压 Vout由于负反馈作用会等于电压基准 Vref— s;
当输出电流 lout小于标定电流基准 Iref— s,时, 充电终止信号 Fin— a 变为有效的高电平, 从而触发充电的终止(如何触发充电终止不是本文 所关注、 且本领域技术人员已掌握多种具体的实现方式, 因而本文对此 不予赘述)。
至此, 充电结束。
如上可见,现有充电装置 1可利用其充电执行电路 11实现输出电压 Vout和输出电流 lout可调节的充电方式, 并利用其充电控制电路 13实 现对充电终止的控制, 但是, 由于现有充电装置 1中的充电控制电路 13 对充电终止的控制不合理、且缺少对充电执行电路 11调节输出电压 Vout 和输出电流 lout的控制, 因而就导致了如下缺陷:
1、 电池 100充电是否充满通常体现在电池 100的内核电压 V0是否 达到标定电压基准 Vref— s,但现有充电装置 1中对于充电终止信号 Fin— a 何时有效的判断,仅仅依据输出电流 lout是否小于标定电流基准 Iref— s,, 这样,就有可能出现输出电流 lout小于标定电流基准 Iref— s,、但电池 100 的内核电压 V0远未达到标定电压基准 Vref— s的情况, 从而导致充电不 足的缺陷;
2、 在电池 100的内核电压 V0远未达到标定电压基准 Vref— s时, 表 示电池 100尚需长时间充电, 但现有充电装置 1中的输出电流 lout在恒 压充电阶段是不断减小的, 这样, 就有可能出现电池 100 的内核电压 V0远未达到标定电压基准 Vref— s、 但输出电流 lout却很小的情况, 从 而导致充电过慢的缺陷;
3、 输出电流 lout在充电启动阶段, 输出电流 lout会出现瞬时上沖, 同样地, 在充电保护电路 12的控制信号 Ctrl— P触发充电暂停后的充电 重启阶段、 或者在电池 100与充电输出端断开后的重新接触阶段, 也容 易出现输出电流 lout瞬时上沖, 这样, 就容易对输入电源 VccO和电池 100产生沖击, 从而导致充电可靠性低的缺陷。
此外, 按照与充电装置 1相同的原理, 现有技术中还存在相应的充 电方法, 该充电方法能够在充电时产生输出电压 Vout和输出电流 Iout、 并调节产生的输出电压 Vout和输出电流 lout、 以及依据输出电流 lout 是否小于标定电流基准 Iref— s,控制充电的终止。 同理, 该充电方法对充 电终止的控制不合理、 且缺少对调节输出电压 Vout和输出电流 lout的 控制, 因而同样存在上述的缺陷。 发明内容
有鉴于此, 本发明提供一种充电控制电路和一种充电装置、 以及一 种充电控制方法和一种充电方法。
根据本发明的第一方面, 提供一种充电控制电路, 所述充电控制电 路用于控制充电执行电路对其充电输出端产生的输出电压和输出电流 的调节、 并触发所述充电执行电路的充电终止, 所述充电控制电路包括 电流调节模块和检测控制模块;
所述电流调节模块用于对外部输入的第一电流基准进行调节, 并将 调节得到的第二电流基准输出至所述充电执行电路的电流基准输入端、 以控制所述充电执行电路对所述输出电压和所述输出电流的调节; 其 中, 所述第二电流基准的最小电流值小于所述第一电流基准、 最大电流 值等于所述第一电流基准;
所述检测控制模块用于周期性地触发充电的中断、 并控制所述电流 调节模块、 以及产生充电终止信号; 其中, 通过在中断期间内对所述电 流调节模块的控制, 所述第二电流基准被限制在所述最小电流值; 通过 在被所述中断期间分隔的充电期间内对所述电流调节模块的控制, 所述 第二电流基准的所述限制被取消; 当在中断期间结束时检测到所述输出 电压低于外部输入的第一电压基准的电压差幅小于预先设置的第一电 压阈值时, 将所述充电终止信号置为有效、 以触发所述充电终止。
可选地, 当在所述充电期间内检测到所述输出电流低于所述第二电 流基准的电流差幅小于第一电流阈值时, 若所述第二电流基准尚未达到 所述最大电流值, 则所述限制被取消的所述第二电流基准被所述电流调 节模块调高;
当在所述充电期间内检测到所述电流差幅大于等于预先设置的第二 电流阈值、 且小于预先设置的第三电流阈值时, 若所述第二电流基准尚 未达到所述最小电流值, 则所述限制被取消的所述第二电流基准被所述 电流调节模块调低;
当在所述充电期间内检测到所述电流差幅大于等于所述第三电流阈 值时, 若所述第二电流基准尚未达到所述最小电流值, 则所述限制被取 消的所述第二电流基准被所述电流调节模块复位至所述最小电流值; 其中, 所述第一电流阈值小于所述第二电流阈值、 所述第二电流阈 值小于所述第三电流阈值。
和 /或, 所述充电控制电路进一步包括电压调节模块, 所述电压调节 模块用于对所述第一电压基准进行调节, 并将调节得到的第二电压基准 输出至所述充电执行电路的电压基准输入端、 以控制所述充电执行电路 对所述输出电压和所述输出电流的调节; 其中, 所述第二电压基准的最 大电压值大于所述第一电压基准、 最小电压值等于所述第一电压基准; 以及,所述检测控制模块进一步用于控制所述电压调节模块, 其中: 当在中断期间结束时检测到所述电压差幅大于等于所述第一电压阈 值、 且小于第二电压阈值时, 若所述第二电压基准尚未达到所述最小电 压值, 则所述第二电压基准被所述电压调节模块调低;
当在中断期间结束时检测到所述电压差幅大于第三电压阈值时, 若 所述第二电压基准尚未达到所述最大电压值, 则所述第二电压基准被所 述电压调节模块调高;
其中, 所述第一电压阈值小于所述第二电压阈值、 所述第二电压阈 值小于所述第三电压阈值。
根据本发明的第二方面, 提供一种充电装置, 所述充电装置包括如 上所述的充电控制电路。
根据本发明的第三方面, 提供一种充电控制方法, 所述充电控制方 法用于控制对充电时产生的输出电压和输出电流的调节、 并触发充电终 止, 所述充电控制方法包括:
al、 对输入的第一电流基准进行调节, 并输出调节得到的第二电流 基准、 以控制对所述输出电压和所述输出电流的调节; 其中, 所述第二 电流基准的最小电流值小于所述第一电流基准、 最大电流值等于所述第 一电流基准;
b0、 周期性地触发充电的中断、 并控制所述 al、 以及产生充电终止 信号; 其中, 通过在中断期间内对所述电流调节模块的控制, 所述第二 电流基准被限制在所述最小电流值; 通过在被所述中断期间分隔的充电 期间内对所述电流调节模块的控制, 所述第二电流基准的所述限制被取 消; 当在中断期间结束时检测到所述输出电压低于外部输入的第一电压 基准的电压差幅小于预先设置的第一电压阈值时, 将所述充电终止信号 置为有效、 以触发所述充电终止。
可选地, 当在所述充电期间内检测到所述输出电流低于所述第二电 流基准的电流差幅小于第一电流阈值时, 若所述第二电流基准尚未达到 所述最大电流值, 则被取消所述限制的所述第二电流基准被所述 al 调 高;
当在所述充电期间内检测到所述电流差幅大于等于预先设置的第二 电流阈值、 且小于预先设置的第三电流阈值时, 若所述第二电流基准尚 未达到所述最小电流值, 则所述限制被取消的所述第二电流基准被所述 al调低;
当在所述充电期间内检测到所述电流差幅大于等于所述第三电流阈 值时, 若所述第二电流基准尚未达到所述最小电流值, 则所述限制被取 消的所述第二电流基准被所述 al复位至所述最小电流值;
其中, 所述第一电流阈值小于所述第二电流阈值、 所述第二电流阈 值小于所述第三电流阈值。 和 /或, 所述充电控制方法进一步包括: a2、 对所述第一电压基准进 行调节, 并输出调节得到的第二电压基准、 以控制对所述输出电压和所 述输出电流的调节; 其中, 所述第二电压基准的最大电压值大于所述第 一电压基准、 最小电压值等于所述第一电压基准;
以及, 所述 b0进一步控制所述 a2, 其中:
当在中断期间结束时检测到所述电压差幅大于等于所述第一电压阈 值、 且小于第二电压阈值时, 若所述第二电压基准尚未达到所述最小电 压值, 则所述第二电压基准被所述 a2调低;
当在中断期间结束时检测到所述电压差幅大于第三电压阈值时, 若 所述第二电压基准尚未达到所述最大电压值, 则所述第二电压基准被所 述 a2调高;
其中, 所述第一电压阈值小于所述第二电压阈值、 所述第二电压阈 值小于所述第三电压阈值。
根据本发明的第四方面, 提供一种充电方法, 所述充电方法包括如 上所述的控制方法中的各步骤。
如上可见, 本发明能够提供一可在小于等于标定的第一电流基准的 范围内调节的第二电流基准、 并在周期性触发的中断期间内通过将第二 电流基准限制在最小电流值而使输出电压更接近电池的内核电压, 因 此, 若在中断期间结束时检测到输出电压趋近于达到标定的第一电压基 准, 则可近似地确定电池的内核电压趋近于达到标定的第一电压基准, 从而, 本发明以输出电压是否趋近于达到标定的第一电压基准为条件来 触发充电终止, 能够改善充电不足的缺陷。 进一步更优地:
本发明还能够提供一可在大于等于标定的第一电压基准的范围内调 节的第二电压基准; 若在中断期间结束时检测到输出电压将要趋近于达 到标定的第一电压基准, 则可近似地确定电池的内核电压将要趋近于达 到标定的第一电压基准, 并可以通过降低第二电压基准来压低充电期间 内的输出电压、 以防止过充; 若在中断期间结束时检测到输出电压远未 达到标定的第一电压基准时, 则可近似地确定电池的内核电压远未达到 标定的第一电压基准, 并可以通过提高第二电压基准来允许输出电压在 充电期间内超过标定的第一电压基准、 以提高充电速度;
和 /或, 本发明还能够在充电期间通过对第二电流基准的调节来限制 输出电流的瞬时上沖。 附图简要说明
图 1为现有技术中的一种充电装置的示例性结构示意图;
图 2为本发明装置实施例一的充电装置的示例性结构示意图; 图 3为本发明装置实施例一的充电装置中的充电控制电路所包含的 电流调节模块的优选结构示意图;
图 4为本发明装置实施例一的充电装置中的充电控制电路所包含的 检测控制模块的优选结构示意图;
图 5为图 4所示检测控制模块中的电压检测器的一具体实例示意图; 图 6为图 4所示检测控制模块中的逻辑控制器的一具体实例示意图; 图 7为本发明装置实施例二的充电装置的示例性结构示意图; 图 8为本发明装置实施例二的充电装置中的充电控制电路所包含的 检测控制模块的优选结构示意图;
图 9为图 8所示检测控制模块中的电流检测器的一具体实例示意图; 图 10为图 8所示检测控制模块中的逻辑控制器的一具体实例示意 图;
图 11 为本发明装置实施例二的充电装置产生的输出电流的波形示 意图; 图 12为本发明装置实施例三的充电装置的示例性结构示意图; 图 13 为本发明装置实施例三的充电装置中的充电控制电路所包含 的电压调节模块的优选结构示意图;
图 14 为本发明装置实施例三的充电装置中的充电控制电路所包含 的检测控制模块的优选结构示意图;
图 15为图 14所示检测控制模块中的电压检测器的一具体实例示意 图;
图 16为图 14所示检测控制模块中的逻辑控制器的一具体实例示意 图;
图 17 为本发明装置实施例三的充电装置产生的输出电压及相应的 输出电流的波形示意图;
图 18为本发明装置实施例四的充电装置的示例性结构示意图; 图 19 为本发明装置实施例四的充电装置中的充电控制电路所包含 的检测控制模块的优选结构示意图;
图 20为图 19所示检测控制模块中的逻辑控制器的一具体实例示意 图。 实施本发明的方式
为使本发明的目的、 技术方案及优点更加清楚明白, 以下参照附图 并举实施例, 对本发明进一步详细说明。 装置实施例一
图 2为本发明装置实施例一的充电装置的示例性结构示意图。 如图 2所示, 该充电装置 2用于对电池 100充电, 该充电装置 2包括充电执 行电路 11、 充电保护电路 12、 以及充电控制电路 23。 其中, 充电执行电路 11和充电保护电路 12的结构和工作原理与现 有技术相同, 本实施例不再赘述, 而且充电保护电路 12是可选的、 而 非必需; 充电控制电路 23则用于控制充电执行电路 11对其充电输出端 产生的输出电压 Vout和输出电流 lout的调节、 并控制充电执行电路 11 的充电终止。
具体说,本实施例中充电装置 2所包含的充电控制电路 23包括: 电 流调节模块 231和检测控制模块 230。
电流调节模块 231用于对外部输入的标定电流基准 Iref— s进行调节, 并将调节得到的可变电流基准 Iref— g输出至充电执行电路 11的电流基准 输入端 (即差分放大器 111的负输入端)、 以控制充电执行电路 11对输 出电压 Vout和输出电流 lout的调节; 其中,可变电流基准 Iref— g的最小 电流值小于标定电流基准 Iref— s, 可变电流基准 Iref— g的最大电流值等 于标定电流基准 Iref— s;
检测控制模块 230用于周期性地触发充电的中断、 并控制电流调节 模块 231、 以及产生充电终止信号 Fin— b; 其中, 通过在中断期间内对电 流调节模块 231的控制, 变电流基准 Iref— g被限制在上述最小电流值; 通过在被中断期间分隔的充电期间内对电流调节模块 231的控制, 可变 电流基准 Iref— g的上述限制被取消; 以及, 当在中断期间结束时检测到 输出电压 Vout低于外部输入的标定电压基准 Vref— s的电压差幅小于预 先设置的电压阈值 Th— vl (近似地表示电池 100的内核电压 V0趋近于 达到标定电压基准 Vref— s ) 时, 将充电终止信号 Fin— b置为有效、 以触 发充电终止。
在本实施例中, 对于可变电流基准 Iref— g的最小电流值的设定, 可 以预先设定一偏差允许范围,并以确保输出电压 Vout相比于电池内核电 压 V0的偏差(即电池 100的内阻 R0产生的压降)处于该偏差允许范围 内为设定最小电流值的约束条件。 当然, 预定偏差允许范围的大小会针 对各种制定要求而有所不同, 相应地, 最小电流值的具体取值存就会在 差异; 而且, 即便在预定偏差允许范围的大小确定时, 对于不同特性的
PMOS 114、或者可替换 PMOS 114实现可调节开关功能的其他器件, 最 小电流值的具体取值也会存在相应的差异。 但是, 在知晓最小电流值的 上述功能作用的前提下, 本领域技术人员能够确定该最小电流值适用于 各种情况的具体取值, 此处不再——列举。
在本实施例中, 所述的"取消对可变电流基准 Iref— g的上述限制"是 指: 可以在可变电流基准 Iref— g的最小电流值与最大电流值之间任意调 任意设置, 例如, 将可变电流基准 Iref— g调节至最大电流值(即标定电 流基准 Iref— s )并在充电期间内稳定保持在最大电流值、 或者将可变电 流基准 Iref— g调节至大于最小电流值且小于等于最大电流值一预先选定 的缺省电流值并在充电期间内稳定保持在该缺省电流值, 此处不再—— 列举。
基于上述充电控制电路 23 , 充电执行电路 11 的电流基准输入端接 收的是可变电流基准 Iref— g、 而不是固定不变的标定电流基准 Iref— s; 另 外, 在本实施例中, 充电执行电路 11 的电压基准输入端 (即差分放大 器 112的负输入端)仍接收输入的标定电压基准 Vref— s。
由于可变电流基准 Iref— g在每个中断期间内都会被限制在上述最小 电流值, 因此, 每当中断期间开始时, 输出电流 lout就会大于、 甚至远 大于突变为最小电流值的可变电流基准 Iref— g; 相应地, 无论输出电压 Vout此时是尚未达到标定电压基准 Vref— s、 还是已达到或略高于标定电 压基准 Vref— s, 控制信号 Ctrl— I的正电压值都会高于控制信号 Ctrl— V的 正电压值, 并控制 PMOS 114 (即可调节开关) 关闭、 或微弱导通, 从 而使得输出电流 lout 降低至与限制在该最小电流值的可变电流基准 Iref— g基本持平。
当输出电流 lout 降低至与限制在该最小电流值的可变电流基准 Iref— g基本持平之后:
若输出电压 Vout此时尚未达到标定电压基准 Vref— s, 则 PMOS 114 仍由控制信号 Ctrl— I来控制、 并保持关闭或微弱导通的状态;
若输出电压 Vout此时已达到或略高于标定电压基准 Vref— s, 则可能 会暂时出现控制信号 Ctrl— V的正电压值高于控制信号 Ctrl— I的正电压值 的情况, 那么, 即便控制信号 Ctrl— V控制 PMOS 114增大导通程度、 使 输出电流 lout增大并略高于限制在最小电流值的可变电流基准 Iref— g, 控制信号 Ctrl— I的正电压值也会再次高于控制信号 Ctrl— V的正电压值、 并重新控制 PMOS 114降低导通程度;
也就是说, 当输出电流 lout 与限制在最小电流值的可变电流基准 Iref— g保持基本持平后,该基本持平的状态能够在中断期间内予以保持。
那么, 最小电流值越小, 电池 100的内阻 R0产生的压降、 即输出 电压 Vout相比于电池 100的内核电压 V0的偏差也就越小, 相应地, 经 过中断期间之后,输出电压 Vout就会越接近真实的内核电压 V0 , 因此, 在中断期间结束时检测输出电压 Vout低于标定电压基准 Vref— s的电压 的电压差幅。
从而, 本实施例在中断期间结束时所检测到的上述电压差幅, 能够 近似地反映出电池 100充电是否充满, 相应地, 相比于以输出电流 lout 是否足够作为触发充电终止条件的现有技术, 本实施例以上述电压差幅 来判断是否需要触发充电终止就更为准确, 进而就能够改善充电不足的 缺陷。 需要说明的是, 虽然充电执行电路 11的电压基准输入端(即差分放 大器 112的负输入端)在本实施例中接收的是标定电压基准 Vref— s, 但 基于后续的装置实施例三和装置实施例四的说明, 本领域技术人员可以 确定,充电执行电路 11的电压基准输入端是否输入标定电压基准 Vref— s 不会对改善充电不足的缺陷产生实质性影响。
下面,对本实施例的充电装置 2中的充电控制电路 23所包含的各模 块进行详细说明。
图 3为本发明装置实施例一的充电装置中的充电控制电路所包含的 电流调节模块的优选结构示意图。 如图 3所示, 电流调节模块 231 于一种可变增益电流镜结构来实现的、 并具有 2m个调节档位, 该电流 调节模块 231 包括一路电流镜干路 2311 、 m 路电流镜支路 2312-l~2312-m、 以及一个 m位的译码器 2313 , m为大于等于 1的正整 数。
电流镜干路 2311中包括一 NMOS0。 该 NMOS0的漏极 D作为电流 镜干路 2311 的输入端、 并连接电流调节模块 231 的输入端, 用于接收 标定电流基准 Iref— s; 该 NMOS0的源极 S作为电流镜干路 2311的输出 端、 并接地; 该 NMOS0的栅极 G连接该 NMOS0的漏极 D、 并被拉高, 从而使栅极 G与源极 S之间产生大于的栅源电压差 VGS为正值、 并大 于 NMOS0的截止电压, 即, NMOS0处于常开状态、 以使电流镜干路 2311 的输入端从电流调节模块 231 的输入端所接收的标定电流基准 Iref— s能够从电流镜干路 2311的输出端输出。
m路电流镜支路 2312-1-2312-m的输入端汇聚于电流镜干路 2311 的输出端, 用于接收标定电流基准 Iref— s的 l/m、 即一个调节档位的大 小; m路电流镜支路 2312-1 -2312-m的输出端汇聚于电流调节模块 231 的输出端,用于输出可变电流基准 Iref— g。并且,每一路电流镜支路 2312-i ( i为大于等于 1且小于等于 m的正整数 ) 包括三个 NMOSiO~NMOSi2 和一个反向器 Revi, 其中:
NMOSiO的源极 S作为电流镜支路 2312-i的输入端、漏极 D作为电 流镜支路 2312-i的输出端;
NMOSil的源极 S连接 NMOSiO的栅极 G、 漏极 D连接 NMOS0的 漏极 D (拉高)、 栅极 G连接译码器 2313的第 i位输出端;
NMOSi2 的源极 S连接 NMOS0 的源极 S (接地)、 漏极 D连接 NMOSiO的栅极 G、 栅极 G通过反向器 Revi连接译码器 2313的第 i位 输出端。
译码器 2313 的输入端通过一电流控制总线接收来自检测控制模块
230的电流编码信号 Icode,并依据电流编码信号 Icode来控制其 m个输 出端的电平状态。
当译码器 2313的第 i位输出端为高电平 1时, NMOSil的栅极 G被 拉高、 并使 NMOSil导通, NMOSi2的栅极 G被反向器 Revi反向后拉 低、 并使 NMOSi2关闭; 导通的 NMOSil又会将 NMOSiO的栅极 G与 NMOS0的栅极 G导通,从而在电流镜支路 2312-i形成与电流镜干路 2311 具有 1/m比例的电流镜, 进而使得标定电流基准 Iref— s的 1/m经过电流 镜支路 2312-i的输出端汇聚至电流调节模块 231的输出端。
当译码器 2313的第 i位输出端为低电平 0时, NMOSi2的栅极 G被 拉低、 并使 NMOSil关闭, NMOSi2的栅极 G被反向器 Revi反向后拉 高、 并使 NMOSi2导通; 导通的 NMOSi2又会将 NMOSiO的栅极 G拉 低、 并使 NMOSiO关闭, 从而使电流镜支路 2312-i的输入端接收到的标 定电流基准 Iref— s的 1/m不会汇聚至电流调节模块 231的输出端。
由此可见, 当译码器 2313的 m位输出端均为高电平 1时, 每一路 电流镜支路 2312-i的电流基准 Iref— s的 1/m均能够汇聚到电流调节模块 231的输出端, 相应地, 电流调节模块 231的输出端产生的可变电流基 准 Iref—g就等于标定电流基准 Iref— s、 即最大电流值。
而当译码器 2313的 m位输出端不全为 1 时, 标定电流基准 Iref— s 至少有 1/m无法汇聚到电流调节模块 231的输出端, 相应地, 电流调节 模块 231 的输出端产生的可变电流基准 Iref—g 就小于标定电流基准 Iref— s。 那么, 按照前文对可变电流基准 Iref— g的最小电流值的作用的说 明,就可以根据需要而从这些小于标定电流基准 Iref— s的电流值 0 m-1 ) Iref— s/m中任选一个作为该最小电流值。
当然, 电流调节模块 231还可以采用其他结构予以实现, 例如, 基 于可变电阻的结构等, 本文不再——列举。 相应地, 除了电流编码信号 Icode之外, 也可以采用其他的信号形式来控制电流调节模块 231。
图 4为本发明装置实施例一的充电装置中的充电控制电路所包含的 检测控制模块的优选结构示意图。 如图 4所示, 检测控制模块 230包括 时钟计时器 2301、 逻辑控制器 2302、 电流计数器 2304、 以及电压检测 器 2305。
时钟计时器 2301用于对基准时钟信号 CLK— s计数, 并依据计数结 果产生中断时钟信号 CLK— t; 其中, 中断时钟信号 CLK— t有效时表示中 断期间、 无效时表示充电期间。
相应地, 逻辑控制器 2302用于依据中断时钟信号 CLK— t产生电流 复位信号 I— res; 其中, 当中断时钟信号 CLK— t有效时, 电流复位信号 I res置为有效。
电流计数器 2304用于依据基准时钟信号以及电流复位信号 I— res进 行计数操作, 并将得到的电流计数结果输出至电流调节模块 231、 以使 电流调节模块 231依据该电流计数结果进行调节(对于电流调节模块 231 采用如图 3 所示优选结构的情况, 该电流计数结果可以电流编码信号 Icode的方式输出至电流调节模块 231、以供译码器 2313的输入端接收); 其中,每当基准时钟信号 CLK— s由无效跳变为有效的时钟沿到来时 (中断期间结束时):
若电流复位信号 I— res有效,则执行一次将电流计数结果复位至最小 电流计数值的计数操作, 该最小电流计数值对应可变电流基准 Iref—g的 最小电流值;
若电流复位信号 I— res无效,则执行一次将电流计数结果增加一个电 流调节步长的计数操作、 直至达到最大电流计数值或预先设定的一缺省 电流计数值, 该最大电流计数值对应可变电流基准 Iref—g的最大电流值 (即标定电流基准 Iref— s )、 缺省电流计数值对应前文提及的预先选定的 缺省电流值; 即, 电流计数器 2304在需要"取消对可变电流基准 Iref— g 的上述限制"时,通过连续计数而将可变电流基准 Iref—g快速调节至最大 电流值并在充电期间内稳定保持在最大电流值、 或者将可变电流基准 Iref—g调节至大于最小电流值且小于等于最大电流值一预先选定的缺省 电流值并在充电期间内稳定保持在该缺省电流值。
电压检测器 2305用于检测输出电压 Vout低于标定电压基准 Vref— s 的电压差幅的大小, 并依据该电压差幅的大小产生电压检测信号 V—tl ; 其中, 电压检测信号 V—tl在该电压差幅小于电压阈值 Th— vl时有效, 即, 该电压检测信号 V—tl有效时表示输出电压 Vout趋近于达到标定电 压基准 Vref— s。
相应地, 逻辑控制器 2302还用于依据中断时钟信号 CLK— t以及电 压检测信号 V—tl产生充电终止信号 Fin— b;其中,当中断时钟信号 CLK— t 由有效跳变为无效的时钟沿到来时, 若电压检测信号 V—tl 有效(在中 断期间结束时近似地表示电池 100的内核电压 V0趋近于达到标定电压 基准 Vref s ), 则充电终止信号 Fin b置为有效。 基于上述的优选结构, 检测控制模块 230即可实现其对应的功能。 其中, 时钟计时器 2301和电流计数器 2304实质上实现的是本领域技术 人员能够熟练掌握的计数器功能, 因而对于的时钟计时器 2301 和电流 计数器 2304实现方式, 此处就不再赘述; 而对于电压检测器 2305和逻 辑控制器 2302 来说, 虽然也能够由本领域技术人员利用各种元器件组 合出多种实现方式, 但下面仍分别举例予以进一步说明。
对于电压检测器 2305来说, 其检测输出电压 Vout低于标定电压基 准 Vref— s的电压差幅的大小, 实际上就是为了检测输出电压 Vout与标 定电压基准 Vref— s的接近程度。 那么, 在具体实现时, 可以先检测出该 电压差幅的具体电压值、 并将电压差幅的具体电压值与电压阈值 Th— vl 进行比较,也可以先从标定电压基准 Vref— s中提取出等同于损失了电压 阈值 Th— vl 的差值电压、 再将输出电压 Vout与提取出的差值电压进行 比较。
图 5为图 4所示检测控制模块中的电压检测器的一具体实例示意图。 图 5中采用的是先从标定电压基准 Vref— s中提取出等同于损失了电压阈 值 Th— vl 的差值电压、 再将输出电压 Vout与该差值电压进行比较的方 式。
如图 5所示, 电压检测器 2305包含一比较器 Comp— vtl , 该比较器 Comp vt 1 的一路负输入端接收输出电压 Vout、 另一路正输入端接收标 定电压基准 Vref— s与电压阈值 Th— vl的差值电压 Vref— s-Th— vl , 该比较 器 Comp— vtl的输出端产生电压检测信号 V— tl。 其中:
当输出电压 Vout小于等于差值电压 Vref— s-Th— vl时,即表示输出电 压 Vout低于标定电压基准 Vref— s的电压差幅大于等于电压阈值 Th— vl (输出电压 Vout尚未趋近于达到标定电压基准 Vref— s ), 因而此时的电 压检测信号 V— tl为高电平的无效; 而当输出电压 Vout大于差值电压 Vref— s-Th— vl时,即表示输出电压 Vout低于标定电压基准 Vref— s的电压差幅小于电压阈值 Th— vl (输出电 压 Vout已趋近于达到标定电压基准 Vref— s ), 因而此时的电压检测信号 V tl为低电平的有效。
对于逻辑控制其 2302来说, 其主要实现的是逻辑判断及触发功能。 图 6为图 4所示检测控制模块中的逻辑控制器的一具体实例示意图。 图 6中采用了一种易于实现的逻辑判断和触发方式。 如图 6所示, 逻辑 控制器 2302包括反向器 Rev— cl和 Rev— c2、 电阻 Rf和电容 Cf、 以及 D 触发器 DFF1和反向器 Rev— vl。
基准时钟信号 CLK— t依次经过反向器 Rev— cl反向、电阻 Rf和电容 Cf构成的延时电路的延迟、 以及反向器 Rev— c2反向后产生电流复位信 号 I— res, 从而, 即可在基准时钟信号 CLK— t处于表示中断期间的高电 平的有效时, 使电流复位信号 I— res置为高电平的有效、 并相比于基准 时钟信号 CLK— t略有延迟, 而在基准时钟信号 CLK— t处于表示充电期 间的低电平的无效时, 使电流复位信号 I— res置为低电平的无效、 并相 比于基准时钟信号 CLK— t略有延迟。
D触发器 DFF1受控于基准时钟信号 CLK— t经过反向器 Rev— cl的 反向信号、 并依据由反向器 Rev— vl反向后的电压检测信号 V—tl的电平 状态触发充电终止信号 Fin— b的电平状态翻转, 从而, 即可在基准时钟 信号 CLK— t反向后的上升沿、 即基准时钟信号 CLK— t从高电平有效跳 变为低电平无效的下降沿到来时 (中断周期结束时), 依据处于低电平 的有效电压检测信号 V—tl而使充电终止信号 Fin— b从低电平的无效翻转 为高电平的有效。 装置实施例二 图 7为本发明装置实施例二的充电装置的示例性结构示意图。 如图 7所示, 该充电装置 3用于对电池 100充电, 该充电装置 3包括充电执 行电路 11、 充电保护电路 12、 以及充电控制电路 33。
其中, 充电执行电路 11和充电保护电路 12的结构和工作原理与现 有技术相同, 本实施例不再赘述, 而且充电保护电路 12是可选的、 而 非必需; 充电控制电路 33则用于控制充电执行电路 11对其充电输出端 产生的输出电压 Vout和输出电流 lout的调节、 并控制充电执行电路 11 的充电终止。
具体说,本实施例中充电装置 3所包含的充电控制电路 33包括电流 调节模块 231和检测控制模块 330。
电流调节模块 231的功能和具体实现已在装置实施例一中予以说明 (当电流调节模块 231选用如图 3所示结构时, m应大于 1 ), 因而本实 施例中不再赘述;
检测控制模块 330用于周期性地触发充电的中断、 并控制电流调节 模块 231、 以及产生充电终止信号 Fin— b; 其中, 通过在中断期间内对电 流调节模块 231的控制, 变电流基准 Iref— g被限制在上述最小电流值; 通过在被中断期间分隔的充电期间内对电流调节模块 231的控制, 可变 电流基准 Iref— g的上述限制被取消; 以及, 当在中断期间结束时检测到 输出电压 Vout低于外部输入的标定电压基准 Vref— s的电压差幅小于电 压阈值 Th— vl (近似地表示电池 100的内核电压 V0趋近于达到标定电 压基准 Vref— s )时, 将充电终止信号 Fin— b置为有效、 以触发充电终止; 而且, 基于检测控制模块 330对电流调节模块 231的控制, 被取消 上述限制的可变电流基准 Iref— g具有如下的几种变化状态:
当在充电期间内检测到输出电流 lout低于可变电流基准 Iref— g的电 流差幅小于预先设置的电流阈值 Th il (表示输出电流 lout已十分接近 当前的可变电流基准 Iref— g ) 时, 若可变电流基准 Iref— g尚未达到其最 大电流值(即标定电流基准 Iref— s ), 则可变电流基准 Iref— g被电流调节 模块 231调高;
当在充电期间内检测到输出电流 lout低于可变电流基准 Iref— g的电 流差幅大于等于预先设置的电流阈值 Th— i2、且小于电流阈值 Th— i3 (表 示输出电流 lout已明显低于当前的可变电流基准 Iref— g ) 时, 若可变电 流基准 Iref— g尚未达到前述的最小电流值, 则可变电流基准 Iref— g被电 流调节模块 231调低;
当在充电期间内检测到输出电流 lout低于可变电流基准 Iref— g的电 流差幅大于等于预先设置的电流阈值 Th—i3 (表示输出电流 lout已远远 低于当前的可变电流基准 Iref— g ) 时, 若可变电流基准 Iref— g尚未达到 前述的最小电流值, 则可变电流基准 Iref— g被电流调节模块 231复位至 前述的最小电流值;
其中, 电流阈值 Th— i 1小于电流阈值 Th— i2、 电流阈值 Th— i2小于电 流阈值 Th— i3。
基于上述充电控制电路 33 , 充电执行电路 11 的电流基准输入端接 收的是可变电流基准 Iref— g、 而不是固定不变的标定电流基准 Iref— s; 另 外, 在本实施例中, 充电执行电路 11 的电压基准输入端 (即差分放大 器 112的负输入端)仍接收输入的标定电压基准 Vref— s。
那么, 由于可变电流基准 Iref— g在每个中断期间内都会被限制在上 述最小电流值, 因此, 本实施例能够像装置实施例一那样改善充电不足 的缺陷。
而且, 本实施例在充电期间, 能够随着输出电流 lout的变化而自适 应调节而自适应调节可变电流基准 Iref— g, 即, 当实施例一中所述的 "取 消对可变电流基准 Iref— g 的上述限制"采用自适应的方式来调节可变电 流基准 Iref— g时, 即可构成本实施例。 由于采用了该自适应调节的方式, 因此:
当输出电流 lout已十分接近当前的可变电流基准 Iref— g时, 通过增 大可变电流基准 Iref— g来允许输出电流 lout继续升高;
当输出电流 lout已明显低于当前的可变电流基准 Iref— g时, 通过减 小可变电流基准 Iref— g来适应输出电流 lout的降低、 以待输出电流 lout 反弹时避免产生瞬时上沖;
当输出电流 lout已远远低于当前的可变电流基准 Iref— g时, 通过将 可变电流基准 Iref— g复位至前述的最小电流值来适应输出电流 lout在突 发波动时的瞬时突降、 以待输出电流 lout突发波动导致的瞬时突升时避 免产生瞬时上沖。
由此可见, 相比于装置实施例一, 本实施例能够进一步在充电期间 通过对可变电流基准 Iref— g的调节来限制输出电流 lout的瞬时上沖。
进一步优选地, 检测控制模块 330还可以进一步用于在充电终止信 号 Fin— b置为有效时, 通过对电流调节模块 231的控制使可变电流基准 Iref g被复位至前述的最小电流值、 以避免下次充电开始后的输出电流 lout产生瞬时上沖。
需要说明的是, 虽然充电执行电路 11的电压基准输入端(即差分放 大器 112的负输入端)在本实施例中接收的是标定电压基准 Vref— s, 但 基于后续的装置实施例四的说明, 本领域技术人员可以确定, 充电执行 电路 11的电压基准输入端是否输入标定电压基准 Vref— s不会对限制瞬 时上沖产生实质性影响。
由于电流调节模块 231的功能和具体实现已在装置实施例一中予以 说明, 因此, 下面仅对本实施例的充电装置 3 中的充电控制电路 23所 包含的检测控制模块 330进行详细说明。 图 8为本发明装置实施例二的充电装置中的充电控制电路所包含的 检测控制模块的优选结构示意图。 如图 8所示, 检测控制模块 330包括 时钟计时器 2301、逻辑控制器 3302、电流检测器 3303、电流计数器 3304、 以及电压检测器 2305。
时钟计时器 2301 已在装置实施例一中予以说明, 本实施例不再赘 号 CLK— t周期性地触发充电的中断的方式与装置实施例一中的逻辑控 制器 2302相同, 本实施例也不再赘述。
电流检测器 3303用于检测输出电流 lout低于可变电流基准 Iref— g 的电流差幅的大小, 并依据该电流差幅的大小产生电流检测信号 I— 11、 电流检测信号 I— 12、 以及电流检测信号 I— 13; 其中, 电流检测信号 I— tl 在上述电流差幅小于电流阈值 Th— il时有效, 电流检测信号 I— 12在上述 电流差幅小于电流阈值 Th— i2时有效, 电流检测信号 I— 13在上述电流差 幅小于电流阈值 Th— i3时有效。 如下所示的表 1中列举出了电流检测信 号 I— tl、 电流检测信号 I— 12、 以及电流检测信号 I—t3的各种电平组合的 含义。
Figure imgf000026_0001
表 1
在表 1中, ΔΙ表示输出电流 lout低于可变电流基准 Iref— g的电流差 相应地, 逻辑控制器 2302用于依据时钟计数器 2301产生的中断时 钟信号 CLK— 1、 电流检测器 3303产生的电流检测信号 I— tl〜: [_t3 , 产生 电流增大信号 I— up、 电流减小信号 I— down、 以及电流复位信号 I— res; 其中, 基于表 1所示的各种电平组合的含义, 逻辑控制器 2302产生的 电流增大信号 I— up、 电流减小信号 I— down、 以及电流复位信号 I— res的 电平变化如下:
当中断时钟信号 CLK— t无效(充电期间 ) 时, 若电流检测信号 I— tl 有效(表示输出电流 lout已十分接近当前的可变电流基准 Iref— g ) , 则电 流增大信号 I— up置为有效; 否则, 电流增大信号 I— up保持无效;
当中断时钟信号 CLK— t无效时, 若电流检测信号 I— 12无效、 电流检 测信号 I— 13有效(表示输出电流 lout 已明显低于当前的可变电流基准 Iref g ),则电流减小信号 I— down置为有效;否则, 电流减小信号 I— down 保持无效;
当中断时钟信号 CLK— t无效时, 若电流检测信号 I— 13无效(表示输 出电流 lout 已远远低于当前的可变电流基准 Iref— g ), 则电流复位信号 I— res置为有效; 以及, 当中断时钟信号 CLK—t有效(进入中断期间) 有效时, 电流复位信号 I— res置为有效;
当电流检测信号 I— 13无效、且延迟的基准时钟信号 CLK—t,无效(表 示充电期间) 时, 电流复位信号 I— res置为无效。
电流计数器 3304 用于依据基准时钟信号 CLK— s、 电流增大信号 I— up、 电流减小信号 I— down、 以及电流复位信号 I— res进行计数操作, 并将得到的电流计数结果输出至电流调节模块 231、 以使电流调节模块 231依据电流计数结果进行调节 (对于电流调节模块 231采用如图 3所 示优选结构的情况, 该电流计数结果可以电流编码信号 Icode的方式输 出至电流调节模块 231、 以供译码器 2313的输入端接收); 其中, 每当 基准时钟信号 CLK s由无效跳变为有效的时钟沿到来时: 若电流增大信号 I— up有效,则执行一次将电流计数结果增加一个电 流调节步长(对于电流调节模块 231采用如图 3所示优选结构的情况, 可以设定每个电流调节步长等长, 即, 设定每个电流调节步长所对应的 调节档位数量相同; 当然, 也可以设定电流调节步长不等长, 即, 设定 每次的电流调节步长相比于前一次或后一次的电流调节步长增加或减 少至少一个调节档位) 的计数操作;
若电流减小信号 I— down有效,则执行一次将电流计数结果减少一个 电流调节步长的计数操作;
若电流复位信号 I— res有效,则执行一次将电流计数结果复位至最小 电流计数值的计数操作, 该最小电流计数值对应前述的最小电流值。
电压检测器 2305 已在装置实施例一中予以说明, 本实施例不再赘 号 CLK— t和电压检测器 2305产生的电压检测信号 V— tl来产生充电终止 信号 Fin— b的方式与装置实施例一中的逻辑控制器 2302相同,本实施例 也不再赘述。
另外, 若需要检测控制模块 330进一步在充电终止信号 Fin— b置为 有效时, 通过对电流调节模块 231的控制使可变电流基准 Iref— g被复位 至前述的最小电流值, 则逻辑控制器 3302 可以进一步在充电终止信号 Fin— b有效时将电流复位信号 I— res置为有效。 这种情况下, 在电流检测 信号 I— 13无效、充电终止信号 Fin— b无效、且延迟的基准时钟信号 CLK— 1, 处于表示充电期间的无效时, 电流复位信号 I— res置为低电平的无效。
基于上述的优选结构, 检测控制模块 330即可实现其对应的功能。 其中, 电流计数器 3304 实质上实现的是本领域技术人员能够熟练掌握 的计数器功能, 因而对于电流计数器 3304 的实现方式, 此处就不再赘 述; 而对于电流检测器 3303和逻辑控制器 3302来说, 虽然也能够由本 领域技术人员利用各种元器件组合出多种实现方式, 但下面仍分别举例 予以进一步说明。
对于电流检测器 3304来说, 其检测输出电流 lout低于可变电流基 准 Iref— g的电流差幅的大小, 实际上就是为了检测输出电流 lout与不断 变化的可变电流基准 Iref— g的接近程度。 那么, 在具体实现时, 可以先 检测出该电流差幅的具体电流值、 并将电流差幅的具体电流值分别与电 流阈值 Th— il~Th— i3进行比较, 也可以先从当前的可变电流基准 Iref— g 中提取分别出等同于损失了电流阈值 Th— il~Th— i3的差值电流、 再将输 出电流 lout与提取出的各差值电流进行比较。
无论采用上述的哪种检测方式, 都可以通过将电流转换为对应电压 进行比较, 这样更易于实现。
图 9为图 8所示检测控制模块中的电流检测器的一具体实例示意图。 图 9中采用的是先从当前的可变电流基准 Iref— g中提取分别出等同于损 失了电流阈值 Th— i 1 ~Th— i3的差值电流、 再将输出电流 lout与提取出的 各差值电流进行比较的方式, 并通过将输出电流 lout与各差值电流转换 为对应的电压进行比较。
如图 9所示, 电流检测器 3304包含电阻 Ra、 Rb、 Rc、 Rd、 Rout, 还包含比较器 Comp— itl~Comp— it3。
电阻 Ra、 Rb、 Rc、 Rd顺序串联构成一电阻串, 该电阻串位于电阻 Ra所在侧的一端接收可变电流基准 Iref— g、 位于 Rd所在侧的另一端接 地。 相应地, 电阻串位于电阻 Ra所在侧的一端即可产生可变电流基准 Iref— g大小对应的电压; 电阻 Ra与 Rb的连接端、 Rb与 Rc的连接端、 Rc与 Rd的连接端则依次产生递增的压降, 并且, 递增的压降大小就依 次对应电流阈值 Th— il~Th— i3。 那么, 电阻 Ra与 Rb的连接端、 Rb与 Rc的连接端、 Rc与 Rd的连接端的电压大小就依次对应可变电流基准 Iref— g中损失了电流阈值 Th— il~Th— i3的差值电流。
电阻 Rout 的一端接收输出电流 Iout、 另一端接地。 相应地, 电阻 Rout接收输出电流 lout的一端即可产生与输出电流 lout大 d、对应的电 压。
如此一来,将电阻 Rout接收输出电流 lout的一端的电压,分别与电 阻 Ra与 Rb的连接端、 Rb与 Rc的连接端、 Rc与 Rd的连接端的电压进 行比较, 即可得知输出电流 lout低于可变电流基准 Iref— g的电流差幅相 比于电流阈值 Th— i 1 ~Th— i3的大小关系。 因此:
该比较器 Comp— itl的一路负输入端连接 Rout接收输出电压 Vout的 一端、 另一路正输入端连接 Ra与 Rb的连接端, 该比较器 Comp— itl的 输出端产生电流检测信号 I— tl ; 其中, 当 Rout接收输出电压 Vout的一 端电压小于等于 Ra与 Rb的连接端电压时,即表示输出电流 lout低于可 变电流基准 Iref— g的电流差幅大于等于电流阈值 Th— il , 因而此时的电 流检测信号 I— tl为高电平的无效; 而当 Rout接收输出电压 Vout的一端 电压大于 Ra与 Rb的连接端电压时,即表示输出电流 lout低于可变电流 基准 Iref— g的电流差幅小于电流阈值 Th— il , 因而此时的电流检测信号 I tl为高电平的无效;
该比较器 Comp— it2的一路负输入端连接 Rout接收输出电压 Vout的 一端、 另一路正输入端连接 Rb与 Rc的连接端, 该比较器 Comp— it2的 输出端按照与比较器 Comp— itl相同的原理产生电流检测信号 I— 12; 该比较器 Comp— it3的一路负输入端连接 Rout接收输出电压 Vout的 一端、 另一路正输入端连接 Rc与 Rd的连接端, 该比较器 Comp— it3的 输出端按照与比较器 Comp— itl相同的原理产生电流检测信号 I— 13。
对于逻辑控制其 3302来说, 其主要实现的是逻辑判断及触发功能。 图 10为图 8所示检测控制模块中的逻辑控制器的一具体实例示意 图。 图 10中采用了一种易于实现的逻辑判断和触发方式。如图 10所示, 逻辑控制器 2302包括反向器 Rev— il和 Rev— i2、 与门 ANDi、 或门 OR, 还包括 Rev— c 1和 Rev— c2、 电阻 Rf和电容 Cf、 以及 D触发器 DFF 1和 反向器 Rev— vl。
电流检测信号 I— tl 经反向器 Rev— il反向后即可产生电流增大信号 I— up; 当电流检测信号 I—tl为低电平的有效时, 电流增大信号 I— up即变 为高电平的有效; 反之, 电流增大信号 I— up即变为低电平的无效。
电流检测信号 I— 12输入至与门 ANDi, 电流检测信号 I— 13经反向器 Rev_i2反向后也输入至与门 ANDi; 当电流检测信号 I— 12为高电平的无 效、 且电流检测信号 I— 12为低电平的有效时, 与门 ANDi输出的电流减 小信号 I— down即变为高电平的有效; 反之, 与门 ANDi输出的电流减 小信号 I— down即变为低电平的无效。
电流检测信号 I— 13输出至或门 OR; 当电流检测信号 I— 13为高电平 的无效时, 或门 OR输出的电流复位信号 I— res即变为高电平的有效。
基准时钟信号 CLK— t依次经过反向器 Rev— cl反向、电阻 Rf和电容 Cf构成的延时电路的延迟、 以及反向器 Rev— c2反向后, 被延迟为基准 时钟信号 CLK— 1,并输出至或门 OR, 当延迟的基准时钟信号 CLK— 1,处 于表示中断期间的高电平的有效时, 或门 OR输出的电流复位信号 I— res 即变为高电平的有效。
D触发器 DFF1受控于基准时钟信号 CLK— t经过反向器 Rev— cl的 反向信号、 并依据被反向器 Rev— vl反向后的电压检测信号 V—tl的电平 状态触发充电终止信号 Fin— b的电平状态翻转, 从而, 即可在基准时钟 信号 CLK— t反向后的上升沿、 即基准时钟信号 CLK— t从高电平有效跳 变为低电平无效的下降沿到来时 (中断周期结束时), 依据处于低电平 的有效电压检测信号 V—tl而使充电终止信号 Fin— b从低电平的无效翻转 为高电平的有效。
实际应用中,若需要检测控制模块 330进一步在充电终止信号 Fin— b 置为有效时, 通过对电流调节模块 231的控制使可变电流基准 Iref— g被 复位至前述的最小电流值, 则充电终止信号 Fin— b除了输出至充电控制 电路 33的外部之外, 还输出至或门 OR (图 10中以虚线表示;); 当充电 终止信号 Fin— b为高电平的有效时, 或门 OR输出的电流复位信号 I— res 即变为高电平的有效。
图 11 为本发明装置实施例二的充电装置产生的输出电流的波形示 意图。 在图 11 中示出了采用本实施例方案时的充电期间内的输出电流 lout的波形、 以及未采用本实施例方式时的输出电流 lout'的波形;并且, 图 11所基于的本实施例方案是以电流调节模块 231采用如图 3所示的 结构、 且如图 3所示结构中的 m取 16为例。
参见图 11 , 在采用本实施例方案的充电期间内, 基于基准时钟信号 CLK t的频率, 电流编码信号 Icode所表示的电流计数结果会随着输出 电流 lout的升高而逐步递增、或者随着输出电流 lout的降低而逐步递增, 由此, 即可避免输出电流 lout的瞬时上沖;
再参见图 11 , 在未采用本实施例方案的充电期间内, 输出电流 lout' 容易出现大幅波动、 并产生瞬时上沖。
那么,从图 11中可以更直观地看出, 当采用本实施例中的自适应方 式调节可变电流基准 Iref— g时,能够有效防止输出电流 lout的瞬时上沖。 装置实施例三
图 12为本发明装置实施例三的充电装置的示例性结构示意图。如图 12所示, 该充电装置 4用于对电池 100充电, 该充电装置 4包括充电执 行电路 11、 充电保护电路 12、 以及充电控制电路 43。 其中, 充电执行电路 11和充电保护电路 12的结构和工作原理与现 有技术相同, 本实施例不再赘述, 而且充电保护电路 12是可选的、 而 非必需; 充电控制电路 43则用于控制充电执行电路 11对其充电输出端 产生的输出电压 Vout和输出电流 lout的调节、 并控制充电执行电路 11 的充电终止。
具体说,本实施例中充电装置 4所包含的充电控制电路 43包括: 电 流调节模块 231、 电压调节模块 432、 以及检测控制模块 430。
电流调节模块 231 的功能和具体实现已在装置实施例一中予以说 明, 因而本实施例中不再赘述;
电压调节模块 432用于对标定电压基准 Vref— s进行调节, 并将调节 得到的可变电压基准 Vref— g输出至充电执行电路 11的电压基准输入端 (即差分放大器 112的一路负输入端)、 以控制充电执行电路 11对输出 电压 Vout和输出电流 lout的调节; 其中, 可变电压基准 Vref— g的最大 电压值大于标定电压基准 Vref— s,可变电压基准 Vref— g的最小电压值等 于标定电压基准 Vref— s;
检测控制模块 430用于周期性地触发充电的中断、 并控制电流调节 模块 231、 以及产生充电终止信号 Fin— b; 其中, 通过在中断期间内对电 流调节模块 231的控制, 变电流基准 Iref— g被限制在上述最小电流值; 通过在被中断期间分隔的充电期间内对电流调节模块 231的控制, 可变 电流基准 Iref— g的上述限制被取消; 以及, 当在中断期间结束时检测到 输出电压 Vout低于外部输入的标定电压基准 Vref— s的电压差幅小于电 压阈值 Th— vl (近似地表示电池 100的内核电压 V0趋近于达到标定电 压基准 Vref— s )时, 将充电终止信号 Fin— b置为有效、 以触发充电终止; 检测控制模块 430还用于控制电压调节模块 432, 基于检测控制模 块 430对电压调节模块 432的控制,可变电压基准 Vref— g具有如下的几 种变化状态:
当在中断期间结束时检测到上述电压差幅大于等于前述的电压阈值
Th— vl、 且小于预先设置的电压阈值 Th— v2时(表示中断期间结束时的 输出电压 Vout将要趋近于达到标定电压基准 Vref— s ) , 若可变电压基准 Vref g尚未达到上述最小电压值,则可变电压基准 Vref— g被电压调节模 块 432调低;
当在中断期间结束时检测到上述电压差幅大于预先设置的电压阈值 Th_v3时(表示中断期间结束时的输出电压 Vout远未达到标定电压基准 Vref s ),若可变电压基准 Vref— g尚未达到上述最大电压值,则可变电压 基准 Vref— g被电压调节模块 432调高;
其中, 电压阈值 Th vl小于电压阈值 Th— v2、 电压阈值 Th_v2小于 电压阈值 Th— v3。
在本实施例中, 对于可变电流基准 Iref— g的最小电流值的设定、 以 及"取消对可变电流基准 Iref— g的上述限制"的实现方式, 可以参照装置 实施例一中的说明, 此处不在赘述。
基于上述充电控制电路 43 , 充电执行电路 11 的电流基准输入端接 收的是可变电流基准 Iref— g、 而不是固定不变的标定电流基准 Iref— s; 充 电执行电路 11 的电压基准输入端输入的是可变电压基准 Vref— g、 而不 是固定不变的标定电压基准 Vref— s。
由于可变电流基准 Iref— g在每个中断期间内都会被限制在上述最小 电流值, 因此, 每当中断期间开始时, 输出电流 lout就会大于、 甚至远 大于突变为最小电流值的可变电流基准 Iref— g; 相应地, 无论输出电压 Vout此时是尚未达到可变电压基准 Vref— g、还是已达到或略高于可变电 压基准 Vref— g,控制信号 Ctrl— I的正电压值都会高于控制信号 Ctrl— V的 正电压值, 并控制 PMOS 114 (即可调节开关) 关闭、 或微弱导通, 从 而使得输出电流 lout 降低至与限制在该最小电流值的可变电流基准 Iref— g基本持平。
当输出电流 lout 降低至与限制在该最小电流值的可变电流基准 Iref— g基本持平之后:
若输出电压 Vout此时尚未达到可变电压基准 Vref— g , 则 PMOS 114 仍由控制信号 Ctrl— I来控制、 并保持关闭或微弱导通的状态;
若输出电压 Vout此时已达到或略高于可变电压基准 Vref— g,则可能 会暂时出现控制信号 Ctrl— V的正电压值高于控制信号 Ctrl— I的正电压值 的情况, 那么, 即便控制信号 Ctrl— V控制 PMOS 114增大导通程度、 使 输出电流 lout增大并略高于限制在最小电流值的可变电流基准 Iref— g, 控制信号 Ctrl— I的正电压值也会再次高于控制信号 Ctrl— V的正电压值、 并重新控制 PMOS 114降低导通程度;
可见,相比于装置实施例一, 虽然本实施例将充电执行电路 11的基 准电压输入端接收的标定电压基准 Vref— s 替换为了可变电压基准 Vref g , 但在输出电流 lout与限制在最小电流值的可变电流基准 Iref— g 保持基本持平后, 本实施例仍能够像装置实施例一那样确保该基本持平 的状态能够在中断期间内予以保持。
因此,如装置实施例一种所述, 充电执行电路 11的电压基准输入端 是否输入标定电压基准 Vref— s不会对改善充电不足的缺陷产生实质性影 响。
相应地, 本实施例就能够像装置实施例一和装置实施例二那样改善 充电不足的缺陷。
而且,本实施例在每次中断期间结束时,能够依照输出电压 Vout(近 似于电池 100的内核电压 V0 )接近标定电压基准 Vref— s的程度而自适 应调节而自适应调节可变电压基准 Vref— g, 因此: 当中断期间结束时的输出电压 Vout将要趋近于达到标定电压基准 Vref s时, 可近似地认为电池 100的内核电压 V0将要趋近于达到标定 电压基准 Vref— s, 相应地, 通过减小可变电压基准 Vref— g而使输出电压 Vout在即将开始的充电周期内减小, 就能够避免由于输出电压 Vout过 大而导致内核电压 V0将要趋近于达到标定电压基准 Vref— s的电池 100 发生过充;
当中断期间结束时的输出电压 Vout远未达到标定电压基准 Vref— s 时, 可近似地认为电池 100 的内核电压 V0 远未达到标定电压基准 Vref s, 相应地, 通过增大可变电压基准 Vref— g 而允许输出电压 Vout 在即将开始的充电周期内增大, 就能够允许输出电流 lout在即将开始的 充电周期内更大、 从而能够加快对内核电压 V0远未达到标定电压基准 Vref s的电池 100的充电速度。
由此可见, 相比于装置实施例一和装置实施例二, 本实施例能够进 一步在中断期间结束时通过对可变电压基准 Vref— g 的调节来加快充电 速度。
进一步优选地, 检测控制模块 430还可以进一步用于在充电终止信 号 Fin— b置为有效时, 通过对电压调节模块 432的控制使可变电压基准 Vref— g被复位至前述的最小电压值。
下面,对本实施例的充电装置 4中的充电控制电路 43所包含的各模 块进行详细说明。
图 13 为本发明装置实施例三的充电装置中的充电控制电路所包含 的电压调节模块的优选结构示意图。 如图 13 所示, 电压调节模块 432 包括具有 n个档位的电阻可调电路 4321、 以及一个 n位的译码器 4322, n为大于 2的正整数。
电阻可调电路 4321包含电阻 Rl~Rn、 以及 NMOSl~NMOSn。 电阻 Rl~Rn顺序串联构成一电阻串, 该电阻串位于电阻 R1所在侧 的一端接收标定电压基准 Vref— s, 该电阻串位于 Rn所在侧的另一端连 接一电源 Vccl并用于产生可变电压基准 Vref— g。
NMOS1的源极 S与上述电阻串接收标定电压基准 Vref— s的一端相 连、 漏极 D与上述电阻串位于 Rn所在侧的另一端相连(即与电源 Vccl 相连)、 栅极 G连接译码器 4322的第 1位输出端;
NMOSj的源极 S与电阻 Rj连接电阻 Rj-1的一端相连、漏极 D与上 述电阻串位于 Rn所在侧的另一端相连(即与电源 Vccl相连)、 栅极 G 连接译码器 4322的第 j位输出端, j为大于 1且小于等于 n的正整数。
译码器 4322 的输入端通过一电压控制总线接收来自检测控制模块 430的电压编码信号 Vcode, 并依据电压编码信号 Vcode来控制其 n个 输出端的电平状态。
由于 NMOS l~NMOSn的漏极 D均被电源 Vccl拉高, 因此: 当译码器 4322的第 1位输出端为高电平时, NMOS1关闭; 而当译 码器 4322的第 1位输出端为高电平时, NMOS1导通、 并将电阻 Rl~Rn 全部短路, 从而使得可变电压基准 Vref— g等于标定电压基准 Vref— s、 即 前文所述的最小电压值;
当译码器 4322的第 j位输出端为高电平时, NMOSj关闭; 而当译 码器 4322的第 j位输出端为高电平时, NMOSj导通、 并将电阻 Rj~Rn 短路, 从而在 NMOSl~NMOSj关闭的情况下, 使可变电压基准 Vref— g 由于未被短路的电阻 Rl~Rj-l而相比于标定电压基准 Vref— s产生一定的 增量;
若译码器 4322的 n位输出端均为高电平、并将 NMOSl~NMOSn全 部关闭, 则会使得可变电压基准 Vref— g会由于未被短路的电阻 Rl~Rn 而相比于标定电压基准 Vref s产生最大的增量, 即达到前文所述的最大 电压值。
也就是说, 在如图 13所示的优选结构中, 通过将电阻 Rl~Rn中不 同数量的电阻短路、 即可实现不同的调节档位。 且通过设定电阻 Rl~Rn 的阻值, 可以实现各调节档位相同或不同。
当然, 电压调节模块 432还可以采用其他结构予以实现, 例如, 基 于标定电压基准 Vref— s, 同时提供大于等于该标定电压基准 Vref— s多个 电压值, 并依据译码器 4322从多个电压值中选择一个作为可变电压基 准 Vref— g。 此外, 除了电压编码信号 Vcode之外, 也可以采用其他的信 号形式来控制电压调节模块 432。
图 14 为本发明装置实施例三的充电装置中的充电控制电路所包含 的检测控制模块的优选结构示意图。 如图 14所示, 检测控制模块 430 包括时钟计时器 2301、 逻辑控制器 4302、 电流计数器 2304、 以及电压 检测器 4305和电压计数器 4306。
时钟计时器 2301 已在装置实施例一中予以说明, 本实施例不再赘 号 CLK— t周期性地触发充电的中断的方式与装置实施例一中的逻辑控 制器 2302相同, 本实施例也不再赘述。
电流计数器 2304 已在装置实施例一中予以说明, 本实施例不再赘 述。 相应地, 逻辑控制器 4302利用电流复位信号 I— res控制电流计数器 2304的方式与装置实施例一中的逻辑控制器 2302相同, 本实施例也不 再赘述。
电压检测器 4305用于检测输出电压 Vout低于可变电压基准 Vref— g 的电压差幅的大小, 并依据该电压差幅的大小产生电压检测信号 V—tl、 电压检测信号 V— 12、以及电压检测信号 V— 13;其中, 电压检测信号 V— tl 在上述电压差幅小于电压阈值 Th vl时有效, 电压检测信号 V t2在上 述电压差幅小于电压阈值 Th— v2时有效, 电压检测信号 V— 13在上述电 压差幅小于电压阈值 Th— v3时有效。 如下所示的表 2中列举出了电压检 测信号 V— tl、 电压检测信号 V— 12、 以及电压检测信号 V—t3的各种电平 组合的含义。
Figure imgf000039_0001
表 2
在表 2中, AV表示输出电压 Vout低于可变电压基准 Vref— g的电压 差幅。
相应地, 逻辑控制器 4302用于依据时钟计数器 2301产生的中断时 钟信号 CLK— t产生调节时钟信号 CLK— g, 并且, 依据中断时钟信号 CLK— 1、 以及电压检测器 4305产生的电压检测信号 V— tl~V— 13 , 产生充 电终止信号 Fin— b、 电压减小信号 V— down、 以及电压增大信号 V— up; 其中, 调节时钟信号 CLK— g为中断时钟信号 CLK— t的反向信号; 并且, 基于表 2所示的各种电平组合的含义, 逻辑控制器 4302产生的充电终 止信号 Fin— b、 电压减小信号 V— down、 电压增大信号 V— up的电平变化 :¾口下:
当中断时钟信号 CLK— t由有效跳变为无效的时钟沿到来(中断期间 结束)时,若电压检测信号 V— tl有效,则充电终止信号 Fin— b置为有效; 否则, 充电终止信号 Fin— b保持无效;
当中断时钟信号 CLK— t由有效跳变为无效的时钟沿到来(中断期间 结束) 时, 若电压检测信号 V— tl无效、 电压检测信号 V— 12有效, 则电 压减小信号 V— down置为有效; 否则, 电压减小信号 V— down保持无效; 当中断时钟信号 CLK— t由有效跳变为无效的时钟沿到来(中断期间 结束 )时,若电压检测信号 V— 13无效,则电压增大信号 V— up置为有效; 否则, 电压增大信号 V— up保持无效。
电压计数器 4306 用于依据调节时钟信号 CLK— g、 电压增大信号 V— up、 电压减小信号 V— down进行计数操作, 并将得到的电压计数结果 输出至电压调节模块 432、 以使电压调节模块 432依据所述电压计数结 果进行调节(对于电压调节模块 432采用如图 13所示优选结构的情况, 该电压计数结果可以电压编码信号 Vcode 的方式输出至电压调节模块 432、以供译码器 4311的输入端接收);其中,每当调节时钟信号 CLK— g 由无效跳变为有效的时钟沿到来(中断期间开始) 时:
若电压增大信号 V— up有效, 则执行一次将电压计数结果增加一个 电压计数步长的计数操作 (对于电压调节模块 432采用如图 13所示优 选结构的情况, 可以设定每个电压调节步长等长, 即, 设定每个调节档 位的调节幅度相同、 且每个电压调节步长所对应的调节档位数量相同; 当然, 也可以设定电压调节步长不等长, 即, 设定每个调节档位的调节 幅度不同、 且每个电压调节步长所对应的调节档位数量相同, 或设定每 个调节档位的调节幅度相同、 但每次的电压调节步长相比于前一次或后 一次的电压调节步长增加或减少至少一个调节档位);
若电压减小信号 V— down有效, 则执行一次将电压计数结果减少一 个电压计数步长的计数操作。
另外, 若需要检测控制模块 430进一步在充电终止信号 Fin— b置为 有效时,通过对电压调节模块 432的控制使可变电压基准 Vref— g被复位 至前述的最小电压值, 则逻辑控制器 4302 可以进一步依据充电终止信 号 Fin— b产生电压复位信号 V— res,其中,在充电终止信号 Fin— b有效时, 电压复位信号 V— res置为有效, 在充电终止信号 Fin— b无效时, 电压复 位信号 V— res无效;相应地, 电压计数器 4306进一步用于依据电压复位 信号 V— res进行计数操作, 当电压复位信号 V— res有效时, 执行一次将 电压计数结果复位至最小电压计数值的计数操作, 该最小电压计数值对 应前述的最小电压值、 即标定电压基准 Vref— s。
基于上述的优选结构, 检测控制模块 330即可实现其对应的功能。 其中, 电压计数器 4306 实质上实现的是本领域技术人员能够熟练掌握 的计数器功能, 因而对于电压计数器 4306 的实现方式, 此处就不再赘 述; 而对于电压检测器 4305和逻辑控制器 4302来说, 虽然也能够由本 领域技术人员利用各种元器件组合出多种实现方式, 但下面仍分别举例 予以进一步说明。
对于电压检测器 4305来说, 其检测输出电压 Vout低于标定电压基 准 Vref— s的电压差幅的大小, 实际上就是为了检测输出电压 Vout与标 定电压基准 Vref— s的接近程度。 那么, 在具体实现时, 可以先检测出该 电压差幅的具体电压值、 并将电压差幅的具体电压值分别与电压阈值 Th— vl~Th— v3进行比较,也可以先从标定电压基准 Vref— s中提取出分别 等同于损失了电压阈值 Th— vl~Th— v3 的差值电压、 再将输出电压 Vout 分别与提取出的各差值电压进行比较。 图 15为图 14所示检测控制模块中的电压检测器的一具体实例示意 图。 图 15中采用的是先从标定电压基准 Vref— s中提取出分别等同于损 失了电压阈值 Th— vl~Th— v3的差值电压、 再将输出电压 Vout分别与各 差值电压进行比较的方式。
如 图 15 所示 , 电压检测 器 4305 包含三个比较器 Comp— vtl〜Comp— vt3。
比较器 Comp— vtl的一路负输入端接收输出电压 Vout、 另一路正输 入端接收标定电压基准 Vref— s 与电压阈值 Th— vl 的差值电压 Vref s-Th vl , 该比较器 Comp— vtl 的输出端产生电压检测信号 V— tl。 其中:
当输出电压 Vout小于等于差值电压 Vref— s-Th— vl时,即表示输出电 压 Vout低于标定电压基准 Vref— s的电压差幅大于等于电压阈值 Th— vl (输出电压 Vout尚未趋近于达到标定电压基准 Vref— s ), 因而此时的电 压检测信号 V— tl为高电平的无效;
而当输出电压 Vout大于差值电压 Vref— s-Th— vl时,即表示输出电压 Vout低于标定电压基准 Vref— s的电压差幅小于电压阈值 Th— vl (输出电 压 Vout已趋近于达到标定电压基准 Vref— s ), 因而此时的电压检测信号 V tl为低电平的有效。
比较器 Comp— vt2的一路负输入端接收输出电压 Vout、 另一路正输 入端接收标定电压基准 Vref— s 与电压阈值 Th— v2 的差值电压 Vref— s-Th— v2, 该比较器 Comp— vt2的输出端产生电压检测信号 V— 12。 其中:
当输出电压 Vout小于等于差值电压 Vref— s-Th— v2时,即表示输出电 压 Vout低于标定电压基准 Vref— s的电压差幅大于等于电压阈值 Th— v2 (输出电压 Vout距达到标定电压基准 Vref— s尚有一定的差距;), 因而此 时的电压检测信号 V— 12为高电平的无效;
而当输出电压 Vout大于差值电压 Vref— s-Th— v2时,即表示输出电压 Vout低于标定电压基准 Vref— s的电压差幅小于电压阈值 Th— v2 (输出电 压 Vout将要趋近于达到标定电压基准 Vref— s ), 因而此时的电压检测信 号 V— 12为低电平的有效。
比较器 Comp— vt3的一路负输入端接收输出电压 Vout、 另一路正输 入端接收标定电压基准 Vref— s 与电压阈值 Th— v3 的差值电压 Vref— s-Th— ν3 , 该比较器 Comp— vt3 的输出端产生电压检测信号 V— 13。 其中:
当输出电压 Vout小于等于差值电压 Vref— s-Th— v3时,即表示输出电 压 Vout低于标定电压基准 Vref— s的电压差幅大于等于电压阈值 Th— v3 (输出电压 Vout远未达到电压基准 Vref— s ), 因而此时的电压检测信号 V— 12为高电平的无效;
而当输出电压 Vout大于差值电压 Vref— s-Th— v3时,即表示输出电压 Vout低于标定电压基准 Vref— s的电压差幅小于电压阈值 Th— v3 (输出电 压 Vout低于标定电压基准 Vref— s的差距尚可 ), 因而此时的电压检测信 号 V— 13为低电平的有效。
对于逻辑控制其 4302来说, 其主要实现的是逻辑判断及触发功能。 图 16为图 14所示检测控制模块中的逻辑控制器的一具体实例示意 图。 图 16中采用了一种易于实现的逻辑判断和触发方式。如图 16所示, 逻辑控制器 4302包括反向器 Rev— cl~Rev— c3、 电阻 Rf和电容 Cf、 D触 发器 DFF1~DFF3、 与门 AND— v、 以及反向器 Rev— vl和 Rev— v2。
其中, 图 16中利用反向器 Rev— cl和 Rev— c2、 电阻 Rf和电容 Cf产 生电流复位信号 I— res的结构, 以及, 利用反向器 Rev— vl和 D触发器 DFF 1产生充电终止信号 Fin b的结构与装置实施例一中如图 6所示的相 应结构相同, 本实施例不再赘述。 此外:
基准时钟信号 CLK— t依次经过反向器 Rev— cl反向、电阻 Rf和电容 Cf 构成的延时电路的延迟、 以及反向器 Rev— c2反向后, 再经反向器 Rev— c3反向, 即可产生与基准时钟信号 CLK— t反向、 并具有一定延迟 的调节时钟信号 CLK— g。
D触发器 DFF2受控于基准时钟信号 CLK— t经过反向器 Rev— cl的 反向信号、 并依据与门 AND— V 输出的电平状态触发电压减小信号 V— down的电平状态翻转,并且与门 AND— V的一路输入接收电压检测信 号 V— tl、另一路输入接收经反向器 Rev— v2反向后的电压检测信号 V— 12; 从而, 即可在基准时钟信号 CLK—t反向后的上升沿、 即基准时钟信号 CLK—t从高电平有效跳变为低电平无效的下降沿到来时(中断周期结束 时), 依据处于高电平无效的电压检测信号 V—tl、 以及低电平的有效电 压检测信号 V— 12而使电压减小信号 V— down从低电平的无效翻转为高电 平的有效。
D触发器 DFF3受控于基准时钟信号 CLK—t经过反向器 Rev— cl的 反向信号、 并依据电压检测信号 V— 13 的电平状态触发电压增大信号 V— up的电平状态翻转, 从而, 即可在基准时钟信号 CLK—t反向后的上 升沿、即基准时钟信号 CLK—t从高电平有效跳变为低电平无效的下降沿 到来时 (中断周期结束时), 依据处于高电平的无效电压检测信号 V— 13 而使电压增大信号 V— up从低电平的无效翻转为高电平的有效。
实际应用中,若需要检测控制模块 430进一步在充电终止信号 Fin— b 置为有效时,通过对电压调节模块 432的控制使可变电压基准 Vref— g被 复位至前述的最小电压值, 则充电终止信号 Fin— b除了输出至充电控制 电路 43的外部之外, 还依次通过反向器 Rev— v3和 Rev— v4 (图 16中以 虚线表示)产生电压复位信号 V— res; 当充电终止信号 Fin— b为高电平 的有效时, 电压复位信号 V— res即变为高电平的有效。
图 17 为本发明装置实施例三的充电装置产生的输出电压及相应的 输出电流的波形示意图。 在图 17 中示出了采用本实施例方案时的充电 期间内的输出电压 Vout和输出电流 lout的波形、 以及未采用本实施例 方式时的输出电压 Vout'和输出电流 lout'的波形; 并且, 图 17所基于的 本实施例方案是以电压调节模块 432采用如图 13所示的结构、 且如图 13所示结构中的 n取 4为例。
参见图 17, 在采用本实施例方案的中断期间内, 输出电压 Vout都 会恢复至与电池 100的内核电压 V0近似相等的状态, 那么, 随着在每 次中断期间结束时通过检测输出 Vout检测到的内核电压 V0的升高, 电 压编码信号 Vcode所表示的电压计数结果会随随之递增, 由此, 即可允 许输出电压 Vout高于标定电压基准 Vref— s,并使得输出电流 lout在输出 电压 Vout达到标定电压基准 Vref— s后也不会减小, 从而能够提高充电 速度。
再参见图 17,在未采用本实施例方案的充电期间内,输出电压 Vout' 不得高于标定电压基准 Vref— s , 因而使得输出电流 lout' 在输出电压 Vout,达到标定电压基准 Vref— s后即开始减小, 从而导致充电速度不高。
将图 17中的输出电流 lout与 lout'相比, 在输出电压 Vout和 Vout' 达到标定电压基准 Vref— s之后的期间内,输出电流 lout的波形位于 lout' 的波形之上的部分就为本实施例提高充电速度所产生的电流增量。 装置实施例四
图 18为本发明装置实施例四的充电装置的示例性结构示意图。如图 18所示, 该充电装置 5用于对电池 100充电, 该充电装置 4包括充电执 行电路 11、 充电保护电路 12、 以及充电控制电路 53。 其中, 充电执行电路 11和充电保护电路 12的结构和工作原理与现 有技术相同, 本实施例不再赘述, 而且充电保护电路 12是可选的、 而 非必需; 充电控制电路 53则用于控制充电执行电路 11对其充电输出端 产生的输出电压 Vout和输出电流 lout的调节、 并控制充电执行电路 11 的充电终止。
具体说,本实施例中充电装置 5所包含的充电控制电路 53包括: 电 流调节模块 231、 电压调节模块 432、 以及检测控制模块 530。
电流调节模块 231 的功能和具体实现已在装置实施例一中予以说 明,电压调节模块 432的功能和具体实现已在装置实施例三中予以说明, 因而本实施例中对电流调节模块 231和电压调节模块 432不再赘述; 检测控制模块 530用于周期性地触发充电的中断、 并控制电流调节 模块 231和电压调节模块 432、 以及产生充电终止信号 Fin— b; 其中, 在 中断期间内, 通过对电流调节模块 231的控制使可变电流基准 Iref— g被 限制在前文所述的最小电流值; 在被中断期间分隔的充电期间内, 通过 对电流调节模块 231的控制取消对可变电流基准 Iref— g的上述限制; 以 及, 当在中断期间结束时检测到输出电压 Vout低于标定电压基准 Vref— s 的电压差幅小于电压阈值 Th— vl时, 将充电终止信号 Fin— b置为有效、 以控制充电终止;
而且, 基于检测控制模块 530对电流调节模块 231的控制, 被取消 上述限制的可变电流基准 Iref— g 具有如装置实施例二中所述的变化状 态; 基于检测控制模块 530对电压调节模块 432的控制, 可变电压基准 Vref— g具有如装置实施例三中所述的变化状态。
基于上述充电控制电路 53 , 充电执行电路 11 的电流基准输入端接 收的是可变电流基准 Iref— g、 而不是固定不变的标定电流基准 Iref— s; 充 电执行电路 11 的电压基准输入端输入的是可变电压基准 Vref— g、 而不 是固定不变的标定电压基准 Vref— s。
由于可变电流基准 Iref— g在每个中断期间内都会被限制在上述最小 电流值, 因此, 本实施例仍能够像装置实施例一、 装置实施例二、 以及 装置实施例三那样改善充电不足的缺陷。
而且,本实施例在每次中断期间结束时,能够依照输出电压 V0Ut(近 似于电池 100的内核电压 V0 )接近标定电压基准 Vref— s的程度而自适 应调节而自适应调节可变电压基准 Vref— g, 因而相比于装置实施例一和 装置实施例二, 本实施例能够进一步像装置实施例三那样加快充电速 度。
以及, 本实施例在充电期间, 能够随着输出电流 lout的变化而自适 应调节而自适应调节可变电流基准 Iref— g, 因而相比于装置实施例一和 装置实施例三, 本实施例还能够进一步像装置实施例二那样限制输出电 流 lout的瞬时上沖。
进一步优选地, 检测控制模块 530还可以进一步用于在充电终止信 号 Fin— b置为有效时, 通过对电流调节模块 231的控制使可变电流基准 Iref— g被复位至前述的最小电流值、 通过对电压调节模块 432的控制使 可变电压基准 Vref— g被复位至前述的最小电压值。
图 19 为本发明装置实施例四的充电装置中的充电控制电路所包含 的检测控制模块的优选结构示意图。 如图 19 所示, 检测控制模块 530 包括时钟计时器 2301、 逻辑控制器 5302、 电流检测器 3303、 电流计数 器 3304、 以及电压检测器 4305和电压计数器 4306。
时钟计时器 2301 已在装置实施例一中予以说明, 本实施例不再赘 号 CLK— t周期性地触发充电的中断的方式与装置实施例一中的逻辑控 制器 2302相同, 本实施例也不再赘述。 电流检测器 3303和电流计数器 3304已在装置实施例二中予以说明, 本实施例不再赘述。 相应地, 逻辑控制器 5302依据电流检测器 3303产 生的电流增大信号 I— up、电流减小信号 I— down、以及电流复位信号 I— res 控制电流计数器 3304 的方式与装置实施例二中的逻辑控制器 3302相 同, 本实施例也不再赘述。
电压检测器 4305和电压计数器 4306已在装置实施例三中予以说明, 本实施例不再赘述。 相应地, 逻辑控制器 5302依据电压检测器 4305产 生的充电终止信号 Fin— b、 电压增大信号 V— up、 电压减小信号 V— down、 以及可选的电压复位信号 V— res控制电压计数器 3304的方式与装置实施 例三中的逻辑控制器 4302相同, 本实施例也不再赘述。
图 20为图 19所示检测控制模块中的逻辑控制器的一具体实例示意 图。 图 20中采用了一种易于实现的逻辑判断和触发方式。如图 20所示, 逻辑控制器 5302包括反向器 Rev— cl~Rev— c3、 电阻 Rf和电容 Cf、 反向 器 Rev— il和 Rev— i2、 与门 AND— i、 或门 OR、 D触发器 DFF1~DFF3、 与门 AND— v、 以及反向器 Rev— vl和 Rev— v2。 其中:
图 20中利用反向器 Rev— c 1和 Rev— c2、 电阻 Rf和电容 Cf、 以及或 门 OR产生电流复位信号 I— res 的结构, 以及, 利用反向器 Rev— il 和 Rev_i2、以及与门 AND— i产生电流增大信号 I— up和电流减小信号 I— down 的结构, 与装置实施例二中如图 10所示的相应结构相同, 本实施例不 再赘述;
图 20中利用反向器 Rev— cl~Rev— c3、电阻 Rf和电容 Cf产生调节时 钟信号 CLK— g的结构, 利用 D触发器 DFF1~DFF3、 与门 AND— v、 以 及反向器 Rev— vl 和 Rev— v2 产生充电终止信号 Fin— b、 电压减小信号 V— down、 电压增大信号 V— up的结构与装置实施例三中如图 16所示的 相应结构相同, 本实施例不再赘述。 可选地, 当图 20中进一步包含反向器 Rev— v3和 Rev— v3时, 利用 反向器 Rev— v3和 Rev— v3产生(图 20中以虚线表示)电压复位信号 V— res 的结构与装置实施例三中如图 16所示的相应结构相同, 本实施例不再 赘述。
本实施例所产生的输出电压 Vout及相应的输出电流 lout的波形可以 参见图 17, 并且图 17中所示的输出电流 lout的每个上升沿的波形参照 图 11。
以上是对本发明各装置实施例中的充电装置 2~5及相应的充电控制 电路 23~53的详细说明。 下面, 再结合若干方法实施例, 对充电控制方 法以及应用该充电控制方法的充电方法进行详细说明。 方法实施例一
本实施例中的充电控制方法包括:
步骤 al、 对输入的标定电流基准 Iref— s进行调节, 并输出调节得到 的可变电流基准 Iref— g、 以控制对充电时产生的输出电压 Vout和输出电 流 lout的调节; 其中, 可变电流基准 Iref— g的最小电流值小于标定电流 基准 Iref— s,可变电流基准 Iref— g的最大电流值等于标定电流基准 Iref— s; 步骤 b0、 周期性地触发充电的中断、 并控制步骤 al、 以及产生充电 终止信号 Fin— b; 其中, 通过在中断期间内对电流调节模块 231的控制, 变电流基准 Iref— g被限制在上述最小电流值; 通过在被中断期间分隔的 充电期间内对电流调节模块 231的控制, 可变电流基准 Iref— g的上述限 制被取消; 以及, 当在中断期间结束时检测到输出电压 Vout低于外部输 入的标定电压基准 Vref— s 的电压差幅小于预先设置的电压阈值 Th— vl (近似地表示电池 100的内核电压 V0趋近于达到标定电压基准 Vref— s ) 时, 将充电终止信号 Fin b置为有效、 以触发充电终止。 在本实施例中, 对于可变电流基准 Iref— g的最小电流值的设定、 所 述的"取消对可变电流基准 Iref— g的上述限制"的具体实现, 可以参照装 置实施例一, 此处不再赘述。
基于本实施例中的充电控制方法, 本实施例的充电方法按照与充电 执行电路 11相同的原理,在充电时产生输出电压 Vout和输出电流 Iout、 并利用可变电流基准 Iref— g和标定电压基准 Vref— s来控制对输出电压 Vout和输出电流 lout的调节。
由于可变电流基准 Iref— g在每个中断期间内都会被限制在上述最小 电流值, 因此, 与装置实施例一同理, 本实施例中的充电控制方法和充 电方法就能够改善充电不足的缺陷。
另外, 在具体实现本实施例时:
步骤 b0 中周期性地触发充电的中断可以包括: 对基准时钟信号 CLK— s计数, 并依据计数结果产生中断时钟信号 CLK—t; 其中, 中断时 钟信号 CLK—t有效时表示中断期间、 无效时表示充电期间。
步骤 b0中对上述电流差幅的检测以及对步骤 al的控制可以包括: bi l l、依据中断时钟信号 CLK—t产生电流复位信号 I— res; 其中, 当 中断时钟信号 CLK—t有效时, 电流复位信号 I— res置为有效。
bl l2、依据基准时钟信号以及电流复位信号 I— res进行计数操作, 并 将得到的电流计数结果提供给步骤 al、以使电流调节模块 231依据该电 流计数结果进行调节; 其中,每当基准时钟信号 CLK—s由无效跳变为有 效的时钟沿到来时(中断期间结束时):
若电流复位信号 I— res有效,则执行一次将电流计数结果复位至最小 电流计数值的计数操作, 该最小电流计数值对应可变电流基准 Iref— g的 最小电流值;
若电流复位信号 I res无效,则执行一次将电流计数结果增加一个电 流调节步长的计数操作、 直至达到最大电流计数值或预先设定的一缺省 电流计数值, 该最大电流计数值对应可变电流基准 Iref— g的最大电流值 (即标定电流基准 Iref— s )、 缺省电流计数值对应前文提及的预先选定的 缺省电流值; 即, 在需要"取消对可变电流基准 Iref— g的上述限制"时, 可以通过连续计数而将可变电流基准 Iref— g快速调节至最大电流值并在 充电期间内稳定保持在最大电流值、 或者将可变电流基准 Iref— g调节至 大于最小电流值且小于等于最大电流值一预先选定的缺省电流值并在 充电期间内稳定保持在该缺省电流值。
步骤 bO中对上述电压差幅的检测并产生充电终止信号 Fin— b的过程 可以包括:
bl21、检测输出电压 Vout低于标定电压基准 Vref— s的电压差幅的大 小, 并依据该电压差幅的大小产生电压检测信号 V—tl ; 其中, 电压检测 信号 V—tl在该电压差幅小于电压阈值 Th— vl时有效, 即, 该电压检测 信号 V—tl有效时表示输出电压 Vout趋近于达到标定电压基准 Vref— s; bl22、 依据中断时钟信号 CLK— t以及电压检测信号 V—tl产生充电 终止信号 Fin— b; 其中, 当中断时钟信号 CLK— t由有效跳变为无效的时 钟沿到来时, 若电压检测信号 V—tl 有效(在中断期间结束时近似地表 示电池 100的内核电压 V0趋近于达到标定电压基准 Vref— s ), 则充电终 止信号 Fin— b置为有效。 方法实施例二
本实施例中的充电控制方法仍包括方法实施例一中的步骤 al 和步 骤 bO, 但是, 对于步骤 bO所述的"取消对可变电流基准 Iref— g的上述限 制",本实施例采用采用自适应的方式,从而使得被取消上述限制的可变 电流基准 Iref— g具有如装置实施例二中所述的变化状态。 基于本实施例中的充电控制方法, 本实施例的充电方法按照与充电 执行电路 11相同的原理,在充电时产生输出电压 Vout和输出电流 Iout、 并利用可变电流基准 Iref— g和标定电压基准 Vref— s来控制对输出电压 Vout和输出电流 lout的调节。
由于可变电流基准 Iref— g在每个中断期间内都会被限制在上述最小 电流值, 因此, 本实施例中的充电控制方法和充电方法就能够像方法实 施例一那样改善充电不足的缺陷。
而且, 本实施例在充电期间, 能够随着输出电流 lout的变化而自适 应调节而自适应调节可变电流基准 Iref— g, 因此, 与装置实施例二同理, 本实施例相比于方法实施例一能够进一步在充电期间内限制输出电流 lout的瞬时上沖。
进一步优选地,在本实施例中, 步骤 b0还可以进一步在充电终止信 号 Fin— b置为有效时,通过对步骤 al的控制使可变电流基准 Iref— g被复 位至前述的最小电流值、 以避免下次充电开始后的输出电流 lout产生瞬 时上沖。
另外, 在具体实现本实施例时:
步骤 b0 中周期性地触发充电的中断的方式可以与方法实施例一相 同, 此处不在赘述。
步骤 b0中对上述电流差幅的检测以及对步骤 al的控制可以包括: b211、 检测输出电流 lout低于可变电流基准 Iref— g的电流差幅的大 小, 并依据该电流差幅的大小产生电流检测信号 I— tl、 电流检测信号 I— 12、 以及电流检测信号 I— 13 ; 其中, 电流检测信号 I—tl在上述电流差 幅小于电流阈值 Th— il时有效, 电流检测信号 I— 12在上述电流差幅小于 电流阈值 Th— i2时有效, 电流检测信号 I— 13在上述电流差幅小于电流阈 值 Th_i3时有效 b212、依据时钟计数器 2301产生的中断时钟信号 CLK— 1、 电流检测 器 3303产生的电流检测信号 I— tl〜: [― t3 , 产生电流增大信号 I— up、 电流 减小信号 I— down、 以及电流复位信号 I— res; 其中, 基于装置实施例二 中的表 1所示的各种电平组合的含义, 产生的电流增大信号 I— up、 电流 减小信号 I— down、 以及电流复位信号 I— res的电平变化如下:
当中断时钟信号 CLK— t无效(充电期间 ) 时, 若电流检测信号 I— tl 有效(表示输出电流 lout已十分接近当前的可变电流基准 Iref— g ) , 则电 流增大信号 I— up置为有效; 否则, 电流增大信号 I— up保持无效;
当中断时钟信号 CLK— t无效时, 若电流检测信号 I— 12无效、 电流检 测信号 I— 13有效(表示输出电流 lout 已明显低于当前的可变电流基准 Iref g ),则电流减小信号 I— down置为有效;否则, 电流减小信号 I— down 保持无效;
当中断时钟信号 CLK— t无效时, 若电流检测信号 I— 13无效(表示输 出电流 lout 已远远低于当前的可变电流基准 Iref— g ), 则电流复位信号 I— res置为有效; 以及, 当中断时钟信号 CLK—t有效(进入中断期间) 有效时, 电流复位信号 I— res置为有效;
当电流检测信号 I— 13无效、且延迟的基准时钟信号 CLK—t,无效(表 示充电期间) 时, 电流复位信号 I— res置为无效;
b213、 依据基准时钟信号 CLK— s、 电流增大信号 I— up、 电流减小信 号 I— down、 以及电流复位信号 I— res进行计数操作, 并将得到的电流计 数结果提供给步骤 al、 以使步骤 al依据电流计数结果进行调节; 其中, 每当基准时钟信号 CLK— s由无效跳变为有效的时钟沿到来时:
若电流增大信号 I— up有效,则执行一次将电流计数结果增加一个电 流调节步长(可以设定每个电流调节步长等长、 也可以设定电流调节步 长不等长) 的计数操作; 若电流减小信号 I— down有效,则执行一次将电流计数结果减少一个 电流调节步长的计数操作;
若电流复位信号 I— res有效,则执行一次将电流计数结果复位至最小 电流计数值的计数操作, 该最小电流计数值对应前述的最小电流值。
步骤 bO中对上述电压差幅的检测并产生充电终止信号 Fin— b的过程 可以与方法实施例一相同, 此处不再赘述。
另外, 若需要步骤 bO进一步在充电终止信号 Fin— b置为有效时, 通 过对步骤 al的控制使可变电流基准 Iref— g被复位至前述的最小电流值, 则 b211可以进一步在充电终止信号 Fin— b有效时将电流复位信号 I— res 置为有效。这种情况下,在电流检测信号 I— 13无效、充电终止信号 Fin— b 无效、且延迟的基准时钟信号 CLK—t,处于表示充电期间的无效时, 电流 复位信号 I— res置为低电平的无效。 方法实施例三
本实施例中的充电控制方法包括方法中的步骤 al和步骤 bO, 但是, 本实施例中的充电控制方法还进一步包括:
步骤 a2、 对标定电压基准 Vref— s进行调节, 并输出调节得到的可变 电压基准 Vref— g、以控制对充电时产生的输出电压 Vout和输出电流 lout 的调节; 其中, 可变电压基准 Vref— g 的最大电压值大于标定电压基准 Vref— s, 可变电压基准 Vref— g的最小电压值等于标定电压基准 Vref— s; 相应地, 步骤 bO就需要进一步用于控制步骤 a2, 并且, 基于步骤 bO对步骤 a2的控制, 可变电压基准 Vref— g就具有如装置实施例三中所 述的变化状态。
基于本实施例中的充电控制方法, 本实施例的充电方法按照与充电 执行电路 11相同的原理,在充电时产生输出电压 Vout和输出电流 Iout、 并利用可变电流基准 Iref— g和可变电压基准 Vref— g来控制对输出电压 Vout和输出电流 lout的调节。
由于可变电流基准 Iref— g在每个中断期间内都会被限制在上述最小 电流值, 因此, 本实施例中的充电控制方法和充电方法就能够像方法实 施例一和方法实施例二那样改善充电不足的缺陷。
而且,本实施例在每次中断期间结束时,能够依照输出电压 Vout(近 似于电池 100的内核电压 V0 )接近标定电压基准 Vref— s的程度而自适 应调节而自适应调节可变电压基准 Vref— g, 因此,与装置实施例三同理, 本实施例相比于方法实施例一和方法实施例二能够进一步在中断期间 结束时通过对可变电压基准 Vref— g的调节来加快充电速度。
进一步优选地,步骤 b0还可以进一步用于在充电终止信号 Fin— b置 为有效时, 通过对步骤 a2的控制使可变电压基准 Vref— g被复位至前述 的最小电压值。
另外, 在具体实现本实施例时:
步骤 b0 中周期性地触发充电的中断的方式可以与方法实施例一相 同, 此处不在赘述。
步骤 b0中对上述电流差幅的检测以及对步骤 al的控制可以与方法 实施例一相同, 此处不在赘述。
步骤 b0中对上述电压差幅的检测、 产生充电终止信号 Fin— b、 以及 对步骤 a2的控制可以包括:
b321、 检测输出电压 Vout低于可变电压基准 Vref— g的电压差幅的 大小, 并依据该电压差幅的大小产生电压检测信号 V—tl、 电压检测信号 V— 12、 以及电压检测信号 V— 13 ; 其中, 电压检测信号 V— tl在上述电压 差幅小于电压阈值 Th— vl时有效, 电压检测信号 V— 12在上述电压差幅 小于电压阈值 Th v2时有效, 电压检测信号 V t3在上述电压差幅小于 电压阈值 Th— v3时有效;
b322、 依据中断时钟信号 CLK— t产生调节时钟信号 CLK— g , 并且, 依据中断时钟信号 CLK— 1、 以及电压检测器 4305产生的电压检测信号 V— tl~V— 13 , 产生充电终止信号 Fin— b、 电压减小信号 V— down、 以及电 压增大信号 V— up; 其中, 调节时钟信号 CLK— g为中断时钟信号 CLK— t 的反向信号; 并且, 基于装置实施例三中的表 2所示的各种电平组合的 含义, 产生的充电终止信号 Fin— b、 电压减小信号 V— down、 电压增大信 号 V— up的电平变化如下:
当中断时钟信号 CLK— t由有效跳变为无效的时钟沿到来(中断期间 结束)时,若电压检测信号 V— tl有效,则充电终止信号 Fin— b置为有效; 否则, 充电终止信号 Fin— b保持无效;
当中断时钟信号 CLK— t由有效跳变为无效的时钟沿到来(中断期间 结束) 时, 若电压检测信号 V— tl无效、 电压检测信号 V— 12有效, 则电 压减小信号 V— down置为有效; 否则, 电压减小信号 V— down保持无效; 当中断时钟信号 CLK— t由有效跳变为无效的时钟沿到来(中断期间 结束 )时,若电压检测信号 V— 13无效,则电压增大信号 V— up置为有效; 否则, 电压增大信号 V— up保持无效;
b323、 依据调节时钟信号 CLK— g、 电压增大信号 V— up、 电压减小 信号 V— down进行计数操作, 并将得到的电压计数结果提供给步骤 a2、 以使步骤 a2依据所述电压计数结果进行调节;其中,每当调节时钟信号 CLK g由无效跳变为有效的时钟沿到来(中断期间开始) 时:
若电压增大信号 V— up有效, 则执行一次将电压计数结果增加一个 电压计数步长的计数操作(可以设定每个电压调节步长等长、 也可以设 定电压调节步长不等长);
若电压减小信号 V down有效, 则执行一次将电压计数结果减少一 个电压计数步长的计数操作。
另外, 若需要步骤 b0进一步在充电终止信号 Fin— b置为有效时, 通 过对步骤 a2的控制使可变电压基准 Vref— g被复位至前述的最小电压值, 则 b322可以进一步依据充电终止信号 Fin— b产生电压复位信号 V— res, 其中, 在充电终止信号 Fin— b有效时, 电压复位信号 V— res置为有效, 在充电终止信号 Fin— b无效时, 电压复位信号 V— res无效;相应地, b323 进一步依据电压复位信号 V— res进行计数操作, 当电压复位信号 V— res 有效时, 执行一次将电压计数结果复位至最小电压计数值的计数操作, 该最小电压计数值对应前述的最小电压值、 即标定电压基准 Vref— s。 方法实施例四
本实施例中的充电控制方法包括方法实施例一中的步骤 a 1、 以及方 法实施例三中的步骤 a2和步骤 b0, 并且, 对于步骤 b0所述的"取消对 可变电流基准 Iref— g的上述限制",本实施例采用方法实施例二中的自适 应方式。
基于本实施例中的充电控制方法, 本实施例的充电方法按照与充电 执行电路 11相同的原理,在充电时产生输出电压 Vout和输出电流 Iout、 并利用可变电流基准 Iref— g和可变电压基准 Vref— g来控制对输出电压 Vout和输出电流 lout的调节。
由于可变电流基准 Iref— g在每个中断期间内都会被限制在上述最小 电流值, 因此, 本实施例中的充电控制方法和充电方法就能够像方法实 施例一和方法实施例二以及方法实施例三那样改善充电不足的缺陷。
而且,本实施例在每次中断期间结束时,能够依照输出电压 Vout(近 似于电池 100的内核电压 V0 )接近标定电压基准 Vref— s的程度而自适 应调节而自适应调节可变电压基准 Vref— g, 因此, 本实施例相比于方法 实施例一和方法实施例二能够进一步在中断期间结束时通过对可变电 压基准 Vref— g的调节来加快充电速度。
以及, 本实施例在充电期间, 还能够随着输出电流 lout的变化而自 适应调节而自适应调节可变电流基准 Iref— g, 因此, 本实施例相比于方 法实施例一和方法实施例三能够进一步在充电期间内限制输出电流 lout 的瞬时上沖。
进一步优选地,在本实施例中, 步骤 b0还可以进一步在充电终止信 号 Fin— b置为有效时,通过对步骤 al的控制使可变电流基准 Iref— g被复 位至前述的最小电流值、 通过对步骤 a2的控制使可变电压基准 Vref— g 被复位至前述的最小电压值。
另外, 在具体实现本实施例时:
步骤 b0 中周期性地触发充电的中断的方式可以与方法实施例一相 同, 此处不在赘述。
步骤 b0中对上述电流差幅的检测以及对步骤 al的控制可以与方法 实施例二相同, 此处不在赘述。
步骤 b0中对上述电压差幅的检测、 产生充电终止信号 Fin— b、 以及 对步骤 a2的控制可以与方法实施例三相同, 此处不在赘述。 基于对上述各实施例的理解, 本发明的技术方案本质上或者说对现 有技术做出贡献的部分既可以以硬件的形式体现出来, 也可以以软件产 品的形式体现出来。 具体说, 当本发明的技术方案以软件产品的形式体 现出来时, 可以提供配有机器可读的存储介质的系统或者装置, 在该存 储介质上存储着实现上述充电控制装置和充电控制方法的功能的软件 程序代码, 且使该系统或者装置的计算机(或 CPU或 MPU )读出并执 行存储在存储介质中的程序代码。 在这种情况下, 从存储介质读取的程序代码本身可实现上述充电控 制装置和充电控制方法的功能, 因此程序代码和存储程序代码的存储介 质构成了实现上述充电控制装置和充电控制方法的技术方案的一部分。
用于提供程序代码的存储介质实施例包括软盘、 硬盘、 磁光盘、 光 盘(如 CD-ROM、 CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW、 DVD+RW )、 磁带、 非易失性存储卡和 ROM。 可选择地, 可以由通信网 络从服务器计算机上下载程序代码。
此外,应该清楚的是,不仅可以通过执行计算机所读出的程序代码, 而且可以通过基于程序代码的指令使计算机上操作的操作系统等来完 成部分或者全部的实际操作, 从而实现上述实例中任意一项实施例的功 能。
此外, 可以理解的是, 将由存储介质读出的程序代码写到插入计算 机内的扩展板中所设置的存储器中或者写到与计算机相连接的扩展单 元中设置的存储器中, 随后基于程序代码的指令使安装在扩展板或者扩 展单元上的 CPU等来执行部分和全部实际操作,从而实现上述充电控制 装置和充电控制方法的功能。
以上所述仅为本发明的较佳实施例而已, 并不用以限制本发明, 凡 在本发明的精神和原则之内, 所做的任何修改、 等同替换、 改进等, 均 应包含在本发明保护的范围之内。

Claims

权利要求书
1、 一种充电控制电路, 其特征在于, 所述充电控制电路用于控制充 电执行电路对其充电输出端产生的输出电压和输出电流的调节、 并触发 所述充电执行电路的充电终止, 所述充电控制电路包括电流调节模块和 检测控制模块;
所述电流调节模块用于对外部输入的第一电流基准进行调节, 并将 调节得到的第二电流基准输出至所述充电执行电路的电流基准输入端、 以控制所述充电执行电路对所述输出电压和所述输出电流的调节; 其 中, 所述第二电流基准的最小电流值小于所述第一电流基准、 最大电流 值等于所述第一电流基准;
所述检测控制模块用于周期性地触发充电的中断、 并控制所述电流 调节模块、 以及产生充电终止信号; 其中, 通过在中断期间内对所述电 流调节模块的控制, 所述第二电流基准被限制在所述最小电流值; 通过 在被所述中断期间分隔的充电期间内对所述电流调节模块的控制, 所述 第二电流基准的所述限制被取消; 当在中断期间结束时检测到所述输出 电压低于外部输入的第一电压基准的电压差幅小于预先设置的第一电 压阈值时, 将所述充电终止信号置为有效、 以触发所述充电终止。
2、根据权利要求 1所述的充电控制电路, 其特征在于, 所述检测控 制模块进一步用于控制所述电流调节模块:
当在所述充电期间内检测到所述输出电流低于所述第二电流基准的 电流差幅小于第一电流阈值时, 若所述第二电流基准尚未达到所述最大 电流值, 则所述限制被取消的所述第二电流基准被所述电流调节模块调 高;
当在所述充电期间内检测到所述电流差幅大于等于预先设置的第二 电流阈值、 且小于预先设置的第三电流阈值时, 若所述第二电流基准尚 未达到所述最小电流值, 则所述限制被取消的所述第二电流基准被所述 电流调节模块调低;
当在所述充电期间内检测到所述电流差幅大于等于所述第三电流阈 值时, 若所述第二电流基准尚未达到所述最小电流值, 则所述限制被取 消的所述第二电流基准被所述电流调节模块复位至所述最小电流值; 其中, 所述第一电流阈值小于所述第二电流阈值、 所述第二电流阈 值小于所述第三电流阈值。
3、 根据权利要求 1所述的充电控制电路, 其特征在于, 所述充电控 制电路进一步包括电压调节模块, 所述电压调节模块用于对所述第一电 压基准进行调节, 并将调节得到的第二电压基准输出至所述充电执行电 路的电压基准输入端、 以控制所述充电执行电路对所述输出电压和所述 输出电流的调节; 其中, 所述第二电压基准的最大电压值大于所述第一 电压基准、 最小电压值等于所述第一电压基准;
以及,所述检测控制模块进一步用于控制所述电压调节模块, 其中: 当在中断期间结束时检测到所述电压差幅大于等于所述第一电压阈 值、 且小于预先设置的第二电压阈值时, 若所述第二电压基准尚未达到 所述最小电压值, 则所述第二电压基准被所述电压调节模块调低;
当在中断期间结束时检测到所述电压差幅大于预先设置的第三电压 阈值时, 若所述第二电压基准尚未达到所述最大电压值, 则所述第二电 压基准被所述电压调节模块调高;
其中, 所述第一电压阈值小于所述第二电压阈值、 所述第二电压阈 值小于所述第三电压阈值。
4、 根据权利要求 3所述的充电控制电路, 其特征在于, 所述检测控 制模块进一步用于控制所述电流调节模块: 当在所述充电期间内检测到所述输出电流低于所述第二电流基准的 电流差幅小于第一电流阈值时, 若所述第二电流基准尚未达到所述最大 电流值, 则所述限制被取消的所述第二电流基准被所述电流调节模块调 高;
当在所述充电期间内检测到所述电流差幅大于等于预先设置的第二 电流阈值、 且小于预先设置的第三电流阈值时, 若所述第二电流基准尚 未达到所述最小电流值, 则所述限制被取消的所述第二电流基准被所述 电流调节模块调低;
当在所述充电期间内检测到所述电流差幅大于等于所述第三电流阈 值时, 若所述第二电流基准尚未达到所述最小电流值, 则所述限制被取 消的所述第二电流基准被所述电流调节模块复位至所述最小电流值; 其中, 所述第一电流阈值小于所述第二电流阈值、 所述第二电流阈 值小于所述第三电流阈值。
5、 根据权利要求 4所述的充电控制电路, 其特征在于, 所述检测控 制模块包括时钟计时器、 逻辑控制器、 电流检测器、 电流计数器、 电压 检测器、 电压计数器;
所述时钟计时器用于对基准时钟信号计数, 并依据计数结果产生中 断时钟信号; 其中, 所述中断时钟信号有效时表示所述中断期间、 无效 时表示所述充电期间;
所述电流检测器用于检测所述电流差幅的大小, 并依据所述电流差 幅的大小产生第一电流检测信号、 第二电流检测信号、 以及第三电流检 测信号; 其中, 所述第一电流检测信号在所述电流差幅小于所述第一电 流阈值时有效, 所述第二电流检测信号在所述电流差幅小于所述第二电 流阈值时有效, 所述第三电流检测信号在所述电流差幅小于所述第三电 流阈值时有效; 所述逻辑控制器用于依据所述中断时钟信号、 所述第一电流检测信 号、 所述第二电流检测信号、 所述第三电流检测信号, 产生电流增大信 号、 电流减小信号、 以及电流复位信号; 其中, 当所述中断时钟信号无 效时, 若所述第一电流检测信号有效, 则所述电流增大信号置为有效, 若所述第二电流检测信号无效、 所述第三电流检测信号有效, 则所述电 流减小信号置为有效, 若所述第三电流检测信号无效, 则所述电流复位 信号置为有效; 当所述中断时钟信号有效时, 所述电流复位信号置为有 效;
所述电流计数器用于依据所述基准时钟信号、 所述电流增大信号、 所述电流减小信号、 以及所述电流复位信号进行计数操作, 并将得到的 电流计数结果输出至所述电流调节模块、 以使所述电流调节模块依据所 述电流计数结果进行调节; 其中, 每当所述基准时钟信号由无效跳变为 有效的时钟沿到来时, 若所述电流增大信号有效, 则执行一次将所述电 流计数结果增加一个电流调节步长的计数操作, 若所述电流减小信号有 效, 则执行一次将所述电流计数结果减少一个电流调节步长的计数操 作, 若所述电流复位信号有效, 则执行一次将所述电流计数结果复位至 最小电流计数值的计数操作, 所述最小电流计数值对应所述最小电流 值;
所述电压检测器用于检测所述电压差幅的大小, 并依据所述电压差 幅的大小产生第一电压检测信号、 第二电压检测信号、 以及第三电压检 测信号; 其中, 所述第一电压检测信号在所述电压差幅小于所述第一电 压阈值时有效, 所述第二电压检测信号在所述电压差幅小于所述第二电 压阈值时有效, 所述第三电压检测信号在所述电流差幅小于所述第三电 压阈值时有效;
所述逻辑控制器还用于依据所述中断时钟信号产生调节时钟信号, 并且, 依据所述中断时钟信号、 所述第一电压检测信号、 所述第二电压 检测信号、 以及所述第三电压检测信号, 产生所述充电终止信号、 以及 电压减小信号和电压增大信号; 其中, 所述调节时钟信号为所述中断时 钟信号的反向信号; 当所述中断时钟信号由有效跳变为无效的时钟沿到 来时, 若所述第一电压检测信号有效, 则所述充电终止信号置为有效, 若所述第一电压检测信号无效、 所述第二电压检测信号有效, 则所述电 压减小信号置为有效, 若所述第三电压检测信号无效, 则所述电压增大 信号置为有效;
所述电压计数器用于依据所述调节时钟信号、 所述电压增大信号、 所述电压减小信号进行计数操作, 并将得到的电压计数结果输出至所述 电压调节模块、 以使所述电压调节模块依据所述电压计数结果进行调 节; 其中, 每当所述调节时钟信号由无效跳变为有效的时钟沿到来时, 若所述电压增大信号有效, 则执行一次将所述电压计数结果增加一个电 压计数步长的计数操作, 若所述电压减小信号有效, 则执行一次将所述 电压计数结果减少一个电压计数步长的计数操作。
6、 一种充电装置, 其特征在于, 所述充电装置包括如权利要求 1 至 5中任意一项所述的充电控制电路。
7、 一种充电控制方法, 其特征在于, 所述充电控制方法用于控制对 充电时产生的输出电压和输出电流的调节、 并触发充电终止, 所述充电 控制方法包括:
al、 对输入的第一电流基准进行调节, 并输出调节得到的第二电流 基准、 以控制对所述输出电压和所述输出电流的调节; 其中, 所述第二 电流基准的最小电流值小于所述第一电流基准、 最大电流值等于所述第 一电流基准;
b0、 周期性地触发充电的中断、 并控制所述 al、 以及产生充电终止 信号; 其中, 通过在中断期间内对所述电流调节模块的控制, 所述第二 电流基准被限制在所述最小电流值; 通过在被所述中断期间分隔的充电 期间内对所述电流调节模块的控制, 所述第二电流基准的所述限制被取 消; 当在中断期间结束时检测到所述输出电压低于外部输入的第一电压 基准的电压差幅小于预先设置的第一电压阈值时, 将所述充电终止信号 置为有效、 以触发所述充电终止。
8、 根据权利要求 7所述的充电控制方法, 其特征在于,
当在所述充电期间内检测到所述输出电流低于所述第二电流基准的 电流差幅小于第一电流阈值时, 若所述第二电流基准尚未达到所述最大 电流值, 则被取消所述限制的所述第二电流基准被所述 al调高;
当在所述充电期间内检测到所述电流差幅大于等于预先设置的第二 电流阈值、 且小于预先设置的第三电流阈值时, 若所述第二电流基准尚 未达到所述最小电流值, 则所述限制被取消的所述第二电流基准被所述 al调低;
当在所述充电期间内检测到所述电流差幅大于等于所述第三电流阈 值时, 若所述第二电流基准尚未达到所述最小电流值, 则所述限制被取 消的所述第二电流基准被所述 al复位至所述最小电流值;
其中, 所述第一电流阈值小于所述第二电流阈值、 所述第二电流阈 值小于所述第三电流阈值。
9、根据权利要求 7所述的充电控制方法, 其特征在于, 所述充电控 制方法进一步包括: a2、 对所述第一电压基准进行调节, 并输出调节得 到的第二电压基准、 以控制对所述输出电压和所述输出电流的调节; 其 中, 所述第二电压基准的最大电压值大于所述第一电压基准、 最小电压 值等于所述第一电压基准;
以及, 所述 b0进一步控制所述 a2, 其中: 当在中断期间结束时检测到所述电压差幅大于等于所述第一电压阈 值、 且小于第二电压阈值时, 若所述第二电压基准尚未达到所述最小电 压值, 则所述第二电压基准被所述 a2调低;
当在中断期间结束时检测到所述电压差幅大于第三电压阈值时, 若 所述第二电压基准尚未达到所述最大电压值, 则所述第二电压基准被所 述 a2调高;
其中, 所述第一电压阈值小于所述第二电压阈值、 所述第二电压阈 值小于所述第三电压阈值。
10、 根据权利要求 9所述的充电控制方法, 其特征在于, 当在所述充电期间内检测到所述输出电流低于所述第二电流基准的 电流差幅小于第一电流阈值时, 若所述第二电流基准尚未达到所述最大 电流值, 则被取消所述限制的所述第二电流基准被所述 al调高;
当在所述充电期间内检测到所述电流差幅大于等于预先设置的第二 电流阈值、 且小于预先设置的第三电流阈值时, 若所述第二电流基准尚 未达到所述最小电流值, 则所述限制被取消的所述第二电流基准被所述 al调低;
当在所述充电期间内检测到所述电流差幅大于等于所述第三电流阈 值时, 若所述第二电流基准尚未达到所述最小电流值, 则所述限制被取 消的所述第二电流基准被所述 al复位至所述最小电流值;
其中, 所述第一电流阈值小于所述第二电流阈值、 所述第二电流阈 值小于所述第三电流阈值。
11、 根据权利要求 10所述的充电控制方法, 其特征在于, 所述 b0 中周期性地触发充电的中断具体包括: 对基准时钟信号计 数, 并依据计数结果产生中断时钟信号; 其中, 所述中断时钟信号有效 时表示所述中断期间、 无效时表示所述充电期间; 所述 b0中对所述电流差幅的检测以及对所述 al的控制具体包括: bl l、依据所述电流差幅的大小产生第一电流检测信号、 第二电流检 测信号、 以及第三电流检测信号; 其中, 所述第一电流检测信号在所述 电流差幅小于所述第一电流阈值时有效, 所述第二电流检测信号在所述 电流差幅小于所述第二电流阈值时有效, 所述第三电流检测信号在所述 电流差幅小于所述第三电流阈值时有效;
bl2、依据所述中断时钟信号、 所述第一电流检测信号、 所述第二电 流检测信号、 所述第三电流检测信号, 产生电流增大信号、 电流减小信 号、 以及电流复位信号; 其中, 当所述中断时钟信号无效时, 若所述第 一电流检测信号有效, 则所述电流增大信号置为有效, 若所述第二电流 检测信号无效、 所述第三电流检测信号有效, 则所述电流减小信号置为 有效, 若所述第三电流检测信号无效, 则所述电流复位信号置为有效; 当所述中断时钟信号有效时, 所述电流复位信号置为有效;
bl3、依据所述基准时钟信号、 所述电流增大信号、 所述电流减小信 号、 以及所述电流复位信号进行计数操作, 并将得到的电流计数结果提 供给所述 al、 以使所述 al依据所述电流计数结果进行调节; 其中, 每 当所述基准时钟信号由无效跳变为有效的时钟沿到来时, 若所述电流增 大信号有效, 则执行一次将所述电流计数结果增加一个电流计数步长的 计数操作, 若所述电流减小信号有效, 则执行一次将所述电流计数结果 减少一个电流计数步长的计数操作, 若所述电流复位信号有效, 则执行 一次将所述电流计数结果复位至最小电流计数值的计数操作, 所述最小 电流计数值对应所述最小电流值;
所述 b0中对所述电压差幅的检测、产生所述充电终止信号、 以及对 所述 a2的控制具体包括:
b21、检测所述电压差幅的大小, 并依据所述电压差幅的大小产生第 一电压检测信号、 第二电压检测信号、 以及第三电压检测信号; 其中, 所述第一电压检测信号在所述电压差幅小于所述第一电压阈值时有效, 所述第二电压检测信号在所述电压差幅小于所述第二电压阈值时有效, 所述第三电压检测信号在所述电流差幅小于所述第三电压阈值时有效; b22、依据所述中断时钟信号产生调节时钟信号, 并且, 依据所述中 断时钟信号、 所述第一电压检测信号、 所述第二电压检测信号、 以及所 述第三电压检测信号, 产生所述充电终止信号、 以及电压减小信号和电 压增大信号;其中,所述调节时钟信号为所述中断时钟信号的反向信号; 当所述中断时钟信号由有效跳变为无效的时钟沿到来时, 若所述第一电 压检测信号有效, 则所述充电终止信号置为有效, 若所述第一电压检测 信号无效、所述第二电压检测信号有效,则所述电压减小信号置为有效, 若所述第三电压检测信号无效, 则所述电压增大信号置为有效;
b23、依据所述调节时钟信号、 所述电压增大信号、 所述电压减小信 号进行计数操作,并将得到的电压计数结果提供给所述 a2、 以使所述 a2 依据所述电压计数结果进行调节; 其中, 每当所述调节时钟信号由无效 跳变为有效的时钟沿到来时, 若所述电压增大信号有效, 则执行一次将 所述电压计数结果增加一个电压计数步长的计数操作, 若所述电压减小 信号有效, 则执行一次将所述电压计数结果减少一个电压计数步长的计 数操作。
12、 一种充电方法, 其特征在于, 所述充电方法包括如权利要求 7 至 11中任意一项所述的控制方法中的各步骤。
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CN103683357B (zh) 2015-08-05
EP2899838B1 (en) 2018-04-11
US9455590B2 (en) 2016-09-27

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