WO2014029413A1

WO2014029413A1 - Device for frequency tripling

Info

Publication number: WO2014029413A1
Application number: PCT/EP2012/066171
Authority: WO
Inventors: Mingquan Bao
Original assignee: Telefonaktiebolaget L M Ericsson (Publ)
Priority date: 2012-08-20
Filing date: 2012-08-20
Publication date: 2014-02-27
Also published as: EP2885871A1

Abstract

A frequency tripler (100) comprises an input port (150) and an output port (155), and a first (140) and a second (145) transistor of the bipolar junction kind. The base of the first transistor (140) is connected to the input port (150) and the collector of the second transistor is connected to the output port (155). The emitters of the first (140) and second (145) transistors are grounded, and the collector of the first transistor (140) is connected to the base of the second transistor (145).

Description

DEVICE FOR FREQUENCY TRIPLING

TECHNICAL FIELD

The present invention discloses an improved frequency tripler.

BACKGROUND

Frequency multipliers are often used in local oscillators, LOs, for example in microwave or millimeter-wave applications. A high frequency LO signal is usually obtained by up-converting a low frequency LO signal by means of a frequency multiplier. For instance, a frequency multiplier in the form of a frequency tripler can be used to generate an output signal with a frequency which is three times that of an input signal to the frequency tripler. Thus, frequency multipliers, in this case frequency triplers, are important in the design of high frequency transceivers, for instance on the E-band. One of the most important parameters when determining a frequency tripler's performance is the conversion gain, defined as the ratio between the output power at a frequency of 3f₀, and the input power at a frequency of f₀.

A frequency tripler usually generates its output signal by means of a generating a higher order (i.e. first, second, third etc.) harmonic of an input signal by means of utilizing nonlinear characteristics of components such as transistors and/or anti-parallel diodes. The third order harmonic is then extracted by means of, for example, either a high pass filter or a band pass filter. Alternatively, a frequency tripler can comprise a mixer and a frequency doubler, so that a signal at the desired frequency 3f₀ is obtained by mixing an input signal at frequency f₀ with a signal at frequency 2f₀, as obtained from the frequency doubler. In other versions of frequency triplers, a nonlinear combiner which mixes two differential inputs is used to generate a signal with a frequency of the third order harmonic, i.e. 3f₀. A drawback of the frequency triplers mentioned above is that they usually exhibit a negative conversion gain, thus necessitating one or more cascaded power amplifier, in order to boost their output power. In the case of a multiplier comprising a mixer and a frequency doubler, there will be a good conversion gain; however, such a tripler consumes a great deal of DC power, and usually requires a high DC supply voltage.

SUMMARY

It is an object of the invention to obtain a frequency tripler which obviates at least some of the drawbacks of previously known frequency triplers.

This object is achieved by means of a frequency tripler which has an input port and an output port. The frequency tripler comprises a first and a second transistor of the bipolar junction kind. In the frequency tripler, the base of the first transistor is connected to the input port, and the collector of the second transistor is connected to the output port.

In addition, in the frequency tripler, the emitters of the first and second transistors are grounded, and the collector of the first transistor is connected to the base of the second transistor.

In embodiments of the frequency tripler, the base of the first transistor is connected to the input port via a DC-decoupler.

In embodiments of the frequency tripler, the collector of the second transistor is connected to the output port via a DC-decoupler. In embodiments of the frequency tripler, the collector of the first transistor is connected to the base of the second transistor via a DC-decoupler. In embodiments of the frequency tripler, at least one of the DC-decouplers comprises a capacitor.

In embodiments of the frequency tripler, at least one of the transistors' collector is also connected to a supply voltage. In embodiments of the frequency tripler, at least one of the supply voltages is connected via a DC pass component.

The invention also discloses a frequency tripler device which comprises a first and a second frequency tripler of any of the embodiments described above. The frequency tripler device additionally comprises a first and a second balun, where each of the baluns has a balanced side with a first and a second port, and an unbalanced side with one port. The first and second ports on the balanced side of the first balun, respectively, are connected to the input ports of the first and second frequency tripler, and the output ports of the first and second frequency triplers are connected, respectively, to the first and second ports of the balanced side of the second balun.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in more detail in the following, with reference to the appended drawings, in which

Fig 1 shows a first embodiment of a frequency tripler, and

Fig 2 shows the output spectrum of a first stage in the frequency tripler of fig

1 , and

Fig 3 shows the output spectrum of the frequency tripler of fig 1 , and Fig 4 shows the frequency tripler of fig 1 with an output filter, and

Figs 5 and 6 show the influence of base voltages on the frequency tripler of fig 1 ,

Fig 7 shows a second embodiment of a frequency tripler, and

Fig 8 shows the output spectrum of the frequency tripler of fig 7.

DETAILED DESCRIPTION

Embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Like numbers in the drawings refer to like elements throughout. The terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the invention.

Fig 1 shows an embodiment of a frequency tripler 100. As shown, the frequency tripler 100 comprises a first 140 and a second 145 transistor, in this case transistors of the bipolar junction type. Naturally, Field Effect Transistors, FET transistors, can also be used.

The two transistors 140, 145, are connected in a two-stage configuration, in this case a so called common-emitter configuration, by virtue of the fact that both of the emitters of the transistors are grounded. The first transistor 140 is comprised in the first stage of the two-stage configuration and the second transistor 145 is comprised in the second stage of the two-stage configuration. The frequency tripler 100 comprises an input port 150, which is connected to the base of the first transistor 140, suitably via a capacitor 141 in order to achieve a DC-decoupling effect between the input port 150 and the first transistor 140.

As can be seen in fig 1 , the frequency tripler 100 also comprises an output port 155 to which the collector of the second transistor 145 is connected, suitably via a capacitor 130 which acts as a DC-decoupler. This can also be seen as letting the collector of the second transistor act as output port for the entire frequency tripler 100.

Thus, the frequency tripler 100 is arranged to receive input signals at a frequency f₀ at the input port 150, and to output the third order harmonic 3f₀ of that signal at the output port 155. Naturally, signals at other frequencies will also be comprised in the output signal, but the signal at the desired frequency 3f₀ can be filtered out by means of a filter, e.g. either a band pass filter or high pass filter, although such a filter is not show in fig 1. The filter is used to suppress the fundamental and the second harmonic. The connections in the frequency tripler 100 will be described in more detail later in this text, but a general description of some principles of the frequency tripler 100 will be given first:

Due to the two-stage configuration of the two transistors 140, 145, signals generated by the first transistor 140 are fed to the second stage of the frequency tripler 100, i.e. the second transistor 145. The signals generated by the first transistor 140 include signals at the fundamental frequency f₀, as well as harmonics of the frequency fo, i.e. 2f₀, 3fo, 4f₀....nfo, where 3fo is the desired tripled frequency. The first transistor 140 has as one of its functions to serve as a generator of harmonics in the frequency tripler 100.

As can be seen in fig 1 , signals generated by the first transistor 140 are fed to the second stage, i.e. the second transistor 145, which has a number of functions, as follows:

1 ) The second transistor 145 acts a trans-conductance mixer in the frequency tripler 100, thus generating signals at the sum and difference frequencies of signals (including the signal at the fundamental frequency f₀) which are fed to its base from the first transistor 140. The third order harmonic 3f₀ is generated 3f₀ by the fundamental, f₀, and the second harmonic 2f₀,(3fo=fo+2fo) being mixed, as well as by mixing of the fundamental, f₀, and the fourth harmonic 4f₀, (3fo=4f₀-fo).

2) The second transistor 145 also acts as an amplifier, so that it amplifies signals, among them signals at the third order harmonic 3fo, which are fed to its base,

3) In addition, the second transistor 145 also acts as a multiplier, so that the fundamental signal f₀ which is fed to its base is multiplied by 3 times, thereby, as will be explained below, obtaining a third order harmonic 3fofrom the input fundamental f₀ at the base.

Components at the frequency 3f₀, i.e. the third harmonic, which are obtained by means of these various mechanisms are inherently added together in the second transistor 145. Returning now to the connections and some additional components of the frequency tripler 100, we see that at least one, and preferably both, of the collectors of the transistors 140, 145, is connected to a respective supply voltage V_Ci, V_C2, via respective inductors 1 15, 125. The inductors 1 15 and 125 have the function of providing a DC pass filter to the collectors, and also, together with respective capacitors 135, 130, one of each also preferably being connected to the collector of each transistor 140, 145, provide the function of a high pass filter for each of the transistors. In addition, the combination of an inductor 1 15/125 and a capacitor 135/130 at the collector of a transistor serves as an impedance matching between the two transistors, as well as between the transistor 145 and a 50 Ω output.

Also, a supply voltage Vci can be supplied to the first transistor 140 via the inductor 1 15, and a supply voltage V_C2 can be supplied to the second transistor 145 via the inductor 125. In addition, a bias voltage V_M can be supplied to the first transistor 140 via a resistor 1 10, and a bias voltage V_b2 can be supplied to the second transistor 145 via a resistor 120. Suitably, the bias voltages V_M and V_b2 are set so that the first transistor 140 (i.e. the transistor at the first stage of the frequency tripler 100) operates at the so called class AB region, and the second transistor 145 (i.e. the transistor at the second stage of the frequency tripler 100) operates at the so called class C region. In order to illustrate the effects of the first stage and the second stage, reference will be made to figs 2 and 3: fig 2 shows the output spectrum at the first stage, i.e. at the collector of the first transistor 140, when an input signal at 50 GHz and a signal power level of -2dBm is applied to the input port 150 of the frequency tripler 100. In this example, V_Ci is used, and set at 2V, and V_M is also used and set at 0.83 V. Fig 2 shows that the power level of the fundamental, f₀, is 8.3 dBm and that of the second harmonic 2f₀ is -6.2 dBm, while that of the third order harmonic, 3f₀, is -7.5 dBm.

Fig 3, on the other hand, shows the output spectrum of the entire frequency tripler 100, when the same parameters are used as were used to obtain the output spectrum shown in fig 2. As can be seen in fig 3, the level of the third order harmonic, 3f₀, is 1 .45dBm, as opposed to the -7.5 dBm of fig 2. This third order harmonic can then be filtered out by means of a band-pass filter after the frequency tripler 100. Fig 4 shows the frequency tripler 100 of fig 1 with a band-pass filter 305 added at the output port 155. In this case, the levels of the fundamental and the second harmonic become -58 dBm and -21 dBm, respectively.

Regarding the influence of the base voltages V_M and V_b2, this will be illustrated by means of figs 5 and 6: the base voltage VM of the first transistor 140 has an influence on the amplitudes of the harmonics, and consequently, on the tripler's 100 conversion gain.

In fig 5, we see what happens with the conversion gain of the frequency tripler 100 when, with a fixed input power of -2.0 dBm, the base voltage V_M is varied and the base voltage V_b2 of the second transistor is fixed at 0.4V. It can be seen that the conversion gain of the frequency tripler has a maximum as the base bias of the first transistor is around 0.83 V, corresponding to the transistor 140 operating in the class AB region.

Fig 6 shows what happens to the conversion gain of the frequency tripler 100 if the input power and the base voltage of the first transistor 140 are fixed at -2dBm and 0.83 V respectively, and the base voltage Vb2 of the second transistor 145 is "swept": it can be seen that the tripler's conversion gain peaks as the base voltage V_b2 is equal to 0.4V. In this case, this means that the transistor 145 at the second stage operates in the class C region.

Turning now to a theoretical explanation of the function of the transistor 145 of the second stage of the frequency tripler 100, in order to understand the functions of the transistor 145 of the second-stage, the Ebers-Moll model for a HBT (Heterodyne Bipolar junction Transistor) device will be used to analyze the mechanism for generating 3fo component. The Ebers-Moll model describes the nonlinear relationship between the collector current, i_c(t) and the base-emitter voltage, v_be(t), as follows:

where V_T=kT/q is the thermal voltage and /_s is a constant used to describe the transfer characteristic of the transistor in the forward-active region. The DC current at the collector is given by/_c = /_s ex The transistor's base-emitter

voltage has a DC bias, v_bias (t) , and produces different harmonics. Ignoring higher- order harmonics (above fourth-order), we obtain:

= ^Vbia_S + A cos(oy)+ A₂ cos(2oy)+ A₃ cos(3oy)+ ... (2) where ω₀=2πί₀ is the angle frequency, A (/=1 ,2,3) are the amplitudes of the input harmonics.

Inserting (2) into (1 ) yields: = ^_c exp - COS¹ (ay) •exp - cos (i 2 y) •exp cos(3ay) - , (3) The exponential functions at the right side of (3) can be expanded: h\— + 2V / 4- \ cos (no) ) cos (2ηω₀ί)

(4)

where n=0, 1,2, ..., is a modified Bessel function which is

larger than zero as x>0. Furthermore, l₀(x) is larger than one, and is equal to one, when x is equal to zero.

Ignoring the terms l_n(x) (n>4) for a given x since the modified Bessel function decreases as n increases, from (4), we obtain the terms associated with the third order harmonic, i.e. the frequency3 >₀:

The first and the second terms on the right-hand side of (5) above represent the mixing components (ω₀+2ω₀) and (4ω₀-ω₀), respectively. However, the mixing component (ωο+2ω₀) is larger than that of (4ω₀-ω₀), since

The third term denotes the amplification of the third harmonic existing at the transistor's base, since /, cos(3oy) originates from A₃ cos(3oy) ; while and /, are constants. The last term on the right-hand side of (5)

above represents the three-time multiplication of the fundamental f₀ at the

base of the transistor, since originates from cos(oy) .

Summing all of those contributions, a high conversion gain is obtained. The 3f₀ (also denoted 3ω₀ above) component containing in the collector current is transferred into output power via the inductive load 125.

The desired harmonic, 3f₀, is an "odd-order" harmonic. In order to cancel "even-order" harmonics, which are thus undesired, the frequency tripler 100 from fig 1 can also be used in a balanced topology, as in the embodiment 400 which is shown in fig 7. In this embodiment, there is comprised a first 100 and a second 100' frequency tripler. The first 100 and the second 100' frequency tripler are connected to each other by means of the emitters of the transistors in the first stage of each tripler being connected to each other and to ground, and the emitters of the transistors in the second stage of each tripler are also connected to each other.

The frequency tripler device 400 additionally comprises a first 105 and a second 106 balun. The first balun 105 has a balanced side with a first port 107 and a second port 108, and an unbalanced side with one port 109. The second balun 106 has a balanced side with a first port 1 1 1 and a second port 1 12, and an unbalanced side with one port 1 13.

The first 107 port on the balanced side of the first balun 105 is connected to the input port of the first frequency tripler 100, and the second 108 port on the balanced side of the first balun 105 is connected to the input port of the second frequency tripler 100'. The output port of the first frequency tripler 100 is connected to the port 1 1 1 of the balanced side of the second balun 106, and the output port of the second frequency tripler 100' is connected to the port 1 12 of the balanced side of the second balun 106.

In this manner, the port 109 on the unbalanced side of the first balun 105 becomes the input port for the entire frequency tripler 200, and the port 1 13 on the unbalanced side of the second balun becomes the output port for the entire frequency tripler 400.

The frequency tripler device 400 can also be seen as adding a balun at the bases of each transistor in the first stage of each frequency tripler 100, 100', the balun being designed to operate at the frequency of the fundamental f₀. This balun makes the harmonics at the outputs of the transistors in the first stage have phase difference 180° for odd-harmonics (1 , 3, 5,...) and 0° for even-harmonics (2, 4, 6...).

Another balun is used at the outputs of each transistor at the second stage of each frequency tripler 100 100', which operates at frequency of 2f₀ or higher frequencies. After this balun, the in-phase 2f₀ signal is suppressed at the unbalanced side of the balun. If the balun's operating frequency covers 2f₀ and 4f₀, the 4f₀ component at the output is reduced as well.

Suitably, a high pass filter 1 15 is cascaded after the second balun 106, in order to to filter out the fundament component. Consequently, the output of the frequency tripler device 200 will be dominated by the frequency component at 3f_0, as shown in fig 8, which shows the output spectrum of the frequency tripler device 200, when the input signal's power is -2 dBm at a frequency of 50 GHz. As can be seen in fig 8, the third harmonic 3f₀ dominates, and has a level of 1 .448 dBm. In other embodiments, the bipolar junction transistors shown in the drawings and described above can be replaced by Field Effect Transistors, FETs. In such embodiments, the following substitutions should be made with regard to the ports of the transistors:

Bipolar junction transistor, port FET, port

Collector Drain

Emitter Source

Base Gate

In the drawings and specification, there have been disclosed exemplary embodiments of the invention. However, many variations and modifications can be made to these embodiments without substantially departing from the principles of the present invention. Accordingly, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation.

The invention is not limited to the examples of embodiments described above and shown in the drawings, but may be freely varied within the scope of the appended claims.

Claims

1. A frequency tripler (100) with an input port (150, 109) and an output port (155, 1 13), the frequency tripler (100) comprising a first (140) and a second (145) transistor of the bipolar junction kind, in which frequency tripler (100) the base of the first transistor (140) is connected to the input port (150, 109) and the collector of the second transistor is connected to the output port (155, 1 13), and in which frequency tripler (100) the emitters of the first (140) and second (145) transistors are grounded, and the collector of the first transistor (140) is connected to the base of the second transistor (145).

2. The frequency tripler (100) of claim 1 , in which the base of the first transistor (140) is connected to the input port (150) via a DC-decoupler (141 ).

3. The frequency tripler (100) of claim 1 or 2, in which the collector of the second transistor (145) is connected to the output port (155) via a DC- decoupler (130).

4. The frequency tripler (100) of any of claims 1 -3, in which the collector of the first transistor (140) is connected to the base of the second transistor (145) via a DC-decoupler (135).

5. The frequency tripler (100) of any of claims 2-4, in which at least one of said DC-decouplers comprises a capacitor (141 , 135, 130).

6. The frequency tripler (100) of any of claims 1 -5, in which at least one of the transistors' collector is also connected to a supply voltage (V_Ci , V_C2).

7. The frequency tripler (100) of any of claims 1 -5, in which at least one of said supply voltage (V_Ci, V_C2) are connected via a DC pass component (1 15, 125).

8. A frequency tripler device (400) comprising a first (100) and a second (100') frequency tripler of any of claims 1 -7, the frequency tripler device (400) additionally comprising a first (105) and a second (106) balun, where each of the baluns (105, 106) has a balanced side with a first (107, 1 1 1 ) and a second port (108, 1 12) and an unbalanced side with one port (109, 1 13), with the first (107) and second (108) ports on the balanced side of the first balun (105) respectively being connected to the input ports of the first (100) and second (100') frequency tripler, and the output ports of the first and second frequency triplers being connected, respectively, to the first (1 1 1 ) and second (1 12) ports of the balanced side of the second balun (106).

9. A frequency tripler (100) or a frequency tripler device (400) of any of the previous claims, in which the bipolar junction transistors are replaced by Field Effect Transistors, with the ports of the bipolar junction transistors being substituted by ports of the Field Effect Transistors as follows:

Bipolar junction transistor, port FET, port

Collector Drain

Emitter Source

Base Gate