WO2014029319A1 - Procédé et dispositif d'estimation de décalage de fréquence de nœud de réseau d'horloge sur paquet - Google Patents

Procédé et dispositif d'estimation de décalage de fréquence de nœud de réseau d'horloge sur paquet Download PDF

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Publication number
WO2014029319A1
WO2014029319A1 PCT/CN2013/081847 CN2013081847W WO2014029319A1 WO 2014029319 A1 WO2014029319 A1 WO 2014029319A1 CN 2013081847 W CN2013081847 W CN 2013081847W WO 2014029319 A1 WO2014029319 A1 WO 2014029319A1
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node
detected
frequency offset
delay information
packet
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PCT/CN2013/081847
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English (en)
Chinese (zh)
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何力
夏靓
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中兴通讯股份有限公司
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Publication of WO2014029319A1 publication Critical patent/WO2014029319A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0664—Clock or time synchronisation among packet nodes using timestamps unidirectional timestamps

Definitions

  • the present invention relates to the field of communications, and in particular, to a frequency offset estimation method and apparatus for a packet clock network node.
  • a packet device replaces a process of a Synchronous Digital Hierarchy (SDH) network
  • the SDH clock network is replaced step by step based on a synchronous Ethernet clock network.
  • the metropolitan area packet network provides an E1 clock for the base station.
  • system retiming differential
  • adaptive clock mode is greatly affected by the delay of the network, and there is uncertainty, and the system is retimed. Differential clocks are becoming more widely available.
  • the accuracy of system retiming and differential clocking technology depends on the synchronization quality and stability of the network based clock. Due to the technical requirements of ground transit time, the 1588 time synchronization technology based on synchronous Ethernet clock network technology is gradually developed. The accuracy of the time network also depends on the synchronization quality and stability of the network base clock. Therefore, both clock and time technology, high quality and stable clock network are prerequisites for high quality networks.
  • the management and maintenance of the clock synchronization network mainly follows the International Telecommunication Union Telecommunication Standardization Organization (ITU-T) G.781/G.8264 standard, and is maintained by Synchronization Status Message (SSM) information, but these maintenance It is built on the protocol function level.
  • ITU-T International Telecommunication Union Telecommunication Standardization Organization
  • SSM Synchronization Status Message
  • the main method is to switch the known clock node faults and re-select the appropriate clock path.
  • the source has a frequency deviation.
  • some techniques at present such as comparing the frequency offset of the clock by comparing the neighboring clocks of adjacent nodes, in complex packet networks, because the paths are intricate, unless the adjacent nodes have reliable physical reference sources, the phase is opposite. It is also difficult to obtain accurate values for the relative estimation of the neighbor nodes, and the above scheme is only for the frequency offset estimation of the adjacent nodes. In view of the above problems in the related art, there is currently no effective solution.
  • the present invention provides a packet clock network for a technical problem in which the frequency offset estimation scheme for non-adjacent nodes and the existing frequency offset estimation for adjacent nodes are not accurate.
  • the method and device for estimating the frequency offset of the node to solve at least the above problem.
  • a frequency offset estimation method for a packet clock network node including: determining a to-be-detected node and a clock reference node in a packet clock network; and acquiring a detection packet received by the to-be-detected node The sending time and the receiving time, wherein the detecting message is sent by the clock reference node to the to-be-detected node; and obtaining the delay information of the detecting packet according to the obtained sending time and the receiving time And performing frequency offset estimation on the to-be-detected node according to the obtained delay information.
  • Acquiring the sending time and the receiving time of the detecting packet received by the node to be detected including: acquiring a sending time and a receiving time of each detecting packet received by the to-be-detected node in a specified time window; Obtaining the delay information of the detection packet, the time and the receiving time, the method includes: acquiring delay information of each detection packet according to the obtained sending time and the receiving time in the specified time window. And performing the frequency offset estimation on the to-be-detected node according to the obtained delay information, including: selecting a specified number of delay information according to a predetermined policy from the obtained delay information of each detection packet; A number of delay information is used to estimate the frequency offset.
  • the method further includes: determining, in the specified time window, that the detection packet received by the to-be-detected node has no packet delay variable (PDV) Jump or frequency jump.
  • PDV packet delay variable
  • the node to be detected and the clock reference node are adjacent nodes.
  • the frequency offset estimation is performed on the to-be-detected node according to the obtained delay information by a linear fitting algorithm. Performing frequency offset estimation on the to-be-detected node according to the obtained delay information by using the following formula: r ⁇ « ⁇ >', " ⁇ -. ⁇ ;;; n 1
  • ⁇ denotes the frequency offset value, which is a constant, indicating the clock phase offset of the clock reference node and the node to be detected, X means time, indicating delay, n is A positive integer.
  • performing the frequency offset estimation on the to-be-detected node according to the obtained delay information including: obtaining an estimated value after performing frequency offset estimation in each time window; The estimated value is averaged to obtain the final frequency offset value.
  • a frequency offset estimating apparatus for a packet clock network node including: a determining module, configured to determine a to-be-detected node and a clock reference node in a packet clock network; a first acquiring module, setting And acquiring, by the clock reference node, the sending time and the receiving time of the detecting packet, where the detecting packet is sent by the clock reference node to the to-be-detected node; The sending time and the receiving time are used to obtain the delay information of the detecting message.
  • the estimating module is configured to perform frequency offset estimation on the to-be-detected node according to the obtained delay information.
  • the first acquiring module is further configured to: acquire a sending time and a receiving time of each detection packet received by the to-be-detected node in a specified time window; and the second acquiring module is further configured to: according to the obtained specified The sending time and the receiving time in the time window acquire delay information of each detecting message.
  • the estimating module includes: a selecting unit, configured to select a specified number of delay information according to a predetermined policy from the acquired delay information of each detection message; and the estimating unit is configured to set the specified number of delays according to the selected The information is estimated by frequency offset.
  • the node to be detected and the clock reference node are non-adjacent nodes.
  • the determining module is further configured to determine that the detection message received by the to-be-detected node within the specified time window has no packet delay variable PDV hopping or frequency hopping.
  • the device further includes: a de-jittering module, configured to perform de-jittering processing on the detection packet, in the embodiment of the invention, obtaining delay information according to the sending time and the receiving time of the detection packet received by the acquired node to be detected And the technical solution for estimating the frequency offset based on the obtained delay information, and solving the related art, the frequency offset estimation scheme for the non-adjacent nodes is not effectively valid, and the existing frequency offset estimation for the adjacent nodes is not accurate.
  • FIG. 1 is a flowchart of a method for estimating a frequency offset of a packet clock network node according to Embodiment 1 of the present invention
  • FIG. 2 is a block diagram showing a structure of a frequency offset estimating apparatus for a packet clock network node according to Embodiment 1 of the present invention
  • 3 is a block diagram showing another structure of a frequency offset estimating apparatus for a packet clock network node according to Embodiment 1 of the present invention
  • FIG. 4 is a flow chart showing a frequency offset estimating method according to Embodiment 2 of the present invention
  • FIG. 6 is a schematic diagram of a packet delay according to Embodiment 3 of the present invention
  • FIG. 7 is a schematic diagram of a packet delay according to Embodiment 3 of the present invention
  • FIG. 7 is a schematic diagram of a packet delay according to Embodiment 3 of the present invention. Schematic diagram of the node architecture of the frequency offset estimation scheme. BEST MODE FOR CARRYING OUT THE INVENTION
  • the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. Considering the related art, there is no technical solution to the frequency offset estimation scheme for non-adjacent nodes, and the existing frequency offset estimation for adjacent nodes is inaccurate. The following embodiments are now provided to solve the above problems. The details are as follows: Embodiment 1 FIG.
  • Step S102 determining a to-be-detected node and a clock reference node in a packet clock network
  • Step S104 acquiring a sending time and a receiving time of the detection packet received by the to-be-detected node, where The packet is sent by the clock reference node to the node to be detected
  • Step S106 Acquire delay information of the detection packet according to the obtained transmission time and the reception time.
  • Step S108 Perform frequency offset estimation on the node to be detected according to the acquired delay information.
  • the detection of frequency offset can be achieved through the above processing steps, especially for the end-to-end detection mode, since it can be determined according to
  • the delay time information is obtained by the sending time and the receiving time of the detecting packet received by the node to be detected, and the frequency offset is estimated according to the obtained delay information. Therefore, the frequency offset of the packet clock network node can be accurately learned, thereby obtaining the clock network.
  • the quality of frequency synchronization is obtained by the sending time and the receiving time of the detecting packet received by the node to be detected.
  • the foregoing method for performing frequency offset estimation may be performed by, for example, estimating according to delay information of a single detection packet, or performing frequency offset according to delay information of multiple (or all) detection packets received within a predetermined time period. Estimate. For the latter implementation, the following processing may be implemented: obtaining a sending time and a receiving time of each detection packet received by the to-be-detected node in the specified time window; and according to the sending time and time in the specified specified time window The receiving time obtains the delay information of each detection packet. Based on the frequency offset estimation method, the frequency offset estimation may be performed according to different application requirements.
  • the following process may be used: but not limited to the following processing: when selecting a specified number of time delay information of each detected message according to a predetermined policy Delay information; frequency offset estimation based on the selected number of delay information selected.
  • the foregoing predetermined policy may be configured to select the delay information according to the delay size or the other information of the detected packet.
  • the former may be implemented in the following manner: The delay information of each detected packet is in the order of delay from small to large. Select a specified number of delay information.
  • the above-mentioned node to be detected and the clock reference node may be non-adjacent nodes.
  • the frequency offset estimation may be performed on the node to be detected according to the acquired delay information by a linear fitting algorithm. At this point, it can be achieved by the following formula: «>, "-. ⁇ ;;;1
  • ⁇ denotes the frequency offset value, which is a constant, indicating the clock phase offset of the clock reference node and the node to be detected, X means time, indicating delay, n is A positive integer.
  • the foregoing specified time windows are multiple; and the estimated values after the frequency offset estimation in each time window are obtained; according to the obtained estimated values.
  • the mean operation gives the final frequency offset value.
  • a frequency offset estimation of a packet clock network node is also provided.
  • the device is used to implement the foregoing embodiment and a preferred embodiment.
  • the description has been omitted, and the following is related to the device.
  • the module is explained.
  • the term "module” may implement a combination of software and/or hardware of a predetermined function.
  • the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and conceivable.
  • 2 is a block diagram showing the structure of a frequency offset estimating apparatus of a packet clock network node according to Embodiment 1 of the present invention.
  • the apparatus includes a determining module 20 coupled to the first obtaining module 22, configured to determine a node to be detected and a clock reference node in the packet clock network, and a first obtaining module 22 connected to the second acquiring module.
  • the second obtaining module 24 is connected to the estimating module 26, and is configured to obtain the sending time and the receiving time of the detecting packet received by the node to be detected, where the detecting packet is sent by the clock reference node to the node to be detected; Acquiring the delay information of the detection packet according to the sending time and the receiving time acquired by the first obtaining module 22; the estimating module 26 is configured to perform frequency matching on the to-be-detected node according to the obtained delay information. Partial estimate.
  • the frequency offset can be detected by the functions implemented by the above processing module, especially for the end-to-end detection mode,
  • the delay information may be obtained according to the determined sending time and the receiving time of the detection packet received by the node to be detected, and the frequency offset estimation is performed according to the obtained delay information. Therefore, the frequency offset of the packet clock network node may be accurately obtained. Therefore, in a preferred embodiment of the present invention, the first acquisition module 22 is further configured to acquire a transmission time and a reception time of each detection packet received by the to-be-detected node in the specified time window; The second acquisition module 24.
  • the method further includes: acquiring delay information of each detection packet according to the obtained sending time and receiving time in the specified time window.
  • the foregoing estimating module 26 may further include: a selecting unit 260, connected to the estimating unit 262, configured to select a specified number of delays according to a predetermined policy from the obtained delay information of each detected message.
  • the information estimating unit 262 is configured to perform frequency offset estimation according to the specified number of delay information selected by the selecting unit 260.
  • the to-be-detected node and the clock reference node are non-adjacent nodes.
  • the determining module 20 may be further connected to the estimating module 26.
  • the determining module is further configured to determine that the detection packet received by the node to be detected within the specified time window has no PDV hopping or frequency. Jump.
  • the foregoing apparatus may further include: a debounce module 28, and a determining module.
  • Embodiment 2 This embodiment provides a method for testing the frequency deviation between the detection point and the reference point in an end-to-end or point-by-point test network under complex network conditions.
  • the detection method in this embodiment includes: Step S402: determining a to-be-detected point and a clock reference point in a clock network: a clock reference point may be a Primary Reference Clock (referred to as a PRC), or Any GM, Boundary Clock (BC), and Transparent Clock (TC) nodes in the clock network are generally nodes upstream of the clock link near the PRC.
  • PRC Primary Reference Clock
  • BC Boundary Clock
  • TC Transparent Clock
  • the to-be-detected point may be any GM, BC, and TC node in the clock network, and is generally located downstream of the clock reference point in the clock link.
  • Step S404, configuring the detection mode the detection mode is divided into end-to-end detection and point-by-point detection. .
  • the end-to-end mode is mainly for any two points (non-adjacent). In some cases, you need to monitor a specific clock synchronization path, or view the frequency deviation of two specific nodes (non-adjacent). You need to configure a monitoring path. It can be set by using Layer 2 unicast or Layer 3 unicast address.
  • ETH1588 is implemented by configuring a vlan switching domain in the middle of all nodes.
  • the detection of 1588 packets is implemented by configuring IP routes on all intermediate nodes. It is mainly used to detect the frequency deviation of the packet clock network, such as the packet clock synchronization network that traverses the third party. The point-by-point method is used to monitor the frequency deviation between two adjacent points. Only one hop is monitored. The monitoring path is not required. The Layer 2 multicast address is used. The device is used to support the Precise Time Protocol (Precise Time Protocol). PTP) A time synchronization network that functions as a boundary clock (BC) or transparent clock (TC) function. In comparison, the end-to-end approach is subject to longer links and many devices, so the frequency offset estimation is susceptible to network traffic and topology changes.
  • PTP Precise Time Protocol
  • Step S406 The reference point sends a time-stamped detection packet: the detection packet can be extended by using a PTP packet or a Network Time Protocol (NTP), or A new type of frequency offset detection operation and maintenance management (OAM) message is created.
  • NTP Network Time Protocol
  • OAM frequency offset detection operation and maintenance management
  • the method mainly includes a timestamp attribute, and records a precise time stamp T1 when the reference point sends the message.
  • Step S408 Processing the detection message by the to-be-detected point: The detection point to be sent by the detection point receives the detection message sent by the reference point, and uses the detection point clock Recording the timestamp T2 of the packet;
  • Step S410 Acquiring and filtering the timestamp information that meets the requirements: In the fixed time window, selecting timestamp information of the plurality of packets with the smallest delay, for estimating the subsequent frequency deviation
  • FIR filtering performing FIR low-pass filtering processing on the packet selected in the previous step to initially remove jitter;
  • Step S418, multi-window obtains the frequency estimation value and calculates the frequency offset: Obtain new timestamp data, select a new time window, repeat the above frequency estimation process, obtain multiple frequency estimation values, and take the average value, that is, obtain the frequency of the point to be detected.
  • Step S420 The reference point sends a time-stamped Sync message: the Sync message records the precise time stamp T1 when the reference point sends the message;
  • Step S422 the pair to be detected Processing of the Sync message: the Detect message acquires the Sync message sent by the reference point, and uses the detection point clock record to obtain the timestamp T2 of the message;
  • Step S424 Frequency estimation: Based on the number of messages in the fixed time window obtained above
  • the delay information is estimated by using a specific algorithm.
  • the basic principle of the algorithm is linear fitting, that is: if the clock network has no frequency offset, and the phase of the clock to be tested and the reference point are locked, the time drifts. The delay is approximately constant.
  • Step S426 multi-window obtains the frequency estimation value, and calculates the frequency offset: when acquiring a new time Extend the information, select a new time window, repeat the above frequency estimation process, obtain multiple frequency estimation values, take the average value, that is, obtain the to-be-detected The frequency of the point. It can be seen from the above process that the present embodiment provides a method for detecting the frequency deviation between the detection point and the reference point in the network by using the end-to-end detection or the point-by-point detection and the point-by-point detection under the condition of a complex network, thereby obtaining the clock network frequency.
  • the quality of the synchronization provides the necessary information for the protection switching of the next clock network, as well as maintenance and management.
  • the detection point may or may not be adjacent to the reference point.
  • the intermediate network node may be a PTP device or a non-PTP device, and may or may not support clock synchronization.
  • Embodiment 3 This embodiment provides an end-to-end detection mode.
  • the node architecture of the frequency offset estimation scheme for non-adjacent nodes in this embodiment is as shown in FIG. 5, and the details are as follows:
  • the solution in this embodiment can be applied to a clock network. Frequency offset detection of the clock of adjacent or non-adjacent synchronization nodes.
  • the packet device that supports the Ethernet technology Take the packet device that supports the Ethernet technology as an example.
  • the nodes to be tested can be slavel, slave2, and slave3.
  • the slavel is used as an example.
  • the reference node Configure the reference node to detect the packet.
  • the 1588 Layer 3 unicast sync packet is used as the detection packet.
  • the packet is counted by the reference node system clock, and the record transmission time is ⁇ .
  • the 1588 packet is forwarded through the intermediate network.
  • the network can support BC, TC, or not.
  • the detection point receives the detection packet, and records the timestamp when the 1588 packet arrives. The timestamp is counted by the system clock of the node to be detected, and the record arrival time is ⁇ .
  • the data packet After the 1588v2 packet passes through the packet network, due to the uncertainty of the forwarding delay, the data packet needs to be processed, and the clock frequency is estimated according to the processed data. Calculate the line delay according to the timestamp representing the clock information of the packet.
  • Indicates the selection point, () indicates the discard point, as shown in Fig. 6 area B indicates the selected point, and Fig. 6 area A indicates the discard point.
  • d - min At.
  • the primary selection packet is subjected to the FIR low-pass filtering module to initially remove the jitter. Assuming that the primary selection packet is, it indicates the delay after processing, and ⁇ is the filter coefficient, which is the filter order. y «i . yy y' H+l ( 4 ) In the example of Fig. 6, the area D represents the filtered data. 7. Analyze the PDV data in the selected time window to detect whether there is a PDV transition.
  • the frequency offset estimation is performed by least square fitting.
  • M group data im-) i - ⁇ h ⁇ denote the delay corresponding to the detection packet received at M time ⁇ , if the network Stable, the phase of the clock to be tested and the reference point are locked.
  • the delay ⁇ '' is approximately constant with time drift.
  • the time delay, delay ' The frequency has a linear relationship. This linear relationship can be used to estimate the model parameters ⁇ and / using the least squares method. As in the formula (5) ⁇ 3 ⁇ 4TM /3 ⁇ 4 + 3 ⁇ 4:3 ⁇ 4 (5) where
  • the frequency offset value which is a constant, indicating the frequency relationship (that is, the clock phase offset between the clock reference node and the node to be detected), X is the time, indicating the delay, and n is a positive integer.
  • the clock master and slaver have a frequency offset.
  • the delay data is initially processed, and D region data is obtained.
  • the D region data is fitted by least squares regression, and the line is fitted.
  • the slope of the slope is normalized to a fixed frequency offset. 9.
  • Obtain new timestamp data select a new time window, repeat the above frequency estimation process, obtain multiple frequency estimation values, and take the average value, that is, obtain the frequency of the point to be detected.
  • Embodiment 4 provides a point-by-point detection mode. As shown in FIG. 7, this is a time synchronization network composed entirely of BCs.
  • the frequency offset detection mechanism is hop-by-hop and real-time detection, and other specific processing mechanisms. Including delay calculation, linear fitting, frequency estimation, multi-window progressive calculation, etc. are the same as end-to-end. I will not repeat them here.
  • software is also provided for performing the technical solutions described in the above embodiments and preferred embodiments.
  • a storage medium is provided, the software being stored, including but not limited to: an optical disk, a floppy disk, a hard disk, a rewritable memory, and the like.
  • modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • the above are only the preferred embodiments of the present invention, and are not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

L'invention concerne un procédé et un dispositif d'estimation du décalage de fréquence d'un nœud de réseau d'horloge par paquet, le procédé consistant à : déterminer un noeud de référence d'horloge et un nœud à détecter dans un réseau d'horloge par paquet ; obtenir l'heure de transmission et l'heure de réception d'un paquet de détection reçu par le noeud à détecter, le paquet de détection étant transmis au nœud à détecter par le nœud de référence d'horloge ; obtenir les informations de retard temporel du paquet de détection conformément à l'heure de transmission et à l'heure de réception obtenues ; et estimer le décalage de fréquence du noeud à détecter conformément aux informations de retard temporel obtenues. Dans l'art considéré, il n'y a pas de solution efficace pour estimer le décalage de fréquence de noeuds qui ne sont pas voisins, et les estimations de décalage de fréquence existantes pour des nœuds voisins ne sont pas précises. La solution technique de la présente invention résout le problème technique, permet d'obtenir avec précision les informations de décalage de fréquence détectées de terminal à terminal ou détectées et estimées de nœud à nœud, et permet également d'obtenir la qualité de synchronisation de fréquence d'un réseau d'horloge pour fournir des informations nécessaires pour la commutation, la maintenance et la gestion de protection ultérieures du réseau d'horloge.
PCT/CN2013/081847 2012-08-22 2013-08-20 Procédé et dispositif d'estimation de décalage de fréquence de nœud de réseau d'horloge sur paquet WO2014029319A1 (fr)

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