WO2014029152A1

WO2014029152A1 - Semiconductor structure and manufacturing method thereof

Info

Publication number: WO2014029152A1
Application number: PCT/CN2012/081513
Authority: WO
Inventors: 梁擎擎; 王冠中; 朱慧珑; 钟汇才; 陈大鹏; 叶甜春
Original assignee: 中国科学院微电子研究所
Priority date: 2012-08-20
Filing date: 2012-09-17
Publication date: 2014-02-27
Also published as: CN103632922A

Abstract

The present invention provides a manufacturing method of a semiconductor structure. The method comprises: a) providing a substrate; b) etching the substrate to form an opening (201) having a bottom; c) forming a metal plug (202) filling the opening (201); and d) forming a grapheme layer (300) on the substrate, the grapheme layer (300) being in contact with an upper plane of the metal plug (202). Correspondingly, the present invention further provides a semiconductor structure formed according to the above manufacturing method. According to the method and the structure, grapheme is crystallized in a predetermined area, the particle size of grapheme crystals is increased, and by using a step of optimally depositing the grapheme, the uniformity of a grapheme material is improved, thereby improving working performance and stability of the grapheme material in the semiconductor structure.

Description

Semiconductor structure and manufacturing method thereof

[0001] The present application claims priority to Chinese Patent Application No. 201210298158, filed on Aug. 20, 2012, which is hereby incorporated by reference. In this application. Technical field

The present invention relates to the field of semiconductor fabrication, and more particularly to a semiconductor structure and a method of fabricating the same. Background technique

[0003] The connection between carbon atoms in graphene is very flexible, and when an external mechanical force is applied, the carbon atom faces are bent and deformed, so that the carbon atoms do not have to be rearranged to accommodate external forces, thereby maintaining structural stability. This stable lattice structure gives carbon atoms excellent electrical conductivity. When electrons in graphene move in orbit, they do not scatter due to lattice defects or introduction of foreign atoms. Since the interatomic force is very strong, at normal temperature, even if the surrounding carbon atoms collide, the electrons in the graphene are very little disturbed. Because of its extremely low resistivity and extremely fast speeds, graphene can be used to develop a new generation of electronic components or transistors that are thinner and more electrically conductive. Understandably, the addition of a graphene portion to the semiconductor device contributes to an improvement in the performance of the semiconductor device.

[0004] Researchers have been working to form better and more stable graphene components in semiconductor devices, thereby maximizing the performance of semiconductor devices. Summary of the invention

It is an object of the present invention to provide a semiconductor structure and a method of fabricating the same to form a stable high quality graphene component in a semiconductor device.

In order to achieve the above object, the present invention provides a method of fabricating a semiconductor structure, the method comprising:

(a) provide a grassroots layer;

(B) etching the base layer forming a bottom opening ^(201); (c) forming a metal plug (202) filling the opening (201);

(d) forming a graphene layer (300) in contact with the upper plane of the metal plug (202) on the base layer.

[0007] Accordingly, the present invention also provides a semiconductor structure, the semiconductor structure comprises a base layer, a metal plug ^{⁽²⁰²⁾} and the graphene layer (300), wherein:

[0008] The metal plug ^{⁽²⁰²⁾} embedded in said base layer;

A plane [0009] The graphene layer ⁽³⁰⁰⁾ formed over the base layer and a metal plug ^{^(202),} the graphene layer (300) and said metal plug (202) is in contact.

[0010] The semiconductor structure and the method of fabricating the same provided by the present invention increase the particle size of graphene crystals by forming graphene crystals in a predetermined region, and in combination with the step of optimizing deposition of graphene, contribute to the improvement of graphene material The uniformity, thus improving the workability and stability of the graphene material in the semiconductor structure. DRAWINGS

Other features, objects, and advantages of the present invention will become more apparent from the Detailed Description of Description

1 is a flow diagram of one embodiment of a method of fabricating a semiconductor structure in accordance with the present invention;

2 to FIG. 5 are cross-sectional structural views showing respective manufacturing stages of the semiconductor structure in the process of fabricating a semiconductor structure in accordance with the flow shown in FIG. 1 according to an embodiment of the present invention;

[0014] The same or similar reference numerals in the drawings represent the same or similar components. detailed description

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

The embodiments of the present invention are described in detail below, and the examples of the embodiments are illustrated in the drawings, wherein the same or similar reference numerals are used to refer to the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the drawings are intended to be illustrative of the invention and are not to be construed as limiting. [0017] The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and arrangements of the specific examples are described below. Of course, they are merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of clarity and clarity and does not in itself indicate the relationship between the various embodiments and/or arrangements discussed. Moreover, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials. Additionally, the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.

[0018] The semiconductor structure provided by the present invention is first summarized. Referring to FIG. 5, FIG. 5 is a cross-sectional structural view of the semiconductor structure including a substrate 100, a dielectric layer 200, a metal plug 202, and a graphene layer. 300 , where:

[0019] The dielectric layer 200 covers the upper plane of the substrate 100;

The metal plug 202 is embedded in the dielectric layer 200, and the lower plane of the metal plug 202 is in electrical contact with the upper surface of the substrate 100;

[0021] A graphene layer 300 is formed over the dielectric layer 200 that is in contact with the upper plane of the metal plug 202 and completely covers the upper plane of the metal plug 202.

[0022] Specifically, the substrate 100 includes a silicon substrate (eg, a wafer). The substrate 100 can include various doping configurations in accordance with design requirements known in the art, such as a P-type substrate or an N-type substrate. The substrate 100 in other embodiments may also include other basic semiconductors such as germanium. Alternatively, the substrate 100 may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide. Typically, the thickness of the substrate 100 can be, but is not limited to, on the order of a few hundred microns, for example, in the range of thicknesses from 400 μm to 800 μm. The dielectric layer 200 has a thickness between 50 nm and 200 nm, and the material thereof includes S i0 ₂ , carbon doped S i0 ₂ , BPSG, PSG, USG, S i ₃ N ₄ , a low-k material, or a combination thereof. The material of the metal plug 202 includes W, Al, Cu, T iAl, or a combination thereof.

In a preferred embodiment, the upper plane of the metal plug 202 is flush with the upper plane of the dielectric layer 200 (herein, the term "flush" means that the height difference between the two is within the tolerance of the process error. ). Typically, the area of the cross section of the metal plug 202 that is parallel to the upper plane of the substrate is 1-100 μηι ² . [0024] Optionally, a contact layer (not shown in FIG. 5) is formed between the lower plane of the metal plug 202 and the upper plane of the substrate 100, taking the substrate 100 as a silicon substrate as an example, the contact The layer can be nickel silicide, titanium silicide, cobalt silicide or copper silicide or other metal silicide.

[0025] The graphene layer 300 at least completely covers the upper plane of the metal plug 202, and in some embodiments, the graphene layer 300 also covers a portion of the upper plane of the dielectric layer 200. Due to the upper plane of the metal plug 202 and the graphene layer 300, and the metal plug 202 is a crystalline structure, the graphene layer 300 formed thereon has a larger crystal grain size, which helps to improve the uniformity of the graphene material. The mobility of the graphene layer 300 is increased. By controlling the cross-sectional shape of the metal plug 202, the range and performance of crystallization on the formed graphene layer 300 can be controlled to meet the requirements for fabricating different devices.

In addition to the embodiments described above, in the second embodiment (not shown), the semiconductor structure of the present invention may further include only the substrate 100, the metal plug 202, and the graphene layer 300, and There is no dielectric layer 200. The metal plug is formed directly in the substrate, and the upper plane of the metal plug is flush with the upper plane of the substrate, and the graphene layer is directly formed on the upper surface of the substrate and the metal plug. The graphene layer is partially in contact with the planar surface of the metal plug.

[0027] The semiconductor structure will be further described below in connection with the method of fabricating the semiconductor structure provided by the present invention.

Referring to FIG. 1, FIG. 1 is a flow chart of a specific embodiment of a method of fabricating a semiconductor structure in accordance with the present invention, the method comprising:

[0029] Step S1 00, providing a substrate, and forming a dielectric layer covering an upper plane of the substrate;

[0030] Step S200, etching the dielectric layer to form an opening having a specific shape penetrating the dielectric layer, the opening exposing a portion of an upper plane of the substrate;

[0031] Step S300, forming a metal plug filling the opening, the lower plane of the metal plug being in electrical contact with the exposed upper plane of the substrate;

[0032] Step S400, forming a graphene layer in contact with the upper plane of the metal plug on the dielectric layer, the graphene layer completely covering the upper plane of the metal plug.

[0033] Steps S 1 00 to S400 are described below with reference to FIGS. 2 through 5, which are semiconductor structures in the process of fabricating a semiconductor structure in accordance with the flow shown in FIG. 1 in accordance with an embodiment of the present invention. The cross-sectional views of the various stages of the present invention are to be considered as illustrative. First, step S100 is performed to provide the substrate 100 and form a dielectric layer 200 covering the upper plane of the substrate 100. Referring to FIG. 2, the substrate 100 includes a silicon substrate (eg, a wafer). The substrate 100 can include various doping configurations in accordance with design requirements known in the art, such as a P-type substrate or an N-type substrate. The substrate 100 in other embodiments may also include other basic semiconductors such as germanium. Alternatively, the substrate 100 may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide. Typically, the thickness of the substrate 100 can be, but is not limited to, about a few hundred meters, for example, can range from 400 μηι to 800 μηι. In the present embodiment, the substrate 100 is a silicon substrate. A dielectric layer 200 is formed on the substrate 100 by chemical vapor deposition (CVD) high-density plasma CVD ALD (atomic layer deposition), plasma enhanced atomic layer deposition (PEALD), Pulsed laser deposition (PLD) or other suitable method is formed on the substrate 100. Typically, the dielectric layer 200 has a thickness between 50 and 200 nm and its material comprises SiO ₂ , carbon doped SiO ₂ BPSG PSG USG Si ₃ N ₄ , low k materials, or combinations thereof.

Referring to FIG. 3, step S200 is performed to form a specific pattern of photoresist on the dielectric layer 200 by a photolithography process, etching the dielectric layer 200 with the photoresist as a mask, and stopping at the substrate 100. To form an opening 201 through the dielectric layer 200 that exposes an upper plane of a portion of the substrate 100. Generally, the method of forming the opening 201 includes a photolithography process, dry etching, or wet etching. Since the opening 201 penetrates the dielectric layer 200, a portion of the upper surface of the substrate 100 is exposed, that is, the silicon surface of the substrate 100 is exposed. Typically, the etching process is controlled such that the cross section of the opening 201 parallel to the upper plane of the substrate 100 has a specific shape, and the cross-sectional area thereof is preferably 1-100 μηι ² . The purpose of forming the opening 201 is to prepare for depositing the metal in the next step.

Referring to FIG. 4, step S300 is performed to form a metal plug 202 filling the opening 201. The lower plane of the metal plug 202 is in electrical contact with the exposed upper plane of the substrate 100 (the meaning of "electrical contact" as used herein is two Direct contact between the conductors forms electrical communication, or indirect conduction through other conductors to form electrical communication). Specifically, the metal plug 202 is formed by depositing a metal material in the opening 201, the metal material including W Al Cu TiAl or a combination thereof. Preferably, after the metal plug 202 is formed, the dielectric layer 200 and the metal plug 202 are subjected to a chemical-mechanical polishing (CMP) process. As shown in FIG. 4, the upper plane of the metal plug 202 and the upper plane of the dielectric layer 200 are formed. Qi Ping.

[0037] Optionally, prior to forming the metal plug 202, a contact layer (not shown in FIG. 4) is first formed on the exposed upper surface of the substrate 100 within the opening 202. The specific step is to first use ion implantation, Depositing an amorphous material or in-situ doping growth, pre-amorphizing the exposed upper plane to form a local amorphous region, and then using metal sputtering or chemical vapor deposition on the amorphous region a metal layer formed, the metal may be Ni, Ti, Co or Cu, etc., and then the substrate 100 is annealed, such as rapid thermal annealing, spike annealing, instantaneous annealing, etc., the deposited metal layer and the non- The amorphous compound of the crystalline region reacts to form the contact layer. Taking the silicon substrate in this embodiment as an example, the contact layer may be nickel silicide, titanium silicide, cobalt silicide or copper silicide or other metal silicide. Finally, chemical etching is used to remove unreacted deposited metal. The advantage of forming the contact layer is that the contact resistance between the metal plug 202 and the substrate 100 is reduced.

Referring to FIG. 5, step S400 is performed to form a graphene layer 300 on the dielectric layer 200 in contact with the upper surface of the metal plug 202, the graphene layer 300 completely covering the upper plane of the metal plug 202. Preferably, the material of the metal plug 202 is Cu, and the metal plug 202 of the Cu material is used as a base to form the graphene layer 300 by using a CVD process, and the specific steps are: using a carbon-containing gas compound such as decane as a gaseous state. a carbon source, the carbon atom cracked and grown by the gaseous carbon source is adsorbed on the upper surface of the metal plug 202 at a high temperature, and further forms a continuous graphene film, and one or more layers of the graphene film are stacked to form a graphene layer 300. . The graphene layer 300 covers not only the upper plane of the metal plug 202 but also the upper plane of the dielectric layer 200.

[0039] Since the graphene layer formed on the plane of the metal plug has a good crystal morphology and performance, and the upper plane of the metal plug can precisely control its shape by an etching process, the above method forms a good crystal morphology having a specific shape. Graphene layer. After forming the graphene layer, it can be peeled off and used to fabricate other semiconductor devices.

The fabrication of the semiconductor structure of the second embodiment of the present invention described above can be achieved by adjusting the steps of the above manufacturing method. Specifically, the following steps are included:

Providing a substrate;

Etching the substrate to stop inside the substrate to form an opening having a specific shape; [0043] forming a metal plug filling the opening;

[0044] A graphene layer in contact with an upper plane of the metal plug is formed on the substrate, the graphene layer completely covering an upper plane of the metal plug.

[0045] The above steps are described in detail below.

[0046] First, a substrate is provided having a flat upper surface. The substrate may include a compound semiconductor, For example, silicon carbide, gallium arsenide, indium arsenide or indium phosphide may also include various insulating materials.

[0047] A photoresist of a specific pattern is formed on the substrate by a photolithography process, and the substrate is etched using the photoresist as a mask and stopped inside the substrate. Generally, a method of forming an opening includes a photolithography process, dry etching, or wet etching. Typically, the etching process is controlled such that the cross section of the opening parallel to the upper plane of the substrate has a specific shape, and the cross-sectional area thereof is preferably 1-1 00 μ ηι ² . The purpose of forming the opening is to prepare for depositing the metal in the next step.

[0048] Next, a metal plug filling the opening is formed, the upper plane of which is flush with the upper plane of the substrate. Specifically, a metal plug is formed by depositing a metal material in the opening, the metal material including W, Al, Cu, T i A l or a combination thereof. Preferably, after the metal plug is formed, the substrate and the metal plug are subjected to chemical mechanical polishing to make the upper surface of the metal plug flush with the upper plane of the substrate.

[0049] A graphene layer is then formed on the substrate and on the metal plug, the graphene layer completely covering the upper plane of the metal plug. Preferably, the metal plug material is Cu, and the metal plug of the Cu material is used as a base to form a graphene layer by using a CVD process, and the specific step is: using a carbon-containing gas compound such as decane as a gaseous carbon source. The carbon atoms cracked and grown by the gaseous carbon source are adsorbed on the upper surface of the metal plug at a high temperature, and further form a continuous graphene film, and one or more layers of the graphene film are stacked to form a graphene layer. The graphene layer not only completely covers the upper plane of the metal plug, but also covers a portion of the upper plane of the substrate.

[0050] In a subsequent process, the formed graphene layer may be stripped. Since the graphene layer formed on the plane of the metal plug has a good crystal morphology and performance, and the upper plane of the metal plug can be precisely controlled by an etching process, the above method forms a graphene having a good crystal shape of a specific shape. Floor. After forming the graphene layer, it can be peeled off and used to fabricate other semiconductor devices.

[0051] In the above two embodiments, the dielectric layer and the substrate of the first embodiment may be collectively referred to as a base layer; in the second embodiment, there is no dielectric layer, but only a substrate, which is equivalent to the first implementation. The base layer of the example is therefore also referred to as the base layer. In the description of the present invention, one or more base layers are taken as an example, and a multi-layer base structure may also be employed in practical applications. That is, the base layer may be a single layer or a multi-layer structure.

[0052] The semiconductor structure provided by the present invention and a method of fabricating the same are formed by crystallizing graphene In the fixed region, especially on the localized metal surface, the particle size of the graphene crystal is increased, and the step of optimizing the deposition of graphene is combined to help improve the uniformity of the graphene material, thereby improving the graphene material. Performance and stability in semiconductor structures.

[0053] While the invention has been described in detail with reference to the preferred embodiments of the embodiments . For other examples, one of ordinary skill in the art will readily appreciate that the order of process steps can be varied while remaining within the scope of the invention.

Further, the scope of application of the present invention is not limited to the process, mechanism, manufacture, composition, means, methods and steps of the specific embodiments described in the specification. From the disclosure of the present invention, it will be readily understood by those skilled in the art that the processes, mechanisms, manufactures, compositions, means, methods, or steps that are presently present or will be developed in the The corresponding embodiments described have substantially the same function or substantially the same results, which can be applied in accordance with the invention. Therefore, the appended claims are intended to cover such modifications, such as

Claims

Rights request

1. A method for manufacturing a semiconductor structure, the method comprising:

(a) Provide grassroots;

(b) Etch the base layer to form a bottomed opening ( ²⁰¹ );

(c) forming a metal plug (202) filling the opening (201);

(d) Form a graphene layer (300) on the base layer that is in contact with the upper plane of the metal plug (202).

2. The method according to claim 1, wherein the base layer is a multi-layer structure composed of a dielectric layer (200) and a substrate (100) or a single-layer substrate.

3. The method according to claim 2, wherein when the base layer is a multi-layer structure composed of a dielectric layer (200) and a substrate (100),

In step b), the dielectric layer (200) above the substrate (100) is etched to form an opening (201) that stops on the upper plane of the substrate (100), and the opening (201) exposes part of the substrate The upper plane of (100);

In step c), the lower plane of the metal plug (202) is in electrical contact with the exposed upper plane of the substrate (100).

4. The method according to claim 1 or 3, wherein step c) further includes:

Carry out CMP process to make the upper plane of the metal plug (202) flush with the upper plane of the base layer or dielectric layer (200).

5. The method according to claim 1, wherein:

The area of the cross section of the opening (201) parallel to the upper plane of the base layer is 1-100 μm ² .

6. The method according to claim 1 or 2, wherein the material of the metal plug (202) includes:

W, Al, Cu, TiAl or combinations thereof.

7. The method according to claim 1 or 2, wherein the material of the dielectric layer (200) includes:

SiO ₂ , carbon doped SiO ₂ , BPSG, PSG, USG, Si ₃ N ₄ , low-k materials or combinations thereof.

8. The method according to claim 1, wherein: The graphene layer (300) is formed using a CVD process.

9. The method according to claim 1, wherein:

After step d), a step of peeling off the graphene layer is also included.

10. A semiconductor structure, the semiconductor structure includes a base layer, a metal plug (202) and a graphene layer (300), wherein:

The metal plug (202) is embedded in the base layer;

The graphene layer (300) is formed on the base layer and the metal plug (202), and the graphene layer (300) is in contact with the upper plane of the metal plug (202).

11. The semiconductor structure according to claim 10, wherein:

The base layer is a multi-layer structure composed of a dielectric layer ( ²⁰⁰ ) and a substrate (100) or a single-layer substrate.

12. The semiconductor structure according to claim 10, wherein:

The upper plane of the metal plug (202) is flush with the upper plane of the base layer.

13. The semiconductor structure according to claim 10, wherein:

The area of the cross-section parallel to the upper plane of the base layer in the metal plug (202) is 1-100 μ

2

m.

14. The semiconductor structure according to any one of claims 10 to 13, wherein the material of the metal plug (202) includes:

W, Al, Cu, TiAl or combinations thereof.