JP2015162668A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which uses a semiconductor layer having favorable crystallinity.SOLUTION: A semiconductor device manufacturing method according to the present embodiment comprises: a step of forming a base layer 10 on a substrate 90; a step of forming on the base layer 10, an amorphous semiconductor layer 11x including first parts 111, 111Y and a second part 115; a step of removing the base layer below the first parts 111Y, 111 so as to leave the base layer 10 below the second part 115; and a step fo crystallizing the semiconductor layer 11X by crystal growth in a direction from the second part 115 toward the first parts 111, 111Y by heat treatment in a state where a cavity 900 is formed below the first parts 111, 111Y.

Description

  Embodiments described herein relate generally to a method for manufacturing a semiconductor device.

  Until now, integrated circuits (ICs) have been realized with high integration and high performance by miniaturization of transistors, that is, scaling.

  As one of the methods for high integration and high performance of semiconductor devices after the critical dimension of device miniaturization, three-dimensional ICs are attracting attention.

  In order to form a semiconductor device having a three-dimensional structure using an inexpensive material (for example, a channel material of a field effect transistor), a semiconductor device is formed on a semiconductor layer formed by polycrystallizing an amorphous layer. It is preferable to form.

  Generally, a semiconductor device with good characteristics is formed by using a high-quality crystalline semiconductor layer in a region (element formation region) for forming a semiconductor device. Therefore, formation of a polycrystalline layer having a large crystal grain size, more preferably formation of a quasi-single crystal layer, is desired for realizing a high-performance three-dimensional IC.

  The process of crystallizing the amorphous semiconductor layer is mainly divided into two processes of nucleation and nucleation. When nucleation occurs at any location in the amorphous semiconductor layer, crystals with a small grain size are formed. Such nucleation at a plurality of locations in the semiconductor layer is not preferable for forming a semiconductor layer having a large crystal grain size.

  Therefore, it is desired to form a semiconductor layer having a large crystal grain size by promoting nucleation while suppressing nucleation.

  An example of a method (for example, Non-Patent Document 1) of promoting nuclear growth while suppressing nucleation is as follows. After a metal (for example, nickel) that forms a metal-germanium compound at a low temperature is deposited on the amorphous germanium semiconductor layer, a part of the metal layer remains on the semiconductor layer and the semiconductor. The laminated structure with the layers is processed. With part of the metal layer remaining, heat treatment is performed at a low temperature of about 360 ° C., and amorphous Ge is crystallized from the metal-germanium compound layer side.

  When the metal layer is provided on the semiconductor layer as in this example, a process for processing the metal layer, such as formation of a mask for etching the metal layer into a predetermined shape, is complicated. In addition, since the metal layer processing process is executed, the manufacturing cost of the semiconductor device increases.

  Further, since the semiconductor layer is in contact with an insulating layer (silicon oxide layer) as a base layer, a nucleus is formed at the interface between the semiconductor layer and the insulating layer. As a result of this nucleation, an increase in the grain size of the crystal grains may be hindered.

Park J.-H. et al., Journal of Applied Physics 104 064501 (2008)

  The present invention has been made in view of the above circumstances, and provides a method for manufacturing a semiconductor device that improves the crystallinity of a semiconductor layer and has good characteristics.

  A method of manufacturing a semiconductor device according to an embodiment of the present invention includes a step of forming a base layer on a substrate, and a second portion connected to the first portion and the first portion having a predetermined line width on the base layer. Forming an amorphous semiconductor layer including a portion; removing the underlying layer below the first portion so that the underlying layer below the second portion remains; And a step of crystallizing the semiconductor layer by crystal growth in a direction from the second portion toward the first portion by heat treatment in a state where a cavity is provided below the one portion.

  A method of manufacturing a semiconductor device according to an embodiment of the present invention includes an amorphous semiconductor layer including a first portion having a predetermined line width and a second portion connected to the first portion above the substrate; A direction from the second part toward the first part by a step of forming a base layer on the two parts and a heat treatment set to a temperature lower than a temperature at which nucleation occurs between the first part and the substrate And crystallizing the first portion by crystal growth.

  In a method for manufacturing a semiconductor device according to an embodiment of the present invention, an amorphous semiconductor layer including a first portion having a predetermined line width and a second portion connected to the first portion is formed on a substrate. The step of forming a first film covering the semiconductor layer, the step of forming an opening exposing the second portion in the first film, and a heat treatment in a reduced-pressure atmosphere. Crystallizing the first part by crystal growth in a direction from the second part exposed to the first part toward the first part.

  According to the present invention, it is possible to realize a nucleus growth process in a state where a region where nucleation occurs is limited by heat treatment in a state where the main part of the semiconductor layer is not in contact with other members. Therefore, the present invention can provide an inexpensive and high-performance semiconductor device.

1 is a bird's-eye view showing a structure of a semiconductor device according to a first embodiment. The top view which shows the structure of the semiconductor device of 1st Embodiment. Sectional drawing which shows the structure of the semiconductor device of 1st Embodiment. Sectional drawing which shows the structure of the semiconductor device of 1st Embodiment. The figure which shows 1 process of the manufacturing method of the semiconductor device of 1st Embodiment. The figure which shows 1 process of the manufacturing method of the semiconductor device of 1st Embodiment. The figure which shows 1 process of the manufacturing method of the semiconductor device of 1st Embodiment. The figure which shows 1 process of the manufacturing method of the semiconductor device of 1st Embodiment. The figure which shows 1 process of the manufacturing method of the semiconductor device of 1st Embodiment. The figure for demonstrating the semiconductor device of 2nd Embodiment. The figure for demonstrating the manufacturing method of the semiconductor device of 2nd Embodiment. The figure for demonstrating the manufacturing method of the semiconductor device of 2nd Embodiment. The figure for demonstrating the manufacturing method of the semiconductor device of 3rd Embodiment. The figure for demonstrating the manufacturing method of the semiconductor device of 3rd Embodiment. The figure for demonstrating the manufacturing method of the semiconductor device of 3rd Embodiment. The figure for demonstrating the manufacturing method of the semiconductor device of 3rd Embodiment. The figure for demonstrating the manufacturing method of the semiconductor device of 4th Embodiment. The figure for demonstrating the manufacturing method of the semiconductor device of 4th Embodiment. The figure for demonstrating the manufacturing method of the semiconductor device of 5th Embodiment. The figure for demonstrating the modification of embodiment. The figure for demonstrating the modification of embodiment.

[Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol shall be attached | subjected to a common structure through embodiment, and the overlapping description is abbreviate | omitted. Each figure is a schematic diagram for promoting explanation and understanding of the invention, and its shape, dimensions, ratio, and the like are different from those of an actual device. However, these are in consideration of the following explanation and known techniques. The design can be changed as appropriate.

(1) First embodiment
(A) Structure
The structure of the semiconductor device according to the embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a bird's eye view showing the structure of the semiconductor device of the embodiment.
FIG. 2 is a diagram illustrating a planar structure of the semiconductor device of the embodiment. FIG. 3 is a diagram showing a cross-sectional structure of the semiconductor device of the embodiment showing a cross section taken along line III-III in FIG. 2. FIG. 4 is a cross-sectional structure diagram of the semiconductor device of the embodiment showing a cross section taken along line IV-IV in FIG. 2.

  As shown in FIGS. 1 to 4, the semiconductor device of the present embodiment is a field effect transistor (hereinafter also referred to as FET).

  As shown in FIGS. 1 to 4, the field effect transistor of the present embodiment is provided above the semiconductor substrate 90 with an insulating film 91 interposed therebetween. For example, the semiconductor substrate 90 is a silicon (Si) substrate, and the insulating film 91 is a film made of silicon oxide. Hereinafter, a configuration including the semiconductor substrate 90 and the silicon oxide film 91 on the semiconductor substrate is also referred to as substrates 90 and 91.

The insulating film 91 made of silicon oxide is not limited to SiO ₂ formed by oxidizing the semiconductor substrate 90, but is a film in which boron (B) or phosphorus (P) is mixed with silicon oxide, for example, a BSG film, A deposited film such as a PSG film, a BPSG film, or a TEOS film may be used. The insulating film 91 may be a film used as an interlayer insulating film in which nitrogen (N), carbon (C), fluorine (F), or the like is mixed in an oxide.

  On the insulating film 91, the compound layer 10 and the insulating film 179 (17) are provided. An insulating film 179 (17) is provided between the compound layers 10. Hereinafter, the insulating film 179 (17) may be referred to as a spacer film 12 for the purpose of differentiation.

  The semiconductor layer 11 is provided on the compound layer 10 and the insulating film 179 (17). This semiconductor layer (semiconductor region) 11 is used as a channel material (active region) of a field effect transistor.

  The field effect transistor of the embodiment is, for example, a field effect transistor having a multi-gate structure, and in the example illustrated in FIGS. 1 to 4, the transistor of the embodiment is a FinFET. When the multi-gate transistor is a FinFET as in this embodiment, the semiconductor layer 11 has a strip-shaped portion (fin portion) 111 having a desired line width (fin width).

  The gate electrode 18 of the field effect transistor extends over the fin portion (also referred to as a wire portion) 111 of the semiconductor layer 11 through the gate insulating film 170, whereby a field effect transistor having a multi-gate structure is formed.

  Source / drain regions are provided in the semiconductor layer 11 so as to sandwich the channel region in the semiconductor layer 11 in the extending direction of the fin portion 111 (X direction, channel length direction of the transistor).

  A portion 115 having a size larger than the fin width in the width direction (Y direction) of the fin portion 111 is provided at one end and the other end in the extending direction of the fin portion 111 (X direction, channel length direction of the transistor). Yes. For example, the contact plug CP is connected to the portion 115 having a dimension larger than the fin width. Hereinafter, the portion 115 having a size larger than the fin width is referred to as a contact portion 115. When the contact portion 115 has a portion having a dimension larger than the fin width, the contact area between the semiconductor layer 11 having the fin portion 111 and the contact plug CP increases, and the contact resistance between the semiconductor layer 11 and the contact plug CP decreases. Is done. The contact portion 115 may be handled as a part of the source / drain region.

  For example, the contact portion 115 is provided on the compound layer 10.

For the gate insulating film 170 (17), for example, an oxide mainly composed of silicon such as SiO ₂ or a high dielectric material such as hafnium aluminum oxide (HfAlO) is used. For the gate electrode 25, a conductive silicon compound such as silicide, a conductive germanide, or a conductive compound such as tantalum nitride (TaN) is used.

  The insulating film 179 provided between the fin portion 111 and the insulating film (substrate) 91 is formed in the same process as the gate insulating film 170, and the insulating film 179 and the gate insulating film 170 are made of the same material. For example, the gate insulating film 170 and the insulating film (spacer film) 179 are one continuous film. 1 to 4, the thickness of the insulating film 179 is shown to be the same as the thickness of the compound layer 10, but the present invention is not limited to this. When the gate insulating film 170 and the spacer film 179 are continuous films, the film thickness of the spacer film 179 is equal to or less than the film thickness of the compound layer 10 depending on the film thickness of the compound layer 10 and the method of forming the gate insulating film. There is a possibility that the gate insulating film 170 or more.

  In the field effect transistor (FinFET) of this embodiment, the gate electrode 18 and the channel region 111 face each other with the gate insulating film 170 sandwiched between the upper surface and the three side surfaces (directions) of the channel region 111. . Note that an insulating film thicker than the gate insulating film 170 may be interposed between the upper surface of the channel region 111 and the gate insulating film 170.

  The field effect transistor of the present embodiment may be a transistor (for example, a junctionless transistor) in which the conductivity type of the source / drain region is the same as that of the channel region. Further, the field effect transistor of the present embodiment may be a transistor in which the conductivity type of the source / drain region and the conductivity type of the channel region are opposite to each other.

  For example, the semiconductor layer 11 including the channel region and the source / drain regions is formed using a semiconductor material other than Si. In the present embodiment, the semiconductor layer 11 is a crystalline germanium (Ge) layer 11.

  In the present embodiment, the polycrystalline (or pseudo single crystal or single crystal) Ge layer 11 includes carbon (C), silicon (Si), tin (Sn), phosphorus (P), arsenic (AS), antimony (Sb). ), Boron (B), aluminum (Al), gallium (Ga), indium (In), or the like. The semiconductor layer 11 may be a layer containing Si as a main component.

  The compound layer 10 is a layer composed of a metal element and an element constituting a semiconductor layer. When the semiconductor layer 11 is made of Ge, the compound layer 10 is, for example, a germanide layer (Ge-metal tube compound layer). As a specific example, the compound layer 10 is a nickel germanium layer (NiGe layer). However, the compound layer includes at least one element selected from cobalt (Co), palladium (Pd), tin (Sn), gold (Au), aluminum (Al) silver (Ag), and lead (Pb). A layer formed of a compound with germanium (or Si) may be used.

The dimension W1 of the compound layer 10 in the extending direction of the fin part 111Y is smaller than the dimension W2 of the contact part 115 in the extending direction of the fin part 111.

  In the semiconductor device of this embodiment, a high-quality crystalline semiconductor region is used as an element formation region, for example, a channel region of a transistor.

  In this embodiment, the base layer (crystal nucleus, seed layer) for crystallizing the semiconductor layer in the semiconductor layer other than the channel region in a state where the channel region of the transistor is not in contact with other members The crystalline semiconductor layer 11 is formed from the amorphous semiconductor layer by heat treatment in contact with the semiconductor layer.

  For example, as a result of heat treatment for crystallization of the semiconductor layer, the base layer (for example, a conductive layer) and the semiconductor layer react with each other, and the compound layer 10 is formed below the semiconductor layer 11. Formation of the compound layer 10 forms crystal nuclei for crystallizing the amorphous semiconductor layer. Thus, the conductive layer / compound layer in contact with the semiconductor layer functions as a base layer (seed layer) for crystallizing the amorphous semiconductor layer.

  Details of a method for forming a high-quality crystalline semiconductor region (channel region) included in the semiconductor device will be described later.

  As described above, according to the present embodiment, it is possible to improve the crystallinity of the semiconductor layer, in particular, to improve the crystallinity of the semiconductor region in which the crystallinity contributes to the characteristics of the semiconductor device.

  Therefore, the semiconductor device of the first embodiment can be realized by a semiconductor device formed from a high-quality crystalline semiconductor layer and having improved element characteristics.

(B) Manufacturing method
A manufacturing method of the semiconductor device (field effect transistor) of the first embodiment will be described with reference to FIGS.

  5 to 9 are diagrams showing each manufacturing process in the manufacturing method of the field effect transistor of this embodiment. Here, the manufacturing method of the semiconductor device of this embodiment will be described with reference to FIGS.

  In the field effect transistor manufacturing method of the present embodiment below, a case where a semiconductor layer (channel material, active region) for forming a channel region of the transistor is germanium will be described.

As shown in FIG. 5, an oxide film (here, SiO ₂ film) 91 is formed on the semiconductor substrate 90 by an oxidation process on the semiconductor substrate (for example, a single crystal Si substrate) 90. The SiO ₂ film 91 on the Si substrate 90 may be deposited on the Si substrate 90 by a CVD method.

The conductive material layer 10Z is formed on the SiO ₂ film 91 by sputtering, for example.
The semiconductor layer 11Z is formed on the conductive material layer 10Z by sputtering, for example.
The semiconductor layer 11Z is an amorphous semiconductor layer. In the manufacturing process described later, when anisotropic etching is performed on the semiconductor layer 11Z, at least a part of the conductive layer 10Z may be etched, or the conductive layer 10Z remains without being etched. Also good. However, since the conductive layer 10Z is selectively etched with respect to the semiconductor layer 11Z in the etching process of the conductive layer 10Z, a large etching selection ratio is ensured between the conductive layer 10Z and the semiconductor layer 11Z. The material is preferably used for the semiconductor layer 10Z and the semiconductor layer 11Z.

  When amorphous germanium is used for the semiconductor layer 11Z, a material that forms a metal compound with Ge is used for the conductive layer 10Z. For example, Ni is used for the conductive material layer 10Z.

  The semiconductor layer 11Z containing Ge as a main component may include one or more elements selected from C, Si, Sn, P, As, Sb, B, Al, Ga, In, and the like. The conductor layer 10Z may be formed of at least one material selected from Ni, Co, Pd, Sn, Au, Al, Ag, and Pb.

  After the resist film is applied on the amorphous Ge layer 11Z, a resist mask 80 having a predetermined pattern is formed on the amorphous Ge layer 11Z by an electron beam drawing process and an etching process for the resist film. The resist film may be patterned by photolithography or sidewall transfer technology.

  As shown in FIG. 6, the amorphous Ge layer is processed by anisotropic etching using the patterned resist mask 80 as a mask.

  Thus, an amorphous Ge layer 11Y having a planar pattern based on the resist mask 80 is formed on the metal layer (Ni layer) 10Z. For example, the fin part (wire part) 111Y is formed in the processed amorphous Ge layer 11Y. Contact portions 115Y are formed on one end and the other end of the amorphous Ge layer 11Y in the extending direction (X direction) of the fin portion 111Y. The contact portion 115Y is patterned and processed so that the dimension of the contact portion 115Y in the direction (fin width direction, Y direction) intersecting the extending direction of the fin portion 111Y is larger than the fin width (diameter) of the fin portion 111Y. ing.

  As shown in FIG. 7, after the Ge layer 11Y including the fin portion 111Y is formed, the resist mask is peeled off.

After stripping the resist mask, the Ni layer is selectively etched using a hot hydrochloric acid (HCl) solution. Thus, the isotropic etching using the Ge layer 11Y as a mask removes the Ni layer from the region below the fin portion 111Y of the amorphous Ge layer 11Y as shown in FIG. A cavity (air gap) 900 is formed in a region between the insulating film 91 and the insulating film 91.
The Ni layer 10Y remains below the contact portion 115Y of the semiconductor layer 11Y. The Ni layer 10Y contacts the contact portion 115Y and does not contact the fin portion 111Y. The fin portion 111Y connected to the contact portion 115Y is held hollow by the contact portion 115Y on the Ni layer 10Y.

  By wet etching using HCl, the dimension of the conductive layer (metal layer) 10Y in the extending direction of the fin part 111Y becomes smaller than the dimension of the contact part 115Y in the extending direction of the fin part 111.

  Thus, by selecting each material, a large etching selection ratio is ensured between the semiconductor layer (Ge layer) 11Y and the metal layer (Ni layer) 10Y. Therefore, the fin portion 111 having a small line width remains above the substrates 90 and 91, and the metal layer between the fin portion 111 and the substrates 90 and 91 is removed. Note that the Ni layer below the fin portion 111Y may be selectively removed by combining anisotropic etching such as reactive etching (RIE) and wet etching.

  As shown in FIG. 9, the heat treatment is performed in a state where the fin portion 111 </ b> Y does not contact any member other than the contact portion 115.

  In the Ge layer 10X (here, the contact portion 115) in contact with the Ni layer, Ge and Ni chemically react by heat treatment at 250 ° C. As a result, the NiGe layer 10 is formed on the insulating film 91.

After the NiGe layer 10 is formed, crystallization of the amorphous Ge layer using the NiGe layer 10 as a seed layer (crystal nucleus) by heat treatment at 350 ° C. is performed at the bottom of the contact portion 115 of the amorphous Ge layer 11X. Proceed from. That is, the Ge layer 11X is crystallized from the contact portion 115 side in contact with the NiGe layer 10 toward the fin portions 111 and 111Y held hollow.
When the Ge layer 11X is crystallized, the fin portions 111 and 111Y do not contact members other than the contact portion 115. Therefore, the formation of crystal nuclei at the interfaces between the fin portions 111 and 111Y and other members is suppressed, and the formation of crystal nuclei in the fin portions 111 and 111Y is a junction between the fin portions 111 and 111Y and the contact portion 115. The nucleation in becomes dominant.

  As described above, the formation positions of the crystal nuclei are limited to the junctions between the contact portions 115 and the underlayer and the junctions between the fin portions 111 and 111Y and the contact portions 115, and nuclei caused by local nucleation. By the growth (crystal growth), the amorphous fin portion 111Y is crystallized, and the polycrystalline fin portion 111 is formed. As a result, in the Ge layer 11X, the interface IF between the crystalline Ge portions 111 and 1115 and the amorphous Ge portion 111Y moves from both ends of the fin portions 111 and 111Y toward the center of the fin portion 111.

  By such crystal growth of Ge in the direction parallel to the substrate surface (transverse direction), a polycrystal (or pseudo single crystal, single crystal) fin portion 111 is formed from the amorphous fin portion 111Y.

  Thus, the polycrystalline Ge layer 10 is formed above the semiconductor substrate 90 with the insulating film 91 interposed therebetween.

When a polycrystalline Ge layer is used as a channel material (active region) of a p-type field effect transistor, a dopant (conductivity type impurity) is added by ion implantation to the polycrystalline Ge layer that forms the p-type field effect transistor formation region. Even if not, a carrier concentration sufficient for the operation of the p-type MISFET (for example, a hole concentration of about 10 ¹⁹ / cm ³ ) is obtained.

  A gate insulating film 170 is formed on the crystalline Ge layer (fin portion) 111. For example, the HfAlO film 170 is deposited on the fin portion 111 as the gate insulating film 170 by an atomic layer deposition (ALD) method. With the formation of the gate insulating film 170, an insulating film (spacer film) 179 is deposited on the insulating film 91. An insulating film 179 is preferably formed below the fin portion 111 by the expansion of the deposited gate insulating film 170 or the wraparound of the deposit. However, the region between the fin portion 111 and the insulating film 91 may be a cavity.

  A conductive film (for example, TaN film) 18 is deposited on the gate insulating film 21 by sputtering. The deposited conductive film 18 is processed into a predetermined shape by electron beam drawing and anisotropic etching.

  As a result, the gate electrode 18 that intersects the channel region (fin portion 111) of the polycrystalline Ge layer 11 via the gate insulating film 170 is formed on the insulating film 91 on the substrate 90.

  Thereafter, a low resistance region such as a NiGe film is formed in a self-aligned manner in the source / drain region and the contact portion of the polycrystalline Ge layer 11 by a known technique.

  After an interlayer insulating film covering the transistor is formed on the substrates 90 and 91 by a known BEOL process, the contact plug CP connected to the gate electrode 18 and the contact portion 115 of the transistor, and the contact plug CP Wirings connected to each are sequentially formed.

  The field effect transistor of this embodiment is formed by the above process.

  As described above, in the semiconductor device manufacturing method of the present embodiment, the semiconductor portion (here, the contact) in contact with the base layer (seed layer) for crystallizing the semiconductor layer in the amorphous semiconductor layer 11Y. Part) 115Y and a semiconductor part (here, fin part) 111Y that is not in contact with other members are formed.

  By heat treatment in a state where nucleation due to contact between the semiconductor portion 111Y and the other member, which is desirably a high-quality crystal, does not occur, the crystallization of the semiconductor layer 11Y is changed from the semiconductor portion 115Y that is in contact with the base layer to another Propagation to the semiconductor part 111Y not contacting the member.

  As a result, according to the manufacturing method of the field effect transistor of the present embodiment, since the crystal growth of the semiconductor layer proceeds in a state where the region where nucleation occurs is limited, high quality crystallinity (for example, pseudo single crystal) A semiconductor layer including a crystalline semiconductor region can be formed from an amorphous semiconductor layer.

  As described above, according to the semiconductor device manufacturing method of the present embodiment, a semiconductor device including a semiconductor layer having high quality crystallinity can be provided.

(2) Second embodiment
With reference to FIGS. 10 to 12, the semiconductor device and the manufacturing method thereof according to the second embodiment will be described. In addition, the description regarding the structure and manufacturing process substantially the same as 1st Embodiment is given as needed.

  This embodiment is different from the first embodiment in that the seed layer for crystallizing the amorphous semiconductor layer is an insulator.

FIG. 10 is a bird's-eye view showing the structure of the semiconductor device (for example, field effect transistor) of the second embodiment.
As shown in FIG. 10, the layer 19 in contact with the bottom surface of the contact portion of the crystalline semiconductor layer (for example, Ge layer) is, for example, a SiO ₂ layer.

  A method for manufacturing a semiconductor device according to the second embodiment will be described with reference to FIGS. 11 and 12 are cross-sectional process diagrams respectively showing one process of the method for manufacturing the semiconductor device of the present embodiment.

As shown in FIG. 11, the insulating layer 19 </ b> X is formed on the insulating film 91 on the substrate 90. An amorphous semiconductor layer (for example, Ge layer) 11Y is formed on the SiO ₂ layer 19X by sputtering, for example.
As the material of the insulating layer 19X in contact with the semiconductor layer 11Y, a material that ensures a large etching selectivity between the semiconductor layer 11Y and the insulating layer 19X is used. The insulating layer 19X is, for example, a SiO ₂ layer formed by PE-CVD (Plasma-Enhanced CVD) method.

  Then, similarly to the steps shown in FIGS. 5 and 6, the amorphous Ge layer 11Y is processed into a predetermined pattern based on the resist mask 80 having a predetermined pattern. Thereby, the amorphous Ge layer 11Y including the fin portion and the contact portion is formed.

After the resist mask is removed, as shown in FIG. 12, the SiO ₂ layer immediately below the fin portion (wire portion) 111Y is selectively removed. The SiO ₂ layer formed by the PE-CVD method is etched with a dilute hydrofluoric acid solution (for example, HF: H ₂ O = 1: 100) having a predetermined concentration.

By this etching of the SiO ₂ layer, a cavity (groove) 900 is formed immediately below the fin portion 111Y. The fin portion 111Y does not contact a member made of another material.

  The heat treatment is performed in a state where the fin portion 111 does not contact a member made of another material (a state where the fin portion 111 is supported in a hollow state).

  In the present embodiment, crystallization of the Ge layer 11Y proceeds from a portion 117 in contact with the insulating layer 19Y in the Ge layer 11X. For example, the portion 117 in contact with the insulating layer 19Y is changed from amorphous to crystalline (polycrystalline or single crystal) by heat treatment at about 500 ° C.

  By continuing the heat treatment at about 500 ° C., the interface between the amorphous Ge and the polycrystalline Ge moves to the fin portion 111Y of the Ge layer 11Y substantially as in the example shown in FIG.

  Since the fin portion 111Y does not contact any member other than the contact portion 115, nucleation does not occur at the interface between the fin portion 111Y and another member. Crystallization of the fin portion 111Y proceeds in a state where nucleation and crystal growth due to the polycrystalline Ge layer connected to one end and the other end of the fin portion are dominant. As a result of crystallization of the amorphous Ge layer mainly composed of crystal growth in the lateral direction, a polycrystalline (or pseudo single crystal, single crystal) Ge layer having good crystallinity is formed.

  As described above, as shown in FIG. 10, the entire fin portion 111 is crystallized by lateral crystal growth, and a high-quality polycrystalline (pseudo single crystal or single crystal) Ge layer 11 is formed on the substrate 90. It is formed above.

  Thereafter, the field effect transistor of the second embodiment is formed by the same process as that of the first embodiment.

The etching rate of SiO ₂ (hereinafter referred to as a PE-CVD film) formed by PE-CVD with respect to dilute hydrofluoric acid (HF: H ₂ O = 1: 100) is 53 nm / min and has the same concentration. The etching rate of SiO ₂ (hereinafter referred to as a thermal oxide film) formed by thermal oxidation of the Si substrate against dilute hydrofluoric acid is 2 nm / min. As described above, the etching rate of the PE-CVD film is 20 times or more faster than the etching rate of the thermal oxide film, so that the side of the PE-CVD film below the fin portion 111 is compared with the etching in the film thickness direction of the thermal oxide film. Directional etching can be performed effectively.

However, in principle, even if the PE-CVD film (SiO ₂ film) 19 is not provided between the Ge layer 11 and the thermal oxide film (SiO ₂ film) 91, the etching time is controlled by dilute hydrofluoric acid. The thermal oxide film 91 in contact with the fin portion 111 of the Ge layer 11 can be selectively removed. However, considering the etching rate in the direction parallel to the substrate surface of the thermal oxide film 91 in contact with the fin portion 111 (lateral direction), an oxide film having a high etching rate is formed between the Ge layer 11 and the thermal oxide film 91. It is preferable to provide it.

Instead of the SiO ₂ film 19 formed by the PE-CVD method, it is relatively easily etched with a dilute hydrofluoric acid solution such as aluminum oxide (Al ₂ O ₃ ) or lanthanum oxide (La ₂ O ₃ ). Other membranes may be used. Furthermore, if the material has a large etching selection ratio with respect to each of the semiconductor layer 11 and the underlying insulating film 91, the SiO ₂ film, hafnium oxide (HfO) formed by a film forming method other than the PE-CVD method. ₂ ) and a film made of a high dielectric material such as zirconium oxide (ZrO ₂ ), or at least one film selected from a nitride-based film such as silicon nitride (Si ₃ N ₄ ) A film may be provided between the semiconductor layer 11 and the insulating film 91.

  As described above, according to the second embodiment, a semiconductor device including a semiconductor layer having high quality crystallinity can be provided.

(3) Third embodiment
The third embodiment will be described with reference to FIGS. 13 to 16.
In addition, the description regarding the structure and manufacturing process substantially the same as 1st and 2nd embodiment is given as needed.

  In the present embodiment, a polycrystalline / single-crystal (pseudo-single-crystal) semiconductor layer (for example, fin portion / wire) is obtained by performing a heat treatment in a state where the polycrystalline layer and the amorphous semiconductor layer are in contact with each other. Is different from the above-described embodiment.

  13 to 15 are schematic views for explaining the method for manufacturing the semiconductor device of the present embodiment. FIG. 13 is a plan view showing one process of the semiconductor device manufacturing method of the present embodiment, and FIGS. 14 and 15 are cross-sectional views showing one process of the semiconductor device manufacturing method of the present embodiment.

As shown in FIGS. 13 and 14, a plurality of polycrystalline semiconductor layers (for example, multiple layers) having a predetermined shape and layout are formed on an insulating film (for example, SiO ₂ film) covering a semiconductor substrate (for example, Si substrate) 90. (Crystal Ge layer) 15A is formed.
The plurality of polycrystalline Ge layers 15 </ _b > A have a predetermined interval with respect to each of the X direction and the Y direction, and the plurality of polycrystalline Ge layers 15 </ _b > A are formed at predetermined positions on the SiO ₂ film 91. Each polycrystalline Ge layer 15A is formed to have a rectangular planar shape. Further, the area and film thickness of the polycrystalline Ge layer 15 are also appropriately controlled.

An amorphous semiconductor layer (for example, an amorphous Ge layer) 11Z is deposited on the polycrystalline Ge layer 15A and the SiO 2 film 91 by, for example, a sputtering method.
The deposited Ge layer 11Y is processed by lithography (or sidewall transfer technology) and etching, and one or more amorphous fin portions 111Y are formed at predetermined positions on the substrates 90 and 91. In addition, a region (contact part) 115Y connected to one end and the other end of the fin part 111Y is formed on the substrates 90 and 91 so as to be in contact with the polycrystalline Ge layer 10 laid out on the substrates 90 and 91. .

  Here, in the crystal growth using the polycrystalline Ge layer 15A laid out at a predetermined position on the substrate as a seed layer (crystal nucleus), a polycrystalline Ge layer 15A is produced so that a necking effect occurs in a direction parallel to the substrate surface. It is preferable that the formation position of the fin portion 111Y is controlled. For example, a predetermined interval is provided between the fin portion 111Y and the polycrystalline Ge layer 15A so that the fin portion 111Y and the polycrystalline Ge layer 15A do not directly contact each other.

  As shown in FIG. 15, a heat treatment is performed on the amorphous Ge layer 11Y including the fin portion 111Y in a state where a part of the amorphous Ge layer 11Y is in contact with the polycrystalline Ge layer 15A.

  The heat treatment starts polycrystallization of the portion 117 in contact with the Ge layer 15A in the amorphous Ge layer 11Y with the polycrystalline Ge layer 15A as a crystal nucleus, and the polycrystallization is a Ge layer that becomes a channel region of the transistor. Propagate to the fin portion 111 of 11Y.

For example, a heat treatment at 450 ° C. for 5 hours is performed on the amorphous Ge layer in order to crystallize the Ge layer.
The amorphous Ge layer 11Y on the SiO ₂ film 91 maintains an amorphous state in the heat treatment at 450 ° C. for 5 hours. On the other hand, the portion 117 of the amorphous Ge layer 11 in contact with the polycrystalline Ge layer 15A is polycrystallized under the same heat treatment conditions (450 ° C., 5 hours).

  As described above, the heat treatment temperature for crystallization of the amorphous Ge layer causes formation of crystal nuclei between the amorphous contact portion 115Y and the polycrystalline Ge layer (underlayer / seed layer) 15A. By setting the temperature to be higher than the temperature and lower than the temperature at which the formation of crystal nuclei between the amorphous fin portion (channel region) 111Y and the substrates 90 and 91 occurs, the amorphous Ge layer The region where the formation of crystal nuclei can be limited to the predetermined region.

  The crystallization of the amorphous semiconductor layer 11X in which the polycrystalline semiconductor layer 15A is used as a seed layer in the heat treatment in consideration of the crystallization temperature will be described with reference to FIG.

FIG. 16 is a graph for showing a Raman spectrum that was executed to measure the presence or absence of crystallization of the Ge layer. The horizontal axis of the graph of FIG. 16 indicates Raman shift (unit: cm ⁻¹ ), and the vertical axis of the graph of FIG. 16 indicates the magnitude (arbitrary value) of the detection signal.

  In the experimental results of FIG. 16, the characteristic line PA1 shows the Raman spectrum of the Ge layer that has been subjected to the heat treatment when the polycrystalline Ge layer (seed layer) in contact with the Ge layer is provided, and the characteristic line PA2 Shows a Raman spectrum of a Ge layer that has been heat-treated when a polycrystalline Ge layer that is in contact with the amorphous Ge layer is not provided.

  For the measurement of the Raman spectrum of FIG. 16, a laser having a wavelength of 488 nm is used. The thickness of the Ge layer to be measured is 120 nm. The penetration length of the 488 nm laser in the Ge layer to be measured is about 50 to 60 nm.

  In the heat treatment applied to each sample, the heating temperature is set to 450 ° C., and the heating time is set to 5 hours.

As indicated by the characteristic line PA1 in FIG. 16, a strong signal is detected in the Raman shift near 300 cm ⁻¹ . The spectrum (peak) of this Raman shift in the characteristic line PA is a spectrum of polycrystalline Ge. This spectrum does not originate from the polycrystalline Ge layer (seed layer) under the Ge layer, but indicates that the amorphous film on the film surface side of the Ge layer is polycrystallized.
On the other hand, when the polycrystalline Ge layer as a seed layer in contact with the Ge layer is not provided, a gentle detection signal indicating amorphous Ge is observed as indicated by the characteristic line PA2.

  In this way, the amorphous Ge layer can be crystallized by heat treatment in a state where the polycrystalline Ge layer is in contact with the amorphous Ge layer 11X.

  Further, due to the necking effect generated by controlling the geometric layout between the polycrystalline Ge layer 10 and the fin portion 111 having a fine line width, no crystal defects occur in the crystallized portion of the Ge layer. Crystallization of the amorphous Ge layer proceeds. In a state where the necking effect is obtained, the entire fin portion 111 changes from amorphous to crystalline.

  Thereby, in this embodiment, the fin part 111 of a polycrystal or a single crystal (pseudo single crystal) is formed.

  Thereafter, similarly to the above-described embodiment, the gate insulating film and the gate electrode are formed so as to cover the fin portion 111, and a field effect transistor having a structure similar to the structure shown in FIG. 10 is formed.

  The polycrystalline Ge layer 15A as the seed layer and the Ge region in the vicinity thereof may be used as a constituent member of a semiconductor device, or may be processed into a predetermined pattern by a lithography process and an etching process. Alternatively, a thin amorphous Ge layer deposited by sputtering is agglomerated by heat treatment, lamp heating, laser treatment or the like to agglomerate Ge to convert the amorphous phase into microcrystalline grains, and then the film is subjected to a lithography process. For example, the seed layer (crystal nucleus) 15A may be formed in the region 115Y. Further, the polycrystalline Ge layer 15A as the seed layer may be removed after the fin portion is crystallized.

  As described above, in the heat treatment of the amorphous semiconductor layer 11Y in a state where the amorphous semiconductor layer 11Y is in contact with the polycrystalline semiconductor layer 15A, nucleation is achieved by controlling the heating temperature in consideration of the crystallization temperature of the semiconductor layer. Crystal growth of the semiconductor layer 11Y in a direction from the portion in contact with the polycrystalline semiconductor layer 15A toward the fin portion (wire portion) 111Y in the amorphous semiconductor layer 11Y can be realized in a state where the region where the occurrence of the semiconductor layer is limited.

  Furthermore, by controlling the arrangement and shape of the polycrystalline semiconductor layer (seed layer) 15A with respect to the fin portion 111Y having a fine line width, crystal defects that may occur during crystallization of the amorphous semiconductor layer 11 are caused by fins. Generation of crystal defects can be suppressed so as not to propagate to the portion 111. As a result of the necking effect by controlling the geometric position between the fine semiconductor region and the seed layer (crystal nucleus), the crystallinity of the amorphous semiconductor layer, in particular, the crystallinity of the fin portion can be improved. .

  As described above, according to the third embodiment, a semiconductor device including a semiconductor layer having high quality crystallinity can be provided.

(4) Fourth embodiment
The fourth embodiment will be described with reference to FIGS. 17 and 18.
In addition, the description regarding the structure and manufacturing process substantially the same as 1st thru | or 3rd embodiment is given as needed.

  The fourth embodiment is different from the first to third embodiments in that crystallization of the semiconductor layer is promoted from the upper surface side of the amorphous semiconductor layer.

17 and 18 are views for explaining the semiconductor device manufacturing method of the second embodiment.
As shown in FIG. 17, the semiconductor layer 11 </ b> X is provided on the insulating film 91 on the semiconductor substrate 90. Substantially similar to FIGS. 13 and 14, an amorphous semiconductor layer (for example, a Ge layer) is deposited on the insulating film 91 by, for example, sputtering. An amorphous Ge layer 11Y including the fin part (or wire part) 111Y and the contact part 115Y is formed by lithography and etching.

  An insulating film (interlayer insulating film) 92 is deposited on the substrates 90 and 91 so as to cover the amorphous Ge layer 11X, and a contact hole 920 is formed in the insulating film 92.

  As shown in FIG. 18, an Sn film 15B is deposited in the formed contact hole 92 by, for example, a sputtering method. The Sn film 15B is formed in contact with the amorphous contact portion 115 of the Ge layer 11X.

Thereafter, heat treatment is performed at 400 ° C. for 5 hours in a nitrogen atmosphere at normal pressure (for example, atmospheric pressure).
By this heat treatment, as shown in FIG. 18, a solid solution of Sn and Ge is generated in the portion 119 of the Ge layer 11X in contact with the Sn film 15B, and the solid solution portion 119 is crystallized. By crystal growth using the portion 119 as a crystal nucleus (seed layer), a polycrystalline Ge region is generated in the contact portion 115 within a range of about 500 nm to 1000 nm from the edge of the contact hole. For example, a GeSn layer is formed in the vicinity of the contact portion 119 between the Sn film 15B and the Ge layer 11X.

By this heat treatment, nucleus growth (crystal growth) using a solid solution of Sn and Ge as a crystal nucleus proceeds, and the boundary IF between the polycrystalline Ge layers 111 and 115 and the amorphous Ge layer 111Y becomes the fin portions 111 and 111Y. Move to the side. As a result, the entire Ge layer 11Y is crystallized.
Thereby, in this embodiment, a polycrystalline (pseudo-single crystal) Ge layer is formed.

  Thereafter, similarly to the above-described embodiment, the gate insulating film and the gate electrode are formed so as to cover the fin portion 111, and a field effect transistor having a structure similar to the structure shown in FIG. 10 is formed.

  The eutectic point of the solid solution of Sn and Ge is lower than the melting point of Ge and is about 231 ° C. In principle, amorphous Ge is polycrystallized by heat treatment at or above the eutectic point of Sn and Ge. However, in consideration of the generation of high-quality crystals and the manufacturing time of the semiconductor device, the heat treatment for crystallization of the Ge layer by the solid solution of Sn and Ge should be performed at a temperature of about 300 ° C. to 500 ° C. Is preferred.

  Instead of Sn, at least one selected from Au, Al, Ag and Pb may be used. Sn, Au, Al, Ag and Pb form a solid solution with Ge. These elements have eutectic points below the melting point of Ge (938 ° C.). Further, instead of Sn, at least one selected from materials forming a compound (germanide) with Ge, for example, Ni, Co, and Pd may be used. At least one material selected from Ni, Co, Pd, Sn, Au, Al, Ag and Pb can be used as a material embedded in the contact hole for crystallization from the upper surface side of the Ge layer. A polycrystalline semiconductor layer (eg, a Ge layer) may be embedded in the contact hole 920 as a seed layer for crystallizing the amorphous semiconductor layer so as to be in contact with the amorphous Ge layer. However, when an element that forms a compound with Ge is used, the compound layer may move by sweeping the amorphous Ge layer. In this case, in order to use a semiconductor layer crystallized by an element forming a compound with Ge as a channel material, it is preferable to stop the movement of the compound layer before the channel.

  In the third embodiment, at least one material selected from Ni, Co, Pd, Sn, Au, Al, Ag, and Pb may be used instead of the polycrystalline semiconductor layer. . In this case, as described above, the solid solution and the compound formed by the heat treatment function as seed layers / crystal nuclei, and the crystallization of the Ge layer proceeds from the bottom side of the amorphous Ge layer.

  In this embodiment, the heating temperature for crystallization of the amorphous Ge layer causes the formation of crystal nuclei between the amorphous contact portion 115Y and the polycrystalline Ge layer (underlayer / seed layer) 15A. The temperature may be set to be equal to or higher than the temperature, and may be set to a temperature lower than the temperature at which the formation of crystal nuclei between the amorphous fin portion (channel region) 111Y and another member (for example, the insulating films 91 and 92) occurs. ,preferable.

  Even when the seed layer is provided on the upper surface of the amorphous semiconductor layer 11X, it can be obtained by controlling the geometric positional relationship between the fin portion 111 and the seed layer 15B, as in the third embodiment. Due to the necking effect, the amorphous semiconductor layer 11X can be polycrystallized (pseudo-single crystallization) while suppressing the generation of crystal defects.

  As described above, the heat treatment for the semiconductor layer 11X is performed in a state where the member (here, the Sn film) 15B for crystallizing the amorphous semiconductor layer 11X is in contact with the upper surface of the semiconductor layer 11X. Thus, the semiconductor layer 11X is crystallized.

  Therefore, according to the fourth embodiment, a semiconductor device including a semiconductor layer having high quality crystallinity can be provided.

(5) Fifth embodiment
The fifth embodiment will be described with reference to FIG.
In addition, the description regarding the structure and manufacturing process substantially the same as 1st thru | or 4th embodiment is given as needed.

This embodiment is different from the above-described embodiment in that an amorphous semiconductor layer is crystallized by heat treatment in a reduced-pressure atmosphere without using a seed layer such as a metal.
By the heat treatment in the reduced pressure atmosphere, the crystalline semiconductor layer can be generated from the amorphous semiconductor layer at a lower heating temperature than in the heat treatment in the normal pressure atmosphere.

When the amorphous Ge layer is subjected to a heat treatment at 450 ° C. or lower in an atmospheric pressure atmosphere, polycrystallization of the amorphous Ge layer does not proceed.
On the other hand, when the gas pressure during the heat treatment is reduced from normal pressure and the heat treatment in a reduced pressure atmosphere is applied to the amorphous Ge layer, the amorphous Ge layer is polycrystallized at a heating temperature of 450 ° C. or less. Is done.

  In the present embodiment, the normal pressure atmosphere refers to a state in which gas is enclosed in the heating chamber at a gas pressure of about atmospheric pressure (for example, 600 Torr to 760 Torr), and the reduced pressure atmosphere refers to a gas pressure lower than the atmospheric pressure. The gas is sealed in the heating chamber (for example, 1 Torr to 10 Torr).

For example, in FIG. 17 described above, a contact hole) 20 is formed in the interlayer insulating film 92 covering the amorphous Ge layer 11Y.
In the present embodiment, after the contact hole 920 is formed and before the member is embedded in the contact hole, a part of the contact portion 115Y of the amorphous Ge layer 11Y is exposed in a 5 Torr hydrogen atmosphere. Heat treatment is performed at 425 ° C. for 5 hours.

FIG. 19 is a graph showing a Raman spectrum of an amorphous Ge layer that has been subjected to a heat treatment at 425 ° C. for 5 hours under a hydrogen atmosphere of 5 Torr. The horizontal axis of the graph of FIG. 19 represents Raman shift (unit: cm ⁻¹ ), and the vertical axis of the graph of FIG. 19 represents the magnitude (arbitrary value) of the detection signal. Note that the measurement conditions of the Raman spectrum of FIG. 19 are the same as the measurement conditions of FIG.

  In the experimental results of FIG. 19, the characteristic line PB1 shows the Raman spectral spectrum of the Ge layer in the vicinity of the contact hole, and the characteristic line PB2 shows the Raman spectral spectrum of the Ge layer in a portion 2 μm away from the contact hole. Further, a characteristic line PB3 in FIG. 19 shows a Raman spectrum of the Ge layer in a portion separated by 5 μm or more from the contact hole.

As shown by the characteristic lines PB1, PB2, and PB3 in FIG. 19, a Raman shift of 300 cm ⁻¹ is detected in the vicinity of the opening of the contact hole and in a portion 2 μm away from the contact hole, and the position of the contact hole It is shown that the Ge layer is polycrystallized within the range of 2 to 2 μm.
On the other hand, in the portion in the Ge layer separated from the contact hole by 5 μm or more, only a broad peak indicating amorphous Ge is detected, and a peak indicating polycrystalline Ge is not detected.

  As described above, the measurement result of the Raman spectrum in FIG. 19 indicates that the amorphous Ge exposed from the contact hole is polycrystallized by the heat treatment in the reduced pressure atmosphere.

  Crystallization of the Ge region exposed in the reduced-pressure atmosphere through the contact hole propagates to the fin part through crystallization of the contact part, and the entire Ge layer is polycrystallized (or pseudo-single-crystallized). .

  Thereby, in this embodiment, a polycrystalline (pseudo-single crystal) Ge layer is formed.

  Thereafter, similarly to the above-described embodiment, the gate insulating film and the gate electrode are formed so as to cover the fin portion 111, and a field effect transistor having a structure similar to the structure shown in FIG. 10 is formed.

  In the present embodiment, the heating temperature for crystallization of the amorphous Ge layer is set to be higher than the temperature at which crystal nuclei are formed in the exposed amorphous contact portion 115Y, and the amorphous fin layer is formed. It is preferable to set the temperature lower than the temperature at which the formation of crystal nuclei between the portion (channel region) 111Y and other members (for example, the insulating films 91 and 92) occurs.

  As described above, the present embodiment controls the gas pressure condition of the heat treatment without using a base layer (for example, a metal layer or a polycrystalline semiconductor layer) for crystallization of the amorphous semiconductor layer. A crystalline semiconductor layer can be generated from the amorphous semiconductor layer.

  Therefore, according to the present embodiment, it is possible to reduce the formation process of the base layer.

  Therefore, according to the fifth embodiment, a semiconductor device including a semiconductor layer having high-quality crystallinity can be provided by relatively simple control of heat treatment conditions.

(6) Modification
A modification of the above-described embodiment will be described with reference to FIGS.

  FIG. 21 is a diagram for explaining a modification of the first and third embodiments.

  FIG. 21 illustrates a cross-sectional structure of a transistor.

  As shown in FIG. 20, the contact plug may be connected to a compound layer (eg, NiGe layer or GeSn layer) 10 below the crystallized semiconductor layer (eg, Ge layer) 11. The NiGe layer 10 is a layer having a lower resistance than the Ge layer 11. An insulating film may be provided between the side surface of the contact plug CP and the Ge layer 11.

  In the semiconductor device manufacturing method according to the first embodiment, a base layer (seed layer) below the Ge layer 11 reacts with the Ge layer, whereby a low-resistance compound layer (NiGe layer) is formed.

  By using the formed NiGe layer 10 as a low resistance layer between the contact plug CP and the Ge layer 11 without using only the underlying layer for crystallization of the amorphous Ge layer 11, the Ge layer 11 The process for forming the low resistance region on the upper surface of the substrate can be reduced.

  FIG. 21 is a diagram for explaining a modification of the first and second embodiments. FIG. 21 is a bird's-eye view for explaining the structure of the transistor.

  As shown in FIG. 21, the semiconductor device of the embodiment may be a gate all-around transistor (GAA transistor) in which the gate electrode covers the top, bottom, and both side surfaces of the channel region.

  According to the semiconductor device manufacturing method of the first and second embodiments, a cavity is formed below the channel region in order to avoid contact between the channel region (fin portion / wire portion) and other members. The Before filling the cavity, a gate insulating film is formed on the entire exposed surface of the channel region, and a gate electrode material is formed in the cavity and on the channel region. Thereby, a transistor having a GAA structure can be formed relatively easily.

When the thickness of the metal layer 10 or the insulating film layer 19 below the semiconductor layer 11 is thinner than the gate insulating film 170, the gate electrode 18 hardly goes below the fin portion 111, so that the transistor structure is FinFET or tri−. gateFET.
On the other hand, when the thickness of the metal layer 10 or the insulating film layer 19 is larger than the thickness of the gate insulating film 170 or when the compound formed from the semiconductor layer 11 and the metal layer 10 expands in volume, the gate electrode 18 Since it becomes easy to go under the fin part 111, the transistor of the GAA structure as shown in FIG. 21 is formed.

  The semiconductor device of the embodiment may be a planar structure field effect transistor in which the polycrystalline semiconductor layer formed by any one of the first to fourth embodiments is used for a channel region (active region).

  As described above, the above-described embodiment can provide the modified examples of FIGS. 20 and 21.

(7) Application examples
An application example of the semiconductor device of the embodiment will be described.

  The semiconductor device of this embodiment is applied to a semiconductor circuit (IC). For example, the semiconductor circuit including the semiconductor device of the present embodiment is a logic circuit, an image sensor, a memory circuit (for example, flash memory, MRAM), an FPGA, or the like.

  For example, the semiconductor device (multi-gate transistor) of this embodiment shown in FIG. 1 is provided on the interlayer insulating film 91 on the single crystal substrate 90.

  A plurality of electric field transistors (not shown) are provided on a semiconductor substrate 90 such as a Si single crystal substrate (bulk substrate). The interlayer insulating film 91 is provided on the bulk substrate 90 so as to cover the transistors on the bulk substrate 90. Various plugs and wirings are formed in the interlayer insulating film 91 by a multilayer wiring technique.

  One or more fin portions (wire portions) are formed on the interlayer insulating film 91 as a channel material (active region) of the field effect transistor by the semiconductor device manufacturing method of the embodiment. A plurality of transistors are formed on the interlayer insulating film 91 using the formed one or more fin portions.

  The transistor on the bulk substrate 90 is connected to the transistor of this embodiment provided on the interlayer insulating film 91 by each plug and each wiring. Thereby, a three-dimensional stacked semiconductor circuit (3D-IC) having a stacked channel structure is formed.

According to this embodiment, a favorable crystalline semiconductor layer (wire portion and fin portion) can be formed on the interlayer insulating film. Therefore, the performance of the transistor formed on the interlayer insulating film can be improved.
As a result, according to the present embodiment, a high-performance 3D-IC can be provided.

(8) Other
The field effect transistor and the manufacturing method thereof according to this embodiment include the following configurations.

  In the embodiment, the semiconductor region (channel material) for forming the channel region and the source / drain region of the FET is not limited to the Ge layer. A general semiconductor material such as silicon, an oxide semiconductor material, or a nitride semiconductor material may be used for the semiconductor region as the channel material.

  As long as the crystallinity of the channel region (fin portion / wire portion) is good, the crystallinity between the channel region and the contact portion may not be uniform.

  In the manufacturing method of the field effect transistor of the embodiment, each film (layer) can be formed by sputtering, vapor deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or pulsed laser deposition ( A well-known deposition method such as PLD) can be used.

  The insulating film (spacer film) provided in the cavity below the semiconductor layer may be formed in a different process using a material different from that of the gate insulating film.

  As mentioned above, although embodiment of this invention was described, this invention is not restricted to these, In the category of the summary of the invention as described in a claim, it can change variously. In addition, the present invention can be variously modified without departing from the scope of the invention in the implementation stage. Furthermore, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment.

  90: semiconductor substrate, 91: insulating film, 10, 15A, 15B, 19: underlayer, 11Y, 11Z: amorphous semiconductor layer, 11: crystalline semiconductor layer, 111: fin portion, 115: contact portion.

Claims (11)

Forming a base layer on the substrate;
Forming an amorphous semiconductor layer including a first portion having a predetermined line width and a second portion connected to the first portion on the underlayer;
Removing the underlying layer below the first portion such that the underlying layer below the second portion remains;
Crystallization of the semiconductor layer by crystal growth in a direction from the second part toward the first part by heat treatment in a state where a cavity is provided below the first part;
A method for manufacturing a semiconductor device, comprising: Forming a compound layer of the base layer and the semiconductor layer on the substrate by the heat treatment;
The method of manufacturing a semiconductor device according to claim 1, further comprising: The amorphous semiconductor layer is mainly composed of germanium.
The method for manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device manufacturing method. The underlayer is formed of at least one selected from Ni, Co, Pd, Sn, Au, Al, Ag, and Pd.
The method for manufacturing a semiconductor device according to claim 1, wherein: The underlayer is made of a first insulator.
The method for manufacturing a semiconductor device according to claim 1, wherein: The substrate includes a semiconductor region and an insulating layer made of a second insulator provided between the base layer and the semiconductor region,
In the etching conditions for removing the underlayer, the etching rate of the first insulator is faster than the etching rate of the second insulator.
A method for manufacturing a semiconductor device according to claim 5. Forming an amorphous semiconductor layer including a first portion having a predetermined line width and a second portion connected to the first portion, and a base layer on the second portion, above the substrate;
The first portion is crystallized by crystal growth in a direction from the second portion toward the first portion by a heat treatment set to a temperature lower than a temperature at which nucleation occurs between the first portion and the substrate. Process,
A method for manufacturing a semiconductor device, comprising: The temperature of the heat treatment is set to be equal to or higher than a temperature at which nucleation occurs between the second portion and the base layer.
The method for manufacturing a semiconductor device according to claim 7. The underlayer is formed so as to be in contact with an upper part of the second part or a bottom part of the second part.
9. A method of manufacturing a semiconductor device according to claim 7, wherein the method is a semiconductor device manufacturing method. Forming an amorphous semiconductor layer including a first portion having a predetermined line width and a second portion connected to the first portion on a substrate;
Forming a first film covering the semiconductor layer;
Forming an opening in the first film to expose the second portion;
Crystallization of the first part by crystal growth in a direction from the second part exposed from the opening to the first part by heat treatment in a reduced pressure atmosphere; and
A method for manufacturing a semiconductor device, comprising: The temperature of the heat treatment is set to be equal to or higher than a temperature at which nucleation occurs between the second part and the base layer and less than a temperature at which nucleation occurs between the first part and the substrate.
The method of manufacturing a semiconductor device according to claim 10.