CN103632922A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN103632922A CN103632922A CN201210298158.2A CN201210298158A CN103632922A CN 103632922 A CN103632922 A CN 103632922A CN 201210298158 A CN201210298158 A CN 201210298158A CN 103632922 A CN103632922 A CN 103632922A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 85
- 239000002184 metal Substances 0.000 claims abstract description 85
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 80
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 69
- 238000000034 method Methods 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 74
- 229910052799 carbon Inorganic materials 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 10
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 229910010038 TiAl Inorganic materials 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 12
- 238000010276 construction Methods 0.000 claims 3
- 239000002356 single layer Substances 0.000 claims 2
- 239000013078 crystal Substances 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 abstract description 4
- 239000002245 particle Substances 0.000 abstract description 4
- 239000010949 copper Substances 0.000 description 8
- 150000001721 carbon Chemical group 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 150000001875 compounds Chemical class 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000002425 crystallisation Methods 0.000 description 5
- 230000008025 crystallization Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 229910000673 Indium arsenide Inorganic materials 0.000 description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- JUZTWRXHHZRLED-UHFFFAOYSA-N [Si].[Cu].[Cu].[Cu].[Cu].[Cu] Chemical compound [Si].[Cu].[Cu].[Cu].[Cu].[Cu] JUZTWRXHHZRLED-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910021360 copper silicide Inorganic materials 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000004549 pulsed laser deposition Methods 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53276—Conductive materials containing carbon, e.g. fullerenes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor structure, which comprises the following steps: a) providing a base layer; b) etching the base layer to form a bottomed opening (201); c) forming a metal plug (202) filling the opening (201); d) forming a graphene layer (300) on the base layer in contact with an upper plane of the metal plug (202). Correspondingly, the invention also provides a semiconductor structure formed according to the manufacturing method. According to the method and the structure, the graphene crystals are formed in the preset area, the particle size of the graphene crystals is increased, and the step of optimally depositing the graphene is combined, so that the uniformity of the graphene material is improved, and the working performance and the stability of the graphene material in the semiconductor structure are improved.
Description
Technical field
The present invention relates to semi-conductive manufacture field, relate in particular to a kind of semiconductor structure and manufacture method thereof.
Background technology
Connection in Graphene between each carbon atom is very pliable and tough, and when applying external mechanical force, carbon atom face is with regard to flexural deformation, thereby makes carbon atom needn't rearrange to adapt to external force, also just kept Stability Analysis of Structures.This stable lattice structure makes carbon atom have outstanding conductivity.When the electronics in Graphene moves in track, can or not introduce foreign atom because of lattice defect scattering occurs.Because active force between atom is very strong, at normal temperatures, even if around carbon atom telescopes, the interference that in Graphene, electronics is subject to is also very little.Because its resistivity is extremely low, the speed that electronics runs is exceedingly fast, thereby Graphene can be used to develop thinner, conduction speed electronic component of new generation or transistor faster.Understandably, in semiconductor device, add Graphene partly to contribute to improve the service behaviour of semiconductor device.
Researcher is devoted to form in semiconductor device the Graphene parts that performance is better, more stable always, thereby obtains the maximum lift of the service behaviour of semiconductor device.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor structure and manufacture method thereof, to form the Graphene parts of stablizing high-quality in semiconductor device.
For achieving the above object, the invention provides a kind of manufacture method of semiconductor structure, the method comprises:
A) provide basic unit;
B) described in etching, basic unit is formed with the opening (201) at the end;
C) form the metal closures (202) of filling described opening (201);
D) in described basic unit, form the graphene layer (300) contacting with the upper plane of described metal closures (202).
Correspondingly, the present invention also provides a kind of semiconductor structure, and this semiconductor structure comprises basic unit, metal closures (202) and graphene layer (300), wherein:
Described metal closures (202) is embedded in described basic unit;
Described graphene layer (300) is formed on described basic unit and metal closures (202), and this graphene layer (300) contacts with the upper plane of described metal closures (202).
Semiconductor structure provided by the invention and manufacture method thereof are by being formed on Graphene crystallization in presumptive area, increased the particle size of Graphene crystallization, and in conjunction with the step of optimization deposition Graphene, contribute to promote the uniformity of Graphene material, therefore promoted service behaviour and the stability of Graphene material in semiconductor structure.
Accompanying drawing explanation
By reading the detailed description that non-limiting example is done of doing with reference to the following drawings, it is more obvious that other features, objects and advantages of the present invention will become:
Fig. 1 is the flow chart of an embodiment of the manufacture method of semiconductor structure, in accordance with the present invention;
Fig. 2 to Fig. 5 is according to the sectional structure schematic diagram of this each fabrication stage of semiconductor structure in the flow manufacturing semiconductor structure process shown in Fig. 1 according to a specific embodiment of the present invention;
In accompanying drawing, same or analogous Reference numeral represents same or analogous parts.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiments of the invention are described in detail.
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Below by the embodiment being described with reference to the drawings, be exemplary, only for explaining the present invention, and can not be interpreted as limitation of the present invention.
Disclosing below provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and object clearly, itself do not indicate the relation between discussed various embodiment and/or setting.In addition, the various specific technique the invention provides and the example of material, but those of ordinary skills can recognize the property of can be applicable to of other techniques and/or the use of other materials.In addition, First Characteristic described below Second Characteristic it " on " structure can comprise that the first and second Characteristics creations are for the direct embodiment of contact, also can comprise the embodiment of other Characteristics creation between the first and second features, such the first and second features may not be direct contacts.
First semiconductor structure provided by the invention is summarized below, be please refer to Fig. 5, Fig. 5 is the sectional structure schematic diagram of this semiconductor structure, and this semiconductor structure comprises substrate 100, dielectric layer 200, metal closures 202 and graphene layer 300, wherein:
Graphene layer 300 is formed on dielectric layer 200, and this graphene layer 300 contacts with the upper plane of metal closures 202, and covers the upper plane of this metal closures 202 completely.
Particularly, substrate 100 comprises silicon substrate (for example wafer).For example, according to the known designing requirement of prior art (P type substrate or N-type substrate), substrate 100 can comprise various doping configurations.In other embodiment, substrate 100 can also comprise other basic semiconductor, for example germanium.Or substrate 100 can comprise compound semiconductor, for example carborundum, GaAs, indium arsenide or indium phosphide.Typically, the thickness of substrate 100 can be but be not limited to about hundreds of micron, for example can be in the thickness range of 400 μ m-800 μ m.The thickness of dielectric layer 200 is between 50nm ~ 200nm, and its material comprises SiO
2, carbon doping SiO
2, BPSG, PSG, USG, Si
3n
4, low-k materials or its combination.The material of metal closures 202 comprises W, Al, Cu, TiAl or its combination.
In a preferred embodiment, the upper plane of metal closures 202 flushes (herein, term " flushes " in the scope that the difference in height that means between the two allows at fabrication error) with the upper plane of dielectric layer 200.Typically, in metal closures 202, be 1-100 μ m with the area in the upper parallel plane cross section of substrate
2.
Alternatively, form contact layer (not shown in Fig. 5) between the lower plane of metal closures 202 and the upper plane of substrate 100, the substrate 100 of take is that silicon substrate is example, and described contact layer can be nickle silicide, titanium silicide, cobalt silicide or copper silicide or other metal silicides.
Graphene layer 300 is the upper plane of covering metal plug 202 at least completely, and in certain embodiments, graphene layer 300 is plane in the part of blanket dielectric layer 200 also.Upper plane and graphene layer 300 due to metal closures 202, and metal closures 202 is crystalline texture, therefore the graphene layer 300 forming thereon has more macrocrystalline particle size, contributes to promote the uniformity of Graphene material, increases the mobility of graphene layer 300.By controlling the shape of cross section of metal closures 202, can control scope and the performance of crystallization on formed graphene layer 300, to meet the requirement of making different components.
Except embodiment mentioned above, (not shown) in a second embodiment, semiconductor structure of the present invention can also only include substrate 100, metal closures 202 and graphene layer 300, and there is no dielectric layer 200.Metal closures is formed directly in substrate, and the upper plane of metal closures and the upper plane of substrate flush, and in the upper plane of the substrate that graphene layer directly forms and metal closures.Plane contact on graphene layer part and metal closures.
Hereinafter the manufacture method in connection with semiconductor structure provided by the invention is further elaborated this semiconductor structure.
Please refer to Fig. 1, Fig. 1 is the flow chart of an embodiment of the manufacture method of semiconductor structure, in accordance with the present invention, and the method comprises:
Step S100, provides substrate, and forms the dielectric layer of the upper plane that covers this substrate;
Step S200, described in etching dielectric layer to form the opening with given shape that runs through described dielectric layer, the upper plane of substrate described in this opening emerges part;
Step S300, forms the metal closures of filling described opening, and the upper plane that the lower plane of this metal closures and described substrate expose electrically contacts;
Step S400 forms the graphene layer contacting with the upper plane of described metal closures on described dielectric layer, and this graphene layer covers the upper plane of described metal closures completely.
Below in conjunction with Fig. 2 to Fig. 5, step S100 is described to step S400, Fig. 2 to Fig. 5 is according to the sectional structure schematic diagram of this each fabrication stage of semiconductor structure in the flow manufacturing semiconductor structure process shown in Fig. 1 according to a specific embodiment of the present invention, it should be noted that, the accompanying drawing of each embodiment of the present invention is only the object in order to illustrate, is therefore not necessarily to scale.
First, execution step S100, provides substrate 100, and forms the dielectric layer 200 of the upper plane that covers this substrate 100.With reference to figure 2, substrate 100 comprises silicon substrate (for example wafer).For example, according to the known designing requirement of prior art (P type substrate or N-type substrate), substrate 100 can comprise various doping configurations.In other embodiment, substrate 100 can also comprise other basic semiconductor, for example germanium.Or substrate 100 can comprise compound semiconductor, for example carborundum, GaAs, indium arsenide or indium phosphide.Typically, the thickness of substrate 100 can be but be not limited to about hundreds of micron, for example can be in the thickness range of 400 μ m-800 μ m.In the present embodiment, substrate 100 is silicon substrates.On this substrate 100, form dielectric layer 200, this dielectric layer 200 is by chemical vapour deposition (CVD) (Chemical vapor deposition, CVD), high-density plasma CVD, ALD(atomic layer deposition), plasma enhanced atomic layer deposit (PEALD), pulsed laser deposition (PLD) or other suitable methods be formed on substrate 100.Typically, the thickness of this dielectric layer 200 is between 50nm ~ 200nm, and its material comprises SiO
2, carbon doping SiO
2, BPSG, PSG, USG, Si
3n
4, low-k materials or its combination.
With reference to figure 3, execution step S200, by photoetching process, on dielectric layer 200, form the photoresist of specific pattern, take described photoresist as mask etching dielectric layer 200 and stop at described substrate 100, to form the opening 201 that runs through dielectric layer 200, the upper plane of these opening 201 expose portion substrates 100.Normally, the method for formation opening 201 comprises photoetching process, dry etching or wet etching.Because this opening 201 runs through dielectric layer 200, in the part of substrate 100, plane exposes, and the silicon face of substrate 100 exposes.Typically, described etching process is controlled, made to have given shape with the upper parallel plane cross section of substrate 100 in opening 201, its area of section is preferably 1-100 μ m
2.The object that forms this opening 201 be in next step for plated metal is prepared.
With reference to figure 4, execution step S300, form the metal closures 202 of filling opening 201, the lower plane of this metal closures 202 electrically contacts (implication of described " electrically contacting " is between two conductors, directly to contact to form electric connection, or forms electric connection by the indirect conducting of other conductors) herein with the upper plane that substrate 100 exposes.Particularly, by forming metal closures 202 in the interior deposit metallic material of opening 201, described metal material comprises W, Al, Cu, TiAl or its combination.Preferably, formation metal closures 202 is rear carries out chemico-mechanical polishing (Chemical-mechanical polish, CMP) processing to dielectric layer 200 and metal closures 202, as shown in Figure 4, the upper plane of metal closures 202 and the upper plane of dielectric layer 200 is flushed.
Alternatively, before forming metal closures 202, in the upper plane first exposing at the interior substrate 100 of opening 202, form contact layer (not shown in Fig. 4).Its concrete steps are, first adopt the mode of Implantation, deposited amorphous compound or in-situ doped growth, upper plane to this exposure is carried out pre-amorphous processing, form local non-crystalline areas, then utilize metal sputtering mode or chemical vapour deposition technique, the metal level forming in this non-crystalline areas, described metal can be Ni, Ti, Co or Cu etc., then substrate 100 is carried out to annealing in process, such as rapid thermal annealing, spike annealing, spike etc., the described metal level of deposition and the amorphous compound of described non-crystalline areas react and generate described contact layer.The silicon substrate of take in the present embodiment is example, and described contact layer can be nickle silicide, titanium silicide, cobalt silicide or copper silicide or other metal silicides.Finally select the mode of chemical etching to remove unreacted plated metal.The advantage that forms this contact layer has been to reduce the contact resistance between metal closures 202 and substrate 100.
Please refer to Fig. 5, execution step S400 forms the graphene layer 300 contacting with the upper plane of metal closures 202, the upper plane of these graphene layer 300 complete covering metal plugs 202 on dielectric layer 200.Preferably, this material that take metal closures 202 is that Cu is example, the metal closures 202 of this Cu material of take is that matrix is used CVD technique to form graphene layer 300, its concrete steps are: use the gaseous compound of the carbon containings such as methane as gaseous carbon source, at high temperature the carbon atom of described gaseous carbon source cracking growth is adsorbed in the upper surface of metal closures 202, and further forming continuous graphene film, described in one or more layers, graphene film is piled up and is formed graphene layer 300.This graphene layer 300 is the upper plane of complete covering metal plug 202 not only, also plane in the part of blanket dielectric layer 200.
Owing to being formed on the graphene layer in plane on metal closures, there is good crystal habit and performance, and the upper plane of metal closures can accurately be controlled its shape by etching technics, therefore above method forms the graphene layer of the well-crystallized form with given shape.Form and can be peeled off after described graphene layer and for making other semiconductor device.
For making the semiconductor structure of the second embodiment of the present invention mentioned above, can realize by adjusting the step of above-mentioned manufacture method.Comprise the steps: specifically
Substrate is provided;
Substrate described in etching, stops at described substrate interior, to form the opening with given shape;
Form the metal closures of filling described opening;
On described substrate, form the graphene layer contacting with the upper plane of described metal closures, this graphene layer covers the upper plane of described metal closures completely.
Below above-mentioned steps is elaborated.
First, provide substrate, it has smooth upper surface.Substrate can comprise compound semiconductor, and for example carborundum, GaAs, indium arsenide or indium phosphide, also can comprise various insulating material.
By photoetching process, on substrate, form the photoresist of specific pattern, take described photoresist as mask etching substrate and stop at described substrate interior.Normally, the method for formation opening comprises photoetching process, dry etching or wet etching.Typically, described etching process is controlled, made to have given shape with the upper parallel plane cross section of substrate in opening, its area of section is preferably 1-100 μ m
2.The object that forms this opening be in next step for plated metal is prepared.
Then, form the metal closures of filling opening, the upper plane of this metal closures flushes with the upper plane of substrate.Particularly, by deposit metallic material in opening, form metal closures, described metal material comprises W, Al, Cu, TiAl or its combination.Preferably, after formation metal closures, substrate and metal closures are carried out to chemico-mechanical polishing (Chemical-mechanical polish, CMP) processing, the upper plane of metal closures and the upper plane of substrate are flushed.
Then on substrate He on metal closures, form graphene layer, the upper plane of the complete covering metal plug of this graphene layer.Preferably, this material that take metal closures is that Cu is example, the metal closures of this Cu material of take is that matrix is used CVD technique to form graphene layer, its concrete steps are: use the gaseous compound of the carbon containings such as methane as gaseous carbon source, at high temperature the carbon atom of described gaseous carbon source cracking growth is adsorbed in the upper surface of metal closures, and further forming continuous graphene film, described in one or more layers, graphene film is piled up and is formed graphene layer.This graphene layer is the complete upper plane of covering metal plug not only, also covers plane in the part of substrate.
In follow-up technique, can peel off formed graphene layer.Owing to being formed on the graphene layer in plane on metal closures, there is good crystal habit and performance, and the upper plane of metal closures can accurately be controlled its shape by etching technics, therefore above method forms the graphene layer of the well-crystallized form with given shape.Form and can be peeled off after described graphene layer and for making other semiconductor device.
In superincumbent two embodiment, the dielectric layer of the first embodiment and substrate can be collectively referred to as basic unit; In the second embodiment, there is no dielectric layer, and only have substrate, this substrate is equivalent to the basic unit of the first embodiment, therefore also referred to as basic unit.In this specification of the present invention, take one or more layers basic unit as example describes, in practical application, also can adopt the base layer structure of multilayer.That is, described basic unit can be single or multiple lift structure.
Semiconductor structure provided by the invention and manufacture method thereof are by being formed on Graphene crystallization in presumptive area, particularly form on local metal surface, increased the particle size of Graphene crystallization, and in conjunction with the step of optimization deposition Graphene, contribute to promote the uniformity of Graphene material, therefore promoted service behaviour and the stability of Graphene material in semiconductor structure.
Although describe in detail about example embodiment and advantage thereof, be to be understood that in the situation that do not depart from the protection range that spirit of the present invention and claims limit, can carry out various variations, substitutions and modifications to these embodiment.For other examples, when those of ordinary skill in the art should easily understand within keeping protection range of the present invention, the order of processing step can change.
In addition, range of application of the present invention is not limited to technique, mechanism, manufacture, material composition, means, method and the step of the specific embodiment of describing in specification.From disclosure of the present invention, as those of ordinary skill in the art, will easily understand, for the technique, mechanism, manufacture, material composition, means, method or the step that have existed or be about to develop at present later, wherein they carry out identical function or the identical result of acquisition cardinal principle of corresponding embodiment cardinal principle of describing with the present invention, according to the present invention, can apply them.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection range.
Claims (14)
1. a manufacture method for semiconductor structure, the method comprises:
A) provide basic unit;
B) described in etching, basic unit is formed with the opening (201) at the end;
C) form the metal closures (202) of filling described opening (201);
D) in described basic unit, form the graphene layer (300) contacting with the upper plane of described metal closures (202).
2. method according to claim 1, wherein, described basic unit is the sandwich construction that forms of dielectric layer (200) and substrate (100) or is a single-layer substrate.
3. method according to claim 2, wherein, when described basic unit be dielectric layer (200) and substrate (100) form sandwich construction time,
In described step b), the dielectric layer (200) of substrate (100) top forms the opening (201) that stops at the upper plane of substrate (100) described in etching, the upper plane of substrate (100) described in this opening (201) expose portion;
In described step c), the upper plane that the lower plane of this metal closures (202) and described substrate (100) expose electrically contacts.
4. according to the method described in claim 1 or 3, wherein step c) also comprises:
Carry out CMP PROCESS FOR TREATMENT, the upper plane of described metal closures (202) is flushed with the upper plane of described basic unit or dielectric layer (200).
5. method according to claim 1, wherein:
In described opening (201), be 1-100 μ m with the area in the upper parallel plane cross section of described basic unit
2.
6. method according to claim 1 and 2, wherein, the material of described metal closures (202) comprising:
W, Al, Cu, TiAl or its combination.
7. method according to claim 1 and 2, wherein, the material of described dielectric layer (200) comprising:
SiO
2, carbon doping SiO
2, BPSG, PSG, USG, Si
3n
4, low-k materials or its combination.
8. method according to claim 1, wherein:
Described graphene layer (300) is used CVD technique to form.
9. method according to claim 1, wherein:
After described step d), also comprise the step of peeling off described graphene layer.
10. a semiconductor structure, this semiconductor structure comprises basic unit, metal closures (202) and graphene layer (300), wherein:
Described metal closures (202) is embedded in described basic unit;
Described graphene layer (300) is formed on described basic unit and metal closures (202), and this graphene layer (300) contacts with the upper plane of described metal closures (202).
11. semiconductor structures according to claim 10, wherein:
Described basic unit is the sandwich construction of dielectric layer (200) and substrate (100) formation or is a single-layer substrate.
12. semiconductor structures according to claim 10, wherein:
The upper plane of described metal closures (202) flushes with the upper plane of described basic unit.
13. semiconductor structures according to claim 10, wherein:
In described metal closures (202), be 1-100 μ m with the area in the upper parallel plane cross section of described basic unit
2.
14. according to claim 10 to the semiconductor structure described in 13 any one, and wherein, the material of described metal closures (202) comprising:
W, Al, Cu, TiAl or its combination.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210298158.2A CN103632922A (en) | 2012-08-20 | 2012-08-20 | Semiconductor structure and manufacturing method thereof |
| PCT/CN2012/081513 WO2014029152A1 (en) | 2012-08-20 | 2012-09-17 | Semiconductor structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210298158.2A CN103632922A (en) | 2012-08-20 | 2012-08-20 | Semiconductor structure and manufacturing method thereof |
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| CN201210298158.2A Pending CN103632922A (en) | 2012-08-20 | 2012-08-20 | Semiconductor structure and manufacturing method thereof |
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| WO (1) | WO2014029152A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328708A (en) * | 2015-07-03 | 2017-01-11 | 三星电子株式会社 | Device including vertically aligned two-dimensional material and method of forming a vertically aligned two-dimensional material |
| CN110629188A (en) * | 2018-06-25 | 2019-12-31 | 新奥光伏能源有限公司 | Preparation method of graphene film and device containing graphene film |
| CN113496992A (en) * | 2020-04-01 | 2021-10-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method for forming semiconductor structure |
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| CN102376624A (en) * | 2010-08-11 | 2012-03-14 | 中国科学院微电子研究所 | Graphene device and manufacturing method thereof |
| US20120080796A1 (en) * | 2010-10-05 | 2012-04-05 | Kabushiki Kaisha Toshiba | Device |
| US20120080662A1 (en) * | 2010-10-05 | 2012-04-05 | Kabushiki Kaisha Toshiba | Graphene interconnection and method of manufacturing the same |
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- 2012-09-17 WO PCT/CN2012/081513 patent/WO2014029152A1/en active Application Filing
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| CN102376624A (en) * | 2010-08-11 | 2012-03-14 | 中国科学院微电子研究所 | Graphene device and manufacturing method thereof |
| US20120080796A1 (en) * | 2010-10-05 | 2012-04-05 | Kabushiki Kaisha Toshiba | Device |
| US20120080662A1 (en) * | 2010-10-05 | 2012-04-05 | Kabushiki Kaisha Toshiba | Graphene interconnection and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328708A (en) * | 2015-07-03 | 2017-01-11 | 三星电子株式会社 | Device including vertically aligned two-dimensional material and method of forming a vertically aligned two-dimensional material |
| CN110629188A (en) * | 2018-06-25 | 2019-12-31 | 新奥光伏能源有限公司 | Preparation method of graphene film and device containing graphene film |
| CN113496992A (en) * | 2020-04-01 | 2021-10-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method for forming semiconductor structure |
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| WO2014029152A1 (en) | 2014-02-27 |
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