WO2014027380A1 - Group iii nitride semiconductor element and method for manufacturing same - Google Patents
Group iii nitride semiconductor element and method for manufacturing same Download PDFInfo
- Publication number
- WO2014027380A1 WO2014027380A1 PCT/JP2012/005158 JP2012005158W WO2014027380A1 WO 2014027380 A1 WO2014027380 A1 WO 2014027380A1 JP 2012005158 W JP2012005158 W JP 2012005158W WO 2014027380 A1 WO2014027380 A1 WO 2014027380A1
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- WIPO (PCT)
- Prior art keywords
- layer
- group iii
- iii nitride
- nitride semiconductor
- plating
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 186
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 114
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 title abstract description 43
- 238000007747 plating Methods 0.000 claims abstract description 146
- 229910052723 transition metal Inorganic materials 0.000 claims abstract description 75
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- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
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- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
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- KERTUBUCQCSNJU-UHFFFAOYSA-L nickel(2+);disulfamate Chemical compound [Ni+2].NS([O-])(=O)=O.NS([O-])(=O)=O KERTUBUCQCSNJU-UHFFFAOYSA-L 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
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- 239000000523 sample Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
Definitions
- the present invention relates to a group III nitride semiconductor device and a manufacturing method thereof.
- Semiconductor devices include various devices such as field effect transistors (FETs) and light emitting diodes (LEDs).
- FETs field effect transistors
- LEDs light emitting diodes
- a III-V semiconductor composed of a compound of a group III element and a group V element is used.
- Group III nitride semiconductors using Al, Ga, In, etc. as group III elements and mainly using N as group V elements have a high melting point, a high dissociation pressure of nitrogen, and bulk single crystal growth is difficult. In general, it is formed by growing on a sapphire substrate because there is no cheap and conductive single crystal substrate.
- the light-emitting diode has conventionally been manufactured by sequentially growing an n-type group III nitride semiconductor layer, an active layer (light-emitting layer) and a p-type III on the sapphire substrate. A part of the semiconductor laminate composed of the group nitride semiconductor layer is removed to expose the n-type group III nitride semiconductor layer, and the exposed n-type group III nitride semiconductor layer and p-type group III nitride are exposed. It has been usual to employ a lateral structure in which an n-type electrode and a p-type electrode are arranged on a physical semiconductor layer and current flows in the lateral direction.
- a group III nitride semiconductor multilayer body including a light emitting layer is formed, and the semiconductor multilayer body is supported by a conductive support body.
- the technology for obtaining the LED chip is put to practical use by selectively dissolving the lift-off layer by chemical etching, peeling off the sapphire substrate (lift-off), and sandwiching the support body and the semiconductor laminate with a pair of electrodes. It has been studied.
- a growth substrate is peeled from an epitaxial layer by etching a lift-off layer made of a metal other than group III or a metal nitride.
- a lift-off layer made of a metal other than group III or a metal nitride.
- Patent Document 1 describes a method for manufacturing a group III nitride semiconductor vertical structure LED chip having no cracks in a light emitting layer, using the chemical lift-off method as described above.
- This document describes an example of forming a conductive support body mainly composed of Cu by growing Cu plating via a plating seed layer of Ni / Au / Cu on a group III nitride semiconductor multilayer body. (See Examples 23 to 25).
- the present inventors previously optimized the thickness of the conductive support and the group III nitride semiconductor layer in the international patent application (PCT / JP2012 / 003431), and thickened the Ni layer as the plating seed layer.
- a Ni-based alloy as a plating seed layer, a group III nitride semiconductor device in which cracks are unlikely to occur in the group III nitride semiconductor layer and a method for manufacturing the same are provided.
- the present invention is a group III nitride semiconductor device in which a group III nitride semiconductor layer is less likely to crack after being mounted on an arbitrary substrate, and an increase in forward voltage due to heating solder mounting is suppressed. It aims at providing the manufacturing method.
- the gist of the present invention is as follows. (1) a conductive support body including a main plating layer made of a first transition metal, the main material of which is the first transition metal; A plating seed layer on the conductive support; A group III nitride semiconductor layer on the plating seed layer, Between the main plating layer and the group III nitride semiconductor layer, at least one of the conductive support body and the plating seed layer includes the first layer made of the first transition metal and the first transition.
- a group III nitride semiconductor device comprising a laminate in which second layers made of a second transition metal different from a metal are alternately laminated a plurality of times.
- a conductive support body including a main Cu plating layer and mainly made of Cu; A plating seed layer on the conductive support; A group III nitride semiconductor layer on the plating seed layer, Between the main Cu plating layer and the group III nitride semiconductor layer, at least one of the conductive support body and the plating seed layer is a first layer made of a first transition metal and the first transition.
- a group III nitride semiconductor device comprising a laminate in which second layers made of a second transition metal different from a metal are alternately laminated a plurality of times.
- the first and second transition metals are selected from the group consisting of Cu, Ti, Ni, Fe, Co, Cr, Au, and a platinum group, and the second transition metal is more than the first transition metal.
- a first step of forming a group III nitride semiconductor layer on the growth substrate A second step of forming a plating seed layer on the group III nitride semiconductor layer; A third step of forming a conductive support body including a main plating layer made of the first transition metal on the plating seed layer and using the first transition metal as a main material; And a fourth step of peeling the growth substrate from the group III nitride semiconductor layer,
- a first layer made of the first transition metal is formed on the conductive support body or the plating seed layer between the main plating layer and the group III nitride semiconductor layer.
- a method of manufacturing a group III nitride semiconductor device comprising: forming a laminate in which second layers made of a second transition metal different from the first transition metal are alternately laminated a plurality of times.
- a first step of forming a group III nitride semiconductor layer on the growth substrate A second step of forming a plating seed layer on the group III nitride semiconductor layer; A third step of forming a conductive support body including a main Cu plating layer and containing Cu as a main material on the plating seed layer; And a fourth step of peeling the growth substrate from the group III nitride semiconductor layer, In the second or third step, a first layer made of a first transition metal is formed on the conductive support body or the plating seed layer between the main Cu plating layer and the group III nitride semiconductor layer. And a method of manufacturing a group III nitride semiconductor device, comprising: forming a laminate in which second layers made of a second transition metal different from the first transition metal are alternately laminated a plurality of times.
- a group III nitride semiconductor device in which a group III nitride semiconductor layer is hardly cracked after being mounted on an arbitrary substrate, and an increase in forward voltage due to mounting by heating solder is suppressed, and a method for manufacturing the same. Can be provided.
- FIG. 1 is a schematic perspective view of one group III nitride semiconductor device 100 according to an embodiment of the present invention.
- FIG. 2 is a schematic cross-sectional view for explaining the layer structure of a conductive support body and a plating seed layer of a group III nitride semiconductor device 100 according to an embodiment of the present invention, where FIG. A second example is shown.
- FIGS. 4A to 4I are schematic side cross-sectional views showing the steps of the method for manufacturing the group III nitride semiconductor device 100 according to the embodiment of the present invention.
- FIGS. 3A to 3D are schematic top views showing some steps of the method for manufacturing the semiconductor element 100 according to the embodiment of the present invention shown in FIG.
- FIGS. 4A to 4D are schematic top views similar to FIG. 3 except that the application mode of the second resist 116 is changed.
- FIG. 3 is a schematic perspective view of a group III nitride semiconductor device assembly 200 before singulation in one embodiment of the present invention.
- a group III nitride semiconductor device 100 (hereinafter simply referred to as “device 100”) according to an embodiment of the present invention will be described with reference to FIG.
- the element 100 includes a conductive support body 122A mainly made of Cu (copper), a plating seed layer 114 on the conductive support body 122A, and a semiconductor as a group III nitride semiconductor layer on the plating seed layer 114. And a structure portion 110.
- An upper electrode 128 is provided on the semiconductor structure 110, and the lower electrode serves as the conductive support body 122A, whereby the element 100 is formed.
- the conductive support body 122A is mainly formed by a plating method such as wet plating or dry plating, as will be described later. Although other methods may be included, it is preferable to form a necessary thickness for the support body because a plating method can be formed at low cost.
- the plating seed layer 114 is a layer for growing the conductive support body 122A thereon.
- FIG. 2A shows a first example of the layer configuration
- FIG. 2B shows a second example of the layer configuration
- the conductive support body 122 ⁇ / b> A includes a main Cu plating layer 130.
- the “main Cu plating layer” means the thickest Cu plating layer among the Cu plating layers in the conductive support body.
- the conductive support body 122A is mainly made of Cu.
- Cu is the main material” means that the thickness of the Cu plating layer occupies 70% or more of the thickness of the conductive support body 122A, and the Cu component in the conductive support body occupies 70% or more.
- the semiconductor structure 110 is not particularly limited as long as it is a group III nitride semiconductor layer, and may be a single layer or a laminate of two or more layers. If the semiconductor structure 110 includes the light emitting layer, it becomes an LED, and if it does not, it becomes another semiconductor element.
- the semiconductor structure 110 can be epitaxially grown on the lift-off layer 102 described later with reference to FIG. 2 by, for example, MOCVD.
- MQW multiple quantum well
- a group III nitride semiconductor layer of a type is sequentially laminated to form the semiconductor structure 110, and the device 100 of the present invention can be a group III nitride semiconductor vertical structure LED chip.
- the first conductivity type may be n-type and the second conductivity type may be p-type, or vice versa.
- the thermal expansion coefficient is different between the conductive support body 122A mainly made of Cu and the semiconductor structure portion 110 made of the group III nitride semiconductor layer.
- the mounting temperature is generally 100 to 300 ° C.
- the device falls to the operating temperature (generally -40 to 85 ° C).
- the characteristic configuration of the element 100 of the present embodiment is between the main Cu plating layer 130 and the semiconductor structure 110 of the conductive support body 122A.
- the conductive support body 122A or the plating seed layer 114 includes a predetermined laminated body.
- FIG. 2A shows an example in which the plating seed layer 114 is composed of a laminate 134.
- the conductive support body 122A includes a main Cu plating layer 130 and a Ni plating layer 132 thereon.
- the laminated body 134 constituting the plating seed layer is formed by alternately laminating a first layer 134A made of the first transition metal and a second layer 134B made of the second transition metal different from the first transition metal a plurality of times. It becomes.
- FIG. 2B illustrates an example in which the conductive support body 122A includes a stacked body 136.
- the conductive support body 122A includes a main Cu plating layer 130 and a laminated body 136 thereon.
- the laminated body 136 is formed by alternately laminating a first layer 136A made of a first transition metal and a second layer 136B made of a second transition metal different from the first transition metal a plurality of times.
- the plating seed layer 114 can have a two-layer structure of a Cu layer 114A and a Ti layer 114B, for example.
- Such a stacked body 134, 136 has a remarkable effect that even if the element 100 is mounted on an arbitrary substrate, cracks are hardly generated in the group III nitride semiconductor layer.
- the effect of such an effect is not necessarily clear, but the laminated body can relieve the residual stress between the conductive support body and the semiconductor structure composed of the group III nitride semiconductor layer, which can be generated by thermal shock. It is speculated that this is possible.
- the present inventors have found that the effect of relaxation of the residual stress by the laminate is very high, and as a result, it is possible to sufficiently suppress an increase in forward voltage (Vf) due to thermal shock, The present invention has been completed.
- the first and second transition metals are selected from the group consisting of Cu, Ti, Ni, Fe, Co, Cr, Au, and the platinum group, and the second transition metal is more heated than the first transition metal.
- Each is preferably selected so that an expansion coefficient (also referred to as a linear expansion coefficient) becomes small.
- the first transition metal is Cu
- the other transition metal has a lower thermal expansion coefficient than Cu.
- the second transition metal may be any other transition metal except Cu.
- Au or platinum group is good for preventing oxidation of the conductive support body, and may be partially used. Moreover, you may use the alloy which combined the metal in the said group for a 1st layer and a 2nd layer. If the second transition metal is selected from a group other than the above group, the difference in thermal expansion coefficient between the first transition metal and the second transition metal becomes large, which may cause peeling.
- the first layer of the laminate is the first transition metal
- the second layer has a thermal expansion coefficient higher than that of the first transition metal.
- the first transition metal is Cu and the second transition metal is a transition metal other than Cu. This is because the thermal expansion can be moderately reduced by using a transition metal other than Cu for one of the laminated bodies against the thermal expansion of the main Cu plating layer 130.
- the laminated body 136 when the conductive support body 122A includes the laminated body 136, the laminated body 136 preferably has Cu and Ni as the first and second transition metals, respectively. This is because by using Ni having a smaller thermal expansion coefficient than Cu, the thermal expansion can be moderately reduced, and both Cu and Ni can be easily plated, and the device can be manufactured at low cost. Other choices include Ni and Cr, Cu and Cr, and Cu and Ni-Fe-Co alloys for the first and second transition metals, respectively. A form in which a third transition metal is incorporated in between may be used, such as Cu / Ni / Co.
- the stacked body 134 when the plating seed layer 114 includes the stacked body 134, the stacked body 134 preferably has Cu and Ti as the first and second transition metals, respectively. If the first layer 134A on the plating growth side is made of Cu, the conductive support body can be preferably grown by plating. If the second layer 134B on the semiconductor structure 110 side is made of Ti, the adhesion to the semiconductor structure portion is made. This is because a sufficient amount can be secured. Moreover, thermal expansion can be gently reduced by using Ti whose thermal expansion coefficient is smaller than Cu. Other choices include Ni and Ti, Cu and Ni, Au and Ni, Au and Cr, Cu and Cr, etc., respectively, for the first and second transition metals. A form in which a third transition metal is incorporated in between may be used, such as Cu / Ni / Ti.
- the thickness of the main Cu plating layer 130 is 140 ⁇ m or more, and further includes a Ni plating layer having a thickness of 5 ⁇ m or more.
- the thickness of the Ni plating layer 132 is set to 5 ⁇ m or more.
- the second layer 136B constituting the stacked body 136 may be a Ni plating layer having a thickness of 5 ⁇ m or more. .
- the total thickness of the conductive support body 122A is preferably 400 ⁇ m or less from the viewpoint of not greatly degrading the throughput.
- the thickness of the semiconductor structure 110 is preferably 6 to 20 ⁇ m. This is because by setting the thickness to 6 ⁇ m or more, it is possible to secure the strength of the semiconductor structure 110 and further suppress the generation of cracks, and by setting the thickness to 20 ⁇ m or less, the throughput is not greatly deteriorated.
- FIG. 3A is a schematic top view of the state shown in FIG. 3B, and the II cross section in FIG. 4A corresponds to FIG. 3B. Note that the cross-sectional views of FIG. 3 other than FIG. 3B are also in the same position.
- FIG. 4B is a top view of the state shown in FIG.
- FIG. 4C is a top view of the state shown in FIG.
- FIG. 4D is a cross-sectional view of the state shown in FIG.
- a lift-off layer 104 and a group III nitride semiconductor layer 106 are formed in this order on a growth substrate 102 (first step).
- a part of the group III nitride semiconductor layer 106 is removed, and a groove 108 in which a part of the growth substrate 102 is exposed at the bottom is formed into a mesh.
- a plurality of semiconductor structure portions 110 made of a group III nitride semiconductor layer having a transverse cross-sectional shape arranged in a vertical and horizontal direction are formed by forming a lattice shape.
- a plating seed layer 114 is formed on the semiconductor structure 110 and the first resist 112 by a sputtering method or an electron beam evaporation method (second step).
- the plating seed layer 114 may be formed by alternately changing the target.
- a lattice-shaped thin film resist 116 is formed above the groove 108 and on the plating seed layer 114.
- a portion 118 exposed without being covered with the second resist 116 is formed.
- a plating layer is formed from the exposed portion 118, and a plurality of semiconductor structures 110 are integrally supported on the plating seed layer 114.
- the support body 122 is formed (third step).
- the conductive support body 122 includes a laminated body (not shown in FIG. 3)
- the conductive support body 122 may be formed by alternately changing the plating bath.
- the conductive support body 122 is formed so as to have a recess 120 on the resist 116 and a hole 124 on the crossing portion of the resist 116, which will be described in detail later.
- the resist 116 and the resist 112 are removed, and a void 126 leading from the hole 124 to the lift-off layer 104 is formed.
- the resist 116 is dissolved by supplying a liquid for dissolving the resist such as acetone from the holes 124.
- the plating seed layer portion sandwiched between the resist 116 and the resist 112 under the hole 124 is mechanically or chemically removed following the removal of the resist 116. Thereafter, when the liquid such as acetone reaches the resist 112, the resist 112 can also be removed.
- the lift-off layer 104 is removed by etching by supplying an etching solution through the holes 124 and the gaps 126.
- the growth substrate 102 is peeled from the semiconductor structure 110 (fourth step, FIG. 3H).
- the conductive support bodies 122 are cut along the recesses 120 between the semiconductor structure portions 110, so that each is supported by the cut conductive support bodies 122A.
- a plurality of elements 100 having the semiconductor structure 110 are separated. It can be seen that the broken line in FIG. 4D is a cutting line and is along the recess 120.
- the upper electrode 128 is formed on the peeling surface side of the semiconductor structure 110.
- the conductive support body 122A also serves as the lower electrode.
- the thickness of the conductive support body 122A and each layer thereof can be adjusted by the growth time of plating, and the thickness of the semiconductor structure 110 can be adjusted by the epitaxial growth time. It can be measured by observing.
- the thickness is the thickness at the center of the element 100.
- the manufacturing method shown in FIGS. 3 and 4 can easily form a hole for supplying an etching solution used in the chemical lift-off method in the conductive support body, and can easily cut the conductive support body (ie, singulation). It is also preferable in that it can be performed. That is, as the plating grows from the exposed portion 118, adjacent plating layers formed on the resist 116 are bonded to each other. As a result, the conductive support body 112 can integrally support the plurality of semiconductor structure portions 110. At that time, a recess 120 as shown in FIG. 2F is formed on the resist 116. By cutting along the recess 120 with a dicing device, it can be more easily cut than a conductive support body having no recess.
- the resist 116 is formed in a lattice shape (see FIG. 3C). For this reason, the hole 124 can be formed on the intersection of the resist 116.
- the elongation rate and shape of the plating layer can be controlled by the type, temperature, and current of the plating bath.
- the application mode is not particularly limited as long as the resist 116 is formed in a mesh shape.
- 5A to 5D are schematic top views similar to FIG. 4 except that the application mode of the resist 116 is changed.
- the shape of the exposed portion of the plating seed is not a square as shown in FIG. 4C, but may be rounded, chamfered, dented or the like at the corners of the square as shown in FIG. 5C. In this case, as shown in FIG. 5D, the diameter of the hole 124 after plating can be made larger than that in FIG.
- FIG. 6 is a schematic perspective view of the semiconductor element combination 200 before singulation, which can be obtained by the above manufacturing method.
- the semiconductor device combination 200 includes a growth substrate 102, a lift-off layer 104 on the growth substrate 102, a plurality of semiconductor structures 110 independent of each other via a groove 108 on the lift-off layer 104, and the plurality A conductive support body 122 that integrally supports the semiconductor structure 110 of the semiconductor device.
- the conductive support body 122 has a recess 120 at a position above the groove 108, and a groove is formed on the intersection of the groove 108.
- a hole 124 leading to 108 is provided.
- a plating seed layer 114 is provided on the semiconductor structure 110.
- the semiconductor element combination 200 is a wafer in the state shown in FIG. That is, in this specification, the “semiconductor element assembly” means a wafer in a state before lift-off in which a plurality of semiconductor structures are sandwiched between a growth substrate and a conductive support and are integrally supported.
- the lift-off layer 104 can be removed by supplying an etching solution to the groove 108 through the hole 124.
- the support body 122 can be more easily cut along the recess 120.
- the growth substrate 102 is preferably a sapphire substrate or an AlN template substrate in which an AlN film is formed on a sapphire substrate. What is necessary is just to select suitably according to the kind of lift-off layer to form, the composition of Al, Ga, In of a group III nitride semiconductor layer, the quality of a LED chip, cost, etc.
- the chemical lift-off method is preferable because a metal other than Group III such as CrN and ScN and a metal nitride buffer layer can be dissolved by chemical selective etching. It is preferable to form the film by sputtering, vacuum deposition, ion plating, or MOCVD. Usually, the thickness of the lift-off layer 104 is about 2 to 100 nm.
- the lift-off layer 104 cannot be etched with an etchant in a subsequent process, and therefore this removal is performed at least until the growth substrate or the lift-off layer is exposed. Shall. In the above-described embodiment, the lift-off layer 104 is removed at the bottom of the groove 108 and the growth substrate 102 is completely exposed.
- the cross-sectional shape of the semiconductor structure 110 is shown as a quadrangle, but the cross-sectional shape of the semiconductor structure 110 is not particularly limited, and may be a circle or a polygon such as a triangle or a hexagon.
- the cross-sectional shape of the semiconductor structure part 110 is a polygon, by forming a resist 116 in a mesh shape along the grooves 108 around the polygonal semiconductor structure 110, A hole 124 communicating with the groove 108 can be formed, and a recess 120 can be formed in the conductive support body 122 at a position above the groove 108.
- the semiconductor structure 110 is preferably aligned so that the groove 108 can be easily cut by a laser dicing apparatus.
- the width of the groove 108 at the straight portion is preferably within the range of 40 to 200 ⁇ m, and more preferably 60 to 100 ⁇ m. This is because when the thickness is 40 ⁇ m or more, the etching solution can be sufficiently smoothly supplied to the groove 108, and when the thickness is 200 ⁇ m or less, the loss of the light emitting area can be minimized.
- the resist 112 is used as a filler for the groove 108, and then all the resist 112 is removed together with the lattice-like resist 116 to form the void 126.
- the present invention is not limited to this, and the filler May be removed to form a gap for supplying etching.
- the shape of the cross section of the semiconductor structure portion 110 is a quadrangle, as described in PCT / JP2011 / 005485, only one side surface of each semiconductor structure portion 110 is closed with a resist as a filler, and the remaining three The side can also be plugged with a metal as a filler.
- etching proceeds from the groove side closed with the resist toward the opposite groove side.
- any material may be used instead of the resist 112.
- a metal that is not used for the conductive support body 122 and the plating seed layer 114, or an insulator such as SiO 2 can be used.
- an etching solution corresponding to the material may be selected.
- resist formation and plating process By appropriately adjusting the width and thickness of the resist 116 and the shape at the intersection of the resist 116, the thickness of the conductive support body 122 at the recessed position 120, the thickness of the conductive support body 122 on the semiconductor structure 110, and The dimension of the hole 124 can be set as appropriate. Moreover, you may employ
- the thickness of the conductive support body 122 at the position of the recess 120 is not particularly limited, but is preferably a thickness that can be easily cut by a dicing apparatus, for example, 120 ⁇ m or less.
- the resist 116 is formed on the plating seed layer 114.
- the plating seed layer corresponding to the position where the hole is formed may be removed in advance, and the resist 116 may be formed in contact with the resist 112.
- an ohmic electrode layer in contact with each of the plurality of semiconductor layers 106 between the main surface of the plurality of semiconductor structures 110 and the plating seed layer 114.
- a reflective layer is further formed between the ohmic electrode layer and the plating seed layer 114, or the ohmic electrode layer also functions as the reflective layer.
- dry film forming methods such as vacuum deposition, ion plating, and sputtering can be used.
- the ohmic electrode layer can be formed of a metal having a large work function, for example, a noble metal such as Pd, Pt, Rh, Au, Ag, or Co, Ni. Further, since the reflection layer has a high reflectance such as Rh, it can also be used as the ohmic electrode layer. However, when the light emitting region is visible light, Ag or Al layer is used, and when the light emitting region is ultraviolet region, Rh is used. More preferably, a Ru layer or the like is used. In addition, since the ohmic electrode layer and the reflective layer are as thin as 0.2 ⁇ m at the maximum, even if they are treated as a part of the conductive support body, the effect of the present invention is not affected.
- a noble metal such as Pd, Pt, Rh, Au, Ag, or Co, Ni.
- Rh since the reflection layer has a high reflectance such as Rh, it can also be used as the ohmic electrode layer. However, when the light emitting region is visible light, Ag or Al layer is used
- Etching solutions usable in the chemical lift-off method of the present invention include, when the lift-off layer is CrN, ceric ammonium nitrate solution or ferricyanium potassium-based solution, such as hydrochloric acid, nitric acid, organic acid, when the lift-off layer is ScN.
- ceric ammonium nitrate solution or ferricyanium potassium-based solution such as hydrochloric acid, nitric acid, organic acid
- known etchants having selectivity can be given.
- the lift-off process is not limited to the above-described chemical lift-off method, and a photochemical lift-off method or a laser lift-off method may be used.
- the surface of the semiconductor structure 110 exposed after the lift-off is cleaned by wet cleaning.
- the thickness of the semiconductor structure portion may be adjusted by cutting a predetermined amount by dry etching and / or wet etching.
- an n-type ohmic electrode and a bonding pad electrode as upper electrodes are formed by a lift-off method using a resist as a mask.
- Al, Cr, Ti, Ni, Pt, Au, etc. are used as the electrode material, and Ti, Pt, Au, etc. are formed on the ohmic electrode and bonding pad as a cover layer to reduce wiring resistance and wire bond. Improve adhesion.
- a protective film (insulating film) such as SiO 2 or SiN may be provided on the exposed side surface and surface (excluding the bonding pad surface) of the semiconductor structure 110.
- the semiconductor structure portions 110 are cut using, for example, a blade dicer or a laser dicing apparatus.
- Example 1 The semiconductor device shown in FIG. 1 was manufactured by the manufacturing method shown in FIGS. Specifically, first, a lift-off layer (CrN layer, thickness: 18 nm) was formed on a growth sapphire substrate by forming a metal Cr layer by sputtering and performing heat treatment in an ammonia atmosphere.
- a lift-off layer CrN layer, thickness: 18 nm
- a buffer layer composition: GaN, thickness: 4 ⁇ m
- an n-GaN layer thickness: 6 ⁇ m
- a light emitting layer AlInGaN-based MQW layer, thickness: 0.1 ⁇ m
- a p-GaN layer thickness: 0.2 ⁇ m
- the thickness of the group III nitride semiconductor layer at this stage is 10.3 ⁇ m.
- a part of the semiconductor layer is removed by dry etching to form a lattice-shaped groove so that a part of the sapphire substrate is exposed, thereby forming a plurality of semiconductor structure parts independent of each other having a square cross section Formed.
- the width of the semiconductor structure was 1350 ⁇ m, and the arrangement of the individual elements was a grid pattern.
- the pitch between elements is 1500 ⁇ m, that is, the groove width is 150 ⁇ m.
- an ohmic electrode layer (Ag, thickness: 0.1 ⁇ m) was formed on the semiconductor structure portion by EB vapor deposition.
- a plating seed layer was formed on the surface of the semiconductor structure, on the p-ohmic electrode layer, and on the resist surface.
- a Ti layer thinness: 0.02 ⁇ m
- a Cu layer thinness: 0.15 ⁇ m
- a laminate in which the first layer is a Cu layer and the second layer is a Ti layer is a plating seed layer.
- Ni plating uses a nickel sulfamate solution: Ni (NH 2 SO 3 ) 2 , the liquid temperature is in the range of 50-60 ° C., the current is 38.5 A, the plating growth time is 2 hours, and the deposition rate is 20 ⁇ m / hr.
- Cu plating is electroplating using a copper sulfate electrolyte, the temperature of the solution is in the range of 25-30 ° C., the current is 67.4 A, the plating growth time is 4.3 hours, and the deposition rate is 35 ⁇ m / hr. Met. At this time, the conductive support body was bonded on the resist, and a plurality of semiconductor structure portions were integrally supported.
- Dents and holes as shown in FIGS. 3 (F) and 4 (D) were formed in the formed conductive support body.
- the thickness of the thinnest portion of the recess was 30 to 50 ⁇ m, that is, about 30 ⁇ m at the position near the hole and about 50 ⁇ m at the thickest position away from the hole.
- the distance between the opposite vertices was about 77 ⁇ m.
- the hole for supplying the etching solution can be easily formed only by forming the plating layer.
- the lift-off layer was removed by a chemical lift-off method using a CrN selective etching solution, and the sapphire substrate was peeled off.
- the surface of the n-GaN layer was roughened by performing a treatment for 10 minutes at 60 ° C. using a 6 mol / L KOH solution, and then a resist was applied to form an n-electrode patterning, followed by EB vapor deposition.
- Ti / Al / Ni / Au, each thickness: 0.02 ⁇ m / 1.5 ⁇ m / 0.02 ⁇ m / 2 ⁇ m was formed, and the resist was removed by lift-off with acetone.
- a support tape (ultraviolet curing tape) is attached to the back side of the conductive support body, the conductive support body is fixed to the table of the laser dicing machine, and the conductive support body is laser-cut from the semiconductor structure side along the recess. 25 group III nitride semiconductor devices were obtained.
- ⁇ Evaluation 2 Increase in forward voltage (Vf) due to thermal shock>
- the forward voltage Vf of each of the 25 elements was measured before and after heating on the hot plate at room temperature and an operating current of 350 mA with an auto probe measuring device.
- the average value of 25 elements of ⁇ Vf obtained by subtracting Vf before heating from Vf after heating was 0.06V.
- Example 1 except that the plating seed layer is formed by electron beam evaporation and the layer structure is a Ti layer (thickness: 0.02 ⁇ m) and a Cu layer (thickness: 0.45 ⁇ m) in this order from the semiconductor structure side.
- a group III nitride semiconductor device was fabricated by the method described above. That is, the laminate was not formed in this comparative example.
- Example 2 A group III nitride semiconductor is manufactured in the same manner as in Example 1 except that the plating seed layer is composed of a Ti layer (thickness: 0.02 ⁇ m) and a Cu layer (thickness: 0.45 ⁇ m) in order from the semiconductor structure side. An element was produced. That is, the laminate was not formed in this comparative example.
- Example 2 A group III nitride semiconductor device was produced in the same manner as in Example 1 except that the layer configuration of the plating seed layer and the conductive support was changed as follows.
- the plating seed layer was a Ti layer (thickness: 0.02 ⁇ m) and a Cu layer (thickness: 0.45 ⁇ m) in this order from the semiconductor structure side.
- the conductive support body the Ni plating layer (thickness 10 ⁇ m) and the Cu plating layer (thickness 10 ⁇ m) are alternately grown twice in order from the plating seed layer side, and the Cu plating layer (thickness 150 ⁇ m) is further grown by plating.
- the conductive support body includes a laminate in which the first layer is a Cu layer and the second layer is a Ni layer. The thickness of each layer was adjusted by the plating growth time.
- Example 3 Example 2 except that the laminated body included in the conductive support was formed by alternately growing the Ni plating layer (thickness 5 ⁇ m) and the Cu plating layer (thickness 5 ⁇ m) four times in order from the plating seed layer side. A group III nitride semiconductor device was fabricated in the same manner.
- Comparative Examples 1 and 2 and Examples 2 and 3 were also evaluated 1 and 2 as in Example 1. The results are shown in Tables 1 and 2.
- Table 1 shows the effect of forming a laminate on the plating seed layer.
- Table 2 shows the effect of forming a laminated body on the conductive support body.
- a group III nitride semiconductor device in which a group III nitride semiconductor layer is hardly cracked after being mounted on an arbitrary substrate, and an increase in forward voltage due to mounting by heating solder is suppressed, and a method for manufacturing the same. Can be provided.
- Group III Nitride Semiconductor Device 102 Growth Substrate 104 Lift-off Layer 106 Group III Nitride Semiconductor Layer 108 Groove 110 Semiconductor Structure 112 Resist (Filler) 114 plating seed layer 116 resist 118 exposed portion of plating seed layer 120 recess 122 conductive support body 122A cut conductive support body 122B corner of conductive support body 122C outer peripheral portion opposite to semiconductor structure portion 124 hole 126 gap 128
- Upper electrode 130 Main Cu plating layer 132 Ni plating layer 134,136 Laminated body 134A, 136A First layer 134B, 136B Second layer 200 Semiconductor element assembly
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Abstract
Description
(1)第1の遷移金属からなる主のメッキ層を含み、該第1の遷移金属を主材料とする導電性サポート体と、
該導電性サポート体上のメッキシード層と、
該メッキシード層上のIII族窒化物半導体層と、を有し、
前記主のメッキ層と前記III族窒化物半導体層との間において、前記導電性サポート体および前記メッキシード層の少なくとも一方が、前記第1の遷移金属からなる第1層および前記第1の遷移金属と異なる第2の遷移金属からなる第2層を交互に複数回積層した積層体を含むことを特徴とするIII族窒化物半導体素子。 In order to achieve the above object, the gist of the present invention is as follows.
(1) a conductive support body including a main plating layer made of a first transition metal, the main material of which is the first transition metal;
A plating seed layer on the conductive support;
A group III nitride semiconductor layer on the plating seed layer,
Between the main plating layer and the group III nitride semiconductor layer, at least one of the conductive support body and the plating seed layer includes the first layer made of the first transition metal and the first transition. A group III nitride semiconductor device comprising a laminate in which second layers made of a second transition metal different from a metal are alternately laminated a plurality of times.
該導電性サポート体上のメッキシード層と、
該メッキシード層上のIII族窒化物半導体層と、を有し、
前記主のCuメッキ層と前記III族窒化物半導体層との間において、前記導電性サポート体および前記メッキシード層の少なくとも一方が、第1の遷移金属からなる第1層および前記第1の遷移金属と異なる第2の遷移金属からなる第2層を交互に複数回積層した積層体を含むことを特徴とするIII族窒化物半導体素子。 (2) a conductive support body including a main Cu plating layer and mainly made of Cu;
A plating seed layer on the conductive support;
A group III nitride semiconductor layer on the plating seed layer,
Between the main Cu plating layer and the group III nitride semiconductor layer, at least one of the conductive support body and the plating seed layer is a first layer made of a first transition metal and the first transition. A group III nitride semiconductor device comprising a laminate in which second layers made of a second transition metal different from a metal are alternately laminated a plurality of times.
前記III族窒化物半導体層上に、メッキシード層を形成する第2工程と、
前記メッキシード層上に、第1の遷移金属からなる主のメッキ層を含み、該第1の遷移金属を主材料とする導電性サポート体を形成する第3工程と、
前記成長用基板を前記III族窒化物半導体層から剥離する第4工程と、を有し、
前記第2または第3工程では、前記主のメッキ層と前記III族窒化物半導体層との間に、前記導電性サポート体または前記メッキシード層に、前記第1の遷移金属からなる第1層および前記第1の遷移金属と異なる第2の遷移金属からなる第2層を交互に複数回積層した積層体を形成することを特徴とするIII族窒化物半導体素子の製造方法。 (8) a first step of forming a group III nitride semiconductor layer on the growth substrate;
A second step of forming a plating seed layer on the group III nitride semiconductor layer;
A third step of forming a conductive support body including a main plating layer made of the first transition metal on the plating seed layer and using the first transition metal as a main material;
And a fourth step of peeling the growth substrate from the group III nitride semiconductor layer,
In the second or third step, a first layer made of the first transition metal is formed on the conductive support body or the plating seed layer between the main plating layer and the group III nitride semiconductor layer. And a method of manufacturing a group III nitride semiconductor device, comprising: forming a laminate in which second layers made of a second transition metal different from the first transition metal are alternately laminated a plurality of times.
前記III族窒化物半導体層上に、メッキシード層を形成する第2工程と、
前記メッキシード層上に、主のCuメッキ層を含み、Cuを主材料とする導電性サポート体を形成する第3工程と、
前記成長用基板を前記III族窒化物半導体層から剥離する第4工程と、を有し、
前記第2または第3工程では、前記主のCuメッキ層と前記III族窒化物半導体層との間に、前記導電性サポート体または前記メッキシード層に、第1の遷移金属からなる第1層および前記第1の遷移金属と異なる第2の遷移金属からなる第2層を交互に複数回積層した積層体を形成することを特徴とするIII族窒化物半導体素子の製造方法。 (9) a first step of forming a group III nitride semiconductor layer on the growth substrate;
A second step of forming a plating seed layer on the group III nitride semiconductor layer;
A third step of forming a conductive support body including a main Cu plating layer and containing Cu as a main material on the plating seed layer;
And a fourth step of peeling the growth substrate from the group III nitride semiconductor layer,
In the second or third step, a first layer made of a first transition metal is formed on the conductive support body or the plating seed layer between the main Cu plating layer and the group III nitride semiconductor layer. And a method of manufacturing a group III nitride semiconductor device, comprising: forming a laminate in which second layers made of a second transition metal different from the first transition metal are alternately laminated a plurality of times.
成長用基板102は、サファイア基板またはサファイア基板上にAlN膜を形成したAlNテンプレート基板を用いるのが好ましい。形成するリフトオフ層の種類やIII族窒化物半導体層のAl,Ga,Inの組成、LEDチップの品質、コストなどにより適宜選択すればよい。 (Semiconductor layer formation process)
The
III族窒化物半導体層106の一部の除去には、ドライエッチング法を用いるのが好ましい。これは、III族窒化物半導体層106のエッチングの終点を再現性良く制御できるからである。また、III族窒化物半導体層106が繋がった状態であると、後工程においてエッチング液でリフトオフ層104をエッチングすることができないため、この除去は、少なくとも成長用基板またはリフトオフ層が露出するまで行うものとする。上記の本実施形態では、溝108の底部ではリフトオフ層104は除去され、成長用基板102が完全に露出する例を示した。 (Groove formation process)
It is preferable to use a dry etching method to remove a part of the group III
図1の実施形態では、溝108の充填剤としてレジスト112を用い、その後全てのレジスト112を格子状のレジスト116とともに除去して空隙126を形成したが、本発明はこれに限らず、充填剤の一部を除去して、エッチング供給用の空隙を形成するものでもよい。例えば、半導体構造部110の横断面の形状が四角形の場合、PCT/JP2011/005485に記載するように、各半導体構造部110の1つの側面のみを充填剤としてのレジストで塞ぎ、残りの3つの側面は充填剤としての金属で塞ぐこともできる。そして、充填剤除去工程では、金属は除去せずレジストのみを除去し、レジストで埋められた溝のみにエッチング供給用の空隙を形成することができる。この場合、図1(H)のリフトオフ工程では、レジストで塞いだ溝側からその反対側の溝側に向かってエッチングが進行する。 (Groove filling / plating seed layer formation process)
In the embodiment of FIG. 1, the resist 112 is used as a filler for the
レジスト116の幅や厚み、およびレジスト116の交差部位における形状を適宜調整することで、凹み位置120での導電性サポート体122の厚み、半導体構造部110上の導電性サポート体122の厚み、および孔124の寸法を適宜設定することができる。また、網目状のレジストを形成する工程と、導電性サポート体を形成する工程とを複数回繰り返す多段階メッキ工程を採用してもよい。 (Resist formation and plating process)
By appropriately adjusting the width and thickness of the resist 116 and the shape at the intersection of the resist 116, the thickness of the
本発明におけるケミカルリフトオフ法に使用可能なエッチング液としては、リフトオフ層がCrNの場合、硝酸第二セリウムアンモン溶液やフェリシアンカリウム系の溶液など、リフトオフ層がScNの場合、塩酸、硝酸、有機酸など選択性のある公知のエッチング液を挙げることができる。また、リフトオフ工程は上記のケミカルリフトオフ法に限らず、フォトケミカルリフトオフ法やレーザーリフトオフ法を用いる場合でもよいことは明らかである。 (Lift-off process)
Etching solutions usable in the chemical lift-off method of the present invention include, when the lift-off layer is CrN, ceric ammonium nitrate solution or ferricyanium potassium-based solution, such as hydrochloric acid, nitric acid, organic acid, when the lift-off layer is ScN. For example, known etchants having selectivity can be given. Further, it is obvious that the lift-off process is not limited to the above-described chemical lift-off method, and a photochemical lift-off method or a laser lift-off method may be used.
個片化工程では、半導体構造部110間を例えばブレードダイサーやレーザーダイシング装置を用いて切断する。 (Individualization process)
In the singulation process, the
図3および図4に示す製造方法で、図1に示す半導体素子を作製した。具体的には、まず、成長用のサファイア基板上に、スパッタ法により金属Cr層を形成しアンモニア雰囲気中で熱処理することによりリフトオフ層(CrN層、厚み:18nm)を形成した。その後、リフトオフ層上にIII族窒化物半導体層として、バッファ層(組成:GaN、厚み:4μm)、n-GaN層(厚み:6μm)、発光層(AlInGaN系MQW層、厚み:0.1μm)、p-GaN層(厚み:0.2μm)を順次積層した。この段階でのIII族窒化物半導体層の厚みは、10.3μmとなる。 (Example 1)
The semiconductor device shown in FIG. 1 was manufactured by the manufacturing method shown in FIGS. Specifically, first, a lift-off layer (CrN layer, thickness: 18 nm) was formed on a growth sapphire substrate by forming a metal Cr layer by sputtering and performing heat treatment in an ammonia atmosphere. Thereafter, as a group III nitride semiconductor layer on the lift-off layer, a buffer layer (composition: GaN, thickness: 4 μm), an n-GaN layer (thickness: 6 μm), a light emitting layer (AlInGaN-based MQW layer, thickness: 0.1 μm) Then, a p-GaN layer (thickness: 0.2 μm) was sequentially laminated. The thickness of the group III nitride semiconductor layer at this stage is 10.3 μm.
このようにして得た25個のIII族窒化物半導体素子を300℃のホットプレート上に5分間静置後、III族窒化物半導体層の表面を観察し、クラックが発生しているか否かを判定した。本実施例では、25個のいずれもクラックが発生していなかった(クラック発生率0%)。 <Evaluation 1: Crack generation due to thermal shock>
The 25 group III nitride semiconductor devices thus obtained were allowed to stand on a hot plate at 300 ° C. for 5 minutes, and then the surface of the group III nitride semiconductor layer was observed to determine whether cracks had occurred. Judged. In this example, none of the 25 cracks occurred (crack occurrence rate 0%).
オートプローブ測定装置にて、室温にて、動作電流350mAで、25個の素子について、上記ホットプレートでの加熱の前後で、それぞれ順方向電圧Vfを測定した。本実施例では、加熱後のVfから加熱前のVfを差し引いたΔVfの25個の素子の平均値は、0.06Vであった。 <Evaluation 2: Increase in forward voltage (Vf) due to thermal shock>
The forward voltage Vf of each of the 25 elements was measured before and after heating on the hot plate at room temperature and an operating current of 350 mA with an auto probe measuring device. In this example, the average value of 25 elements of ΔVf obtained by subtracting Vf before heating from Vf after heating was 0.06V.
メッキシード層を電子ビーム蒸着法により形成し、層構成を半導体構造部側から順にTi層(厚み:0.02μm)およびCu層(厚み:0.45μm)とした以外は、実施例1と同様の方法でIII族窒化物半導体素子を作製した。すなわち、本比較例では積層体を形成しなかった。 (Comparative Example 1)
Example 1 except that the plating seed layer is formed by electron beam evaporation and the layer structure is a Ti layer (thickness: 0.02 μm) and a Cu layer (thickness: 0.45 μm) in this order from the semiconductor structure side. A group III nitride semiconductor device was fabricated by the method described above. That is, the laminate was not formed in this comparative example.
メッキシード層の層構成を半導体構造部側から順にTi層(厚み:0.02μm)およびCu層(厚み:0.45μm)とした以外は、実施例1と同様の方法でIII族窒化物半導体素子を作製した。すなわち、本比較例では積層体を形成しなかった。 (Comparative Example 2)
A group III nitride semiconductor is manufactured in the same manner as in Example 1 except that the plating seed layer is composed of a Ti layer (thickness: 0.02 μm) and a Cu layer (thickness: 0.45 μm) in order from the semiconductor structure side. An element was produced. That is, the laminate was not formed in this comparative example.
メッキシード層および導電性サポート体の層構成を以下のように変更した以外は、実施例1と同様の方法でIII族窒化物半導体素子を作製した。まず、メッキシード層は、半導体構造部側から順にTi層(厚み:0.02μm)およびCu層(厚み:0.45μm)とした。次に、導電性サポート体は、メッキシード層側から順にNiメッキ層(厚み10μm)およびCuメッキ層(厚み10μm)を交互に2回メッキ成長させ、さらにCuメッキ層(厚み150μm)をメッキ成長させた。すなわち、本実施例では、導電性サポート体が、第1層がCu層、第2層がNi層の積層体を含む。各層の厚みはメッキ成長時間により調整した。 (Example 2)
A group III nitride semiconductor device was produced in the same manner as in Example 1 except that the layer configuration of the plating seed layer and the conductive support was changed as follows. First, the plating seed layer was a Ti layer (thickness: 0.02 μm) and a Cu layer (thickness: 0.45 μm) in this order from the semiconductor structure side. Next, as for the conductive support body, the Ni plating layer (thickness 10 μm) and the Cu plating layer (thickness 10 μm) are alternately grown twice in order from the plating seed layer side, and the Cu plating layer (thickness 150 μm) is further grown by plating. I let you. In other words, in this embodiment, the conductive support body includes a laminate in which the first layer is a Cu layer and the second layer is a Ni layer. The thickness of each layer was adjusted by the plating growth time.
導電性サポート体に含まれる積層体を、メッキシード層側から順にNiメッキ層(厚み5μm)およびCuメッキ層(厚み5μm)を交互に4回メッキ成長させて形成した以外は、実施例2と同様の方法でIII族窒化物半導体素子を作製した。 (Example 3)
Example 2 except that the laminated body included in the conductive support was formed by alternately growing the Ni plating layer (thickness 5 μm) and the Cu plating layer (thickness 5 μm) four times in order from the plating seed layer side. A group III nitride semiconductor device was fabricated in the same manner.
102 成長用基板
104 リフトオフ層
106 III族窒化物半導体層
108 溝
110 半導体構造部
112 レジスト(充填材)
114 メッキシード層
116 レジスト
118 メッキシード層の露出部位
120 凹み
122 導電性サポート体
122A 切断された導電性サポート体
122B 導電性サポート体のコーナー
122C 半導体構造部と反対側の外周部
124 孔
126 空隙
128 上部電極
130 主のCuメッキ層
132 Niメッキ層
134,136 積層体
134A,136A 第1層
134B,136B 第2層
200 半導体素子結合体
100 Group III
114
Claims (9)
- 第1の遷移金属からなる主のメッキ層を含み、該第1の遷移金属を主材料とする導電性サポート体と、
該導電性サポート体上のメッキシード層と、
該メッキシード層上のIII族窒化物半導体層と、を有し、
前記主のメッキ層と前記III族窒化物半導体層との間において、前記導電性サポート体および前記メッキシード層の少なくとも一方が、前記第1の遷移金属からなる第1層および前記第1の遷移金属と異なる第2の遷移金属からなる第2層を交互に複数回積層した積層体を含むことを特徴とするIII族窒化物半導体素子。 A conductive support body including a main plating layer made of a first transition metal, the main material of which is the first transition metal;
A plating seed layer on the conductive support;
A group III nitride semiconductor layer on the plating seed layer,
Between the main plating layer and the group III nitride semiconductor layer, at least one of the conductive support body and the plating seed layer includes the first layer made of the first transition metal and the first transition. A group III nitride semiconductor device comprising a laminate in which second layers made of a second transition metal different from a metal are alternately laminated a plurality of times. - 主のCuメッキ層を含み、Cuを主材料とする導電性サポート体と、
該導電性サポート体上のメッキシード層と、
該メッキシード層上のIII族窒化物半導体層と、を有し、
前記主のCuメッキ層と前記III族窒化物半導体層との間において、前記導電性サポート体および前記メッキシード層の少なくとも一方が、第1の遷移金属からなる第1層および前記第1の遷移金属と異なる第2の遷移金属からなる第2層を交互に複数回積層した積層体を含むことを特徴とするIII族窒化物半導体素子。 A conductive support including a main Cu plating layer and Cu as a main material;
A plating seed layer on the conductive support;
A group III nitride semiconductor layer on the plating seed layer,
Between the main Cu plating layer and the group III nitride semiconductor layer, at least one of the conductive support body and the plating seed layer is a first layer made of a first transition metal and the first transition. A group III nitride semiconductor device comprising a laminate in which second layers made of a second transition metal different from a metal are alternately laminated a plurality of times. - 前記第1および第2の遷移金属は、Cu,Ti,Ni,Fe,Co,Cr,Auおよび白金族からなる群から、前記第2の遷移金属が前記第1の遷移金属よりも熱膨張係数が小さくなるように、それぞれ選択される請求項1または2に記載のIII族窒化物半導体素子。 The first and second transition metals are selected from the group consisting of Cu, Ti, Ni, Fe, Co, Cr, Au, and a platinum group, and the second transition metal has a thermal expansion coefficient higher than that of the first transition metal. The group III nitride semiconductor device according to claim 1, wherein each is selected so as to be small.
- 前記第1の遷移金属がCuである請求項3に記載のIII族窒化物半導体素子。 The group III nitride semiconductor device according to claim 3, wherein the first transition metal is Cu.
- 前記導電性サポート体が、前記第1および第2の遷移金属がそれぞれCuおよびNiである前記積層体を含む請求項1~4のいずれか1項に記載のIII族窒化物半導体素子。 The group III nitride semiconductor device according to any one of claims 1 to 4, wherein the conductive support body includes the stacked body in which the first and second transition metals are Cu and Ni, respectively.
- 前記メッキシード層が、前記第1および第2の遷移金属がそれぞれCuおよびTiである前記積層体を含む請求項1~5のいずれか1項に記載のIII族窒化物半導体素子。 The group III nitride semiconductor device according to any one of claims 1 to 5, wherein the plating seed layer includes the stacked body in which the first and second transition metals are Cu and Ti, respectively.
- 前記導電性サポート体は、前記主のCuメッキ層の厚みが140μm以上であり、さらに厚み5μm以上のNiメッキ層を含む請求項2に記載のIII族窒化物半導体素子。 The group III nitride semiconductor device according to claim 2, wherein the conductive support body includes a Ni plating layer having a thickness of the main Cu plating layer of 140 µm or more and a thickness of 5 µm or more.
- 成長用基板上にIII族窒化物半導体層を形成する第1工程と、
前記III族窒化物半導体層上に、メッキシード層を形成する第2工程と、
前記メッキシード層上に、第1の遷移金属からなる主のメッキ層を含み、該第1の遷移金属を主材料とする導電性サポート体を形成する第3工程と、
前記成長用基板を前記III族窒化物半導体層から剥離する第4工程と、を有し、
前記第2または第3工程では、前記主のメッキ層と前記III族窒化物半導体層との間に、前記導電性サポート体または前記メッキシード層に、前記第1の遷移金属からなる第1層および前記第1の遷移金属と異なる第2の遷移金属からなる第2層を交互に複数回積層した積層体を形成することを特徴とするIII族窒化物半導体素子の製造方法。 A first step of forming a group III nitride semiconductor layer on the growth substrate;
A second step of forming a plating seed layer on the group III nitride semiconductor layer;
A third step of forming a conductive support body including a main plating layer made of the first transition metal on the plating seed layer and using the first transition metal as a main material;
And a fourth step of peeling the growth substrate from the group III nitride semiconductor layer,
In the second or third step, a first layer made of the first transition metal is formed on the conductive support body or the plating seed layer between the main plating layer and the group III nitride semiconductor layer. And a method of manufacturing a group III nitride semiconductor device, comprising: forming a laminate in which second layers made of a second transition metal different from the first transition metal are alternately laminated a plurality of times. - 成長用基板上にIII族窒化物半導体層を形成する第1工程と、
前記III族窒化物半導体層上に、メッキシード層を形成する第2工程と、
前記メッキシード層上に、主のCuメッキ層を含み、Cuを主材料とする導電性サポート体を形成する第3工程と、
前記成長用基板を前記III族窒化物半導体層から剥離する第4工程と、を有し、
前記第2または第3工程では、前記主のCuメッキ層と前記III族窒化物半導体層との間に、前記導電性サポート体または前記メッキシード層に、第1の遷移金属からなる第1層および前記第1の遷移金属と異なる第2の遷移金属からなる第2層を交互に複数回積層した積層体を形成することを特徴とするIII族窒化物半導体素子の製造方法。
A first step of forming a group III nitride semiconductor layer on the growth substrate;
A second step of forming a plating seed layer on the group III nitride semiconductor layer;
A third step of forming a conductive support body including a main Cu plating layer and containing Cu as a main material on the plating seed layer;
And a fourth step of peeling the growth substrate from the group III nitride semiconductor layer,
In the second or third step, a first layer made of a first transition metal is formed on the conductive support body or the plating seed layer between the main Cu plating layer and the group III nitride semiconductor layer. And a method of manufacturing a group III nitride semiconductor device, comprising: forming a laminate in which second layers made of a second transition metal different from the first transition metal are alternately laminated a plurality of times.
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