JP5936696B2 - Group III nitride semiconductor device and manufacturing method thereof - Google Patents

Group III nitride semiconductor device and manufacturing method thereof Download PDF

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JP5936696B2
JP5936696B2 JP2014530395A JP2014530395A JP5936696B2 JP 5936696 B2 JP5936696 B2 JP 5936696B2 JP 2014530395 A JP2014530395 A JP 2014530395A JP 2014530395 A JP2014530395 A JP 2014530395A JP 5936696 B2 JP5936696 B2 JP 5936696B2
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iii nitride
nitride semiconductor
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JPWO2014027380A1 (en
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明煥 ▲チョ▼
明煥 ▲チョ▼
錫雨 李
錫雨 李
鳥羽 隆一
隆一 鳥羽
嘉孝 門脇
嘉孝 門脇
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BBSA Ltd
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Description

本発明は、III族窒化物半導体素子およびその製造方法に関する。   The present invention relates to a group III nitride semiconductor device and a method for manufacturing the same.

半導体素子には、電界効果トランジスタ(FET)、発光ダイオード(LED)などの各種デバイスがある。これらには、例えば、III族元素とV族元素との化合物からなるIII−V族半導体が用いられる。   Semiconductor devices include various devices such as field effect transistors (FETs) and light emitting diodes (LEDs). For these, for example, a group III-V semiconductor composed of a compound of a group III element and a group V element is used.

III族元素としてAl,Ga,In等を用い、V族元素として主にNを用いたIII族窒化物半導体は、高融点で窒素の解離圧が高くバルク単結晶成長が困難であり、大口径で安価な導電性単結晶基板が無いという理由から、サファイア基板上に成長させることにより形成するのが一般的である。   Group III nitride semiconductors using Al, Ga, In, etc. as group III elements and mainly using N as group V elements have a high melting point, a high dissociation pressure of nitrogen, and bulk single crystal growth is difficult. In general, it is formed by growing on a sapphire substrate because there is no cheap and conductive single crystal substrate.

しかしながら、サファイア基板は絶縁性であって電流が流れないため、発光ダイオードは従来、サファイア基板上に順に成長させたn型のIII族窒化物半導体層、活性層(発光層)およびp型のIII族窒化物半導体層からなる半導体積層体の一部を除去してn型のIII族窒化物半導体層を露出させ、この露出させたn型のIII族窒化物半導体層およびp型のIII族窒化物半導体層の上にn型電極およびp型電極をそれぞれ配置して、電流を横方向に流す横型構造を採用するのが通常であった。   However, since the sapphire substrate is insulative and no current flows, the light-emitting diode has conventionally been manufactured by sequentially growing an n-type group III nitride semiconductor layer, an active layer (light-emitting layer) and a p-type III on the sapphire substrate. A part of the semiconductor laminate composed of the group nitride semiconductor layer is removed to expose the n-type group III nitride semiconductor layer, and the exposed n-type group III nitride semiconductor layer and p-type group III nitride are exposed. It has been usual to employ a lateral structure in which an n-type electrode and a p-type electrode are arranged on a physical semiconductor layer and current flows in the lateral direction.

これに対し、近年、サファイア基板などの成長用基板上にリフトオフ層を形成後、発光層を含むIII族窒化物半導体積層体を形成し、この半導体積層体を導電性のサポート体で支持した後、リフトオフ層を化学的なエッチングにより選択的に溶解してサファイア基板を剥離(リフトオフ)し、これらサポート体と半導体積層体を一対の電極で挟むことで、LEDチップを得る技術が実用に向けて研究されている。   On the other hand, in recent years, after forming a lift-off layer on a growth substrate such as a sapphire substrate, a group III nitride semiconductor multilayer body including a light emitting layer is formed, and the semiconductor multilayer body is supported by a conductive support body. The technology for obtaining the LED chip is put to practical use by selectively dissolving the lift-off layer by chemical etching, peeling off the sapphire substrate (lift-off), and sandwiching the support body and the semiconductor laminate with a pair of electrodes. It has been studied.

このような縦型構造のIII族窒化物半導体LEDチップを作製するには、例えば、III族以外の金属や金属窒化物からなるリフトオフ層をエッチングすることでエピタキシャル層から成長用基板を剥離する一般的なケミカルリフトオフ法や、エッチング中に紫外光等の光を照射し、リフトオフ層を活性化させながらエッチングを行うフォトケミカルリフトオフ法がある。これらは、特定のエッチング溶液に浸漬して、リフトオフ層をエッチングによって溶解することによりエピタキシャル層から成長用基板をリフトオフする方法であり、本明細書において「ケミカルリフトオフ法」と総称される。   In order to fabricate a group III nitride semiconductor LED chip having such a vertical structure, for example, a growth substrate is peeled from an epitaxial layer by etching a lift-off layer made of a metal other than group III or a metal nitride. There are known chemical lift-off methods and photo-chemical lift-off methods in which etching is performed while irradiating light such as ultraviolet light during etching and activating the lift-off layer. These are methods in which the growth substrate is lifted off from the epitaxial layer by dipping in a specific etching solution and dissolving the lift-off layer by etching, and are collectively referred to as “chemical lift-off method” in this specification.

特許文献1には、上記のようなケミカルリフトオフ法を用いた、発光層にクラックのないIII族窒化物半導体縦型構造LEDチップの製造方法が記載されている。この文献では、III族窒化物半導体積層体上にNi/Au/Cuのメッキシード層を介してCuメッキを成長させて、Cuを主材料とする導電性サポート体を形成する例が記載されている(実施例23〜25参照)。   Patent Document 1 describes a method for manufacturing a group III nitride semiconductor vertical structure LED chip having no cracks in a light emitting layer, using the chemical lift-off method as described above. This document describes an example of forming a conductive support body mainly composed of Cu by growing Cu plating via a plating seed layer of Ni / Au / Cu on a group III nitride semiconductor multilayer body. (See Examples 23 to 25).

国際公開第2011/055462号International Publication No. 2011/055462

しかしながら、特許文献1に記載の、Cuを主材料とする導電性サポート体上にIII族窒化物半導体層が形成されたIII族窒化物半導体縦型構造LEDチップにおいて、このLEDチップをランプ・モジュール基板に加熱ハンダ実装すると、III族窒化物半導体層にクラックが発生するという問題があることが判明した。この課題は、III族窒化物半導体縦型構造LEDチップにかかわらず、その他のIII族窒化物半導体素子にもあてはまる。   However, in the group III nitride semiconductor vertical structure LED chip described in Patent Document 1 in which a group III nitride semiconductor layer is formed on a conductive support body mainly composed of Cu, the LED chip is used as a lamp module. It has been found that there is a problem that cracks occur in the group III nitride semiconductor layer when the soldering is mounted on the substrate. This problem applies to other group III nitride semiconductor devices regardless of the group III nitride semiconductor vertical structure LED chip.

そこで本発明者らは、先に国際特許出願(PCT/JP2012/003431)において、導電性サポート体およびIII族窒化物半導体層の厚さを最適化すること、メッキシード層としてのNi層を厚くしたり、メッキシード層としてNi系合金を用いたりすることによって、III族窒化物半導体層にクラックが生じにくいIII族窒化物半導体素子およびその製造方法を提供した。   Therefore, the present inventors previously optimized the thickness of the conductive support and the group III nitride semiconductor layer in the international patent application (PCT / JP2012 / 003431), and thickened the Ni layer as the plating seed layer. In addition, by using a Ni-based alloy as a plating seed layer, a group III nitride semiconductor device in which cracks are unlikely to occur in the group III nitride semiconductor layer and a method for manufacturing the same are provided.

しかしながら、本発明者らのさらなる検討により、このようにクラックを生じにくくしたIII族窒化物半導体素子であっても、加熱ハンダ実装を想定した300℃の熱衝撃を与えると、順方向電圧(Vf)が増大してしまうことが判明した。   However, according to further studies by the present inventors, even in the case of a group III nitride semiconductor element in which cracks are hardly generated as described above, when a thermal shock at 300 ° C. assuming heating solder mounting is applied, the forward voltage (Vf ) Increased.

そこで本発明は、上記課題に鑑み、任意の基板に実装後にIII族窒化物半導体層にクラックが生じにくく、かつ、加熱ハンダ実装による順方向電圧の増加が抑制されたIII族窒化物半導体素子およびその製造方法を提供することを目的とする。   Therefore, in view of the above problems, the present invention is a group III nitride semiconductor device in which a group III nitride semiconductor layer is less likely to crack after being mounted on an arbitrary substrate, and an increase in forward voltage due to heating solder mounting is suppressed. It aims at providing the manufacturing method.

上記目的を達成するため、本発明の要旨構成は以下のとおりである。
(1)主のCuメッキ層を含み、Cuを主材料とする導電性サポート体と、
該導電性サポート体上のメッキシード層と、
該メッキシード層上のオーミック電極層と、
該オーミック電極層上のIII族窒化物半導体層と、を有し、
前記主のCuメッキ層と前記メッキシード層との間において、Cuからなる第1層およびNiからなる第2層を交互に複数回積層した積層体を含むことを特徴とするIII族窒化物半導体素子。
In order to achieve the above object, the gist of the present invention is as follows.
(1) a main for Cu plating layer, and a conductive support of Cu as the main material,
A plating seed layer on the conductive support;
An ohmic electrode layer on the plating seed layer;
A group III nitride semiconductor layer on the ohmic electrode layer ,
A group III nitride semiconductor comprising a laminate in which a first layer made of Cu and a second layer made of Ni are alternately laminated a plurality of times between the main Cu plating layer and the plating seed layer element.

(2)主のCuメッキ層を含み、Cuを主材料とする導電性サポート体と、
該導電性サポート体上のメッキシード層と、
該メッキシード層上のオーミック電極層と、
該オーミック電極層上のIII族窒化物半導体層と、を有し、
前記主のCuメッキ層と前記オーミック電極層との間において、前記導電性サポート体および前記メッキシード層の少なくとも一方が、Cuからなる第1層ならびに、Cuよりも熱膨張係数の小さいTi,Ni,Fe,Co,Cr,Auおよび白金族からなる群から選択される遷移金属からなる第2層を交互に複数回積層した積層体を含み、
前記導電性サポート体は、前記主のCuメッキ層の厚みが140μm以上であり、さらに厚み5μm以上のNiメッキ層を含むことを特徴とするIII族窒化物半導体素子。
(2) a conductive support body including a main Cu plating layer and mainly made of Cu;
A plating seed layer on the conductive support;
An ohmic electrode layer on the plating seed layer;
A group III nitride semiconductor layer on the ohmic electrode layer ,
In between the ohmic electrode layer and the main of Cu plating layer, at least one of the conductive support and the plating seed layer, a first layer made of Cu and having a small coefficient of thermal expansion than Cu Ti, Ni , look-containing Fe, Co, Cr, a laminate formed by laminating a plurality of times alternately second layer comprising a transition metal selected from the group consisting of Au and platinum group,
The conductive support body, the main of and the thickness of the Cu plating layer is 140μm or more, more Group III nitride semiconductor device according to claim including Mukoto a Ni plating layer or thickness of 5 [mu] m.

)前記導電性サポート体の前記遷移金属がNiであり、前記導電性サポート体が前記積層体を含む上記(2)に記載のIII族窒化物半導体素子。 (3) wherein the transition metal is Ni der the conductive support is, the conductive support comprises said laminate, III nitride semiconductor device according to the above (2).

)前記メッキシード層の前記遷移金属がTiであり、前記メッキシード層が前記積層体を含む上記(2)に記載のIII族窒化物半導体素子。 (4) wherein the transition metal is Ti der the plating seed layer is, the plating seed layer comprises the laminate, III nitride semiconductor device according to the above (2).

)成長用基板上にIII族窒化物半導体層を形成する第1工程と、
前記III族窒化物半導体層上に、オーミック電極層およびメッキシード層をこの順に形成する第2工程と、
前記メッキシード層上に、主のCuメッキ層を含み、Cuを主材料とする導電性サポート体を形成する第3工程と、
前記成長用基板を前記III族窒化物半導体層から剥離する第4工程と、を有し、
記第3工程では、前記主のCuメッキ層と前記メッキシード層との間に、Cuからなる第1層およびNiからなる第2層を交互に複数回積層した積層体を形成することを特徴とするIII族窒化物半導体素子の製造方法。
( 5 ) a first step of forming a group III nitride semiconductor layer on the growth substrate;
A second step of forming an ohmic electrode layer and a plating seed layer in this order on the group III nitride semiconductor layer;
A third step of forming a conductive support body including a main Cu plating layer on the plating seed layer, the main material being Cu ;
And a fourth step of peeling the growth substrate from the group III nitride semiconductor layer,
Prior Symbol third step, during the main of Cu plating layer and the plating seed layer, forming a laminate formed by laminating a plurality of times alternately second layer of the first layer and Ni of Cu A method for producing a group III nitride semiconductor device.

)成長用基板上にIII族窒化物半導体層を形成する第1工程と、
前記III族窒化物半導体層上に、オーミック電極層およびメッキシード層をこの順に形成する第2工程と、
前記メッキシード層上に、主のCuメッキ層を含み、Cuを主材料とする導電性サポート体を形成する第3工程と、
前記成長用基板を前記III族窒化物半導体層から剥離する第4工程と、を有し、
前記第2または第3工程では、前記主のCuメッキ層と前記III族窒化物半導体層との間に、前記導電性サポート体または前記メッキシード層に、Cuからなる第1層およびCuよりも熱膨張係数の小さいTi,Ni,Fe,Co,Cr,Auおよび白金族からなる群から選択される遷移金属からなる第2層を交互に複数回積層した積層体を形成し、
前記導電性サポート体は、前記主のCuメッキ層の厚みが140μm以上であり、さらに厚み5μm以上のNiメッキ層を含むことを特徴とするIII族窒化物半導体素子の製造方法。
( 6 ) a first step of forming a group III nitride semiconductor layer on the growth substrate;
A second step of forming an ohmic electrode layer and a plating seed layer in this order on the group III nitride semiconductor layer;
A third step of forming a conductive support body including a main Cu plating layer and containing Cu as a main material on the plating seed layer;
And a fourth step of peeling the growth substrate from the group III nitride semiconductor layer,
In the second or third step, between the main of the Cu plating layer and the group III nitride semiconductor layer, the conductive support or the plating seed layer, than the first layer and Cu of Cu Forming a laminate in which a second layer made of a transition metal selected from the group consisting of Ti, Ni, Fe, Co, Cr, Au and a platinum group having a small thermal expansion coefficient is alternately laminated a plurality of times ;
The method of manufacturing a group III nitride semiconductor device, wherein the conductive support body includes a Ni plating layer having a thickness of the main Cu plating layer of 140 μm or more and further a thickness of 5 μm or more .

本発明によれば、任意の基板に実装後にIII族窒化物半導体層にクラックが生じにくく、かつ、加熱ハンダ実装による順方向電圧の増加が抑制されたIII族窒化物半導体素子およびその製造方法を提供することができる。   According to the present invention, there is provided a group III nitride semiconductor device in which a group III nitride semiconductor layer is hardly cracked after being mounted on an arbitrary substrate, and an increase in forward voltage due to mounting by heating solder is suppressed, and a method for manufacturing the same. Can be provided.

本発明の一実施形態にかかる、個片化した1つのIII族窒化物半導体素子100の模式斜視図である。1 is a schematic perspective view of one group III nitride semiconductor device 100 according to an embodiment of the present invention. 本発明の一実施形態にかかるIII族窒化物半導体素子100の導電性サポート体およびメッキシード層の層構成を説明する摸式断面図であり、(A)はその第1例、(B)はその第2例を示す。FIG. 2 is a schematic cross-sectional view illustrating the layer configuration of a conductive support body and a plating seed layer of a group III nitride semiconductor device 100 according to an embodiment of the present invention, where (A) is a first example, and (B) is a first example. A second example is shown. (A)〜(I)は、本発明の一実施形態にかかるIII族窒化物半導体素子100の製造方法の各工程を模式側面断面図で示したものである。(A)-(I) show each process of the manufacturing method of the group III nitride semiconductor element 100 concerning one Embodiment of this invention with a schematic side sectional drawing. (A)〜(D)は、図3に示した、本発明の一実施形態にかかる半導体素子100の製造方法の一部の工程を模式上面図で示したものである。(A)-(D) show the one part process of the manufacturing method of the semiconductor element 100 concerning one Embodiment of this invention shown in FIG. 3 with a schematic top view. (A)〜(D)は、第2レジスト116の塗布態様を変更した以外は図3と同様の模式上面図である。(A)-(D) are the same schematic top views as FIG. 3 except having changed the application | coating aspect of the 2nd resist 116. FIG. 本発明の一実施形態における、個片化前のIII族窒化物半導体素子結合体200の模式斜視図である。FIG. 3 is a schematic perspective view of a group III nitride semiconductor device assembly 200 before singulation in one embodiment of the present invention.

以下、図面を参照しつつ、ケミカルリフトオフ法を用いて成長用基板を剥離する場合を例に、本発明の実施形態を説明する。なお、図面では、説明の便宜上、導電性サポート体に対してリフトオフ層、III族窒化物半導体層およびメッキシード層を実状とは異なる比率で誇張して示す。   Hereinafter, an embodiment of the present invention will be described with reference to the drawings, taking as an example the case where a growth substrate is peeled off using a chemical lift-off method. In the drawings, for convenience of explanation, the lift-off layer, the group III nitride semiconductor layer, and the plating seed layer are exaggerated at a ratio different from the actual state with respect to the conductive support body.

本発明の一実施形態にかかるIII族窒化物半導体素子100(以下、単に「素子100」という。)を、図1により説明する。素子100は、Cu(銅)を主材料とする導電性サポート体122Aと、この導電性サポート体122A上のメッキシード層114と、このメッキシード層114上のIII族窒化物半導体層としての半導体構造部110と、を有する。半導体構造部110上には上部電極128が設けられ、下部電極は導電性サポート体122Aが兼ねることで、素子100が成立する。   A group III nitride semiconductor device 100 (hereinafter simply referred to as “device 100”) according to an embodiment of the present invention will be described with reference to FIG. The element 100 includes a conductive support body 122A mainly made of Cu (copper), a plating seed layer 114 on the conductive support body 122A, and a semiconductor as a group III nitride semiconductor layer on the plating seed layer 114. And a structure portion 110. An upper electrode 128 is provided on the semiconductor structure 110, and the lower electrode serves as the conductive support body 122A, whereby the element 100 is formed.

本実施形態において、導電性サポート体122Aは、後述するように、主に湿式メッキまたは乾式メッキなどのメッキ法により形成される。他の方法を含んでも良いが、サポート体に必要な厚さを形成するにはメッキ法が安価に形成できるため好ましい。メッキシード層114は、その上に導電性サポート体122Aをメッキ成長させるための層である。   In the present embodiment, the conductive support body 122A is mainly formed by a plating method such as wet plating or dry plating, as will be described later. Although other methods may be included, it is preferable to form a necessary thickness for the support body because a plating method can be formed at low cost. The plating seed layer 114 is a layer for growing the conductive support body 122A thereon.

本実施形態は、主のメッキ層がCuからなる場合を示すものである。素子100の導電性サポート体およびメッキシード層の層構成を図2に示す。図2(A)は層構成の第1例、図2(B)は層構成の第2例である。図2(A)および(B)に示すように、導電性サポート体122Aは、主のCuメッキ層130を含む。ここで、本明細書において「主のCuメッキ層」とは、導電性サポート体中のCuメッキ層のうち最も厚いCuメッキ層を意味する。また、導電性サポート体122Aは、Cuを主材料とする。ここで、「Cuを主材料とする」とは、Cuメッキ層の厚みが導電性サポート体122Aの厚みの7割以上を占め、導電性サポート体中のCu成分が7割以上を占めることをいう。   This embodiment shows a case where the main plating layer is made of Cu. The layer structure of the conductive support body and the plating seed layer of the element 100 is shown in FIG. FIG. 2A shows a first example of the layer configuration, and FIG. 2B shows a second example of the layer configuration. As shown in FIGS. 2A and 2B, the conductive support body 122 </ b> A includes a main Cu plating layer 130. Here, in this specification, the “main Cu plating layer” means the thickest Cu plating layer among the Cu plating layers in the conductive support body. The conductive support body 122A is mainly made of Cu. Here, “Cu is the main material” means that the thickness of the Cu plating layer occupies 70% or more of the thickness of the conductive support body 122A, and the Cu component in the conductive support body occupies 70% or more. Say.

半導体構造部110は、III族窒化物半導体層であれば層構成は特に限定されず、1層でもよいし、2層以上の積層体であってもよい。半導体構造部110が発光層を含めばLEDとなり、含まない場合は他の半導体素子となる。半導体構造部110は、例えばMOCVD法により、図2で後述するリフトオフ層102上にエピタキシャル成長させることができる。例えば、リフトオフ層102上に、第1伝導型のIII族窒化物半導体層、III族窒化物半導体により多重量子井戸(MQW)構造を形成した発光層、および第1伝導型とは異なる第2伝導型のIII族窒化物半導体層を順次積層して半導体構造部110として、本発明の素子100をIII族窒化物半導体縦型構造LEDチップとすることができる。この場合、第1伝導型をn型とし、第2伝導型をp型としてもよいし、この逆であってもよい。   The semiconductor structure 110 is not particularly limited as long as it is a group III nitride semiconductor layer, and may be a single layer or a laminate of two or more layers. If the semiconductor structure 110 includes the light emitting layer, it becomes an LED, and if it does not, it becomes another semiconductor element. The semiconductor structure 110 can be epitaxially grown on the lift-off layer 102 described later with reference to FIG. 2 by, for example, MOCVD. For example, a group III nitride semiconductor layer of the first conductivity type on the lift-off layer 102, a light emitting layer in which a multiple quantum well (MQW) structure is formed of a group III nitride semiconductor, and a second conductivity different from the first conductivity type A group III nitride semiconductor layer of a type is sequentially laminated to form the semiconductor structure 110, and the device 100 of the present invention can be a group III nitride semiconductor vertical structure LED chip. In this case, the first conductivity type may be n-type and the second conductivity type may be p-type, or vice versa.

このようにCuを主材料とする導電性サポート体122AとIII族窒化物半導体層からなる半導体構造部110とでは、熱膨張係数が異なる。ここで、素子をランプ・モジュール基板に加熱ハンダ実装するためには、ハンダを加熱・溶融する必要がある。用いるハンダにも依るが、一般的に実装温度は100〜300℃となる。実装後、素子は使用温度(一般的には−40〜85℃)まで下がる。このような熱衝撃が加わることによって、熱膨張係数が異なる導電性サポート体とIII族窒化物半導体層からなる半導体構造部との間に残留応力が発生し、III族窒化物半導体層のクラックの原因となるものと思われる。   Thus, the thermal expansion coefficient differs between the conductive support body 122A mainly composed of Cu and the semiconductor structure portion 110 made of a group III nitride semiconductor layer. Here, it is necessary to heat and melt the solder in order to mount the element on the lamp / module board by heating solder. Although it depends on the solder to be used, the mounting temperature is generally 100 to 300 ° C. After mounting, the device is lowered to the operating temperature (generally −40 to 85 ° C.). By applying such a thermal shock, a residual stress is generated between the conductive support body having a different thermal expansion coefficient and the semiconductor structure composed of the group III nitride semiconductor layer, and cracks in the group III nitride semiconductor layer are generated. It seems to be a cause.

ここで、本実施形態の素子100の特徴的構成は、図2(A)および(B)に示すように、導電性サポート体122Aの主のCuメッキ層130と半導体構造部110との間において、導電性サポート体122Aまたはメッキシード層114が所定の積層体を含むことである。   Here, as shown in FIGS. 2A and 2B, the characteristic configuration of the element 100 of the present embodiment is between the main Cu plating layer 130 and the semiconductor structure 110 of the conductive support body 122A. The conductive support body 122A or the plating seed layer 114 includes a predetermined laminated body.

図2(A)は、メッキシード層114が積層体134からなる例を示している。導電性サポート体122Aは、主のCuメッキ層130と、その上のNiメッキ層132からなる。そして、メッキシード層を構成する積層体134は、第1の遷移金属からなる第1層134Aおよび第1の遷移金属と異なる第2の遷移金属からなる第2層134Bを交互に複数回積層してなる。   FIG. 2A shows an example in which the plating seed layer 114 is composed of a stacked body 134. The conductive support body 122A includes a main Cu plating layer 130 and a Ni plating layer 132 thereon. The laminated body 134 constituting the plating seed layer is formed by alternately laminating a first layer 134A made of the first transition metal and a second layer 134B made of the second transition metal different from the first transition metal a plurality of times. It becomes.

図2(B)は、導電性サポート体122Aが積層体136を含む例を示している。導電性サポート体122Aは、主のCuメッキ層130と、その上の積層体136からなる。積層体136は、第1の遷移金属からなる第1層136Aおよび第1の遷移金属と異なる第2の遷移金属からなる第2層136Bを交互に複数回積層してなる。メッキシード層114は、例えばCu層114AおよびTi層114Bの2層構造とすることができる。   FIG. 2B illustrates an example in which the conductive support body 122 </ b> A includes a stacked body 136. The conductive support body 122A includes a main Cu plating layer 130 and a laminated body 136 thereon. The laminated body 136 is formed by alternately laminating a first layer 136A made of a first transition metal and a second layer 136B made of a second transition metal different from the first transition metal a plurality of times. The plating seed layer 114 can have a two-layer structure of a Cu layer 114A and a Ti layer 114B, for example.

このような積層体134,136によって、素子100を任意の基板に実装しても、III族窒化物半導体層にクラックが生じにくいという顕著な効果を奏する。このような効果を奏する作用は必ずしも明らかではないが、熱衝撃によって生じうる、導電性サポート体とIII族窒化物半導体層からなる半導体構造部との間の残留応力を、積層体によって緩和することができるためと推測される。さらに、本発明者らは、積層体による上記残留応力の緩和の効果が非常に高く、その結果、熱衝撃に起因する順方向電圧(Vf)が増加も十分に抑制することができることを見出し、本発明を完成するに至った。   Such stacked bodies 134 and 136 have a remarkable effect that even if the device 100 is mounted on an arbitrary substrate, cracks are hardly generated in the group III nitride semiconductor layer. The effect of such an effect is not necessarily clear, but the laminated body can relieve the residual stress between the conductive support body and the semiconductor structure composed of the group III nitride semiconductor layer, which can be generated by thermal shock. It is speculated that this is possible. Furthermore, the present inventors have found that the effect of relaxation of the residual stress by the laminate is very high, and as a result, it is possible to sufficiently suppress an increase in forward voltage (Vf) due to thermal shock, The present invention has been completed.

ここで、第1および第2の遷移金属は、Cu,Ti,Ni,Fe,Co,Cr,Auおよび白金族からなる群から、前記第2の遷移金属が前記第1の遷移金属よりも熱膨張係数(線膨張率ともいう)が小さくなるように、それぞれ選択されることが好ましい。例えば、第1の遷移金属がCuの場合、上記の他の遷移金属は、熱膨張係数がCuよりも低い。第1の遷移金属がNiの場合には、第2の遷移金属はCuを除く上記の他の遷移金属とすればよい。これらの遷移金属は、スパッタやメッキなどによる形成が容易かつ比較的安価であり、一般的に半導体素子の製造に利用できる材料であり好ましい。なお、Auや白金族は高価なため他の金属がより好ましい。ただし、Auや白金族は、導電性サポート体の酸化防止として良好なので、部分的に使用してもよい。また、上記群内の金属を組み合わせた合金を第1層および第2層に用いてもよい。なお、第2の遷移金属を上記群以外から選択すると、第1の遷移金属と第2の遷移金属との熱膨張係数差が大きくなり、剥がれの原因となりうる。   Here, the first and second transition metals are selected from the group consisting of Cu, Ti, Ni, Fe, Co, Cr, Au, and the platinum group, and the second transition metal is more heated than the first transition metal. Each is preferably selected so that an expansion coefficient (also referred to as a linear expansion coefficient) becomes small. For example, when the first transition metal is Cu, the other transition metal has a lower thermal expansion coefficient than Cu. When the first transition metal is Ni, the second transition metal may be any other transition metal except Cu. These transition metals are preferable because they are easy and relatively inexpensive to form by sputtering or plating, and are generally materials that can be used for manufacturing semiconductor devices. Since Au and platinum group are expensive, other metals are more preferable. However, Au or platinum group is good for preventing oxidation of the conductive support body, and may be partially used. Moreover, you may use the alloy which combined the metal in the said group for a 1st layer and a 2nd layer. If the second transition metal is selected from a group other than the above group, the difference in thermal expansion coefficient between the first transition metal and the second transition metal becomes large, which may cause peeling.

主のメッキ層を構成する第1の遷移金属がCu以外の場合には、積層体の第1層は前記第1の遷移金属とし、第2層は、第1の遷移金属よりも熱膨張係数の小さい第2の遷移金属とすることにより、任意の基板に実装後にIII族窒化物半導体層にクラックが生じにくく、かつ、加熱ハンダ実装による順方向電圧の増加が抑制できるという本発明の効果を奏する。   When the first transition metal constituting the main plating layer is other than Cu, the first layer of the laminate is the first transition metal, and the second layer has a thermal expansion coefficient higher than that of the first transition metal. By making the second transition metal small in size, the effect of the present invention that the group III nitride semiconductor layer is hardly cracked after being mounted on an arbitrary substrate and the increase in the forward voltage due to mounting by heating solder can be suppressed. Play.

本実施形態では、第1の遷移金属がCuとし、第2の遷移金属をCu以外の遷移金属とすることが好ましい。主のCuメッキ層130の熱膨張に対して、積層体の一方にCu以外の遷移金属を用いることで、熱膨張を緩やかに低減させることができるからである。   In the present embodiment, it is preferable that the first transition metal is Cu and the second transition metal is a transition metal other than Cu. This is because the thermal expansion can be moderately reduced by using a transition metal other than Cu for one of the laminated bodies against the thermal expansion of the main Cu plating layer 130.

図2(B)のように、導電性サポート体122Aが積層体136を含む場合、積層体136は、第1および第2の遷移金属がそれぞれCuおよびNiであることが好ましい。Cuより熱膨張係数が小さいNiを用いることで熱膨張を緩やかに低減させることができる上に、Cu、Ni共にメッキが容易であり、安価に素子を製造することができるからである。他の選択としては、第1および第2の遷移金属がそれぞれNiおよびCr、CuおよびCrや、CuおよびNi-Fe-Co合金などがある。Cu/Ni/Coのように第3の遷移金属を間に組み込む形態でも良い。   As shown in FIG. 2B, when the conductive support body 122A includes the stacked body 136, the stacked body 136 preferably includes Cu and Ni as the first and second transition metals, respectively. This is because by using Ni having a smaller thermal expansion coefficient than Cu, the thermal expansion can be moderately reduced, and both Cu and Ni can be easily plated, and the device can be manufactured at low cost. Other choices include Ni and Cr, Cu and Cr, and Cu and Ni-Fe-Co alloys for the first and second transition metals, respectively. A form in which a third transition metal is incorporated in between may be used, such as Cu / Ni / Co.

図2(A)のように、メッキシード層114が積層体134を含む場合、積層体134は、第1および第2の遷移金属がそれぞれCuおよびTiであることが好ましい。メッキ成長側となる第1層134AをCuとすると導電性サポート体のメッキ成長を好適に行なうことができ、半導体構造部110側となる第2層134BをTiとすると半導体構造部との密着性を十分に確保できるからである。また、Cuより熱膨張係数が小さいTiを用いることで熱膨張を緩やかに低減させることができる。他の選択としては、第1および第2の遷移金属がそれぞれNiおよびTi、CuおよびNi、AuおよびNi、AuおよびCr、CuおよびCrなどがある。Cu/Ni/Tiのように第3の遷移金属を間に組み込む形態でも良い。   As shown in FIG. 2A, when the plating seed layer 114 includes the stacked body 134, the stacked body 134 preferably includes Cu and Ti as the first and second transition metals, respectively. If the first layer 134A on the plating growth side is made of Cu, the conductive support body can be preferably grown by plating. If the second layer 134B on the semiconductor structure 110 side is made of Ti, the adhesion to the semiconductor structure portion is made. This is because a sufficient amount can be secured. Moreover, thermal expansion can be gently reduced by using Ti whose thermal expansion coefficient is smaller than Cu. Other choices include Ni and Ti, Cu and Ni, Au and Ni, Au and Cr, Cu and Cr, etc., respectively, for the first and second transition metals. A form in which a third transition metal is incorporated in between may be used, such as Cu / Ni / Ti.

また、導電性サポート体122Aは、主のCuメッキ層130の厚みが140μm以上であり、さらに厚み5μm以上のNiメッキ層を含むことが好ましい。図2(A)の場合、Niメッキ層132の厚みを5μm以上とし、図2(B)の場合、例えば積層体136を構成する第2層136Bを厚み5μm以上のNiメッキ層とすればよい。主のCuメッキ層130の厚みを140μm以上とすることにより、導電性サポート体122Aの反りを十分に抑制することができ、また、厚み5μm以上のNiメッキ層を設けることにより、主のCuメッキ層とメッキシード層との間の熱膨張の緩和効果を得ることができるため、加熱ハンダ実装に伴うクラックの抑制および順方向電圧増加の抑制の効果をより確実に得ることができる。導電性サポート体122Aの全体の厚みは、スループットを大きく悪化させない観点から400μm以下とすることが好ましい。   In addition, in the conductive support body 122A, the thickness of the main Cu plating layer 130 is preferably 140 μm or more, and further preferably includes a Ni plating layer having a thickness of 5 μm or more. In the case of FIG. 2A, the thickness of the Ni plating layer 132 is set to 5 μm or more. In the case of FIG. 2B, for example, the second layer 136B constituting the stacked body 136 may be a Ni plating layer having a thickness of 5 μm or more. . By setting the thickness of the main Cu plating layer 130 to 140 μm or more, warping of the conductive support body 122A can be sufficiently suppressed, and by providing the Ni plating layer having a thickness of 5 μm or more, the main Cu plating layer 130 Since the effect of mitigating thermal expansion between the layer and the plating seed layer can be obtained, the effects of suppressing cracks associated with heating solder mounting and suppressing increase in forward voltage can be more reliably obtained. The total thickness of the conductive support body 122A is preferably 400 μm or less from the viewpoint of not greatly degrading the throughput.

半導体構造部110の厚みは6〜20μmとすることが好ましい。6μm以上とすることにより、半導体構造部110の強度を確保して、クラック発生をより抑制することができ、20μm以下とすることにより、スループットを大きく悪化させることがないからである。   The thickness of the semiconductor structure 110 is preferably 6 to 20 μm. This is because by setting the thickness to 6 μm or more, it is possible to secure the strength of the semiconductor structure 110 and further suppress the generation of cracks, and by setting the thickness to 20 μm or less, the throughput is not greatly deteriorated.

素子100の製造方法の一例を、図3および図4によって以下詳細に説明する。まず、図3と図4との対応関係を先に説明する。図4(A)は、図3(B)に示した状態の模式上面図であり、図4(A)のI−I断面が図3(B)に相当する。なお、図3(B)以外の図3の断面図も同様の位置でのものである。図4(B)は、図3(C)に示した状態の上面図である。図4(C)は、図3(E)に示した状態の上面図である。図4(D)は、図3(F)に示した状態の横断面図である。   An example of a method for manufacturing the element 100 will be described in detail below with reference to FIGS. First, the correspondence between FIG. 3 and FIG. 4 will be described first. 4A is a schematic top view of the state shown in FIG. 3B, and the II cross section in FIG. 4A corresponds to FIG. 3B. Note that the cross-sectional views of FIG. 3 other than FIG. 3B are also in the same position. FIG. 4B is a top view of the state shown in FIG. FIG. 4C is a top view of the state shown in FIG. FIG. 4D is a cross-sectional view of the state shown in FIG.

まず、図3(A)に示すように、成長用基板102の上にリフトオフ層104およびIII族窒化物半導体層106をこの順に形成する(第1工程)。   First, as shown in FIG. 3A, a lift-off layer 104 and a group III nitride semiconductor layer 106 are formed in this order on a growth substrate 102 (first step).

次に、図3(B)および図4(A)に示すように、III族窒化物半導体層106の一部を除去して、成長用基板102の一部が底部で露出する溝108を網目状、本実施形態では格子状に形成することで、横断面形状が四角形の縦横に整列したIII族窒化物半導体層からなる半導体構造部110を複数個形成する。   Next, as shown in FIGS. 3B and 4A, a part of the group III nitride semiconductor layer 106 is removed, and a groove 108 in which a part of the growth substrate 102 is exposed at the bottom is formed into a mesh. In this embodiment, a plurality of semiconductor structure portions 110 made of a group III nitride semiconductor layer having a transverse cross-sectional shape arranged in a vertical and horizontal direction are formed by forming a lattice shape.

次に、図3(C)および図4(B)に示すように、全ての溝108を充填材としてのレジスト112で塞ぐ。   Next, as shown in FIGS. 3C and 4B, all the grooves 108 are closed with a resist 112 as a filler.

次に、図3(D)に示すように、半導体構造部110および第1レジスト112の上にスパッタ法または電子ビーム蒸着法によりメッキシード層114を形成する(第2工程)。メッキシード層114が積層体(図3では図示せず)を含む場合は、ターゲットを交互に代えることにより形成すればよい。   Next, as shown in FIG. 3D, a plating seed layer 114 is formed on the semiconductor structure 110 and the first resist 112 by sputtering or electron beam evaporation (second step). When the plating seed layer 114 includes a stacked body (not shown in FIG. 3), the plating seed layer 114 may be formed by alternately changing the target.

次に、図3(E)および図4(C)に示すように、溝108の上方かつメッキシード層114上に、格子状の薄膜のレジスト116を形成する。ここで、第2レジスト116に覆われず露出した部位118が形成される。   Next, as shown in FIGS. 3E and 4C, a lattice-like thin film resist 116 is formed above the groove 108 and on the plating seed layer 114. Here, a portion 118 exposed without being covered with the second resist 116 is formed.

次に、図3(F)および図4(D)に示すように、露出部位118からメッキ層を成膜させ、メッキシード層114上に、複数個の半導体構造部110を一体支持する導電性サポート体122を形成する(第3工程)。導電性サポート体122が積層体(図3では図示せず)を含む場合は、メッキ浴を交互に代えることにより形成すればよい。ここで、導電性サポート体122は、レジスト116の上に凹み120を有し、かつ、レジスト116の交差部位上に孔124を有するように成膜させるが、詳細は後述する。   Next, as shown in FIGS. 3 (F) and 4 (D), a plating layer is formed from the exposed portion 118, and a plurality of semiconductor structures 110 are integrally supported on the plating seed layer 114. The support body 122 is formed (third step). When the conductive support body 122 includes a laminated body (not shown in FIG. 3), the conductive support body 122 may be formed by alternately changing the plating bath. Here, the conductive support body 122 is formed so as to have a recess 120 on the resist 116 and a hole 124 on the crossing portion of the resist 116, which will be described in detail later.

次に、図3(G)に示すように、レジスト116およびレジスト112を除去して、孔124からリフトオフ層104に通じる空隙126を形成する。具体的には、アセトンなどのレジストを溶解する液体を孔124から供給することにより、レジスト116を溶解する。本実施形態では、孔124の下のレジスト116とレジスト112とに挟まれたメッキシード層部分は、レジスト116の除去の後に続いて、機械的または化学的に除去される。その後、レジスト112にもアセトンなどの液体が達することにより、レジスト112も除去できる。   Next, as shown in FIG. 3G, the resist 116 and the resist 112 are removed, and a void 126 that leads from the hole 124 to the lift-off layer 104 is formed. Specifically, the resist 116 is dissolved by supplying a liquid for dissolving the resist such as acetone from the holes 124. In the present embodiment, the plating seed layer portion sandwiched between the resist 116 and the resist 112 under the hole 124 is mechanically or chemically removed following the removal of the resist 116. Thereafter, when the liquid such as acetone reaches the resist 112, the resist 112 can also be removed.

次に、エッチング液を孔124および空隙126を介して供給することにより、リフトオフ層104をエッチングにより除去する。この結果、成長用基板102は半導体構造部110から剥離される(第4工程、図3(H))。   Next, the lift-off layer 104 is removed by etching by supplying an etching solution through the holes 124 and the gaps 126. As a result, the growth substrate 102 is peeled from the semiconductor structure 110 (fourth step, FIG. 3H).

最後に、図3(I)に示すように、半導体構造部110の間で凹み120に沿って導電性サポート体122を切断することにより、各々が切断された導電性サポート体122Aに支持された半導体構造部110を有する複数個の素子100に個片化する。図4(D)の破線が切断ラインであり、凹み120に沿っていることがわかる。また、上部電極128を半導体構造部110の剥離面側に形成する。下部電極は導電性サポート体122Aが兼ねる。   Finally, as shown in FIG. 3 (I), the conductive support bodies 122 are cut along the recesses 120 between the semiconductor structure portions 110, so that each is supported by the cut conductive support bodies 122A. A plurality of elements 100 having the semiconductor structure 110 are separated. It can be seen that the broken line in FIG. 4D is a cutting line and is along the recess 120. Further, the upper electrode 128 is formed on the peeling surface side of the semiconductor structure 110. The conductive support body 122A also serves as the lower electrode.

ここで、導電性サポート体122Aやその各層の厚みはメッキの成長時間により調整し、半導体構造部110の厚みは、エピタキシャル成長時間により調整することができ、いずれの厚みもSEMにより素子100の断面を観察することにより、測定することができる。厚みはいずれも素子100の中央部での厚みとする。   Here, the thickness of the conductive support body 122A and each layer thereof can be adjusted by the growth time of plating, and the thickness of the semiconductor structure 110 can be adjusted by the epitaxial growth time. It can be measured by observing. The thickness is the thickness at the center of the element 100.

図3および図4に示した製造方法は、ケミカルリフトオフ法に用いるエッチング液を供給する孔を導電性サポート体に容易に形成でき、かつ、導電性サポート体の切断(すなわち個片化)を容易に行える点でも好ましい。すなわち、露出部位118からメッキが成長するにつれて、レジスト116上で隣接して成膜するメッキ層同士が結合する。これにより、複数の半導体構造部110を導電性サポート体112が一体支持することが可能となる。その際、レジスト116上に図2(F)のような凹み120が形成される。ダイシング装置により凹み120に沿って切断することにより、凹みを有しない導電性サポート体よりも容易に切断することができる。   The manufacturing method shown in FIGS. 3 and 4 can easily form a hole for supplying an etching solution used in the chemical lift-off method in the conductive support body, and can easily cut the conductive support body (ie, singulation). It is also preferable in that it can be performed. That is, as the plating grows from the exposed portion 118, adjacent plating layers formed on the resist 116 are bonded to each other. As a result, the conductive support body 112 can integrally support the plurality of semiconductor structure portions 110. At that time, a recess 120 as shown in FIG. 2F is formed on the resist 116. By cutting along the recess 120 with a dicing device, it can be more easily cut than a conductive support body having no recess.

また、レジスト116は、格子状に形成している(図3(C)参照)。このため、レジスト116の交差部位上に孔124を形成することができる。なお、メッキ層の伸長速度および形状は、メッキ浴の種類、温度、電流により制御できる。   The resist 116 is formed in a lattice shape (see FIG. 3C). For this reason, the hole 124 can be formed on the intersection of the resist 116. The elongation rate and shape of the plating layer can be controlled by the type, temperature, and current of the plating bath.

なお、レジスト116は網目状に形成すれば、その塗布態様は特に限定されない。図5(A)〜(D)は、レジスト116の塗布態様を変更した以外は図4と同様の模式上面図である。メッキシードの露出部位の形状は、図4(C)のように正方形ではなく、図5(C)に示すように正方形の角部に丸みや面取り、へこみ等がついていてもよい。この場合、図5(D)に示すように、メッキ後の孔124の径を図4(D)よりも大きくすることができる。   Note that the application mode is not particularly limited as long as the resist 116 is formed in a mesh shape. 5A to 5D are schematic top views similar to FIG. 4 except that the application mode of the resist 116 is changed. The shape of the exposed portion of the plating seed is not a square as shown in FIG. 4C, but may be rounded, chamfered, dented or the like at the corners of the square as shown in FIG. 5C. In this case, as shown in FIG. 5D, the diameter of the hole 124 after plating can be made larger than that in FIG.

図6は、上記製造方法で得ることができる、個片化前の半導体素子結合体200の模式斜視図である。半導体素子結合体200は、成長用基板102と、該成長用基板102上のリフトオフ層104と、該リフトオフ層104上で溝108を介して互いに独立した複数の半導体構造部110と、前記複数個の半導体構造部110を一体支持する導電性サポート体122と、を有し、該導電性サポート体122は、溝108の上方の位置に凹み120を有し、溝108の交差部位上に、溝108に通じる孔124を有する。なお、半導体構造部110上にはメッキシード層114がある。半導体素子結合体200は、図3(G)に示す状態のウェハである。すなわち、本明細書において「半導体素子結合体」とは、複数の半導体構造部が成長用基板と導電性サポート体で挟まれかつ一体支持された、リフトオフ前の状態のウェハを意味する。   FIG. 6 is a schematic perspective view of the semiconductor element combination 200 before singulation, which can be obtained by the above manufacturing method. The semiconductor device combination 200 includes a growth substrate 102, a lift-off layer 104 on the growth substrate 102, a plurality of semiconductor structures 110 independent of each other via a groove 108 on the lift-off layer 104, and the plurality A conductive support body 122 that integrally supports the semiconductor structure 110 of the semiconductor device. The conductive support body 122 has a recess 120 at a position above the groove 108, and a groove is formed on the intersection of the groove 108. A hole 124 leading to 108 is provided. Note that a plating seed layer 114 is provided on the semiconductor structure 110. The semiconductor element combination 200 is a wafer in the state shown in FIG. That is, in this specification, the “semiconductor element assembly” means a wafer in a state before lift-off in which a plurality of semiconductor structures are sandwiched between a growth substrate and a conductive support and are integrally supported.

半導体素子結合体200では、孔124を介して溝108にエッチング液を供給して、リフトオフ層104を除去することができる。また、凹み120に沿ってより容易にサポート体122を切断することができる。   In the semiconductor element assembly 200, the lift-off layer 104 can be removed by supplying an etching solution to the groove 108 through the hole 124. In addition, the support body 122 can be more easily cut along the recess 120.

(半導体層形成工程)
成長用基板102は、サファイア基板またはサファイア基板上にAlN膜を形成したAlNテンプレート基板を用いるのが好ましい。形成するリフトオフ層の種類やIII族窒化物半導体層のAl,Ga,Inの組成、LEDチップの品質、コストなどにより適宜選択すればよい。
(Semiconductor layer formation process)
The growth substrate 102 is preferably a sapphire substrate or an AlN template substrate in which an AlN film is formed on a sapphire substrate. What is necessary is just to select suitably according to the kind of lift-off layer to form, the composition of Al, Ga, In of a group III nitride semiconductor layer, the quality of a LED chip, cost, etc.

リフトオフ層104としては、ケミカルリフトオフ法ではCrNやScNなどのIII族以外の金属や金属窒化物バッファ層が化学選択エッチングで溶解できるので好ましい。スパッタリング法、真空蒸着法、イオンプレーティング法やMOCVD法で成膜するのが好ましい。通常、リフトオフ層104の膜厚は2〜100nm程度とする。   As the lift-off layer 104, a chemical lift-off method is preferable because a metal other than Group III such as CrN and ScN and a metal nitride buffer layer can be dissolved by chemical selective etching. It is preferable to form the film by sputtering, vacuum deposition, ion plating, or MOCVD. Usually, the thickness of the lift-off layer 104 is about 2 to 100 nm.

(溝形成工程)
III族窒化物半導体層106の一部の除去には、ドライエッチング法を用いるのが好ましい。これは、III族窒化物半導体層106のエッチングの終点を再現性良く制御できるからである。また、III族窒化物半導体層106が繋がった状態であると、後工程においてエッチング液でリフトオフ層104をエッチングすることができないため、この除去は、少なくとも成長用基板またはリフトオフ層が露出するまで行うものとする。上記の本実施形態では、溝108の底部ではリフトオフ層104は除去され、成長用基板102が完全に露出する例を示した。
(Groove formation process)
It is preferable to use a dry etching method to remove a part of the group III nitride semiconductor layer 106. This is because the etching end point of the group III nitride semiconductor layer 106 can be controlled with good reproducibility. Further, when the group III nitride semiconductor layer 106 is connected, the lift-off layer 104 cannot be etched with an etchant in a subsequent process, and therefore this removal is performed at least until the growth substrate or the lift-off layer is exposed. Shall. In the above-described embodiment, the lift-off layer 104 is removed at the bottom of the groove 108 and the growth substrate 102 is completely exposed.

本実施形態において半導体構造部110の横断面形状は四角形で示したが、半導体構造部110の横断面形状は特に限定されず、円形でも、三角形や六角形などの多角形でもよい。半導体構造部110の横断面形状を多角形とする場合は、多角形の半導体構造部110の周囲の溝108に沿って網目状にレジスト116を形成することにより、レジスト116の交差部位上に、溝108に通じる孔124を形成するとともに、溝108の上方の位置の導電性サポート体122に凹み120を形成することができる。なお、半導体素子を個片化する工程において、レーザーダイシング装置により溝108を直線で切断しやすいように、半導体構造部110は整列していることが好ましい。   In the present embodiment, the cross-sectional shape of the semiconductor structure 110 is shown as a quadrangle, but the cross-sectional shape of the semiconductor structure 110 is not particularly limited, and may be a circle or a polygon such as a triangle or a hexagon. When the cross-sectional shape of the semiconductor structure part 110 is a polygon, by forming a resist 116 in a mesh shape along the grooves 108 around the polygonal semiconductor structure 110, A hole 124 communicating with the groove 108 can be formed, and a recess 120 can be formed in the conductive support body 122 at a position above the groove 108. In the step of dividing the semiconductor element into pieces, the semiconductor structure 110 is preferably aligned so that the groove 108 can be easily cut by a laser dicing apparatus.

半導体構造部110の横断面が四角形の場合、1辺は通常250〜3000μmとする。また、溝108の直線部位における幅は、40〜200μmの範囲内とすることが好ましく、60〜100μmとすることがより好ましい。40μm以上とすることにより、溝108へのエッチング液の供給を十分に円滑に行うことができ、200μm以下とすることにより、発光面積のロスを最小限に抑えることができるからである。   When the cross section of the semiconductor structure 110 is a square, one side is usually 250 to 3000 μm. Further, the width of the straight portion of the groove 108 is preferably within a range of 40 to 200 μm, and more preferably 60 to 100 μm. This is because when the thickness is 40 μm or more, the etching solution can be sufficiently smoothly supplied to the groove 108, and when the thickness is 200 μm or less, the loss of the light emitting area can be minimized.

(溝部充填・メッキシード層形成工程)
図1の実施形態では、溝108の充填剤としてレジスト112を用い、その後全てのレジスト112を格子状のレジスト116とともに除去して空隙126を形成したが、本発明はこれに限らず、充填剤の一部を除去して、エッチング供給用の空隙を形成するものでもよい。例えば、半導体構造部110の横断面の形状が四角形の場合、PCT/JP2011/005485に記載するように、各半導体構造部110の1つの側面のみを充填剤としてのレジストで塞ぎ、残りの3つの側面は充填剤としての金属で塞ぐこともできる。そして、充填剤除去工程では、金属は除去せずレジストのみを除去し、レジストで埋められた溝のみにエッチング供給用の空隙を形成することができる。この場合、図1(H)のリフトオフ工程では、レジストで塞いだ溝側からその反対側の溝側に向かってエッチングが進行する。
(Groove filling / plating seed layer formation process)
In the embodiment of FIG. 1, the resist 112 is used as a filler for the groove 108, and then all the resist 112 is removed together with the lattice-like resist 116 to form the void 126. However, the present invention is not limited to this, and the filler May be removed to form a gap for supplying etching. For example, when the shape of the cross section of the semiconductor structure portion 110 is a quadrangle, as described in PCT / JP2011 / 005485, only one side surface of each semiconductor structure portion 110 is closed with a resist as a filler, and the remaining three The side can also be plugged with a metal as a filler. In the filler removing step, the metal is not removed, but only the resist is removed, and an etching supply gap can be formed only in the groove filled with the resist. In this case, in the lift-off process of FIG. 1H, etching proceeds from the groove side closed with the resist toward the opposite groove side.

溝108の充填剤としては、レジスト112に替えて、任意の材料を用いてもよい。例えば、導電性サポート体122やメッキシード層114に使用されない金属、またはSiOなどの絶縁物を用いることができる。充填剤を除去する場合は、材料に応じたエッチング液を選択すればよい。As a filler for the groove 108, any material may be used instead of the resist 112. For example, a metal that is not used for the conductive support body 122 and the plating seed layer 114, or an insulator such as SiO 2 can be used. In order to remove the filler, an etching solution corresponding to the material may be selected.

(レジスト形成・メッキ形成工程)
レジスト116の幅や厚み、およびレジスト116の交差部位における形状を適宜調整することで、凹み位置120での導電性サポート体122の厚み、半導体構造部110上の導電性サポート体122の厚み、および孔124の寸法を適宜設定することができる。また、網目状のレジストを形成する工程と、導電性サポート体を形成する工程とを複数回繰り返す多段階メッキ工程を採用してもよい。
(Resist formation and plating process)
By appropriately adjusting the width and thickness of the resist 116 and the shape at the intersection of the resist 116, the thickness of the conductive support body 122 at the recessed position 120, the thickness of the conductive support body 122 on the semiconductor structure 110, and The dimension of the hole 124 can be set as appropriate. Moreover, you may employ | adopt the multistep plating process which repeats the process of forming a mesh-like resist, and the process of forming an electroconductive support body in multiple times.

凹み120位置での導電性サポート体122の厚みは特に限定されないが、ダイシング装置により切断し易い厚みであることが好ましく、例えば120μm以下とする。   The thickness of the conductive support body 122 at the position of the dent 120 is not particularly limited, but is preferably a thickness that can be easily cut by a dicing apparatus, for example, 120 μm or less.

なお、本実施形態では、メッキシード層114の上にレジスト116を形成した。しかし、孔を形成する位置にあたるメッキシード層は予め除去し、レジスト112に接してレジスト116を形成してもよい。   In the present embodiment, the resist 116 is formed on the plating seed layer 114. However, the plating seed layer corresponding to the position where the hole is formed may be removed in advance, and the resist 116 may be formed in contact with the resist 112.

図には示されないが、複数個の半導体構造部110の主表面とメッキシード層114との間に、複数個の半導体層106の各々と接するオーミック電極層を形成するのが好ましい。また、本発明をLEDチップの製造に使用する場合には、オーミック電極層とメッキシード層114との間にさらに反射層を形成するか、オーミック電極層が反射層の機能を兼ねることがより好ましい。これらの層形成には、真空蒸着法、イオンプレーティング法、スパッタリング法などの乾式成膜法を用いることができる。   Although not shown in the drawing, it is preferable to form an ohmic electrode layer in contact with each of the plurality of semiconductor layers 106 between the main surface of the plurality of semiconductor structures 110 and the plating seed layer 114. Further, when the present invention is used for manufacturing an LED chip, it is more preferable that a reflective layer is further formed between the ohmic electrode layer and the plating seed layer 114, or the ohmic electrode layer also functions as the reflective layer. . For the formation of these layers, dry film forming methods such as vacuum deposition, ion plating, and sputtering can be used.

上記オーミック電極層は、仕事関数の大きな金属、例えばPd,Pt,Rh,Au,Agなどの貴金属やCo,Niにより形成することができる。また、反射層としては、Rh等の反射率が高いため、上記オーミック電極層との兼用も可能だが、発光領域が可視光の場合にはAgやAl層等を、紫外線領域の場合にはRhやRu層等を用いるのがより好ましい。なお、オーミック電極層および反射層は合計しても高々0.2μmと薄いので、これらは導電性サポート体の一部として扱っても本発明の効果に影響はない。   The ohmic electrode layer can be formed of a metal having a large work function, for example, a noble metal such as Pd, Pt, Rh, Au, Ag, or Co, Ni. Further, since the reflection layer has a high reflectance such as Rh, it can also be used as the ohmic electrode layer. However, when the light emitting region is visible light, Ag or Al layer is used, and when the light emitting region is ultraviolet region, Rh is used. More preferably, a Ru layer or the like is used. In addition, since the ohmic electrode layer and the reflective layer are as thin as 0.2 μm at the maximum, even if they are treated as a part of the conductive support body, the effect of the present invention is not affected.

(リフトオフ工程)
本発明におけるケミカルリフトオフ法に使用可能なエッチング液としては、リフトオフ層がCrNの場合、硝酸第二セリウムアンモン溶液やフェリシアンカリウム系の溶液など、リフトオフ層がScNの場合、塩酸、硝酸、有機酸など選択性のある公知のエッチング液を挙げることができる。また、リフトオフ工程は上記のケミカルリフトオフ法に限らず、フォトケミカルリフトオフ法やレーザーリフトオフ法を用いる場合でもよいことは明らかである。
(Lift-off process)
Etching solutions usable in the chemical lift-off method of the present invention include, when the lift-off layer is CrN, ceric ammonium nitrate solution or ferricyanium potassium-based solution, such as hydrochloric acid, nitric acid, organic acid, when the lift-off layer is ScN. For example, known etchants having selectivity can be given. Further, it is obvious that the lift-off process is not limited to the above-described chemical lift-off method, and a photochemical lift-off method or a laser lift-off method may be used.

また、リフトオフ後に露呈した半導体構造部110の面は、ウエット洗浄で清浄化されるのが好ましい。次いで、ドライエッチングおよび/またはウエットエッチングで所定量削ることにより、半導体構造部の厚みを調整してもよい。   The surface of the semiconductor structure 110 exposed after lift-off is preferably cleaned by wet cleaning. Next, the thickness of the semiconductor structure portion may be adjusted by cutting a predetermined amount by dry etching and / or wet etching.

さらに、レジストをマスクとしたリフトオフ法により上部電極としてのn型オーミック電極およびボンディングパッド電極を形成する。電極材としてはAl,Cr,Ti,Ni,Pt,Auなどが用いられ、オーミック電極、ボンディングパッドにはTi,Pt,Auなどをカバー層として成膜して、配線抵抗の低減とワイヤーボンドの密着性を向上させる。なお、半導体構造部110の露出している側面ならびに表面(ボンディングパッド表面を除く)には、SiOやSiNなどの保護膜(絶縁膜)を付与してもよい。Further, an n-type ohmic electrode and a bonding pad electrode as upper electrodes are formed by a lift-off method using a resist as a mask. Al, Cr, Ti, Ni, Pt, Au, etc. are used as the electrode material, and Ti, Pt, Au, etc. are formed on the ohmic electrode and bonding pad as a cover layer to reduce wiring resistance and wire bond. Improve adhesion. Note that a protective film (insulating film) such as SiO 2 or SiN may be provided on the exposed side surface and surface (excluding the bonding pad surface) of the semiconductor structure 110.

(個片化工程)
個片化工程では、半導体構造部110間を例えばブレードダイサーやレーザーダイシング装置を用いて切断する。
(Individualization process)
In the singulation process, the semiconductor structure portions 110 are cut using, for example, a blade dicer or a laser dicing apparatus.

以上は代表的な実施形態の例を示したものであって、本発明はこの実施形態に限定されるものではなく、請求の範囲を逸脱しない範囲において適宜変更が可能である。   The above is an example of a typical embodiment, and the present invention is not limited to this embodiment, and can be modified as appropriate without departing from the scope of the claims.

(実施例1)
図3および図4に示す製造方法で、図1に示す半導体素子を作製した。具体的には、まず、成長用のサファイア基板上に、スパッタ法により金属Cr層を形成しアンモニア雰囲気中で熱処理することによりリフトオフ層(CrN層、厚み:18nm)を形成した。その後、リフトオフ層上にIII族窒化物半導体層として、バッファ層(組成:GaN、厚み:4μm)、n−GaN層(厚み:6μm)、発光層(AlInGaN系MQW層、厚み:0.1μm)、p−GaN層(厚み:0.2μm)を順次積層した。この段階でのIII族窒化物半導体層の厚みは、10.3μmとなる。
Example 1
The semiconductor device shown in FIG. 1 was manufactured by the manufacturing method shown in FIGS. Specifically, first, a lift-off layer (CrN layer, thickness: 18 nm) was formed on a growth sapphire substrate by forming a metal Cr layer by sputtering and performing heat treatment in an ammonia atmosphere. Thereafter, as a group III nitride semiconductor layer on the lift-off layer, a buffer layer (composition: GaN, thickness: 4 μm), an n-GaN layer (thickness: 6 μm), and a light emitting layer (AlInGaN-based MQW layer, thickness: 0.1 μm) , P-GaN layers (thickness: 0.2 μm) were sequentially stacked. The thickness of the group III nitride semiconductor layer at this stage is 10.3 μm.

その後、サファイア基板の一部が露出するよう、半導体層の一部をドライエッチングにより除去して格子状の溝を形成することで、横断面の形状が正方形の互いに独立した複数個の半導体構造部を形成した。半導体構造部の幅は1350μmであり、個々の素子の配置は碁盤の目状とした。素子間のピッチは1500μm、すなわち溝幅は150μmである。   Thereafter, a part of the semiconductor layer is removed by dry etching to form a lattice-shaped groove so that a part of the sapphire substrate is exposed, thereby forming a plurality of semiconductor structure parts independent of each other having a square cross section Formed. The width of the semiconductor structure was 1350 μm, and the arrangement of the individual elements was a grid pattern. The pitch between elements is 1500 μm, that is, the groove width is 150 μm.

次に、半導体構造部の上に、EB蒸着法によりオーミック電極層(Ag、厚み:0.1μm)を形成した。次に、図3(C)および図4(B)に示すように、全ての溝をフォトレジストで塞ぎ、個々の半導体構造部上の領域は開口させた。その後、半導体構造部の表面、p−オーミック電極層上およびレジストの表面にメッキシード層を形成した。メッキシード層は、スパッタ法(230W,4.5mtorr)により、半導体構造部側から順にTi層(厚み:0.02μm)およびCu層(厚み:0.15μm)を交互に3回積層した。すなわち、本実施例では、第1層がCu層、第2層がTi層の積層体がメッキシード層となる。   Next, an ohmic electrode layer (Ag, thickness: 0.1 μm) was formed on the semiconductor structure portion by EB vapor deposition. Next, as shown in FIGS. 3C and 4B, all the grooves were closed with a photoresist, and the regions on the individual semiconductor structures were opened. Thereafter, a plating seed layer was formed on the surface of the semiconductor structure, on the p-ohmic electrode layer, and on the surface of the resist. As the plating seed layer, a Ti layer (thickness: 0.02 μm) and a Cu layer (thickness: 0.15 μm) were alternately stacked three times in order from the semiconductor structure side by a sputtering method (230 W, 4.5 mtorr). That is, in the present embodiment, a laminate in which the first layer is a Cu layer and the second layer is a Ti layer is a plating seed layer.

次に、高さ10μm、幅160μmの、図4(C)に示すような格子状のフォトレジストを形成した。その後、露出したメッキシード層上からメッキ法によりNiを40μm、Cuを150μm成膜し、導電性サポート体を完成させた。Niメッキは、スルファミン酸ニッケル溶液:Ni(NHSO)を用い、液温は50〜60℃の範囲で、電流は38.5A、メッキ成長時間は2時間とし、析出速度は20μm/hrであった。Cuメッキは硫酸銅系の電解液を用いた電気メッキであり、液温は25〜30℃の範囲で、電流は67.4A、メッキ成長時間は4.3時間とし、析出速度は35μm/hrであった。このとき、導電性サポート体はレジスト上で結合し、複数の半導体構造部を一体支持する状態となった。Next, a lattice-like photoresist having a height of 10 μm and a width of 160 μm as shown in FIG. 4C was formed. Thereafter, Ni was deposited to a thickness of 40 μm and Cu was deposited to a thickness of 150 μm by plating from the exposed plating seed layer to complete a conductive support body. Ni plating uses a nickel sulfamate solution: Ni (NH 2 SO 3 ) 2 , the liquid temperature is in the range of 50-60 ° C., the current is 38.5 A, the plating growth time is 2 hours, and the deposition rate is 20 μm / hr. Cu plating is electroplating using a copper sulfate electrolyte, the temperature of the solution is in the range of 25-30 ° C., the current is 67.4 A, the plating growth time is 4.3 hours, and the deposition rate is 35 μm / hr. Met. At this time, the conductive support body was bonded on the resist, and a plurality of semiconductor structure portions were integrally supported.

形成された導電性サポート体には、図3(F)および図4(D)に示すような凹みと孔が形成されていた。凹みの最も薄い部位の厚みは30〜50μm、すなわち孔近傍の位置で約30μm、孔から離れた最も厚い位置で約50μmとなった。孔の寸法は、対向する頂点間の距離が約77μmとなった。このように、メッキ層を成膜するのみでエッチング液を供給するための孔を容易に形成することができた。   The formed conductive support body was formed with recesses and holes as shown in FIGS. 3 (F) and 4 (D). The thickness of the thinnest portion of the recess was 30 to 50 μm, that is, about 30 μm at the position near the hole and about 50 μm at the thickest position away from the hole. As for the hole size, the distance between the opposite vertices was about 77 μm. As described above, the hole for supplying the etching solution can be easily formed only by forming the plating layer.

次に、孔内にアセトンを供給して、レジストを除去した。この際、孔直下のメッキシード層は塩化第2鉄の希薄溶液、Ni選択エッチング液で溶解除去した。そして、孔を介して、引き続きアセトンにより溝に充填していたレジストを取り除き、空隙を形成した。このとき、レジストの残渣が残るようなことはなかった。   Next, acetone was supplied into the holes to remove the resist. At this time, the plating seed layer directly under the hole was dissolved and removed with a dilute ferric chloride solution and a Ni selective etching solution. And the resist which filled the groove | channel with acetone continuously was removed through the hole, and the space | gap was formed. At this time, no resist residue remained.

次に、CrN選択エッチング液を用いて、ケミカルリフトオフ法によりリフトオフ層を除去し、サファイア基板を剥離した。   Next, the lift-off layer was removed by a chemical lift-off method using a CrN selective etching solution, and the sapphire substrate was peeled off.

その後、バッファ層全部とn−GaN層の一部の計5.3μmを、IPC−RIE装置を用いてドライエッチングを行い、III族窒化物半導体層の厚みを5.0μmとした。   Thereafter, a total of 5.3 μm of the entire buffer layer and a part of the n-GaN layer was dry-etched using an IPC-RIE apparatus, so that the thickness of the group III nitride semiconductor layer was 5.0 μm.

その後、6mol/LのKOH溶液を用いて60℃で10分間の処理を行いn−GaN層の表面を荒らした後、レジストを塗布して、n電極のパターニングを形成した後、EB蒸着法により(Ti/Al/Ni/Au、各厚み:0.02μm/1.5μm/0.02μm/2μm)を形成し、アセトンにてリフトオフを行うことでレジストを除去した。   Then, after treating the surface of the n-GaN layer by using a 6 mol / L KOH solution at 60 ° C. for 10 minutes, a resist is applied to form an n-electrode patterning, and then an EB vapor deposition method is used. (Ti / Al / Ni / Au, each thickness: 0.02 μm / 1.5 μm / 0.02 μm / 2 μm) was formed, and the resist was removed by lift-off with acetone.

導電性サポート体の裏面側に支持テープ(紫外線硬化テープ)を貼り付けて、導電性サポート体をレーザーダイシング装置のテーブルに固定し、凹みに沿って導電性サポート体を半導体構造部側からレーザー切断し、25個のIII族窒化物半導体素子を得た。   A support tape (ultraviolet curing tape) is attached to the back side of the conductive support body, the conductive support body is fixed to the table of the laser dicing machine, and the conductive support body is laser-cut from the semiconductor structure side along the recess. 25 group III nitride semiconductor devices were obtained.

<評価1:熱衝撃によるクラック発生>
このようにして得た25個のIII族窒化物半導体素子を300℃のホットプレート上に5分間静置後、III族窒化物半導体層の表面を観察し、クラックが発生しているか否かを判定した。本実施例では、25個のいずれもクラックが発生していなかった(クラック発生率0%)。
<Evaluation 1: Crack generation due to thermal shock>
The 25 group III nitride semiconductor devices thus obtained were allowed to stand on a hot plate at 300 ° C. for 5 minutes, and then the surface of the group III nitride semiconductor layer was observed to determine whether cracks had occurred. Judged. In this example, none of the 25 cracks occurred (crack occurrence rate 0%).

<評価2:熱衝撃による順方向電圧(Vf)の上昇>
オートプローブ測定装置にて、室温にて、動作電流350mAで、25個の素子について、上記ホットプレートでの加熱の前後で、それぞれ順方向電圧Vfを測定した。本実施例では、加熱後のVfから加熱前のVfを差し引いたΔVfの25個の素子の平均値は、0.06Vであった。
<Evaluation 2: Increase in forward voltage (Vf) due to thermal shock>
The forward voltage Vf of each of the 25 elements was measured before and after heating on the hot plate at room temperature and an operating current of 350 mA with an auto probe measuring device. In this example, the average value of 25 elements of ΔVf obtained by subtracting Vf before heating from Vf after heating was 0.06V.

(比較例1)
メッキシード層を電子ビーム蒸着法により形成し、層構成を半導体構造部側から順にTi層(厚み:0.02μm)およびCu層(厚み:0.45μm)とした以外は、実施例1と同様の方法でIII族窒化物半導体素子を作製した。すなわち、本比較例では積層体を形成しなかった。
(Comparative Example 1)
Example 1 except that the plating seed layer is formed by electron beam evaporation and the layer structure is a Ti layer (thickness: 0.02 μm) and a Cu layer (thickness: 0.45 μm) in this order from the semiconductor structure side. A group III nitride semiconductor device was fabricated by the method described above. That is, the laminate was not formed in this comparative example.

(比較例2)
メッキシード層の層構成を半導体構造部側から順にTi層(厚み:0.02μm)およびCu層(厚み:0.45μm)とした以外は、実施例1と同様の方法でIII族窒化物半導体素子を作製した。すなわち、本比較例では積層体を形成しなかった。
(Comparative Example 2)
A group III nitride semiconductor is manufactured in the same manner as in Example 1 except that the plating seed layer is composed of a Ti layer (thickness: 0.02 μm) and a Cu layer (thickness: 0.45 μm) in order from the semiconductor structure side An element was produced. That is, the laminate was not formed in this comparative example.

(実施例2)
メッキシード層および導電性サポート体の層構成を以下のように変更した以外は、実施例1と同様の方法でIII族窒化物半導体素子を作製した。まず、メッキシード層は、半導体構造部側から順にTi層(厚み:0.02μm)およびCu層(厚み:0.45μm)とした。次に、導電性サポート体は、メッキシード層側から順にNiメッキ層(厚み10μm)およびCuメッキ層(厚み10μm)を交互に2回メッキ成長させ、さらにCuメッキ層(厚み150μm)をメッキ成長させた。すなわち、本実施例では、導電性サポート体が、第1層がCu層、第2層がNi層の積層体を含む。各層の厚みはメッキ成長時間により調整した。
(Example 2)
A group III nitride semiconductor device was produced in the same manner as in Example 1 except that the layer configuration of the plating seed layer and the conductive support was changed as follows. First, the plating seed layer was a Ti layer (thickness: 0.02 μm) and a Cu layer (thickness: 0.45 μm) in this order from the semiconductor structure side. Next, as for the conductive support body, the Ni plating layer (thickness 10 μm) and the Cu plating layer (thickness 10 μm) are alternately grown twice in order from the plating seed layer side, and the Cu plating layer (thickness 150 μm) is further grown by plating. I let you. In other words, in this embodiment, the conductive support body includes a laminate in which the first layer is a Cu layer and the second layer is a Ni layer. The thickness of each layer was adjusted by the plating growth time.

(実施例3)
導電性サポート体に含まれる積層体を、メッキシード層側から順にNiメッキ層(厚み5μm)およびCuメッキ層(厚み5μm)を交互に4回メッキ成長させて形成した以外は、実施例2と同様の方法でIII族窒化物半導体素子を作製した。
(Example 3)
Example 2 except that the laminated body included in the conductive support was formed by alternately growing the Ni plating layer (thickness 5 μm) and the Cu plating layer (thickness 5 μm) four times in order from the plating seed layer side. A group III nitride semiconductor device was fabricated in the same manner.

比較例1,2および実施例2,3についても、実施例1と同様に評価1および評価2を行なった。その結果を表1および表2に示す。表1は、メッキシード層に積層体を形成することの効果を示すものである。表2は、導電性サポート体に積層体を形成することの効果を示すものである。   For Comparative Examples 1 and 2 and Examples 2 and 3, Evaluation 1 and Evaluation 2 were performed in the same manner as Example 1. The results are shown in Tables 1 and 2. Table 1 shows the effect of forming a laminate on the plating seed layer. Table 2 shows the effect of forming a laminated body on the conductive support body.

Figure 0005936696
Figure 0005936696

Figure 0005936696
Figure 0005936696

本発明によれば、任意の基板に実装後にIII族窒化物半導体層にクラックが生じにくく、かつ、加熱ハンダ実装による順方向電圧の増加が抑制されたIII族窒化物半導体素子およびその製造方法を提供することができる。   According to the present invention, there is provided a group III nitride semiconductor device in which a group III nitride semiconductor layer is hardly cracked after being mounted on an arbitrary substrate, and an increase in forward voltage due to mounting by heating solder is suppressed, and a method for manufacturing the same. Can be provided.

100 III族窒化物半導体素子
102 成長用基板
104 リフトオフ層
106 III族窒化物半導体層
108 溝
110 半導体構造部
112 レジスト(充填材)
114 メッキシード層
116 レジスト
118 メッキシード層の露出部位
120 凹み
122 導電性サポート体
122A 切断された導電性サポート体
122B 導電性サポート体のコーナー
122C 半導体構造部と反対側の外周部
124 孔
126 空隙
128 上部電極
130 主のCuメッキ層
132 Niメッキ層
134,136 積層体
134A,136A 第1層
134B,136B 第2層
200 半導体素子結合体
100 Group III Nitride Semiconductor Device 102 Growth Substrate 104 Lift-off Layer 106 Group III Nitride Semiconductor Layer 108 Groove 110 Semiconductor Structure 112 Resist (Filler)
114 plating seed layer 116 resist 118 exposed portion of plating seed layer 120 recess 122 conductive support body 122A cut conductive support body 122B corner of conductive support body 122C outer peripheral portion opposite to semiconductor structure portion 124 hole 126 gap 128 Upper electrode 130 Main Cu plating layer 132 Ni plating layer 134,136 Laminated body 134A, 136A First layer 134B, 136B Second layer 200 Semiconductor element assembly

Claims (6)

主のCuメッキ層を含み、Cuを主材料とする導電性サポート体と、
該導電性サポート体上のメッキシード層と、
該メッキシード層上のオーミック電極層と、
該オーミック電極層上のIII族窒化物半導体層と、を有し、
前記主のCuメッキ層と前記メッキシード層との間において、Cuからなる第1層およびNiからなる第2層を交互に複数回積層した積層体を含むことを特徴とするIII族窒化物半導体素子。
A conductive support body including a main Cu plating layer and made of Cu as a main material;
A plating seed layer on the conductive support;
An ohmic electrode layer on the plating seed layer;
A group III nitride semiconductor layer on the ohmic electrode layer ,
A group III nitride semiconductor comprising a laminate in which a first layer made of Cu and a second layer made of Ni are alternately laminated a plurality of times between the main Cu plating layer and the plating seed layer element.
主のCuメッキ層を含み、Cuを主材料とする導電性サポート体と、
該導電性サポート体上のメッキシード層と、
該メッキシード層上のオーミック電極層と、
該オーミック電極層上のIII族窒化物半導体層と、を有し、
前記主のCuメッキ層と前記オーミック電極層との間において、前記導電性サポート体および前記メッキシード層の少なくとも一方が、Cuからなる第1層ならびに、Cuよりも熱膨張係数の小さいTi,Ni,Fe,Co,Cr,Auおよび白金族からなる群から選択される遷移金属からなる第2層を交互に複数回積層した積層体を含み、
前記導電性サポート体は、前記主のCuメッキ層の厚みが140μm以上であり、さらに厚み5μm以上のNiメッキ層を含むことを特徴とするIII族窒化物半導体素子。
A conductive support including a main Cu plating layer and Cu as a main material;
A plating seed layer on the conductive support;
An ohmic electrode layer on the plating seed layer;
A group III nitride semiconductor layer on the ohmic electrode layer ,
In between the ohmic electrode layer and the main of Cu plating layer, at least one of the conductive support and the plating seed layer, a first layer made of Cu and having a small coefficient of thermal expansion than Cu Ti, Ni , look-containing Fe, Co, Cr, a laminate formed by laminating a plurality of times alternately second layer comprising a transition metal selected from the group consisting of Au and platinum group,
The conductive support body, the main of and the thickness of the Cu plating layer is 140μm or more, more Group III nitride semiconductor device according to claim including Mukoto a Ni plating layer or thickness of 5 [mu] m.
前記導電性サポート体の前記遷移金属がNiであり、前記導電性サポート体が前記積層体を含む請求項に記載のIII族窒化物半導体素子。 Wherein said transition metal is Ni der the conductive support is, the conductive support comprises said laminate, III nitride semiconductor device according to claim 2. 前記メッキシード層の前記遷移金属がTiであり、前記メッキシード層が前記積層体を含む請求項に記載のIII族窒化物半導体素子。 Wherein the transition metal is Ti der the plating seed layer is, the plating seed layer comprises the laminate, III nitride semiconductor device according to claim 2. 成長用基板上にIII族窒化物半導体層を形成する第1工程と、
前記III族窒化物半導体層上に、オーミック電極層およびメッキシード層をこの順に形成する第2工程と、
前記メッキシード層上に、主のCuメッキ層を含み、Cuを主材料とする導電性サポート体を形成する第3工程と、
前記成長用基板を前記III族窒化物半導体層から剥離する第4工程と、を有し、
記第3工程では、前記主のCuメッキ層と前記メッキシード層との間に、Cuからなる第1層およびNiからなる第2層を交互に複数回積層した積層体を形成することを特徴とするIII族窒化物半導体素子の製造方法。
A first step of forming a group III nitride semiconductor layer on the growth substrate;
A second step of forming an ohmic electrode layer and a plating seed layer in this order on the group III nitride semiconductor layer;
A third step of forming a conductive support body including a main Cu plating layer on the plating seed layer, the main material being Cu ;
And a fourth step of peeling the growth substrate from the group III nitride semiconductor layer,
Prior Symbol third step, during the main of Cu plating layer and the plating seed layer, forming a laminate formed by laminating a plurality of times alternately second layer of the first layer and Ni of Cu A method for producing a group III nitride semiconductor device.
成長用基板上にIII族窒化物半導体層を形成する第1工程と、
前記III族窒化物半導体層上に、オーミック電極層およびメッキシード層をこの順に形成する第2工程と、
前記メッキシード層上に、主のCuメッキ層を含み、Cuを主材料とする導電性サポート体を形成する第3工程と、
前記成長用基板を前記III族窒化物半導体層から剥離する第4工程と、を有し、
前記第2または第3工程では、前記主のCuメッキ層と前記III族窒化物半導体層との間に、前記導電性サポート体または前記メッキシード層に、Cuからなる第1層およびCuよりも熱膨張係数の小さいTi,Ni,Fe,Co,Cr,Auおよび白金族からなる群から選択される遷移金属からなる第2層を交互に複数回積層した積層体を形成し、
前記導電性サポート体は、前記主のCuメッキ層の厚みが140μm以上であり、さらに厚み5μm以上のNiメッキ層を含むことを特徴とするIII族窒化物半導体素子の製造方法。
A first step of forming a group III nitride semiconductor layer on the growth substrate;
A second step of forming an ohmic electrode layer and a plating seed layer in this order on the group III nitride semiconductor layer;
A third step of forming a conductive support body including a main Cu plating layer and containing Cu as a main material on the plating seed layer;
And a fourth step of peeling the growth substrate from the group III nitride semiconductor layer,
In the second or third step, between the main of the Cu plating layer and the group III nitride semiconductor layer, the conductive support or the plating seed layer, than the first layer and Cu of Cu Forming a laminate in which a second layer made of a transition metal selected from the group consisting of Ti, Ni, Fe, Co, Cr, Au and a platinum group having a small thermal expansion coefficient is alternately laminated a plurality of times ;
The method of manufacturing a group III nitride semiconductor device, wherein the conductive support body includes a Ni plating layer having a thickness of the main Cu plating layer of 140 μm or more and further a thickness of 5 μm or more .
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JP2012146898A (en) * 2011-01-14 2012-08-02 Toshiba Corp Light emitting device, light emitting module, and method for manufacturing light emitting device

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