JP5936696B2 - Group III nitride semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a group III nitride semiconductor device and a method for manufacturing the same.

  Semiconductor devices include various devices such as field effect transistors (FETs) and light emitting diodes (LEDs). For these, for example, a group III-V semiconductor composed of a compound of a group III element and a group V element is used.

  Group III nitride semiconductors using Al, Ga, In, etc. as group III elements and mainly using N as group V elements have a high melting point, a high dissociation pressure of nitrogen, and bulk single crystal growth is difficult. In general, it is formed by growing on a sapphire substrate because there is no cheap and conductive single crystal substrate.

  However, since the sapphire substrate is insulative and no current flows, the light-emitting diode has conventionally been manufactured by sequentially growing an n-type group III nitride semiconductor layer, an active layer (light-emitting layer) and a p-type III on the sapphire substrate. A part of the semiconductor laminate composed of the group nitride semiconductor layer is removed to expose the n-type group III nitride semiconductor layer, and the exposed n-type group III nitride semiconductor layer and p-type group III nitride are exposed. It has been usual to employ a lateral structure in which an n-type electrode and a p-type electrode are arranged on a physical semiconductor layer and current flows in the lateral direction.

  On the other hand, in recent years, after forming a lift-off layer on a growth substrate such as a sapphire substrate, a group III nitride semiconductor multilayer body including a light emitting layer is formed, and the semiconductor multilayer body is supported by a conductive support body. The technology for obtaining the LED chip is put to practical use by selectively dissolving the lift-off layer by chemical etching, peeling off the sapphire substrate (lift-off), and sandwiching the support body and the semiconductor laminate with a pair of electrodes. It has been studied.

  In order to fabricate a group III nitride semiconductor LED chip having such a vertical structure, for example, a growth substrate is peeled from an epitaxial layer by etching a lift-off layer made of a metal other than group III or a metal nitride. There are known chemical lift-off methods and photo-chemical lift-off methods in which etching is performed while irradiating light such as ultraviolet light during etching and activating the lift-off layer. These are methods in which the growth substrate is lifted off from the epitaxial layer by dipping in a specific etching solution and dissolving the lift-off layer by etching, and are collectively referred to as “chemical lift-off method” in this specification.

  Patent Document 1 describes a method for manufacturing a group III nitride semiconductor vertical structure LED chip having no cracks in a light emitting layer, using the chemical lift-off method as described above. This document describes an example of forming a conductive support body mainly composed of Cu by growing Cu plating via a plating seed layer of Ni / Au / Cu on a group III nitride semiconductor multilayer body. (See Examples 23 to 25).

International Publication No. 2011/055462

  However, in the group III nitride semiconductor vertical structure LED chip described in Patent Document 1 in which a group III nitride semiconductor layer is formed on a conductive support body mainly composed of Cu, the LED chip is used as a lamp module. It has been found that there is a problem that cracks occur in the group III nitride semiconductor layer when the soldering is mounted on the substrate. This problem applies to other group III nitride semiconductor devices regardless of the group III nitride semiconductor vertical structure LED chip.

  Therefore, the present inventors previously optimized the thickness of the conductive support and the group III nitride semiconductor layer in the international patent application (PCT / JP2012 / 003431), and thickened the Ni layer as the plating seed layer. In addition, by using a Ni-based alloy as a plating seed layer, a group III nitride semiconductor device in which cracks are unlikely to occur in the group III nitride semiconductor layer and a method for manufacturing the same are provided.

  However, according to further studies by the present inventors, even in the case of a group III nitride semiconductor element in which cracks are hardly generated as described above, when a thermal shock at 300 ° C. assuming heating solder mounting is applied, the forward voltage (Vf ) Increased.

  Therefore, in view of the above problems, the present invention is a group III nitride semiconductor device in which a group III nitride semiconductor layer is less likely to crack after being mounted on an arbitrary substrate, and an increase in forward voltage due to heating solder mounting is suppressed. It aims at providing the manufacturing method.

In order to achieve the above object, the gist of the present invention is as follows.
(1) a main for Cu plating layer, and a conductive support of Cu as the main material,
A plating seed layer on the conductive support;
An ohmic electrode layer on the plating seed layer;
A group III nitride semiconductor layer on the ohmic electrode layer ,
A group III nitride semiconductor comprising a laminate in which a first layer made of Cu and a second layer made of Ni are alternately laminated a plurality of times between the main Cu plating layer and the plating seed layer element.

(2) a conductive support body including a main Cu plating layer and mainly made of Cu;
A plating seed layer on the conductive support;
An ohmic electrode layer on the plating seed layer;
A group III nitride semiconductor layer on the ohmic electrode layer ,
In between the ohmic electrode layer and the main of Cu plating layer, at least one of the conductive support and the plating seed layer, a first layer made of Cu and having a small coefficient of thermal expansion than Cu Ti, Ni , look-containing Fe, Co, Cr, a laminate formed by laminating a plurality of times alternately second layer comprising a transition metal selected from the group consisting of Au and platinum group,
The conductive support body, the main of and the thickness of the Cu plating layer is 140μm or more, more Group III nitride semiconductor device according to claim including Mukoto a Ni plating layer or thickness of 5 [mu] m.

(3) wherein the transition metal is Ni der the conductive support is, the conductive support comprises said laminate, III nitride semiconductor device according to the above (2).

(4) wherein the transition metal is Ti der the plating seed layer is, the plating seed layer comprises the laminate, III nitride semiconductor device according to the above (2).

( 5 ) a first step of forming a group III nitride semiconductor layer on the growth substrate;
A second step of forming an ohmic electrode layer and a plating seed layer in this order on the group III nitride semiconductor layer;
A third step of forming a conductive support body including a main Cu plating layer on the plating seed layer, the main material being Cu ;
And a fourth step of peeling the growth substrate from the group III nitride semiconductor layer,
Prior Symbol third step, during the main of Cu plating layer and the plating seed layer, forming a laminate formed by laminating a plurality of times alternately second layer of the first layer and Ni of Cu A method for producing a group III nitride semiconductor device.

( 6 ) a first step of forming a group III nitride semiconductor layer on the growth substrate;
A second step of forming an ohmic electrode layer and a plating seed layer in this order on the group III nitride semiconductor layer;
A third step of forming a conductive support body including a main Cu plating layer and containing Cu as a main material on the plating seed layer;
And a fourth step of peeling the growth substrate from the group III nitride semiconductor layer,
In the second or third step, between the main of the Cu plating layer and the group III nitride semiconductor layer, the conductive support or the plating seed layer, than the first layer and Cu of Cu Forming a laminate in which a second layer made of a transition metal selected from the group consisting of Ti, Ni, Fe, Co, Cr, Au and a platinum group having a small thermal expansion coefficient is alternately laminated a plurality of times ;
The method of manufacturing a group III nitride semiconductor device, wherein the conductive support body includes a Ni plating layer having a thickness of the main Cu plating layer of 140 μm or more and further a thickness of 5 μm or more .

  According to the present invention, there is provided a group III nitride semiconductor device in which a group III nitride semiconductor layer is hardly cracked after being mounted on an arbitrary substrate, and an increase in forward voltage due to mounting by heating solder is suppressed, and a method for manufacturing the same. Can be provided.

1 is a schematic perspective view of one group III nitride semiconductor device 100 according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view illustrating the layer configuration of a conductive support body and a plating seed layer of a group III nitride semiconductor device 100 according to an embodiment of the present invention, where (A) is a first example, and (B) is a first example. A second example is shown. (A)-(I) show each process of the manufacturing method of the group III nitride semiconductor element 100 concerning one Embodiment of this invention with a schematic side sectional drawing. (A)-(D) show the one part process of the manufacturing method of the semiconductor element 100 concerning one Embodiment of this invention shown in FIG. 3 with a schematic top view. (A)-(D) are the same schematic top views as FIG. 3 except having changed the application | coating aspect of the 2nd resist 116. FIG. FIG. 3 is a schematic perspective view of a group III nitride semiconductor device assembly 200 before singulation in one embodiment of the present invention.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings, taking as an example the case where a growth substrate is peeled off using a chemical lift-off method. In the drawings, for convenience of explanation, the lift-off layer, the group III nitride semiconductor layer, and the plating seed layer are exaggerated at a ratio different from the actual state with respect to the conductive support body.

  A group III nitride semiconductor device 100 (hereinafter simply referred to as “device 100”) according to an embodiment of the present invention will be described with reference to FIG. The element 100 includes a conductive support body 122A mainly made of Cu (copper), a plating seed layer 114 on the conductive support body 122A, and a semiconductor as a group III nitride semiconductor layer on the plating seed layer 114. And a structure portion 110. An upper electrode 128 is provided on the semiconductor structure 110, and the lower electrode serves as the conductive support body 122A, whereby the element 100 is formed.

  In the present embodiment, the conductive support body 122A is mainly formed by a plating method such as wet plating or dry plating, as will be described later. Although other methods may be included, it is preferable to form a necessary thickness for the support body because a plating method can be formed at low cost. The plating seed layer 114 is a layer for growing the conductive support body 122A thereon.

  This embodiment shows a case where the main plating layer is made of Cu. The layer structure of the conductive support body and the plating seed layer of the element 100 is shown in FIG. FIG. 2A shows a first example of the layer configuration, and FIG. 2B shows a second example of the layer configuration. As shown in FIGS. 2A and 2B, the conductive support body 122 </ b> A includes a main Cu plating layer 130. Here, in this specification, the “main Cu plating layer” means the thickest Cu plating layer among the Cu plating layers in the conductive support body. The conductive support body 122A is mainly made of Cu. Here, “Cu is the main material” means that the thickness of the Cu plating layer occupies 70% or more of the thickness of the conductive support body 122A, and the Cu component in the conductive support body occupies 70% or more. Say.

  The semiconductor structure 110 is not particularly limited as long as it is a group III nitride semiconductor layer, and may be a single layer or a laminate of two or more layers. If the semiconductor structure 110 includes the light emitting layer, it becomes an LED, and if it does not, it becomes another semiconductor element. The semiconductor structure 110 can be epitaxially grown on the lift-off layer 102 described later with reference to FIG. 2 by, for example, MOCVD. For example, a group III nitride semiconductor layer of the first conductivity type on the lift-off layer 102, a light emitting layer in which a multiple quantum well (MQW) structure is formed of a group III nitride semiconductor, and a second conductivity different from the first conductivity type A group III nitride semiconductor layer of a type is sequentially laminated to form the semiconductor structure 110, and the device 100 of the present invention can be a group III nitride semiconductor vertical structure LED chip. In this case, the first conductivity type may be n-type and the second conductivity type may be p-type, or vice versa.

  Thus, the thermal expansion coefficient differs between the conductive support body 122A mainly composed of Cu and the semiconductor structure portion 110 made of a group III nitride semiconductor layer. Here, it is necessary to heat and melt the solder in order to mount the element on the lamp / module board by heating solder. Although it depends on the solder to be used, the mounting temperature is generally 100 to 300 ° C. After mounting, the device is lowered to the operating temperature (generally −40 to 85 ° C.). By applying such a thermal shock, a residual stress is generated between the conductive support body having a different thermal expansion coefficient and the semiconductor structure composed of the group III nitride semiconductor layer, and cracks in the group III nitride semiconductor layer are generated. It seems to be a cause.

  Here, as shown in FIGS. 2A and 2B, the characteristic configuration of the element 100 of the present embodiment is between the main Cu plating layer 130 and the semiconductor structure 110 of the conductive support body 122A. The conductive support body 122A or the plating seed layer 114 includes a predetermined laminated body.

  FIG. 2A shows an example in which the plating seed layer 114 is composed of a stacked body 134. The conductive support body 122A includes a main Cu plating layer 130 and a Ni plating layer 132 thereon. The laminated body 134 constituting the plating seed layer is formed by alternately laminating a first layer 134A made of the first transition metal and a second layer 134B made of the second transition metal different from the first transition metal a plurality of times. It becomes.

  FIG. 2B illustrates an example in which the conductive support body 122 </ b> A includes a stacked body 136. The conductive support body 122A includes a main Cu plating layer 130 and a laminated body 136 thereon. The laminated body 136 is formed by alternately laminating a first layer 136A made of a first transition metal and a second layer 136B made of a second transition metal different from the first transition metal a plurality of times. The plating seed layer 114 can have a two-layer structure of a Cu layer 114A and a Ti layer 114B, for example.

  Such stacked bodies 134 and 136 have a remarkable effect that even if the device 100 is mounted on an arbitrary substrate, cracks are hardly generated in the group III nitride semiconductor layer. The effect of such an effect is not necessarily clear, but the laminated body can relieve the residual stress between the conductive support body and the semiconductor structure composed of the group III nitride semiconductor layer, which can be generated by thermal shock. It is speculated that this is possible. Furthermore, the present inventors have found that the effect of relaxation of the residual stress by the laminate is very high, and as a result, it is possible to sufficiently suppress an increase in forward voltage (Vf) due to thermal shock, The present invention has been completed.

  Here, the first and second transition metals are selected from the group consisting of Cu, Ti, Ni, Fe, Co, Cr, Au, and the platinum group, and the second transition metal is more heated than the first transition metal. Each is preferably selected so that an expansion coefficient (also referred to as a linear expansion coefficient) becomes small. For example, when the first transition metal is Cu, the other transition metal has a lower thermal expansion coefficient than Cu. When the first transition metal is Ni, the second transition metal may be any other transition metal except Cu. These transition metals are preferable because they are easy and relatively inexpensive to form by sputtering or plating, and are generally materials that can be used for manufacturing semiconductor devices. Since Au and platinum group are expensive, other metals are more preferable. However, Au or platinum group is good for preventing oxidation of the conductive support body, and may be partially used. Moreover, you may use the alloy which combined the metal in the said group for a 1st layer and a 2nd layer. If the second transition metal is selected from a group other than the above group, the difference in thermal expansion coefficient between the first transition metal and the second transition metal becomes large, which may cause peeling.

  When the first transition metal constituting the main plating layer is other than Cu, the first layer of the laminate is the first transition metal, and the second layer has a thermal expansion coefficient higher than that of the first transition metal. By making the second transition metal small in size, the effect of the present invention that the group III nitride semiconductor layer is hardly cracked after being mounted on an arbitrary substrate and the increase in the forward voltage due to mounting by heating solder can be suppressed. Play.

  In the present embodiment, it is preferable that the first transition metal is Cu and the second transition metal is a transition metal other than Cu. This is because the thermal expansion can be moderately reduced by using a transition metal other than Cu for one of the laminated bodies against the thermal expansion of the main Cu plating layer 130.

  As shown in FIG. 2B, when the conductive support body 122A includes the stacked body 136, the stacked body 136 preferably includes Cu and Ni as the first and second transition metals, respectively. This is because by using Ni having a smaller thermal expansion coefficient than Cu, the thermal expansion can be moderately reduced, and both Cu and Ni can be easily plated, and the device can be manufactured at low cost. Other choices include Ni and Cr, Cu and Cr, and Cu and Ni-Fe-Co alloys for the first and second transition metals, respectively. A form in which a third transition metal is incorporated in between may be used, such as Cu / Ni / Co.

  As shown in FIG. 2A, when the plating seed layer 114 includes the stacked body 134, the stacked body 134 preferably includes Cu and Ti as the first and second transition metals, respectively. If the first layer 134A on the plating growth side is made of Cu, the conductive support body can be preferably grown by plating. If the second layer 134B on the semiconductor structure 110 side is made of Ti, the adhesion to the semiconductor structure portion is made. This is because a sufficient amount can be secured. Moreover, thermal expansion can be gently reduced by using Ti whose thermal expansion coefficient is smaller than Cu. Other choices include Ni and Ti, Cu and Ni, Au and Ni, Au and Cr, Cu and Cr, etc., respectively, for the first and second transition metals. A form in which a third transition metal is incorporated in between may be used, such as Cu / Ni / Ti.

  In addition, in the conductive support body 122A, the thickness of the main Cu plating layer 130 is preferably 140 μm or more, and further preferably includes a Ni plating layer having a thickness of 5 μm or more. In the case of FIG. 2A, the thickness of the Ni plating layer 132 is set to 5 μm or more. In the case of FIG. 2B, for example, the second layer 136B constituting the stacked body 136 may be a Ni plating layer having a thickness of 5 μm or more. . By setting the thickness of the main Cu plating layer 130 to 140 μm or more, warping of the conductive support body 122A can be sufficiently suppressed, and by providing the Ni plating layer having a thickness of 5 μm or more, the main Cu plating layer 130 Since the effect of mitigating thermal expansion between the layer and the plating seed layer can be obtained, the effects of suppressing cracks associated with heating solder mounting and suppressing increase in forward voltage can be more reliably obtained. The total thickness of the conductive support body 122A is preferably 400 μm or less from the viewpoint of not greatly degrading the throughput.

  The thickness of the semiconductor structure 110 is preferably 6 to 20 μm. This is because by setting the thickness to 6 μm or more, it is possible to secure the strength of the semiconductor structure 110 and further suppress the generation of cracks, and by setting the thickness to 20 μm or less, the throughput is not greatly deteriorated.

  An example of a method for manufacturing the element 100 will be described in detail below with reference to FIGS. First, the correspondence between FIG. 3 and FIG. 4 will be described first. 4A is a schematic top view of the state shown in FIG. 3B, and the II cross section in FIG. 4A corresponds to FIG. 3B. Note that the cross-sectional views of FIG. 3 other than FIG. 3B are also in the same position. FIG. 4B is a top view of the state shown in FIG. FIG. 4C is a top view of the state shown in FIG. FIG. 4D is a cross-sectional view of the state shown in FIG.

  First, as shown in FIG. 3A, a lift-off layer 104 and a group III nitride semiconductor layer 106 are formed in this order on a growth substrate 102 (first step).

  Next, as shown in FIGS. 3B and 4A, a part of the group III nitride semiconductor layer 106 is removed, and a groove 108 in which a part of the growth substrate 102 is exposed at the bottom is formed into a mesh. In this embodiment, a plurality of semiconductor structure portions 110 made of a group III nitride semiconductor layer having a transverse cross-sectional shape arranged in a vertical and horizontal direction are formed by forming a lattice shape.

  Next, as shown in FIGS. 3C and 4B, all the grooves 108 are closed with a resist 112 as a filler.

  Next, as shown in FIG. 3D, a plating seed layer 114 is formed on the semiconductor structure 110 and the first resist 112 by sputtering or electron beam evaporation (second step). When the plating seed layer 114 includes a stacked body (not shown in FIG. 3), the plating seed layer 114 may be formed by alternately changing the target.

  Next, as shown in FIGS. 3E and 4C, a lattice-like thin film resist 116 is formed above the groove 108 and on the plating seed layer 114. Here, a portion 118 exposed without being covered with the second resist 116 is formed.

  Next, as shown in FIGS. 3 (F) and 4 (D), a plating layer is formed from the exposed portion 118, and a plurality of semiconductor structures 110 are integrally supported on the plating seed layer 114. The support body 122 is formed (third step). When the conductive support body 122 includes a laminated body (not shown in FIG. 3), the conductive support body 122 may be formed by alternately changing the plating bath. Here, the conductive support body 122 is formed so as to have a recess 120 on the resist 116 and a hole 124 on the crossing portion of the resist 116, which will be described in detail later.

  Next, as shown in FIG. 3G, the resist 116 and the resist 112 are removed, and a void 126 that leads from the hole 124 to the lift-off layer 104 is formed. Specifically, the resist 116 is dissolved by supplying a liquid for dissolving the resist such as acetone from the holes 124. In the present embodiment, the plating seed layer portion sandwiched between the resist 116 and the resist 112 under the hole 124 is mechanically or chemically removed following the removal of the resist 116. Thereafter, when the liquid such as acetone reaches the resist 112, the resist 112 can also be removed.

  Next, the lift-off layer 104 is removed by etching by supplying an etching solution through the holes 124 and the gaps 126. As a result, the growth substrate 102 is peeled from the semiconductor structure 110 (fourth step, FIG. 3H).

  Finally, as shown in FIG. 3 (I), the conductive support bodies 122 are cut along the recesses 120 between the semiconductor structure portions 110, so that each is supported by the cut conductive support bodies 122A. A plurality of elements 100 having the semiconductor structure 110 are separated. It can be seen that the broken line in FIG. 4D is a cutting line and is along the recess 120. Further, the upper electrode 128 is formed on the peeling surface side of the semiconductor structure 110. The conductive support body 122A also serves as the lower electrode.

  Here, the thickness of the conductive support body 122A and each layer thereof can be adjusted by the growth time of plating, and the thickness of the semiconductor structure 110 can be adjusted by the epitaxial growth time. It can be measured by observing. The thickness is the thickness at the center of the element 100.

  The manufacturing method shown in FIGS. 3 and 4 can easily form a hole for supplying an etching solution used in the chemical lift-off method in the conductive support body, and can easily cut the conductive support body (ie, singulation). It is also preferable in that it can be performed. That is, as the plating grows from the exposed portion 118, adjacent plating layers formed on the resist 116 are bonded to each other. As a result, the conductive support body 112 can integrally support the plurality of semiconductor structure portions 110. At that time, a recess 120 as shown in FIG. 2F is formed on the resist 116. By cutting along the recess 120 with a dicing device, it can be more easily cut than a conductive support body having no recess.

  The resist 116 is formed in a lattice shape (see FIG. 3C). For this reason, the hole 124 can be formed on the intersection of the resist 116. The elongation rate and shape of the plating layer can be controlled by the type, temperature, and current of the plating bath.

  Note that the application mode is not particularly limited as long as the resist 116 is formed in a mesh shape. 5A to 5D are schematic top views similar to FIG. 4 except that the application mode of the resist 116 is changed. The shape of the exposed portion of the plating seed is not a square as shown in FIG. 4C, but may be rounded, chamfered, dented or the like at the corners of the square as shown in FIG. 5C. In this case, as shown in FIG. 5D, the diameter of the hole 124 after plating can be made larger than that in FIG.

  FIG. 6 is a schematic perspective view of the semiconductor element combination 200 before singulation, which can be obtained by the above manufacturing method. The semiconductor device combination 200 includes a growth substrate 102, a lift-off layer 104 on the growth substrate 102, a plurality of semiconductor structures 110 independent of each other via a groove 108 on the lift-off layer 104, and the plurality A conductive support body 122 that integrally supports the semiconductor structure 110 of the semiconductor device. The conductive support body 122 has a recess 120 at a position above the groove 108, and a groove is formed on the intersection of the groove 108. A hole 124 leading to 108 is provided. Note that a plating seed layer 114 is provided on the semiconductor structure 110. The semiconductor element combination 200 is a wafer in the state shown in FIG. That is, in this specification, the “semiconductor element assembly” means a wafer in a state before lift-off in which a plurality of semiconductor structures are sandwiched between a growth substrate and a conductive support and are integrally supported.

  In the semiconductor element assembly 200, the lift-off layer 104 can be removed by supplying an etching solution to the groove 108 through the hole 124. In addition, the support body 122 can be more easily cut along the recess 120.

(Semiconductor layer formation process)
The growth substrate 102 is preferably a sapphire substrate or an AlN template substrate in which an AlN film is formed on a sapphire substrate. What is necessary is just to select suitably according to the kind of lift-off layer to form, the composition of Al, Ga, In of a group III nitride semiconductor layer, the quality of a LED chip, cost, etc.

  As the lift-off layer 104, a chemical lift-off method is preferable because a metal other than Group III such as CrN and ScN and a metal nitride buffer layer can be dissolved by chemical selective etching. It is preferable to form the film by sputtering, vacuum deposition, ion plating, or MOCVD. Usually, the thickness of the lift-off layer 104 is about 2 to 100 nm.

(Groove formation process)
It is preferable to use a dry etching method to remove a part of the group III nitride semiconductor layer 106. This is because the etching end point of the group III nitride semiconductor layer 106 can be controlled with good reproducibility. Further, when the group III nitride semiconductor layer 106 is connected, the lift-off layer 104 cannot be etched with an etchant in a subsequent process, and therefore this removal is performed at least until the growth substrate or the lift-off layer is exposed. Shall. In the above-described embodiment, the lift-off layer 104 is removed at the bottom of the groove 108 and the growth substrate 102 is completely exposed.

  In the present embodiment, the cross-sectional shape of the semiconductor structure 110 is shown as a quadrangle, but the cross-sectional shape of the semiconductor structure 110 is not particularly limited, and may be a circle or a polygon such as a triangle or a hexagon. When the cross-sectional shape of the semiconductor structure part 110 is a polygon, by forming a resist 116 in a mesh shape along the grooves 108 around the polygonal semiconductor structure 110, A hole 124 communicating with the groove 108 can be formed, and a recess 120 can be formed in the conductive support body 122 at a position above the groove 108. In the step of dividing the semiconductor element into pieces, the semiconductor structure 110 is preferably aligned so that the groove 108 can be easily cut by a laser dicing apparatus.

  When the cross section of the semiconductor structure 110 is a square, one side is usually 250 to 3000 μm. Further, the width of the straight portion of the groove 108 is preferably within a range of 40 to 200 μm, and more preferably 60 to 100 μm. This is because when the thickness is 40 μm or more, the etching solution can be sufficiently smoothly supplied to the groove 108, and when the thickness is 200 μm or less, the loss of the light emitting area can be minimized.

(Groove filling / plating seed layer formation process)
In the embodiment of FIG. 1, the resist 112 is used as a filler for the groove 108, and then all the resist 112 is removed together with the lattice-like resist 116 to form the void 126. However, the present invention is not limited to this, and the filler May be removed to form a gap for supplying etching. For example, when the shape of the cross section of the semiconductor structure portion 110 is a quadrangle, as described in PCT / JP2011 / 005485, only one side surface of each semiconductor structure portion 110 is closed with a resist as a filler, and the remaining three The side can also be plugged with a metal as a filler. In the filler removing step, the metal is not removed, but only the resist is removed, and an etching supply gap can be formed only in the groove filled with the resist. In this case, in the lift-off process of FIG. 1H, etching proceeds from the groove side closed with the resist toward the opposite groove side.

As a filler for the groove 108, any material may be used instead of the resist 112. For example, a metal that is not used for the conductive support body 122 and the plating seed layer 114, or an insulator such as SiO ₂ can be used. In order to remove the filler, an etching solution corresponding to the material may be selected.

(Resist formation and plating process)
By appropriately adjusting the width and thickness of the resist 116 and the shape at the intersection of the resist 116, the thickness of the conductive support body 122 at the recessed position 120, the thickness of the conductive support body 122 on the semiconductor structure 110, and The dimension of the hole 124 can be set as appropriate. Moreover, you may employ | adopt the multistep plating process which repeats the process of forming a mesh-like resist, and the process of forming an electroconductive support body in multiple times.

  The thickness of the conductive support body 122 at the position of the dent 120 is not particularly limited, but is preferably a thickness that can be easily cut by a dicing apparatus, for example, 120 μm or less.

  In the present embodiment, the resist 116 is formed on the plating seed layer 114. However, the plating seed layer corresponding to the position where the hole is formed may be removed in advance, and the resist 116 may be formed in contact with the resist 112.

  Although not shown in the drawing, it is preferable to form an ohmic electrode layer in contact with each of the plurality of semiconductor layers 106 between the main surface of the plurality of semiconductor structures 110 and the plating seed layer 114. Further, when the present invention is used for manufacturing an LED chip, it is more preferable that a reflective layer is further formed between the ohmic electrode layer and the plating seed layer 114, or the ohmic electrode layer also functions as the reflective layer. . For the formation of these layers, dry film forming methods such as vacuum deposition, ion plating, and sputtering can be used.

  The ohmic electrode layer can be formed of a metal having a large work function, for example, a noble metal such as Pd, Pt, Rh, Au, Ag, or Co, Ni. Further, since the reflection layer has a high reflectance such as Rh, it can also be used as the ohmic electrode layer. However, when the light emitting region is visible light, Ag or Al layer is used, and when the light emitting region is ultraviolet region, Rh is used. More preferably, a Ru layer or the like is used. In addition, since the ohmic electrode layer and the reflective layer are as thin as 0.2 μm at the maximum, even if they are treated as a part of the conductive support body, the effect of the present invention is not affected.

(Lift-off process)
Etching solutions usable in the chemical lift-off method of the present invention include, when the lift-off layer is CrN, ceric ammonium nitrate solution or ferricyanium potassium-based solution, such as hydrochloric acid, nitric acid, organic acid, when the lift-off layer is ScN. For example, known etchants having selectivity can be given. Further, it is obvious that the lift-off process is not limited to the above-described chemical lift-off method, and a photochemical lift-off method or a laser lift-off method may be used.

  The surface of the semiconductor structure 110 exposed after lift-off is preferably cleaned by wet cleaning. Next, the thickness of the semiconductor structure portion may be adjusted by cutting a predetermined amount by dry etching and / or wet etching.

Further, an n-type ohmic electrode and a bonding pad electrode as upper electrodes are formed by a lift-off method using a resist as a mask. Al, Cr, Ti, Ni, Pt, Au, etc. are used as the electrode material, and Ti, Pt, Au, etc. are formed on the ohmic electrode and bonding pad as a cover layer to reduce wiring resistance and wire bond. Improve adhesion. Note that a protective film (insulating film) such as SiO ₂ or SiN may be provided on the exposed side surface and surface (excluding the bonding pad surface) of the semiconductor structure 110.

(Individualization process)
In the singulation process, the semiconductor structure portions 110 are cut using, for example, a blade dicer or a laser dicing apparatus.

  The above is an example of a typical embodiment, and the present invention is not limited to this embodiment, and can be modified as appropriate without departing from the scope of the claims.

Example 1
The semiconductor device shown in FIG. 1 was manufactured by the manufacturing method shown in FIGS. Specifically, first, a lift-off layer (CrN layer, thickness: 18 nm) was formed on a growth sapphire substrate by forming a metal Cr layer by sputtering and performing heat treatment in an ammonia atmosphere. Thereafter, as a group III nitride semiconductor layer on the lift-off layer, a buffer layer (composition: GaN, thickness: 4 μm), an n-GaN layer (thickness: 6 μm), and a light emitting layer (AlInGaN-based MQW layer, thickness: 0.1 μm) , P-GaN layers (thickness: 0.2 μm) were sequentially stacked. The thickness of the group III nitride semiconductor layer at this stage is 10.3 μm.

  Thereafter, a part of the semiconductor layer is removed by dry etching to form a lattice-shaped groove so that a part of the sapphire substrate is exposed, thereby forming a plurality of semiconductor structure parts independent of each other having a square cross section Formed. The width of the semiconductor structure was 1350 μm, and the arrangement of the individual elements was a grid pattern. The pitch between elements is 1500 μm, that is, the groove width is 150 μm.

  Next, an ohmic electrode layer (Ag, thickness: 0.1 μm) was formed on the semiconductor structure portion by EB vapor deposition. Next, as shown in FIGS. 3C and 4B, all the grooves were closed with a photoresist, and the regions on the individual semiconductor structures were opened. Thereafter, a plating seed layer was formed on the surface of the semiconductor structure, on the p-ohmic electrode layer, and on the surface of the resist. As the plating seed layer, a Ti layer (thickness: 0.02 μm) and a Cu layer (thickness: 0.15 μm) were alternately stacked three times in order from the semiconductor structure side by a sputtering method (230 W, 4.5 mtorr). That is, in the present embodiment, a laminate in which the first layer is a Cu layer and the second layer is a Ti layer is a plating seed layer.

Next, a lattice-like photoresist having a height of 10 μm and a width of 160 μm as shown in FIG. 4C was formed. Thereafter, Ni was deposited to a thickness of 40 μm and Cu was deposited to a thickness of 150 μm by plating from the exposed plating seed layer to complete a conductive support body. Ni plating uses a nickel sulfamate solution: Ni (NH ₂ SO ₃ ) ₂ , the liquid temperature is in the range of 50-60 ° C., the current is 38.5 A, the plating growth time is 2 hours, and the deposition rate is 20 μm / hr. Cu plating is electroplating using a copper sulfate electrolyte, the temperature of the solution is in the range of 25-30 ° C., the current is 67.4 A, the plating growth time is 4.3 hours, and the deposition rate is 35 μm / hr. Met. At this time, the conductive support body was bonded on the resist, and a plurality of semiconductor structure portions were integrally supported.

  The formed conductive support body was formed with recesses and holes as shown in FIGS. 3 (F) and 4 (D). The thickness of the thinnest portion of the recess was 30 to 50 μm, that is, about 30 μm at the position near the hole and about 50 μm at the thickest position away from the hole. As for the hole size, the distance between the opposite vertices was about 77 μm. As described above, the hole for supplying the etching solution can be easily formed only by forming the plating layer.

  Next, acetone was supplied into the holes to remove the resist. At this time, the plating seed layer directly under the hole was dissolved and removed with a dilute ferric chloride solution and a Ni selective etching solution. And the resist which filled the groove | channel with acetone continuously was removed through the hole, and the space | gap was formed. At this time, no resist residue remained.

  Next, the lift-off layer was removed by a chemical lift-off method using a CrN selective etching solution, and the sapphire substrate was peeled off.

  Thereafter, a total of 5.3 μm of the entire buffer layer and a part of the n-GaN layer was dry-etched using an IPC-RIE apparatus, so that the thickness of the group III nitride semiconductor layer was 5.0 μm.

  Then, after treating the surface of the n-GaN layer by using a 6 mol / L KOH solution at 60 ° C. for 10 minutes, a resist is applied to form an n-electrode patterning, and then an EB vapor deposition method is used. (Ti / Al / Ni / Au, each thickness: 0.02 μm / 1.5 μm / 0.02 μm / 2 μm) was formed, and the resist was removed by lift-off with acetone.

  A support tape (ultraviolet curing tape) is attached to the back side of the conductive support body, the conductive support body is fixed to the table of the laser dicing machine, and the conductive support body is laser-cut from the semiconductor structure side along the recess. 25 group III nitride semiconductor devices were obtained.

<Evaluation 1: Crack generation due to thermal shock>
The 25 group III nitride semiconductor devices thus obtained were allowed to stand on a hot plate at 300 ° C. for 5 minutes, and then the surface of the group III nitride semiconductor layer was observed to determine whether cracks had occurred. Judged. In this example, none of the 25 cracks occurred (crack occurrence rate 0%).

<Evaluation 2: Increase in forward voltage (Vf) due to thermal shock>
The forward voltage Vf of each of the 25 elements was measured before and after heating on the hot plate at room temperature and an operating current of 350 mA with an auto probe measuring device. In this example, the average value of 25 elements of ΔVf obtained by subtracting Vf before heating from Vf after heating was 0.06V.

(Comparative Example 1)
Example 1 except that the plating seed layer is formed by electron beam evaporation and the layer structure is a Ti layer (thickness: 0.02 μm) and a Cu layer (thickness: 0.45 μm) in this order from the semiconductor structure side. A group III nitride semiconductor device was fabricated by the method described above. That is, the laminate was not formed in this comparative example.

(Comparative Example 2)
A group III nitride semiconductor is manufactured in the same manner as in Example 1 except that the plating seed layer is composed of a Ti layer (thickness: 0.02 μm) and a Cu layer (thickness: 0.45 μm) in order from the semiconductor structure side An element was produced. That is, the laminate was not formed in this comparative example.

(Example 2)
A group III nitride semiconductor device was produced in the same manner as in Example 1 except that the layer configuration of the plating seed layer and the conductive support was changed as follows. First, the plating seed layer was a Ti layer (thickness: 0.02 μm) and a Cu layer (thickness: 0.45 μm) in this order from the semiconductor structure side. Next, as for the conductive support body, the Ni plating layer (thickness 10 μm) and the Cu plating layer (thickness 10 μm) are alternately grown twice in order from the plating seed layer side, and the Cu plating layer (thickness 150 μm) is further grown by plating. I let you. In other words, in this embodiment, the conductive support body includes a laminate in which the first layer is a Cu layer and the second layer is a Ni layer. The thickness of each layer was adjusted by the plating growth time.

(Example 3)
Example 2 except that the laminated body included in the conductive support was formed by alternately growing the Ni plating layer (thickness 5 μm) and the Cu plating layer (thickness 5 μm) four times in order from the plating seed layer side. A group III nitride semiconductor device was fabricated in the same manner.

  For Comparative Examples 1 and 2 and Examples 2 and 3, Evaluation 1 and Evaluation 2 were performed in the same manner as Example 1. The results are shown in Tables 1 and 2. Table 1 shows the effect of forming a laminate on the plating seed layer. Table 2 shows the effect of forming a laminated body on the conductive support body.

  According to the present invention, there is provided a group III nitride semiconductor device in which a group III nitride semiconductor layer is hardly cracked after being mounted on an arbitrary substrate, and an increase in forward voltage due to mounting by heating solder is suppressed, and a method for manufacturing the same. Can be provided.

100 Group III Nitride Semiconductor Device 102 Growth Substrate 104 Lift-off Layer 106 Group III Nitride Semiconductor Layer 108 Groove 110 Semiconductor Structure 112 Resist (Filler)
114 plating seed layer 116 resist 118 exposed portion of plating seed layer 120 recess 122 conductive support body 122A cut conductive support body 122B corner of conductive support body 122C outer peripheral portion opposite to semiconductor structure portion 124 hole 126 gap 128 Upper electrode 130 Main Cu plating layer 132 Ni plating layer 134,136 Laminated body 134A, 136A First layer 134B, 136B Second layer 200 Semiconductor element assembly

Claims (6)

A conductive support body including a main Cu plating layer and made of Cu as a main material;
A plating seed layer on the conductive support;
An ohmic electrode layer on the plating seed layer;
A group III nitride semiconductor layer on the ohmic electrode layer ,
A group III nitride semiconductor comprising a laminate in which a first layer made of Cu and a second layer made of Ni are alternately laminated a plurality of times between the main Cu plating layer and the plating seed layer element. A conductive support including a main Cu plating layer and Cu as a main material;
A plating seed layer on the conductive support;
An ohmic electrode layer on the plating seed layer;
A group III nitride semiconductor layer on the ohmic electrode layer ,
In between the ohmic electrode layer and the main of Cu plating layer, at least one of the conductive support and the plating seed layer, a first layer made of Cu and having a small coefficient of thermal expansion than Cu Ti, Ni , look-containing Fe, Co, Cr, a laminate formed by laminating a plurality of times alternately second layer comprising a transition metal selected from the group consisting of Au and platinum group,
The conductive support body, the main of and the thickness of the Cu plating layer is 140μm or more, more Group III nitride semiconductor device according to claim including Mukoto a Ni plating layer or thickness of 5 [mu] m. Wherein said transition metal is Ni der the conductive support is, the conductive support comprises said laminate, III nitride semiconductor device according to claim 2. Wherein the transition metal is Ti der the plating seed layer is, the plating seed layer comprises the laminate, III nitride semiconductor device according to claim 2. A first step of forming a group III nitride semiconductor layer on the growth substrate;
A second step of forming an ohmic electrode layer and a plating seed layer in this order on the group III nitride semiconductor layer;
A third step of forming a conductive support body including a main Cu plating layer on the plating seed layer, the main material being Cu ;
And a fourth step of peeling the growth substrate from the group III nitride semiconductor layer,
Prior Symbol third step, during the main of Cu plating layer and the plating seed layer, forming a laminate formed by laminating a plurality of times alternately second layer of the first layer and Ni of Cu A method for producing a group III nitride semiconductor device. A first step of forming a group III nitride semiconductor layer on the growth substrate;
A second step of forming an ohmic electrode layer and a plating seed layer in this order on the group III nitride semiconductor layer;
A third step of forming a conductive support body including a main Cu plating layer and containing Cu as a main material on the plating seed layer;
And a fourth step of peeling the growth substrate from the group III nitride semiconductor layer,
In the second or third step, between the main of the Cu plating layer and the group III nitride semiconductor layer, the conductive support or the plating seed layer, than the first layer and Cu of Cu Forming a laminate in which a second layer made of a transition metal selected from the group consisting of Ti, Ni, Fe, Co, Cr, Au and a platinum group having a small thermal expansion coefficient is alternately laminated a plurality of times ;
The method of manufacturing a group III nitride semiconductor device, wherein the conductive support body includes a Ni plating layer having a thickness of the main Cu plating layer of 140 μm or more and further a thickness of 5 μm or more .

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