WO2014017160A1 - Module, and device having module mounted thereon - Google Patents

Module, and device having module mounted thereon Download PDF

Info

Publication number
WO2014017160A1
WO2014017160A1 PCT/JP2013/064618 JP2013064618W WO2014017160A1 WO 2014017160 A1 WO2014017160 A1 WO 2014017160A1 JP 2013064618 W JP2013064618 W JP 2013064618W WO 2014017160 A1 WO2014017160 A1 WO 2014017160A1
Authority
WO
WIPO (PCT)
Prior art keywords
module
semiconductor substrate
main surface
resin layer
substrate
Prior art date
Application number
PCT/JP2013/064618
Other languages
French (fr)
Japanese (ja)
Inventor
野村　忠志
陽一 高木
伸明 小川
明彦 鎌田
憲正 西田
充弘 松本
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Publication of WO2014017160A1 publication Critical patent/WO2014017160A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate

Definitions

  • the present invention relates to a module in which a semiconductor substrate is disposed on one main surface of a wiring board, and a module mounting apparatus on which the module is mounted.
  • the semiconductor substrate 102 is flip-chip mounted, and the resin layer 104 covering the semiconductor substrate 102 and the connection terminals 103 is further formed. . Then, the module 100 is formed by polishing the upper surfaces of the resin layer 104 and the semiconductor substrate 102 so that the connection terminals 103 and the end surfaces of the semiconductor substrate 102 are exposed from the surface of the resin layer 104.
  • the semiconductor substrate 102 to be flip-chip mounted has a circuit formed on the surface facing the wiring substrate 101.
  • the semiconductor substrate 102 By polishing the upper surface of the semiconductor substrate 102 (the main surface not facing the wiring substrate), the semiconductor substrate 102 Since the height of the module 100 can be reduced without changing the characteristics, the height of the module 100 can be reduced by polishing the resin layer 104 and the semiconductor substrate 102 until the end face of the connection terminal 103 is exposed. Further, since the upper surface of the semiconductor substrate 102 having a higher thermal conductivity than the resin of the resin layer 104 is exposed from the surface of the resin layer 104, the heat dissipation characteristics of the module 100 are also improved.
  • JP 2002-343904 (see paragraph 0013, FIG. 1, etc.)
  • the heat dissipation characteristics of the module are improved as compared with the module in which the upper surface of the semiconductor substrate 102 is covered with the resin layer 104.
  • a semiconductor substrate with high heat generation for example, a power amplifier IC used in a high frequency module or the like
  • the semiconductor substrate 102 malfunctions due to insufficient heat dissipation.
  • further improvement of the heat dissipation characteristics of the module 100 is required.
  • the present invention has been made in view of the above-described problems, and it is an object of the present invention to provide a module with excellent heat dissipation characteristics and a module mounting device on which the module is mounted.
  • a module of the present invention includes a wiring board, a semiconductor substrate mounted on one main surface of the wiring board, and a non-opposing main surface on the side of the semiconductor substrate that does not face the wiring substrate. And a resin layer formed on the one main surface covering the semiconductor substrate so as to be exposed, and a metal film is formed on at least a part of the non-opposing main surface of the semiconductor substrate.
  • the heat generated from the module can be radiated through the metal film having a higher thermal conductivity than the semiconductor substrate. Therefore, the non-opposing main surface of the semiconductor substrate that does not face the wiring substrate is a resin layer. Compared with a conventional module that is only exposed from the module, the heat dissipation characteristics of the module can be improved.
  • the non-opposing main surface of the semiconductor substrate exposed from the resin layer is protected.
  • the semiconductor substrate can be prevented from being damaged by an external impact or the like.
  • irregularities may be formed on the surface of the metal film. In this way, the surface area of the metal film exposed from the surface of the resin layer increases, so that the heat dissipation characteristics of the module are further improved.
  • the metal film may be formed by plating.
  • the metal film can be formed by plating.
  • connection terminal enables connection between an external mother board and the module.
  • the module mounting apparatus of the present invention is characterized by including the above-described module and a mother substrate connected to the metal film of the module. By comprising in this way, the module mounting board
  • the metal film of the semiconductor substrate is used for connection to the mother substrate, whereby the connection terminal and the metal film of the semiconductor substrate are used. Therefore, the connection strength between the module and the mother board is increased as compared with the conventional module that is connected to the mother board only with the connection terminals.
  • connection area between the module and the mother board increases when the module and the mother board are connected, so the connection strength between the module and the mother board increases.
  • the metal film of the module may be connected to a ground electrode for grounding formed on the mother substrate.
  • the metal film (module) and the mother substrate are connected such that the non-opposing main surface of the semiconductor substrate that does not face the wiring substrate faces the mother substrate.
  • the distance between the semiconductor substrate and the ground electrode of the mother substrate is closer, so that the shielding characteristics of the semiconductor substrate by the ground electrode are improved.
  • the distance between the semiconductor substrate and the ground electrode is reduced, heat generated from the module is easily radiated through the ground electrode of the mother substrate, so that the heat dissipation characteristics of the module are also improved.
  • the exposed semiconductor substrate is formed by forming the resin layer covering the semiconductor substrate so that the non-opposing main surface of the semiconductor substrate mounted on the one main surface of the wiring substrate is not opposed to the wiring substrate.
  • a conventional module in which the non-opposing main surface of the semiconductor substrate is only exposed from the resin layer by forming a metal film having higher thermal conductivity than the semiconductor substrate on at least a part of the non-opposing main surface of In comparison, the heat dissipation characteristics of the module can be improved.
  • FIG. 1 is a cut front view of the module mounting apparatus 1 on which the module 2 is mounted.
  • a module mounting apparatus 1 on which a module 2 according to this embodiment is mounted includes a mother board 3, a module 2 mounted on the mother board 3, and a connecting portion between the mother board 3 and the module 2. And an underfill resin layer 4 made of a resin, for example, and mounted on an electronic device using a high frequency such as a mobile phone.
  • the mother board 3 has a ground electrode 5 for grounding and wiring patterns (not shown) constituting various circuits, and the ground electrode 5 and the wiring pattern are formed in a predetermined wiring pattern or mother board 3 by a via conductor 6 or the like.
  • the ground electrode 5 formed on the mother substrate 3 is a metal film formed on the non-opposing main surface 9a on the side not facing the wiring substrate of the columnar connection terminals 8 and the semiconductor substrate 9 of the module 2 described later.
  • 10 is connected to the mounting electrode 7 connected to 10 via the via conductor 6.
  • the mother substrate 3 is formed of a material such as glass epoxy resin or ceramic.
  • the connection terminal 8 does not necessarily have to be connected to the ground electrode 5. For example, only one side of the two connection terminals 8 shown in FIG. 1 is connected to the ground electrode 5 via the via conductor 6. It may be.
  • the underfill resin layer 4 is made of, for example, an epoxy resin, and is formed by filling a resin so as to fill a gap between the mother substrate 3 and the module 2 when the module 2 is mounted on the mother substrate 3.
  • the underfill resin layer 4 may be omitted.
  • the module 2 includes a wiring board 11, a semiconductor substrate 9 mounted on one main surface 11 a of the wiring board 11, a column-shaped connection terminal 8 erected, and the other main board 11 of the wiring board 11.
  • Chip components 12a, 12b, and 12c mounted on the surface 11b, a resin layer 13a that covers the semiconductor substrate 9 and the connection terminals 8 on one main surface 11a of the wiring substrate 11, and a chip component on the other main surface 11b of the wiring substrate 11 And a resin layer 13b covering 12a to 12c.
  • the module include a Bluetooth (registered trademark) module, a wireless LAN module, and an antenna switch module disposed immediately below an antenna of a mobile phone.
  • the wiring substrate 11 is formed of a glass epoxy resin substrate, a low-temperature co-fired ceramic (LTCC) substrate, a glass substrate, and the like, and both main surfaces 11a and 11b have mounting electrodes 15 and electrodes 15a for forming connection terminals 8; A wiring pattern (not shown) and the like are formed, and a ground electrode 14 for grounding, another wiring pattern (not shown), a via conductor (not shown) and the like are formed inside.
  • the wiring board 11 may be either a single layer board or a multilayer board.
  • the wiring substrate 11 is an LTCC multilayer substrate
  • a ceramic green sheet in which a slurry in which a mixed powder such as alumina and glass is mixed with an organic binder and a solvent is formed into a sheet is formed.
  • Via holes are formed at predetermined positions of the ceramic green sheet by laser processing, etc., and the formed via holes are filled with a conductor paste containing Ag, Cu, etc., and via conductors for interlayer connection are formed, and printing by the conductor paste is performed.
  • Various electrode patterns are formed. Thereafter, the ceramic green sheets are laminated and pressed to form a ceramic laminate, which is fired at a low temperature of about 1000 ° C., so-called low temperature firing.
  • the semiconductor substrate 9 and the chip components 12a to 12c are mounted on both the main surfaces 11a and 11b of the wiring substrate 11 as mounting components.
  • the semiconductor substrate 9 forms a system IC that processes, for example, an RF signal and a baseband signal by forming a predetermined electric circuit on the surface of the wiring substrate 11 that faces the one main surface 11a.
  • face down mounting flip chip mounting
  • the chip components 12a to 12c are composed of a chip capacitor, a chip inductor, and a chip resistor, and are mounted on the other main surface 11b of the wiring board 11 by a known surface mounting technique.
  • a columnar (pin-shaped) connection terminal 8 is further mounted on one main surface 11 a of the wiring substrate 11.
  • the connection terminal 8 is mainly composed of Cu, for example, and is mounted on the electrode 15a via solder.
  • a metal film 10 is formed on the non-facing main surface 9 a of the semiconductor substrate 9 and the tip surface 8 a of the connection terminal 8.
  • a Ni layer is formed on the non-facing main surface 9 a of the semiconductor substrate 9 (or the front end surface 8 a of the connection terminal 8) by plating, and an Au layer is formed on the Ni layer. Ni / Au film. Note that the metal film 10 may not be formed on the distal end surface 8a of the connection terminal 8.
  • the chip components 12a to 12c mounted on the other main surface 11b of the wiring board 11 there are some chip components 12a to 12c that are different in height from the other main surface 11b of the wiring board 11, In this embodiment, as shown in FIG. 1, the chip component 12a has the lowest height from the other main surface 11b of the wiring board 11 among all the chip components 12a to 12c. Further, each of the semiconductor substrate 9 and the connection terminal 8 is formed so that the height from the one main surface 11a of the wiring substrate 11 is the same in the mounted or standing state.
  • the height Ht of the semiconductor substrate 9 (or connection terminal 8) having the highest height from the one main surface 11a of the wiring substrate 11 on the one main surface 11a of the wiring substrate 11 is the other main surface of the wiring substrate 11.
  • 11b of the chip component 12a that other from the main surface 11b of the height H 0 semiconductor substrate to be lower than the (other main surface tallest low chip component in 11b) 9 (or the connection terminal 8) is formed ing.
  • the semiconductor substrate 9 has a larger area (cross-sectional area) than any of the other mounting components (each chip component 12a to 12c). .
  • the resin layer 13a on the one main surface 11a of the wiring board 11 is made of, for example, an epoxy resin so that the non-facing main surface of the semiconductor substrate 9 and the front end surface 8a of the connection terminal 8 are exposed as shown in FIG.
  • the semiconductor substrate 9 and the connection terminals 8 are covered.
  • one main surface side of the wiring substrate 11 of the module 2 is in a so-called flush state in which the surface of the resin layer 13a, the non-opposing main surface 9a of the semiconductor substrate 9, and the tip surface 8a of the connection terminal 8 form the same surface. Is formed.
  • This flush state can be formed by a polishing / grinding process described later.
  • the resin layer 13b on the other main surface 11b of the wiring board 11 is made of, for example, the same kind of epoxy resin as the resin layer 13a on the one main surface 11a, so that the chip components 12a to 12c are not exposed as shown in FIG. It is formed in a state where all of the chip parts are covered.
  • the resin forming the resin layer 13b is a resin layer. It is preferable to use a resin having a smaller linear expansion coefficient than the resin forming 13a.
  • FIGS. 2 shows a part of each process of manufacturing the module 2
  • FIG. 3 shows each process following FIG.
  • a planar grounding ground electrode 14 and a wiring pattern are formed therein, and the semiconductor substrate 9 and the chip components 12a to 12c are formed on both main surfaces 11a and 11b.
  • the wiring board 11 on which the mounting electrode 15 and the connection terminal forming electrode 15a are formed is prepared (wiring board preparation step).
  • the semiconductor substrate 9, the connection terminal 8, and the chip components 12a to 12c are mounted at positions corresponding to the mounting electrodes 15 of the wiring substrate 11 (component, connection terminal mounting).
  • the semiconductor component 9 is face-down mounted (flip chip mounting) on the one main surface 11a of the wiring substrate 11, and the chip components 12a to 12c are mounted on the other main surface 11b of the wiring substrate 11 by a known surface mounting technique.
  • the pin-like connection terminals 8 are mounted on the electrodes 15 for forming the connection terminals of the wiring board 11 via solder.
  • the connection terminal 8 for example, a columnar metal made of Cu or an alloy containing Cu as a main component can be used.
  • a resin layer 13a covering the semiconductor substrate 9 and the connection terminals 8 is formed on one main surface 11a of the wiring board 11, and each chip component is formed on the other main surface 11b.
  • a resin layer 13b covering 12a to 12c is formed (resin layer forming step).
  • a resin is applied or printed on both the main surfaces 11a and 11b by using a dispensing method or a printing method, and put into an oven set at a predetermined curing temperature (for example, about 180 ° C. for an epoxy resin).
  • the resin is cured to form both resin layers 13a and 13b.
  • a module body 18 is formed by covering the mounting components (9, 12a to 12c) and the connection terminals 8 arranged on both main surfaces 11a and 11b of the wiring board 11 with resin.
  • the columnar connection terminals 8 may be formed by plating before the semiconductor substrate 9 is mounted on the one main surface 11a of the wiring board 11 in addition to the method described above.
  • the semiconductor substrate 9 is mounted after the connection terminal 8 is formed, and the resin layer 13a is formed by covering the connection terminal 8 with resin together with the semiconductor substrate 9 mounted on the one main surface 11a.
  • connection terminals 8 are formed after mounting the semiconductor substrate 9, the resin layer 13 a is formed before the connection terminals 8 are formed, and the surface of the connection terminal forming electrode 15 a is exposed by irradiating the surface of the resin layer 13 a with a laser.
  • a connection terminal forming recess and filling the recess with a conductive paste for example, Ag paste or Cu paste
  • a printing technique for example, a printing technique
  • a conductor for example, Cu
  • connection terminal 8 When the connection terminal 8 is formed by plating, unlike the case where the pin-shaped connection terminal 8 is mounted, the solder at the joint between the wiring substrate 11 and the connection terminal 8 even if the connection terminal 8 is polished or ground. However, the side surface of the connection terminal 8 does not wet and the solder is not exposed from the resin layer 13a. Therefore, the connection terminals 8 having a fine diameter can be formed with high precision on the one main surface 11a of the wiring board 11, and the pitch of the connection terminals 8 can be reduced.
  • the resin layer 13a of the module body 18 is exposed so that the non-facing main surface 9a of the semiconductor substrate 9 and the front end surface 8a of the connection terminal 8 are exposed from the surface of the resin layer 13a.
  • Polishing or grinding the surface can be performed by grinding using a cup grindstone, lapping using a free abrasive, sand blasting, or the like.
  • the surface of the resin layer 13 a, the non-opposing main surface 9 a of the semiconductor substrate 9, and the front end surface 8 a of the connection terminal 8 form the same plane.
  • the semiconductor substrate 9 and the connection terminal 8 are polished or ground together with the resin of the resin layer 13a so as to be in a state.
  • the chip component 11a having the lowest height Ht of the semiconductor substrate 9 (or the connection terminal 8) from the one main surface 11a of the wiring substrate 11 is the lowest from the other main surface 11b of the wiring substrate 11. polishing or grinding a semiconductor substrate 9 (or the connection terminal 8) to be lower than the height H 0 of the.
  • the non-opposing main surface 9a of the semiconductor substrate 9 may be uneven.
  • the metal film 10 can also be formed with unevenness, and has high thermal conductivity.
  • the surface area of the metal film 10 can be increased.
  • the metal film 10 is formed thick so as to fill the unevenness of the non-opposing main surface 9a of the semiconductor substrate 9. 10 surfaces can be flattened.
  • the average roughness (Ra) of the non-opposing main surface 9a of the semiconductor substrate 9 is in the range of 0.1 ⁇ m to 15 ⁇ m. It is preferable to form.
  • a metal film 10 is formed on the non-opposing main surface 9a of the semiconductor substrate 9 and the front end surface 8a of the connection terminal 8 exposed from the surface of the resin layer 13a (metal film formation).
  • module 2 is manufactured.
  • the metal film 10 is formed using a plating process or a printing technique.
  • a plating process a Ni layer is grown on the non-opposing main surface 9a of the semiconductor substrate 9 and the front end surface 8a of the connection terminal 8, and an Au layer is grown thereon to form the metal film 10.
  • the metal film 10 on the non-opposing main surface 9a of the semiconductor substrate 9 does not need to be formed on the entire surface of the non-facing main surface 9a of the semiconductor substrate 9, and may be formed at least partially.
  • the one main surface 11a (the non-opposing main surface 9a of the semiconductor substrate 9) of the wiring board 11 of the module 2 manufactured by the method for manufacturing the module 2 is opposed to the mother substrate 3.
  • the metal film 10 formed on the non-opposing main surface 9a of the semiconductor substrate 9 and the front end surface 8a of the connection terminal 8 and the mounting electrode 7 formed on the surface of the mother substrate 3 are connected via solder or the like. It is manufactured by doing.
  • the resin layer 13a is formed on the one main surface 11a of the wiring substrate 11 so that the non-opposing main surface of the semiconductor substrate 9 on the side not facing the wiring substrate 11 is exposed, and the resin layer 13a. Since the metal film 10 having higher thermal conductivity than the semiconductor substrate 9 is formed on the non-opposing main surface 9a of the semiconductor substrate 9 exposed from above, the non-facing main surface 9a of the semiconductor substrate 9 is exposed from the surface of the resin layer 13a. Compared with a conventional module that is merely provided, the heat dissipation characteristics of the module 2 are improved.
  • the metal film 10 formed on the non-facing main surface Since unevenness can also be formed on the surface, the surface area of the metal film 10 exposed from the surface of the resin layer 13a increases, and thereby the heat dissipation characteristics of the module 2 are further improved.
  • the ductile metal film 10 on the non-opposing main surface 9a of the semiconductor substrate 9, the non-opposing main surface 9a of the semiconductor substrate 9 exposed from the resin layer 13a is protected, so that the semiconductor substrate 9 is It is possible to suppress damage due to external impact or the like.
  • the metal film 10 is formed of a Ni / Au film, the wettability of solder when the module 2 and the mother board 3 are connected by solder is improved.
  • connection terminal 8 having a higher thermal conductivity than the resin of the resin layer 13a is erected on the one main surface 11a of the wiring substrate 11 on which the semiconductor substrate 9 is mounted, and the front end surface 8a of the connection terminal 8 is also a resin layer. Since it is exposed from the surface of 13a, the heat dissipation characteristic of the module 2 is further improved. Further, the connection terminal 8 allows the mother board 3 and the module 2 to be connected.
  • connection terminal 8 connected to the ground electrode 5 of the mother board 3 (height from the one main surface 11a of the wiring board 11) can be shortened.
  • the parasitic inductance due to the connection terminal 8 is reduced, and the ground can be strengthened.
  • the flip-chip mounted semiconductor substrate 9 and connection terminal 8 are arranged on one main surface 11a of the wiring board 11, and the chip component 12a such as a chip capacitor is arranged on the other main surface 11b. To 12c are arranged.
  • the module 2 In order to reduce the size of the module 2 (to reduce the mounting area of the wiring board 11), it is effective to dispose mounting components on both main surfaces 11a and 11b of the wiring board 11. As in the prior art shown in FIG. 4, it is also effective to reduce the height of the module 2 by reducing the height by polishing the non-opposing main surface 9 a of the semiconductor substrate 9 together with the connection terminals 8. However, for example, when the semiconductor substrate 9 and the chip components 12a to 12c are mounted on the same main surface of the wiring substrate 11, the module 2 is reduced in height by polishing the non-opposing main surface 9a of the semiconductor substrate 9. It is difficult to plan.
  • the chip components 12a to 12c which are chip capacitors and chip inductors, are shaved by polishing or the like, the characteristics may be deteriorated. Therefore, with such a configuration, the height of the semiconductor substrate 9 from the same main surface cannot be made lower than the height of each of the chip components 12a to 12c mounted on the same main surface.
  • the flip-chip mounted semiconductor substrate 9 and the connection terminals 8 that do not deteriorate in characteristics even when the non-opposing main surface 9a is polished on the one main surface 11a of the wiring substrate 11 are provided.
  • the chip components 12 a to 12 b such as chip capacitors and chip inductors are arranged on the other main surface 11 b, and the surface of the resin layer 13 a on the one main surface 11 a of the wiring substrate 11 together with the semiconductor substrate 9 and the connection terminals 8.
  • the module configuration is such that the module 2 can be reduced in height by polishing or grinding.
  • the height Ht of the semiconductor substrate 9 (or connection terminal 8) having the highest height from the one main surface 11a of the wiring substrate 11 is the chip component 12a having the lowest height from the other main surface 11b of the wiring substrate 11.
  • the height H 0 semiconductor substrate 9 to be lower than (or connecting terminals 8) is polished or ground, it is possible to reduce the height of reliably module 2.
  • the resin layer 13a is coated with the non-facing main surface 9a of the semiconductor substrate 9 by polishing or grinding the resin layer 13a so that the non-facing main surface 9a of the semiconductor substrate 9 is exposed from the surface of the resin layer 13a.
  • the distance between the non-opposing main surface 9a of the semiconductor substrate 9 and the ground electrode 5 of the mother substrate 3 is reduced. Heat generated from the module 2 can be easily dissipated through the ground electrode 5, and the heat dissipation characteristics of the module 2 are improved.
  • the metal film 10 of the semiconductor substrate 9 is connected to the mounting electrode 7 connected to the ground electrode 5 of the mother substrate 3 via solder, the heat generated from the module 2 is more effectively dissipated. be able to.
  • the circuit surface of the semiconductor substrate 9 (the surface of the semiconductor substrate 9 facing the wiring substrate 11) and the ground electrode. Since the distance to the semiconductor substrate 9 is reduced, the influence of unnecessary noise radiated from the circuit surface of the semiconductor substrate 9 can be effectively suppressed, and unnecessary noise irradiated to the semiconductor substrate 9 from the outside is suppressed. can do.
  • the tip surface 8 a of the connection terminal 8 and the non-facing surface 9 a of the semiconductor substrate 9 are used. Since the mother substrate 3 and the module 2 can be connected by the metal film 10 formed on each of them, the module 2 is compared with the conventional module mounting apparatus that connects to the mother substrate 3 only by the connection terminal 8 of the module 2. The connection strength between the mother board 3 and the mother board 3 is improved.
  • connection area between the metal film 10 of the semiconductor substrate 9 and the mother substrate 3 increases, so that the connection between the module 2 and the mother substrate 3 is increased. Strength is further improved.
  • the amount of resin forming the resin layer 13a is smaller than the amount of resin in the resin layer 13b on the other main surface 11b.
  • 13b may cause the balance of shrinkage stress to be lost, and the wiring substrate 11 may be warped.
  • the semiconductor substrate 9 that is harder than the resin that forms the resin layers 13a, 13b has both main surfaces 11a of the wiring substrate 11.
  • 11b the one having the largest area (cross-sectional area) in plan view is used among the mounting parts 9, 12a to 12c mounted on each of the resin layers 13a, 11b. Warping of the wiring board 11 caused by collapse can be suppressed.
  • the resin forming the resin layer 13b has a smaller linear expansion coefficient than that of the resin forming the resin layer 13a, warping of the wiring board 11 can be further suppressed.
  • each of the above-described embodiments there may be a plurality of semiconductor substrates 9 flip-chip mounted on the one main surface 11a of the wiring substrate 11.
  • the area of the semiconductor substrate 9 in plan view may be smaller than the area of any of the other mounted components.
  • it may be disposed on the one main surface 11a of the wiring substrate 11. That is, any configuration is possible as long as the semiconductor substrate 9 capable of polishing or grinding the main surface 9a is mounted on or arranged on the one main surface 11a of the wiring substrate 11, and the other is to reduce the mounting area of the wiring substrate 11.
  • the arrangement of each mounted component can be appropriately devised.
  • chip components 12a to 12c such as chip capacitors and chip inductors are mounted on the other main surface 11b of the wiring board 11, but the other main surface 11b is the same as the semiconductor substrate 9 mounted on the one main surface 11a.
  • another different semiconductor substrate 9 may be mounted.
  • the metal film 10 may be formed using, for example, a conductive paste, or may be formed by sputtering or vapor deposition.
  • connection terminals 8 formed on one main surface 11 a of the wiring board 11 may be any number, and the connection terminals 8 may be arranged on the other main surface 11 b of the wiring board 11. Further, the connection terminals 8 are not necessarily arranged on the one main surface 11 a of the wiring board 11. That is, the connection terminal 8 and the semiconductor substrate 9 may be disposed on different main surfaces of the wiring substrate 11. When the connection terminal and the semiconductor substrate 9 are arranged on different main surfaces of the wiring substrate 11, the metal film is not only formed on the non-opposing main surface 9a of the semiconductor substrate 9, but also the resin layer 13b. By forming also around, it can function as a shield layer of the module 2.
  • the resin layers 13a and 13b are not necessarily provided on both main surfaces 11a and 11b of the wiring board 11.
  • each surface is formed so that the non-opposing main surface 9a of the semiconductor substrate 9, the front end surface 8a of the connection terminal 8, and the surface of the resin layer 13a are the same surface, so-called flush.
  • the height of the surface of the resin layer 13a may be formed lower than the height of the semiconductor substrate 9 (non-opposing main surface 9a) and the connection terminal 8 (tip surface 8a). That is, the resin layer 13a may be formed so that the end of the semiconductor substrate 9 and the end of the connection terminal 8 protrude from the surface of the resin layer 13a.
  • the present invention can be applied to any module as long as the semiconductor substrate is flip-chip mounted on one main surface of the wiring board.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The purpose of the present invention is to provide a module exhibiting excellent heat dissipation characteristics, and a device having this module mounted thereon. A module (2) is provided with: a wiring board (11); a semiconductor substrate (9) mounted on one main surface (11a) of the wiring board (11); and a resin layer (13a) which is formed on the one main surface (11a) of the wiring board (11), and which covers the semiconductor substrate (9) such that a non-facing main surface (9a) of a side of the semiconductor substrate (9), said side not facing the wiring board (11), is exposed. A metal film (10) having greater thermal conductivity than the resin of the resin layer (13a) is formed on at least a portion of the non-facing main surface (9a) of the semiconductor substrate (9), said non-facing surface being exposed from a surface of the resin layer (13a). As a result, the module (2) exhibiting excellent heat dissipation characteristics can be achieved.

Description

モジュールおよびモジュール搭載装置Module and module mounting device
本発明は、配線基板の一方主面に半導体基板が配置されたモジュールおよびこのモジュールが搭載されたモジュール搭載装置に関する。 The present invention relates to a module in which a semiconductor substrate is disposed on one main surface of a wiring board, and a module mounting apparatus on which the module is mounted.
　近年、携帯電話などの携帯端末装置の小型・薄型化に伴って、これに搭載されるモジュールの小型化が要求されている。そこで、従来では、図４に示すように、モジュール１００を構成する配線基板１０１の一方主面上にフェイスダウンで実装（フリップチップ実装）された半導体基板１０２と、該半導体基板１０２と同一主面上に配置された柱状の接続端子１０３と、半導体基板１０２および柱状の接続端子１０３を被覆する樹脂層１０４を備えるモジュールが提案されている（特許文献１）。 In recent years, with the reduction in size and thickness of mobile terminal devices such as mobile phones, there has been a demand for downsizing of modules mounted thereon. Therefore, conventionally, as shown in FIG. 4, a semiconductor substrate 102 mounted face-down (flip chip mounting) on one main surface of a wiring substrate 101 constituting the module 100, and the same main surface as the semiconductor substrate 102 There has been proposed a module including a columnar connection terminal 103 disposed on top and a resin layer 104 covering the semiconductor substrate 102 and the columnar connection terminal 103 (Patent Document 1).
　この場合、モジュール１００の一方主面上に柱状の接続端子１０３を形成した後、半導体基板１０２をフリップチップ実装し、さらに、当該半導体基板１０２および接続端子１０３を被覆する樹脂層１０４が形成される。そして、樹脂層１０４の表面から接続端子１０３と半導体基板１０２の端面が露出するように、樹脂層１０４と半導体基板１０２の上面を研磨してモジュール１００を形成する。 In this case, after forming the columnar connection terminals 103 on one main surface of the module 100, the semiconductor substrate 102 is flip-chip mounted, and the resin layer 104 covering the semiconductor substrate 102 and the connection terminals 103 is further formed. . Then, the module 100 is formed by polishing the upper surfaces of the resin layer 104 and the semiconductor substrate 102 so that the connection terminals 103 and the end surfaces of the semiconductor substrate 102 are exposed from the surface of the resin layer 104.
　フリップチップ実装される半導体基板１０２は、配線基板１０１との対向面に回路が形成されており、半導体基板１０２の上面（配線基板との非対向主面）を研磨することで、半導体基板１０２の特性を変えずにモジュール１００の低背化が可能であるため、接続端子１０３の端面が露出するまで樹脂層１０４および半導体基板１０２を研磨することにより、モジュール１００の低背化が可能である。また、熱伝導率が樹脂層１０４の樹脂よりも高い半導体基板１０２の上面が樹脂層１０４の表面から露出するため、モジュール１００の放熱特性も向上する。 The semiconductor substrate 102 to be flip-chip mounted has a circuit formed on the surface facing the wiring substrate 101. By polishing the upper surface of the semiconductor substrate 102 (the main surface not facing the wiring substrate), the semiconductor substrate 102 Since the height of the module 100 can be reduced without changing the characteristics, the height of the module 100 can be reduced by polishing the resin layer 104 and the semiconductor substrate 102 until the end face of the connection terminal 103 is exposed. Further, since the upper surface of the semiconductor substrate 102 having a higher thermal conductivity than the resin of the resin layer 104 is exposed from the surface of the resin layer 104, the heat dissipation characteristics of the module 100 are also improved.
特開２００２－３４３９０４号（段落００１３、図１等参照）JP 2002-343904 (see paragraph 0013, FIG. 1, etc.)
　しかしながら、上記した従来技術では、半導体基板１０２の上面が樹脂層１０４から露出しているため、半導体基板１０２の上面が樹脂層１０４に覆われているモジュールと比較して、モジュールの放熱特性が向上しているものの、発熱性が高い半導体基板（例えば、高周波モジュール等で使用されるパワーアンプＩＣ等）を実装した場合には、放熱が足りずに、半導体基板１０２が誤動作する等の不具合が生じるおそれがあり、モジュール１００のさらなる放熱特性の向上が要求されている。 However, in the above-described prior art, since the upper surface of the semiconductor substrate 102 is exposed from the resin layer 104, the heat dissipation characteristics of the module are improved as compared with the module in which the upper surface of the semiconductor substrate 102 is covered with the resin layer 104. However, when a semiconductor substrate with high heat generation (for example, a power amplifier IC used in a high frequency module or the like) is mounted, there is a problem that the semiconductor substrate 102 malfunctions due to insufficient heat dissipation. There is a fear that further improvement of the heat dissipation characteristics of the module 100 is required.
　本発明は、上記した課題に鑑みてなされたものであり、放熱特性の優れたモジュールを提供するとともに、このモジュールが搭載されたモジュール搭載装置を提供することを目的とする。 The present invention has been made in view of the above-described problems, and it is an object of the present invention to provide a module with excellent heat dissipation characteristics and a module mounting device on which the module is mounted.
　上記した目的を達成するために、本発明のモジュールは、配線基板と、前記配線基板の一方主面に実装された半導体基板と、前記半導体基板の前記配線基板と対向しない側の非対向主面が露出するように前記半導体基板を被覆する前記一方主面に形成された樹脂層とを備え、前記半導体基板の前記非対向主面の少なくとも一部に金属膜が形成されていることを特徴としている。 To achieve the above object, a module of the present invention includes a wiring board, a semiconductor substrate mounted on one main surface of the wiring board, and a non-opposing main surface on the side of the semiconductor substrate that does not face the wiring substrate. And a resin layer formed on the one main surface covering the semiconductor substrate so as to be exposed, and a metal film is formed on at least a part of the non-opposing main surface of the semiconductor substrate. Yes.
　このように構成することにより、半導体基板よりも熱伝導率が高い金属膜を介してモジュールから発生する熱を放熱することができるため、半導体基板の配線基板と対向しない非対向主面が樹脂層から露出しているだけの従来のモジュールと比較して、モジュールの放熱特性を向上することができる。 With this configuration, the heat generated from the module can be radiated through the metal film having a higher thermal conductivity than the semiconductor substrate. Therefore, the non-opposing main surface of the semiconductor substrate that does not face the wiring substrate is a resin layer. Compared with a conventional module that is only exposed from the module, the heat dissipation characteristics of the module can be improved.
　また、半導体基板の配線基板と対向しない側の非対向主面の少なくとも一部に延性を有する金属膜を形成することにより、樹脂層から露出した半導体基板の当該非対向主面が保護されるため、半導体基板が外部からの衝撃等により破損するのを抑制することができる。 Further, by forming a ductile metal film on at least a part of the non-opposing main surface of the semiconductor substrate that does not face the wiring substrate, the non-opposing main surface of the semiconductor substrate exposed from the resin layer is protected. The semiconductor substrate can be prevented from being damaged by an external impact or the like.
　また、前記金属膜の表面に凹凸が形成されていてもよい。このようにすると、樹脂層の表面から露出した金属膜の表面積が増加するため、さらにモジュールの放熱特性が向上する。 Further, irregularities may be formed on the surface of the metal film. In this way, the surface area of the metal film exposed from the surface of the resin layer increases, so that the heat dissipation characteristics of the module are further improved.
　また、前記金属膜がめっきにより形成されていてもよい。このように構成することにより金属膜をめっきにより形成することができる。 Further, the metal film may be formed by plating. With this configuration, the metal film can be formed by plating.
　また、前記一方主面に立設された柱状の接続端子をさらに備え、前記接続端子の先端面が、前記樹脂層の表面から露出していてもよい。このように構成することにより、樹脂層よりも熱伝導率が高い接続端子の先端面も樹脂層から露出するため、さらにモジュールの放熱特性が向上する。また、接続端子により、外部のマザー基板等とモジュールとの接続が可能になる。 Further, a columnar connection terminal erected on the one main surface may be further provided, and a front end surface of the connection terminal may be exposed from the surface of the resin layer. By comprising in this way, since the front end surface of the connection terminal whose heat conductivity is higher than the resin layer is also exposed from the resin layer, the heat dissipation characteristics of the module are further improved. In addition, the connection terminal enables connection between an external mother board and the module.
　また、本発明のモジュール搭載装置は、上記したモジュールと、前記モジュールの前記金属膜と接続されるマザー基板とを備えることを特徴としている。このように構成することにより、放熱特性が優れたモジュールを搭載したモジュール搭載基板を提供することができる。 The module mounting apparatus of the present invention is characterized by including the above-described module and a mother substrate connected to the metal film of the module. By comprising in this way, the module mounting board | substrate which mounts the module with the outstanding heat dissipation characteristic can be provided.
　また、例えば、配線基板の一方主面に半導体基板と接続端子が配置されるモジュール構成の場合、半導体基板の金属膜をマザー基板との接続に利用することにより、接続端子と半導体基板の金属膜の両方でモジュールとマザー基板との接続を行うことができるため、接続端子のみでマザー基板と接続する従来のモジュールと比較して、モジュールとマザー基板との接続強度が増大する。 Further, for example, in the case of a module configuration in which a semiconductor substrate and a connection terminal are arranged on one main surface of a wiring substrate, the metal film of the semiconductor substrate is used for connection to the mother substrate, whereby the connection terminal and the metal film of the semiconductor substrate are used. Therefore, the connection strength between the module and the mother board is increased as compared with the conventional module that is connected to the mother board only with the connection terminals.
　また、金属膜の表面に凹凸が形成されていると、モジュールとマザー基板とを接続する際の、モジュールのマザー基板との接続面積が増加するため、モジュールとマザー基板との接続強度が増大する。 In addition, if the surface of the metal film is uneven, the connection area between the module and the mother board increases when the module and the mother board are connected, so the connection strength between the module and the mother board increases. .
　また、前記モジュールの前記金属膜が、前記マザー基板に形成された接地用のグランド電極と接続されていてもよい。このように構成することにより、半導体基板の配線基板と対向しない側の非対向主面とマザー基板が対向するように、金属膜（モジュール）とマザー基板とを接続した場合に、半導体基板の当該非対向主面が樹脂により覆われた従来のモジュールと比較して、半導体基板とマザー基板のグランド電極との距離が近くなるため、グランド電極による半導体基板のシールド特性が向上する。さらに、半導体基板とグランド電極との距離が近くなると、モジュールから発生する熱がマザー基板のグランド電極を介して放熱し易くなるため、モジュールの放熱特性も向上する。 Further, the metal film of the module may be connected to a ground electrode for grounding formed on the mother substrate. With this configuration, when the metal film (module) and the mother substrate are connected such that the non-opposing main surface of the semiconductor substrate that does not face the wiring substrate faces the mother substrate, Compared to a conventional module in which the non-opposing main surface is covered with a resin, the distance between the semiconductor substrate and the ground electrode of the mother substrate is closer, so that the shielding characteristics of the semiconductor substrate by the ground electrode are improved. Further, when the distance between the semiconductor substrate and the ground electrode is reduced, heat generated from the module is easily radiated through the ground electrode of the mother substrate, so that the heat dissipation characteristics of the module are also improved.
　本発明によれば、配線基板の一方主面に実装された半導体基板の配線基板と対向しない側の非対向主面が露出するように半導体基板を被覆する樹脂層を形成し、露出した半導体基板の当該非対向主面の少なくとも一部に半導体基板よりも熱伝導率の高い金属膜を形成することにより、半導体基板の当該非対向主面が樹脂層から露出しているだけの従来のモジュールと比較して、モジュールの放熱特性の向上を図ることができる。 According to the present invention, the exposed semiconductor substrate is formed by forming the resin layer covering the semiconductor substrate so that the non-opposing main surface of the semiconductor substrate mounted on the one main surface of the wiring substrate is not opposed to the wiring substrate. A conventional module in which the non-opposing main surface of the semiconductor substrate is only exposed from the resin layer by forming a metal film having higher thermal conductivity than the semiconductor substrate on at least a part of the non-opposing main surface of In comparison, the heat dissipation characteristics of the module can be improved.
本発明の一実施形態にかかるモジュールが実装されたモジュール搭載装置の切断正面図である。It is a cutting | disconnection front view of the module mounting apparatus with which the module concerning one Embodiment of this invention was mounted. 図１のモジュールの製造方法の説明図である。It is explanatory drawing of the manufacturing method of the module of FIG. 図１のモジュールの製造方法の説明図である。It is explanatory drawing of the manufacturing method of the module of FIG. 従来のモジュールの断面図である。It is sectional drawing of the conventional module.
　（モジュール搭載装置の構成）
　本発明の一実施形態にかかるモジュール２が搭載されたモジュール搭載装置１について、図１を参照して説明する。なお、図１はモジュール２が搭載されたモジュール搭載装置１の切断正面図である。 (Configuration of module mounting device)
A module mounting apparatus 1 on which a module 2 according to an embodiment of the present invention is mounted will be described with reference to FIG. FIG. 1 is a cut front view of the module mounting apparatus 1 on which the module 2 is mounted.
　この実施形態にかかるモジュール２を搭載したモジュール搭載装置１は、図１に示すように、マザー基板３と、該マザー基板３に実装されたモジュール２と、マザー基板３とモジュール２との接続部を保護するための、樹脂により形成されたアンダーフィル樹脂層４とを備え、例えば、携帯電話等の高周波が用いられる電子機器に搭載される。 As shown in FIG. 1, a module mounting apparatus 1 on which a module 2 according to this embodiment is mounted includes a mother board 3, a module 2 mounted on the mother board 3, and a connecting portion between the mother board 3 and the module 2. And an underfill resin layer 4 made of a resin, for example, and mounted on an electronic device using a high frequency such as a mobile phone.
　マザー基板３は、内部に接地用のグランド電極５と各種回路を構成する配線パターン（図示せず）が形成され、グランド電極５および配線パターンはビア導体６等により所定の配線パターンやマザー基板３の表裏面に形成された実装用電極７等に接続される。この実施形態では、マザー基板３に形成されたグランド電極５は、後述するモジュール２の柱状の接続端子８および半導体基板９の配線基板と対向しない側の非対向主面９ａに形成された金属膜１０に接続される実装電極７にビア導体６を介して接続される。また、マザー基板３は、ガラスエポキシ樹脂、セラミック等の材料により形成される。なお、接続端子８は、必ずしもグランド電極５に接続されていなくてもよく、例えば、図１に示す２つの接続端子８のうち、片側のみをビア導体６を介してグランド電極５と接続する構成であってもよい。 The mother board 3 has a ground electrode 5 for grounding and wiring patterns (not shown) constituting various circuits, and the ground electrode 5 and the wiring pattern are formed in a predetermined wiring pattern or mother board 3 by a via conductor 6 or the like. Are connected to the mounting electrodes 7 formed on the front and back surfaces. In this embodiment, the ground electrode 5 formed on the mother substrate 3 is a metal film formed on the non-opposing main surface 9a on the side not facing the wiring substrate of the columnar connection terminals 8 and the semiconductor substrate 9 of the module 2 described later. 10 is connected to the mounting electrode 7 connected to 10 via the via conductor 6. The mother substrate 3 is formed of a material such as glass epoxy resin or ceramic. The connection terminal 8 does not necessarily have to be connected to the ground electrode 5. For example, only one side of the two connection terminals 8 shown in FIG. 1 is connected to the ground electrode 5 via the via conductor 6. It may be.
　また、アンダーフィル樹脂層４は、例えば、エポキシ樹脂からなり、マザー基板３上にモジュール２を実装した時のマザー基板３とモジュール２との間の隙間を埋めるように樹脂を充填して形成される。なお、アンダーフィル樹脂層４はなくてもかまわない。 The underfill resin layer 4 is made of, for example, an epoxy resin, and is formed by filling a resin so as to fill a gap between the mother substrate 3 and the module 2 when the module 2 is mounted on the mother substrate 3. The The underfill resin layer 4 may be omitted.
　（モジュール２の構成）
　次に、この実施形態にかかるモジュール２について図１を参照して説明する。 (Configuration of module 2)
Next, the module 2 according to this embodiment will be described with reference to FIG.
　モジュール２は、図１に示すように、配線基板１１と、該配線基板１１の一方主面１１ａに実装された半導体基板９および立設された柱状の接続端子８と、配線基板１１の他方主面１１ｂに実装されたチップ部品１２ａ，１２ｂ，１２ｃと、配線基板１１の一方主面１１ａの半導体基板９と接続端子８を被覆する樹脂層１３ａと、配線基板１１の他方主面１１ｂのチップ部品１２ａ～１２ｃを被覆する樹脂層１３ｂとを備えるモジュールであり、その例として、Ｂｌｕｅｔｏｏｔｈ（登録商標）モジュール、無線ＬＡＮモジュール、携帯電話のアンテナ直下に配置されるアンテナスイッチモジュールなどが挙げられる。 As shown in FIG. 1, the module 2 includes a wiring board 11, a semiconductor substrate 9 mounted on one main surface 11 a of the wiring board 11, a column-shaped connection terminal 8 erected, and the other main board 11 of the wiring board 11. Chip components 12a, 12b, and 12c mounted on the surface 11b, a resin layer 13a that covers the semiconductor substrate 9 and the connection terminals 8 on one main surface 11a of the wiring substrate 11, and a chip component on the other main surface 11b of the wiring substrate 11 And a resin layer 13b covering 12a to 12c. Examples of the module include a Bluetooth (registered trademark) module, a wireless LAN module, and an antenna switch module disposed immediately below an antenna of a mobile phone.
　配線基板１１は、ガラスエポキシ樹脂基板、低温同時焼成セラミック（ＬＴＣＣ）基板、ガラス基板などから形成され、その両主面１１ａ，１１ｂには、実装用電極１５、接続端子８形成用の電極１５ａ、配線パターン（図示せず）などが形成されるとともに、内部には接地用のグランド電極１４、他の配線パターン（図示せず）、ビア導体（図示せず）等が形成される。なお、配線基板１１は、単層基板および多層基板のいずれを使用してもかまわない。 The wiring substrate 11 is formed of a glass epoxy resin substrate, a low-temperature co-fired ceramic (LTCC) substrate, a glass substrate, and the like, and both main surfaces 11a and 11b have mounting electrodes 15 and electrodes 15a for forming connection terminals 8; A wiring pattern (not shown) and the like are formed, and a ground electrode 14 for grounding, another wiring pattern (not shown), a via conductor (not shown) and the like are formed inside. Note that the wiring board 11 may be either a single layer board or a multilayer board.
　例えば、配線基板１１がＬＴＣＣ多層基板である場合の製造方法は、アルミナおよびガラスなどの混合粉末が有機バインダおよび溶剤などと一緒に混合されたスラリーがシート化されたセラミックグリーンシートを形成し、このセラミックグリーンシートの所定位置に、レーザー加工などによりビアホールが形成され、形成されたビアホールにＡｇやＣｕなどを含む導体ペーストが充填されて、層間接続用のビア導体が形成され、導体ペーストによる印刷により種々の電極パターンが形成される。その後、各セラミックグリーンシートを積層、圧着することによりセラミック積層体を形成して、約１０００℃前後の低い温度で焼成する、所謂、低温焼成して製造される。 For example, when the wiring substrate 11 is an LTCC multilayer substrate, a ceramic green sheet in which a slurry in which a mixed powder such as alumina and glass is mixed with an organic binder and a solvent is formed into a sheet is formed. Via holes are formed at predetermined positions of the ceramic green sheet by laser processing, etc., and the formed via holes are filled with a conductor paste containing Ag, Cu, etc., and via conductors for interlayer connection are formed, and printing by the conductor paste is performed. Various electrode patterns are formed. Thereafter, the ceramic green sheets are laminated and pressed to form a ceramic laminate, which is fired at a low temperature of about 1000 ° C., so-called low temperature firing.
　また、配線基板１１の両主面１１ａ，１１ｂには、実装部品として、半導体基板９とチップ部品１２ａ～１２ｃが実装される。半導体基板９は、配線基板１１の一方主面１１ａに対向する表面に所定の電気回路が形成されることにより、例えば、ＲＦ信号やベースバンド信号を処理するシステムＩＣを構成し、配線基板１１の一方主面１１ａにフェイスダウン実装（フリップチップ実装）される。また、チップ部品１２ａ～１２ｃは、チップコンデンサ、チップインダクタ、チップ抵抗からなり、配線基板１１の他方主面１１ｂに周知の表面実装技術により実装される。また、配線基板１１の一方主面１１ａには、さらに柱状（ピン状）の接続端子８が実装される。なお、接続端子８は、例えばＣｕを主成分とし、電極１５ａに半田を介して実装される。 Further, the semiconductor substrate 9 and the chip components 12a to 12c are mounted on both the main surfaces 11a and 11b of the wiring substrate 11 as mounting components. The semiconductor substrate 9 forms a system IC that processes, for example, an RF signal and a baseband signal by forming a predetermined electric circuit on the surface of the wiring substrate 11 that faces the one main surface 11a. On the other hand, face down mounting (flip chip mounting) is performed on the main surface 11a. The chip components 12a to 12c are composed of a chip capacitor, a chip inductor, and a chip resistor, and are mounted on the other main surface 11b of the wiring board 11 by a known surface mounting technique. Further, a columnar (pin-shaped) connection terminal 8 is further mounted on one main surface 11 a of the wiring substrate 11. The connection terminal 8 is mainly composed of Cu, for example, and is mounted on the electrode 15a via solder.
　この場合、配線基板１１の一方主面１１ａには、フリップチップ実装された半導体基板９と接続端子８のみが配置され、配線基板１１の他方主面１１ｂには、半導体基板９を除く他の実装部品（チップ部品１２ａ～１２ｃ）が配置される。また、半導体基板９の非対向主面９ａと接続端子８の先端面８ａには、金属膜１０が形成される。この金属膜１０は、例えば、めっき処理により、半導体基板９の非対向主面９ａ（または、接続端子８の先端面８ａ）にＮｉ層が形成され、そのＮｉ層の上からＡｕ層が形成されたＮｉ／Ａｕ膜である。なお、接続端子８の先端面８ａに金属膜１０を形成しない構成であってもかまわない。 In this case, only the flip-chip mounted semiconductor substrate 9 and the connection terminal 8 are arranged on the one main surface 11a of the wiring substrate 11, and the other main surface 11b of the wiring substrate 11 is mounted on the other main surface 11b except for the semiconductor substrate 9. Components (chip components 12a to 12c) are arranged. A metal film 10 is formed on the non-facing main surface 9 a of the semiconductor substrate 9 and the tip surface 8 a of the connection terminal 8. In the metal film 10, for example, a Ni layer is formed on the non-facing main surface 9 a of the semiconductor substrate 9 (or the front end surface 8 a of the connection terminal 8) by plating, and an Au layer is formed on the Ni layer. Ni / Au film. Note that the metal film 10 may not be formed on the distal end surface 8a of the connection terminal 8.
　また、配線基板１１の他方主面１１ｂに実装されるチップ部品１２ａ～１２ｃの中には、それぞれが実装された状態で、配線基板１１の他方主面１１ｂからの高さが異なるものがあり、この実施形態では、図１に示すように、チップ部品１２ａが全チップ部品１２ａ～１２ｃの中で配線基板１１の他方主面１１ｂからの高さが最も低い。また、半導体基板９と接続端子８それぞれは、実装または立設された状態で、配線基板１１の一方主面１１ａからの高さが同じになるように形成されている。 Further, among the chip components 12a to 12c mounted on the other main surface 11b of the wiring board 11, there are some chip components 12a to 12c that are different in height from the other main surface 11b of the wiring board 11, In this embodiment, as shown in FIG. 1, the chip component 12a has the lowest height from the other main surface 11b of the wiring board 11 among all the chip components 12a to 12c. Further, each of the semiconductor substrate 9 and the connection terminal 8 is formed so that the height from the one main surface 11a of the wiring substrate 11 is the same in the mounted or standing state.
　さらに、配線基板１１の一方主面１１ａにおいて、配線基板１１の一方主面１１ａからの高さが最も高い半導体基板９（または、接続端子８）の高さＨｔが、配線基板１１の他方主面１１ｂのチップ部品１２ａ（他方主面１１ｂにおいて最も高さの低いチップ部品）の当該他方主面１１ｂからの高さＨ０よりも低くなるように半導体基板９（または、接続端子８）が形成されている。 Furthermore, the height Ht of the semiconductor substrate 9 (or connection terminal 8) having the highest height from the one main surface 11a of the wiring substrate 11 on the one main surface 11a of the wiring substrate 11 is the other main surface of the wiring substrate 11. 11b of the chip component 12a that other from the main surface 11b of the height H 0 semiconductor substrate to be lower than the (other main surface tallest low chip component in 11b) 9 (or the connection terminal 8) is formed ing.
　また、各実装部品９，１２ａ～１２ｃそれぞれを平面視した場合、半導体基板９は他の実装部品（各チップ部品１２ａ～１２ｃ）のいずれよりも面積（横断面積）が大きいものが使用されている。 Further, when each mounting component 9, 12a to 12c is viewed in plan, the semiconductor substrate 9 has a larger area (cross-sectional area) than any of the other mounting components (each chip component 12a to 12c). .
　配線基板１１の一方主面１１ａの樹脂層１３ａは、例えば、エポキシ樹脂からなり、図１に示すように、半導体基板９の非対向主面および接続端子８の先端面８ａそれぞれが露出するように、半導体基板９および接続端子８を被覆して形成される。このとき、モジュール２の配線基板１１の一方主面側は、樹脂層１３ａの表面、半導体基板９の非対向主面９ａ、接続端子８の先端面８ａが同一面を成す、いわゆる面一状態に形成されている。なお、この面一状態は、後述する研磨・研削工程により形成することができる。 The resin layer 13a on the one main surface 11a of the wiring board 11 is made of, for example, an epoxy resin so that the non-facing main surface of the semiconductor substrate 9 and the front end surface 8a of the connection terminal 8 are exposed as shown in FIG. The semiconductor substrate 9 and the connection terminals 8 are covered. At this time, one main surface side of the wiring substrate 11 of the module 2 is in a so-called flush state in which the surface of the resin layer 13a, the non-opposing main surface 9a of the semiconductor substrate 9, and the tip surface 8a of the connection terminal 8 form the same surface. Is formed. This flush state can be formed by a polishing / grinding process described later.
　配線基板１１の他方主面１１ｂの樹脂層１３ｂは、例えば、一方主面１１ａの樹脂層１３ａと同種のエポキシ樹脂からなり、図１に示すように、各チップ部品１２ａ～１２ｃが露出しないように各チップ部品の全てを被覆した状態で形成される。 The resin layer 13b on the other main surface 11b of the wiring board 11 is made of, for example, the same kind of epoxy resin as the resin layer 13a on the one main surface 11a, so that the chip components 12a to 12c are not exposed as shown in FIG. It is formed in a state where all of the chip parts are covered.
　なお、樹脂層１３ａ側の厚み対して樹脂層１３ｂ側の厚みが十分厚い場合など、モジュール２の反りが大きい場合には、その反りを抑制するため、樹脂層１３ｂを形成する樹脂は、樹脂層１３ａを形成する樹脂よりも、線膨張係数が小さいものを使用することが好ましい。 In addition, when the warp of the module 2 is large, such as when the thickness of the resin layer 13b side is sufficiently thick with respect to the thickness of the resin layer 13a side, in order to suppress the warp, the resin forming the resin layer 13b is a resin layer. It is preferable to use a resin having a smaller linear expansion coefficient than the resin forming 13a.
　（モジュール２の製造方法）
　次に、この実施形態にかかるモジュール２の製造方法について、図２および図３を参照して説明する。なお、図２はモジュール２を製造する各工程の一部を示し、図３は図２に続く各工程を示す。 (Manufacturing method of module 2)
Next, a method for manufacturing the module 2 according to this embodiment will be described with reference to FIGS. 2 shows a part of each process of manufacturing the module 2, and FIG. 3 shows each process following FIG.
　まず、図２（ａ）に示すように、その内部に面状の接地用グランド電極１４と配線パターンが形成されるとともに、その両主面１１ａ，１１ｂに半導体基板９と各チップ部品１２ａ～１２ｃの実装用電極１５および接続端子形成用の電極１５ａが形成された配線基板１１を準備する（配線基板準備工程）。 First, as shown in FIG. 2 (a), a planar grounding ground electrode 14 and a wiring pattern are formed therein, and the semiconductor substrate 9 and the chip components 12a to 12c are formed on both main surfaces 11a and 11b. The wiring board 11 on which the mounting electrode 15 and the connection terminal forming electrode 15a are formed is prepared (wiring board preparation step).
　次に、図２（ｂ）に示すように、配線基板１１の実装用電極１５それぞれに対応する位置に半導体基板９、接続端子８および各チップ部品１２ａ～１２ｃを実装する（部品、接続端子実装工程）。このとき、半導体部品９を配線基板１１の一方主面１１ａにフェイスダウン実装（フリップチップ実装）し、各チップ部品１２ａ～１２ｃを、配線基板１１の他方主面１１ｂに周知の表面実装技術により実装する。また、配線基板１１の接続端子形成用の電極１５に半田を介して、ピン状の接続端子８を実装する。接続端子８としては、例えばＣｕや、Ｃｕを主成分とする合金からなる柱状の金属を用いることができる。 Next, as shown in FIG. 2B, the semiconductor substrate 9, the connection terminal 8, and the chip components 12a to 12c are mounted at positions corresponding to the mounting electrodes 15 of the wiring substrate 11 (component, connection terminal mounting). Process). At this time, the semiconductor component 9 is face-down mounted (flip chip mounting) on the one main surface 11a of the wiring substrate 11, and the chip components 12a to 12c are mounted on the other main surface 11b of the wiring substrate 11 by a known surface mounting technique. To do. Further, the pin-like connection terminals 8 are mounted on the electrodes 15 for forming the connection terminals of the wiring board 11 via solder. As the connection terminal 8, for example, a columnar metal made of Cu or an alloy containing Cu as a main component can be used.
　次に、図２（ｃ）に示すように、配線基板１１の一方主面１１ａにおいて、半導体基板９および接続端子８を被覆する樹脂層１３ａを形成するとともに、他方主面１１ｂにおいて、各チップ部品１２ａ～１２ｃを被覆する樹脂層１３ｂを形成する（樹脂層形成工程）。このとき、ディスペンス方式または印刷方式などを用いて両主面１１ａ，１１ｂ上に樹脂を塗布または印刷し、所定の硬化温度（例えば、エポキシ樹脂であれば１８０℃程度）に設定されたオーブンに投入するなどして樹脂を硬化させて両樹脂層１３ａ，１３ｂを形成する。そして、配線基板１１の両主面１１ａ，１１ｂに配置された各実装部品（９，１２ａ～１２ｃ）および接続端子８を樹脂により被覆してなるモジュール素体１８を形成する。 Next, as shown in FIG. 2C, a resin layer 13a covering the semiconductor substrate 9 and the connection terminals 8 is formed on one main surface 11a of the wiring board 11, and each chip component is formed on the other main surface 11b. A resin layer 13b covering 12a to 12c is formed (resin layer forming step). At this time, a resin is applied or printed on both the main surfaces 11a and 11b by using a dispensing method or a printing method, and put into an oven set at a predetermined curing temperature (for example, about 180 ° C. for an epoxy resin). For example, the resin is cured to form both resin layers 13a and 13b. Then, a module body 18 is formed by covering the mounting components (9, 12a to 12c) and the connection terminals 8 arranged on both main surfaces 11a and 11b of the wiring board 11 with resin.
　なお、接続端子８の形成方法は上記した方法のほか、配線基板１１の一方主面１１ａに半導体基板９を実装する前に、めっき処理により柱状の接続端子８を形成してもよい。この場合、接続端子８の形成後に半導体基板９を実装し、一方主面１１ａ上に実装された半導体基板９とともに、接続端子８を樹脂により被覆して樹脂層１３ａを形成するとよい。 In addition to the method described above, the columnar connection terminals 8 may be formed by plating before the semiconductor substrate 9 is mounted on the one main surface 11a of the wiring board 11 in addition to the method described above. In this case, the semiconductor substrate 9 is mounted after the connection terminal 8 is formed, and the resin layer 13a is formed by covering the connection terminal 8 with resin together with the semiconductor substrate 9 mounted on the one main surface 11a.
　また、半導体基板９を実装後、接続端子８を形成する前に樹脂層１３ａを形成し、樹脂層１３ａの表面に対してレーザーを照射するなどにより接続端子形成用電極１５ａの表面が露出するように接続端子形成用の凹部を形成し、印刷技術を用いて当該凹部に導電ペースト（例えば、ＡｇペーストやＣｕペースト）を充填したり、めっき処理などにより導体（例えば、Ｃｕ）を形成したりして、配線基板１１の一方主面１１ａに柱状の接続端子８を形成してもよい。 In addition, after mounting the semiconductor substrate 9, the resin layer 13 a is formed before the connection terminals 8 are formed, and the surface of the connection terminal forming electrode 15 a is exposed by irradiating the surface of the resin layer 13 a with a laser. Forming a connection terminal forming recess and filling the recess with a conductive paste (for example, Ag paste or Cu paste) using a printing technique, or forming a conductor (for example, Cu) by plating or the like. Thus, the columnar connection terminals 8 may be formed on the one main surface 11 a of the wiring board 11.
　接続端子８をめっき処理で形成する場合は、上記したピン状の接続端子８を実装する場合と異なり、接続端子８を研磨または研削しても配線基板１１と接続端子８との接合部の半田が、接続端子８の側面を濡れ上がって樹脂層１３ａから半田が露出することがない。したがって、配線基板１１の一方主面１１ａ上に微細な径の接続端子８を高精度に形成することができ、接続端子８の狭ピッチ化が可能になる。 When the connection terminal 8 is formed by plating, unlike the case where the pin-shaped connection terminal 8 is mounted, the solder at the joint between the wiring substrate 11 and the connection terminal 8 even if the connection terminal 8 is polished or ground. However, the side surface of the connection terminal 8 does not wet and the solder is not exposed from the resin layer 13a. Therefore, the connection terminals 8 having a fine diameter can be formed with high precision on the one main surface 11a of the wiring board 11, and the pitch of the connection terminals 8 can be reduced.
　次に、図３（ａ）に示すように、樹脂層１３ａの表面から半導体基板９の非対向主面９ａと接続端子８の先端面８ａが露出するように、モジュール素体１８の樹脂層１３ａの表面を研磨または研削する（研磨・研削工程）。例えば、樹脂層１３ａの表面を研磨する場合、その研磨は、カップ砥石を使用したグラインド、遊離砥粒を使用したラップ研磨、サンドブラスト等により行うことができる。 Next, as shown in FIG. 3A, the resin layer 13a of the module body 18 is exposed so that the non-facing main surface 9a of the semiconductor substrate 9 and the front end surface 8a of the connection terminal 8 are exposed from the surface of the resin layer 13a. Polishing or grinding the surface (polishing and grinding process). For example, when the surface of the resin layer 13a is polished, the polishing can be performed by grinding using a cup grindstone, lapping using a free abrasive, sand blasting, or the like.
　このとき、モジュール素体１８の配線基板１１の一方主面側において、樹脂層１３ａの表面、半導体基板９の非対向主面９ａ、接続端子８の先端面８ａが同一面を成す、いわゆる面一状態になるように、樹脂層１３ａの樹脂とともに、半導体基板９および接続端子８を研磨または研削する。 At this time, on the one main surface side of the wiring substrate 11 of the module body 18, the surface of the resin layer 13 a, the non-opposing main surface 9 a of the semiconductor substrate 9, and the front end surface 8 a of the connection terminal 8 form the same plane. The semiconductor substrate 9 and the connection terminal 8 are polished or ground together with the resin of the resin layer 13a so as to be in a state.
　また、配線基板１１の一方主面１１ａからの高さが最も高い半導体基板９（または接続端子８）の高さＨｔが、配線基板１１の他方主面１１ｂからの高さが最も低いチップ部品１１ａの高さＨ０よりも低くなるように半導体基板９（または接続端子８）を研磨または研削する。 Further, the chip component 11a having the lowest height Ht of the semiconductor substrate 9 (or the connection terminal 8) from the one main surface 11a of the wiring substrate 11 is the lowest from the other main surface 11b of the wiring substrate 11. polishing or grinding a semiconductor substrate 9 (or the connection terminal 8) to be lower than the height H 0 of the.
　なお、半導体基板９の非対向主面９ａに凹凸ができるように研磨または研削するのが好ましい。半導体基板９の非対向主面９ａに凹凸を形成すると、その主面９ａに金属膜１０を形成したときに、当該金属膜１０にも凹凸を形成することが可能になり、熱伝導率の高い金属膜１０の表面積を増加することができる。また、配線基板１１の一方主面１１ａ側の平坦度が要求されるモジュール２においては、半導体基板９の非対向主面９ａの凹凸を埋めるように金属膜１０を厚く形成することにより、金属膜１０の表面を平坦にすることができる。 In addition, it is preferable to polish or grind so that the non-opposing main surface 9a of the semiconductor substrate 9 may be uneven. When unevenness is formed on the non-opposing main surface 9a of the semiconductor substrate 9, when the metal film 10 is formed on the main surface 9a, the metal film 10 can also be formed with unevenness, and has high thermal conductivity. The surface area of the metal film 10 can be increased. Further, in the module 2 in which the flatness on the one main surface 11a side of the wiring substrate 11 is required, the metal film 10 is formed thick so as to fill the unevenness of the non-opposing main surface 9a of the semiconductor substrate 9. 10 surfaces can be flattened.
　ところで、半導体基板９の非対向主面９ａの平均粗さ（Ｒａ）の値が小さすぎると半導体基板９の非対向主面９ａにめっき処理により金属膜１０を形成することが困難になり、平均粗さ（Ｒａ）の値が大きすぎると半導体基板９が破損するおそれがあるため、半導体基板９の非対向主面９ａの表面の平均粗さ（Ｒａ）は、０．１μｍ～１５μｍの範囲に形成することが好ましい。 By the way, if the value of the average roughness (Ra) of the non-opposing main surface 9a of the semiconductor substrate 9 is too small, it becomes difficult to form the metal film 10 on the non-opposing main surface 9a of the semiconductor substrate 9 by plating. If the value of the roughness (Ra) is too large, the semiconductor substrate 9 may be damaged. Therefore, the average roughness (Ra) of the surface of the non-opposing main surface 9a of the semiconductor substrate 9 is in the range of 0.1 μm to 15 μm. It is preferable to form.
　次に、図３（ｂ）に示すように、樹脂層１３ａの表面から露出した半導体基板９の非対向主面９ａおよび接続端子８の先端面８ａに金属膜１０を形成して（金属膜形成工程）、モジュール２を製造する。このとき、金属膜１０は、めっき処理や印刷技術などを用いて形成する。例えば、めっき処理の場合は、半導体基板９の非対向主面９ａおよび接続端子８の先端面８ａにＮｉ層を成長させ、その上からＡｕ層を成長させて金属膜１０を形成する。なお、半導体基板９の非対向主面９ａの金属膜１０は、半導体基板９の当該非対向主面９ａの全面に形成する必要はなく、少なくとも一部に形成すればよい。 Next, as shown in FIG. 3B, a metal film 10 is formed on the non-opposing main surface 9a of the semiconductor substrate 9 and the front end surface 8a of the connection terminal 8 exposed from the surface of the resin layer 13a (metal film formation). Step), module 2 is manufactured. At this time, the metal film 10 is formed using a plating process or a printing technique. For example, in the case of a plating process, a Ni layer is grown on the non-opposing main surface 9a of the semiconductor substrate 9 and the front end surface 8a of the connection terminal 8, and an Au layer is grown thereon to form the metal film 10. The metal film 10 on the non-opposing main surface 9a of the semiconductor substrate 9 does not need to be formed on the entire surface of the non-facing main surface 9a of the semiconductor substrate 9, and may be formed at least partially.
　なお、モジュール搭載装置１を製造する場合は、上記したモジュール２の製造方法により製造したモジュール２の配線基板１１の一方主面１１ａ（半導体基板９の非対向主面９ａ）がマザー基板３と対向するようにして、半導体基板９の非対向主面９ａおよび接続端子８の先端面８ａに形成された金属膜１０とマザー基板３の表面に形成された実装電極７とを半田などを介して接続することにより製造する。 When the module mounting apparatus 1 is manufactured, the one main surface 11a (the non-opposing main surface 9a of the semiconductor substrate 9) of the wiring board 11 of the module 2 manufactured by the method for manufacturing the module 2 is opposed to the mother substrate 3. In this way, the metal film 10 formed on the non-opposing main surface 9a of the semiconductor substrate 9 and the front end surface 8a of the connection terminal 8 and the mounting electrode 7 formed on the surface of the mother substrate 3 are connected via solder or the like. It is manufactured by doing.
　したがって、上記した実施形態によれば、半導体基板９の配線基板１１と対向しない側の非対向主面が露出するように配線基板１１の一方主面１１ａに樹脂層１３ａが形成され、樹脂層１３ａから露出した半導体基板９の非対向主面９ａに半導体基板９よりも熱伝導率が高い金属膜１０が形成されるため、樹脂層１３ａの表面から半導体基板９の非対向主面９ａが露出しているだけの従来のモジュールと比較して、モジュール２の放熱特性が向上する。 Therefore, according to the above-described embodiment, the resin layer 13a is formed on the one main surface 11a of the wiring substrate 11 so that the non-opposing main surface of the semiconductor substrate 9 on the side not facing the wiring substrate 11 is exposed, and the resin layer 13a. Since the metal film 10 having higher thermal conductivity than the semiconductor substrate 9 is formed on the non-opposing main surface 9a of the semiconductor substrate 9 exposed from above, the non-facing main surface 9a of the semiconductor substrate 9 is exposed from the surface of the resin layer 13a. Compared with a conventional module that is merely provided, the heat dissipation characteristics of the module 2 are improved.
　また、半導体基板９の非対向主面９ａに凹凸が形成されるように、半導体基板９の非対向主面９ａを研磨または研削する場合は、当該非対向主面に形成される金属膜１０の表面にも凹凸を形成することができるため、樹脂層１３ａの表面から露出する金属膜１０の表面積が増加し、これにより、さらにモジュール２の放熱特性が向上する。 Further, when the non-opposing main surface 9a of the semiconductor substrate 9 is polished or ground so that irregularities are formed on the non-opposing main surface 9a of the semiconductor substrate 9, the metal film 10 formed on the non-facing main surface Since unevenness can also be formed on the surface, the surface area of the metal film 10 exposed from the surface of the resin layer 13a increases, and thereby the heat dissipation characteristics of the module 2 are further improved.
　また、半導体基板９の非対向主面９ａに、延性を有する金属膜１０を形成することにより、樹脂層１３ａから露出した半導体基板９の非対向主面９ａが保護されるため、半導体基板９が外部からの衝撃等により破損するのを抑制することができる。 Further, by forming the ductile metal film 10 on the non-opposing main surface 9a of the semiconductor substrate 9, the non-opposing main surface 9a of the semiconductor substrate 9 exposed from the resin layer 13a is protected, so that the semiconductor substrate 9 is It is possible to suppress damage due to external impact or the like.
　また、金属膜１０がＮｉ／Ａｕ膜で形成されているため、モジュール２とマザー基板３とを半田により接続する際の半田の濡れ性が向上する。 In addition, since the metal film 10 is formed of a Ni / Au film, the wettability of solder when the module 2 and the mother board 3 are connected by solder is improved.
　また、半導体基板９が実装された配線基板１１の一方主面１１ａに、樹脂層１３ａの樹脂よりも熱伝導率が高い接続端子８が立設され、該接続端子８の先端面８ａも樹脂層１３ａの表面から露出しているため、さらにモジュール２の放熱特性が向上する。また、接続端子８により、マザー基板３とモジュール２との接続が可能になる。 Further, a connection terminal 8 having a higher thermal conductivity than the resin of the resin layer 13a is erected on the one main surface 11a of the wiring substrate 11 on which the semiconductor substrate 9 is mounted, and the front end surface 8a of the connection terminal 8 is also a resin layer. Since it is exposed from the surface of 13a, the heat dissipation characteristic of the module 2 is further improved. Further, the connection terminal 8 allows the mother board 3 and the module 2 to be connected.
　また、樹脂層１３ａの表面を研磨または研削することにより、マザー基板３のグランド電極５に接続される接続端子８の長さ（配線基板１１の一方主面１１ａからの高さ）を短くできるため、接続端子８に起因する寄生インダクタンスが低減し、これによりグランドの強化を図ることができる。 Further, by polishing or grinding the surface of the resin layer 13a, the length of the connection terminal 8 connected to the ground electrode 5 of the mother board 3 (height from the one main surface 11a of the wiring board 11) can be shortened. The parasitic inductance due to the connection terminal 8 is reduced, and the ground can be strengthened.
　ところで、この実施形態では、配線基板１１の一方主面１１ａには、フリップチップ実装された半導体基板９と接続端子８のみが配置されるとともに、他方主面１１ｂにはチップコンデンサなどのチップ部品１２ａ～１２ｃが配置される。 By the way, in this embodiment, only the flip-chip mounted semiconductor substrate 9 and connection terminal 8 are arranged on one main surface 11a of the wiring board 11, and the chip component 12a such as a chip capacitor is arranged on the other main surface 11b. To 12c are arranged.
　モジュール２を小型化（配線基板１１の実装面積を小さくする）するためには、配線基板１１の両主面１１ａ，１１ｂに実装部品を配置することが効果的である。また、図４に示した従来技術と同様に、半導体基板９の非対向主面９ａを接続端子８とともに研磨等することにより低背化し、モジュール２の小型化を図ることも有効である。しかしながら、例えば、配線基板１１の同一主面上に半導体基板９と各チップ部品１２ａ～１２ｃを実装する構成にすると、半導体基板９の非対向主面９ａを研磨等してモジュール２の低背化を図ることは困難である。なぜなら、チップコンデンサやチップインダクタである各チップ部品１２ａ～１２ｃを研磨等により削ると特性が劣化するおそれがあるためである。そのため、このような構成にすると、半導体基板９の当該同一主面からの高さを、同一主面上に実装された各チップ部品１２ａ～１２ｃの高さよりも低くすることができない。 In order to reduce the size of the module 2 (to reduce the mounting area of the wiring board 11), it is effective to dispose mounting components on both main surfaces 11a and 11b of the wiring board 11. As in the prior art shown in FIG. 4, it is also effective to reduce the height of the module 2 by reducing the height by polishing the non-opposing main surface 9 a of the semiconductor substrate 9 together with the connection terminals 8. However, for example, when the semiconductor substrate 9 and the chip components 12a to 12c are mounted on the same main surface of the wiring substrate 11, the module 2 is reduced in height by polishing the non-opposing main surface 9a of the semiconductor substrate 9. It is difficult to plan. This is because if the chip components 12a to 12c, which are chip capacitors and chip inductors, are shaved by polishing or the like, the characteristics may be deteriorated. Therefore, with such a configuration, the height of the semiconductor substrate 9 from the same main surface cannot be made lower than the height of each of the chip components 12a to 12c mounted on the same main surface.
　そこで、この実施形態では、上記したように配線基板１１の一方主面１１ａにはその非対向主面９ａを研磨しても特性が劣化しないフリップチップ実装された半導体基板９と接続端子８のみを配置するとともに、他方主面１１ｂにチップコンデンサやチップインダクタ等の各チップ部品１２ａ～１２ｂを配置して、配線基板１１の一方主面１１ａの樹脂層１３ａの表面を半導体基板９および接続端子８とともに研磨または研削することによりモジュール２の低背化を図ることができるモジュール構成とした。 Thus, in this embodiment, as described above, only the flip-chip mounted semiconductor substrate 9 and the connection terminals 8 that do not deteriorate in characteristics even when the non-opposing main surface 9a is polished on the one main surface 11a of the wiring substrate 11 are provided. In addition, the chip components 12 a to 12 b such as chip capacitors and chip inductors are arranged on the other main surface 11 b, and the surface of the resin layer 13 a on the one main surface 11 a of the wiring substrate 11 together with the semiconductor substrate 9 and the connection terminals 8. The module configuration is such that the module 2 can be reduced in height by polishing or grinding.
　また、配線基板１１の一方主面１１ａからの高さが最も高い半導体基板９（または接続端子８）の高さＨｔが、配線基板１１の他方主面１１ｂからの高さが最も低いチップ部品１２ａの高さＨ０よりも低くなるように半導体基板９（または接続端子８）が研磨または研削されるため、確実にモジュール２の低背化を図ることができる。 Further, the height Ht of the semiconductor substrate 9 (or connection terminal 8) having the highest height from the one main surface 11a of the wiring substrate 11 is the chip component 12a having the lowest height from the other main surface 11b of the wiring substrate 11. for the height H 0 semiconductor substrate 9 to be lower than (or connecting terminals 8) is polished or ground, it is possible to reduce the height of reliably module 2.
　また、樹脂層１３ａの表面から半導体基板９の非対向主面９ａが露出するように樹脂層１３ａを研磨または研削することで、半導体基板９の非対向主面９ａが樹脂層１３ａに被覆された従来のモジュールと比較して、モジュール２をマザー基板３に搭載した場合（図１参照）の、半導体基板９の非対向主面９ａとマザー基板３のグランド電極５との距離が近くなるため、モジュール２から発生した熱をグランド電極５を介して放熱し易くなり、モジュール２の放熱特性が向上する。また、半導体基板９の金属膜１０が、マザー基板３のグランド電極５と接続された実装用電極７と半田を介して接続されているため、モジュール２から発生した熱をより効果的に放熱することができる。 Further, the resin layer 13a is coated with the non-facing main surface 9a of the semiconductor substrate 9 by polishing or grinding the resin layer 13a so that the non-facing main surface 9a of the semiconductor substrate 9 is exposed from the surface of the resin layer 13a. Compared to the conventional module, when the module 2 is mounted on the mother substrate 3 (see FIG. 1), the distance between the non-opposing main surface 9a of the semiconductor substrate 9 and the ground electrode 5 of the mother substrate 3 is reduced. Heat generated from the module 2 can be easily dissipated through the ground electrode 5, and the heat dissipation characteristics of the module 2 are improved. Further, since the metal film 10 of the semiconductor substrate 9 is connected to the mounting electrode 7 connected to the ground electrode 5 of the mother substrate 3 via solder, the heat generated from the module 2 is more effectively dissipated. be able to.
　また、半導体基板９の非対向主面９ａとマザー基板３のグランド電極５との距離が近くなることにより、半導体基板９の回路面（半導体基板９の配線基板１１との対向面）とグランド電極５との距離が近くなるため、半導体基板９の回路面から輻射する不要なノイズの影響を効果的に抑制することができるとともに、外部から半導体基板９に対して照射される不要なノイズを抑制することができる。 Further, since the distance between the non-opposing main surface 9a of the semiconductor substrate 9 and the ground electrode 5 of the mother substrate 3 is reduced, the circuit surface of the semiconductor substrate 9 (the surface of the semiconductor substrate 9 facing the wiring substrate 11) and the ground electrode. Since the distance to the semiconductor substrate 9 is reduced, the influence of unnecessary noise radiated from the circuit surface of the semiconductor substrate 9 can be effectively suppressed, and unnecessary noise irradiated to the semiconductor substrate 9 from the outside is suppressed. can do.
　また、半導体基板９の非対向主面９ａに形成された金属膜１０をモジュール２とマザー基板３との接続に利用することで、接続端子８の先端面８ａおよび半導体基板９の非対向面９ａそれぞれに形成された金属膜１０でマザー基板３とモジュール２との接続が可能になるため、モジュール２の接続端子８のみでマザー基板３と接続する従来のモジュール搭載装置と比較して、モジュール２とマザー基板３との接続強度が向上する。 Further, by using the metal film 10 formed on the non-opposing main surface 9 a of the semiconductor substrate 9 for connection between the module 2 and the mother substrate 3, the tip surface 8 a of the connection terminal 8 and the non-facing surface 9 a of the semiconductor substrate 9 are used. Since the mother substrate 3 and the module 2 can be connected by the metal film 10 formed on each of them, the module 2 is compared with the conventional module mounting apparatus that connects to the mother substrate 3 only by the connection terminal 8 of the module 2. The connection strength between the mother board 3 and the mother board 3 is improved.
　また、半導体基板９の金属膜１０の表面に凹凸が形成される場合には、半導体基板９の金属膜１０とマザー基板３との接続面積が増大するため、モジュール２とマザー基板３との接続強度がさらに向上する。 Further, in the case where irregularities are formed on the surface of the metal film 10 of the semiconductor substrate 9, the connection area between the metal film 10 of the semiconductor substrate 9 and the mother substrate 3 increases, so that the connection between the module 2 and the mother substrate 3 is increased. Strength is further improved.
　また、配線基板１１の一方主面１１ａの樹脂層１３ａを研磨すると、樹脂層１３ａを形成する樹脂の量が他方主面１１ｂの樹脂層１３ｂの樹脂の量よりも少なくなるため、両樹脂層１３ａ，１３ｂそれぞれで生じる収縮応力のバランスが崩れ、配線基板１１が反るおそれがあるが、両樹脂層１３ａ，１３ｂを形成する樹脂よりも硬い半導体基板９には、配線基板１１の両主面１１ａ，１１ｂに実装される各実装部品９，１２ａ～１２ｃのうち、平面視での面積（横断面積）が最も大きいものが使用されるため、上記した両樹脂層１３ａ，１３ｂの収縮応力のバランスが崩れることにより生じる配線基板１１の反りを抑制することができる。 In addition, when the resin layer 13a on the one main surface 11a of the wiring board 11 is polished, the amount of resin forming the resin layer 13a is smaller than the amount of resin in the resin layer 13b on the other main surface 11b. , 13b may cause the balance of shrinkage stress to be lost, and the wiring substrate 11 may be warped. However, the semiconductor substrate 9 that is harder than the resin that forms the resin layers 13a, 13b has both main surfaces 11a of the wiring substrate 11. , 11b, the one having the largest area (cross-sectional area) in plan view is used among the mounting parts 9, 12a to 12c mounted on each of the resin layers 13a, 11b. Warping of the wiring board 11 caused by collapse can be suppressed.
　また、樹脂層１３ｂを形成する樹脂は樹脂層１３ａを形成する樹脂よりも線膨張係数が小さいものが使用されるため、さらに配線基板１１の反りを抑制することができる。 Further, since the resin forming the resin layer 13b has a smaller linear expansion coefficient than that of the resin forming the resin layer 13a, warping of the wiring board 11 can be further suppressed.
　なお、本発明は上記した各実施形態に限定されるものではなく、その趣旨を逸脱しない限りにおいて、上記したもの以外に種々の変更を行なうことが可能である。 The present invention is not limited to the above-described embodiments, and various modifications other than those described above can be made without departing from the spirit of the invention.
　例えば、上記した各実施形態において、配線基板１１の一方主面１１ａにフリップチップ実装される半導体基板９は複数個あっても構わない。 For example, in each of the above-described embodiments, there may be a plurality of semiconductor substrates 9 flip-chip mounted on the one main surface 11a of the wiring substrate 11.
　また、半導体基板９の平面視での面積は、他の実装部品のいずれかの面積よりも小さいものであってもよい。なお、実装後の高さが、研磨または研削後の半導体基板９の高さより低くなる実装部品であれば、配線基板１１の一方主面１１ａに配置してもよい。すなわち、配線基板１１の一方主面１１ａに、その主面９ａを研磨または研削可能な半導体基板９を実装または配置する構成であればよく、その他は、配線基板１１の実装面積を小さくするために、適宜、各実装部品の配置を工夫すればよい。 Also, the area of the semiconductor substrate 9 in plan view may be smaller than the area of any of the other mounted components. In addition, if it is a mounting component in which the height after mounting is lower than the height of the semiconductor substrate 9 after polishing or grinding, it may be disposed on the one main surface 11a of the wiring substrate 11. That is, any configuration is possible as long as the semiconductor substrate 9 capable of polishing or grinding the main surface 9a is mounted on or arranged on the one main surface 11a of the wiring substrate 11, and the other is to reduce the mounting area of the wiring substrate 11. The arrangement of each mounted component can be appropriately devised.
　また、配線基板１１の他方主面１１ｂにはチップコンデンサやチップインダクタなどのチップ部品１２ａ～１２ｃのみを実装したが、他方主面１１ｂには一方主面１１ａに実装される半導体基板９と同じ、または異なる他の半導体基板９を実装してもよい。 Further, only the chip components 12a to 12c such as chip capacitors and chip inductors are mounted on the other main surface 11b of the wiring board 11, but the other main surface 11b is the same as the semiconductor substrate 9 mounted on the one main surface 11a. Alternatively, another different semiconductor substrate 9 may be mounted.
　また、金属膜１０は、例えば、導電性ペーストを用いて形成されてもよいし、スパッタリングや蒸着により形成されてもよい。 Further, the metal film 10 may be formed using, for example, a conductive paste, or may be formed by sputtering or vapor deposition.
　また、配線基板１１の一方主面１１ａに形成される接続端子８の個数はいくつでもよく、配線基板１１の他方主面１１ｂにも接続端子８を配置してもよい。また、接続端子８は、必ずしも配線基板１１の一方主面１１ａに配置する必要はない。すなわち、接続端子８と半導体基板９とは配線基板１１の異なる主面に配置してもよい。なお、接続端子と半導体基板９とが配線基板１１の異なる主面に配置されている場合には、金属膜は半導体基板９の非対向主面９ａにのみ形成するだけでなく、樹脂層１３ｂの周囲にも形成することにより、モジュール２のシールド層として機能させることができる。 Further, the number of connection terminals 8 formed on one main surface 11 a of the wiring board 11 may be any number, and the connection terminals 8 may be arranged on the other main surface 11 b of the wiring board 11. Further, the connection terminals 8 are not necessarily arranged on the one main surface 11 a of the wiring board 11. That is, the connection terminal 8 and the semiconductor substrate 9 may be disposed on different main surfaces of the wiring substrate 11. When the connection terminal and the semiconductor substrate 9 are arranged on different main surfaces of the wiring substrate 11, the metal film is not only formed on the non-opposing main surface 9a of the semiconductor substrate 9, but also the resin layer 13b. By forming also around, it can function as a shield layer of the module 2.
　また、上記した各実施形態において、配線基板１１の他方主面１１ｂに各チップ部品１２ａ～１２ｃを実装しない構成であってもかまわない。 Further, in each of the above-described embodiments, a configuration in which the chip components 12a to 12c are not mounted on the other main surface 11b of the wiring board 11 may be employed.
　また、各樹脂層１３ａ，１３ｂは、必ずしも配線基板１１の両主面１１ａ，１１ｂに、設けられていなくともよい。 Further, the resin layers 13a and 13b are not necessarily provided on both main surfaces 11a and 11b of the wiring board 11.
　また、上記した実施形態では、半導体基板９の非対向主面９ａ、接続端子８の先端面８ａ、樹脂層１３ａの表面が同一面を成す、いわゆる面一状態になるように各面を形成したが、樹脂層１３ａの表面の高さを半導体基板９（非対向主面９ａ）および接続端子８（先端面８ａ）の高さよりも低く形成してもよい。すなわち、樹脂層１３ａの表面から半導体基板９の端部および接続端子８の端部が突出するように樹脂層１３ａを形成してもかまわない。このように樹脂層１３ａを形成することにより、樹脂層１３ａの樹脂よりも熱伝導率が高い半導体基板９および接続端子８それぞれの端部が樹脂層１３ａの表面から露出するため、さらにモジュール２の放熱特性が向上する。 In the above-described embodiment, each surface is formed so that the non-opposing main surface 9a of the semiconductor substrate 9, the front end surface 8a of the connection terminal 8, and the surface of the resin layer 13a are the same surface, so-called flush. However, the height of the surface of the resin layer 13a may be formed lower than the height of the semiconductor substrate 9 (non-opposing main surface 9a) and the connection terminal 8 (tip surface 8a). That is, the resin layer 13a may be formed so that the end of the semiconductor substrate 9 and the end of the connection terminal 8 protrude from the surface of the resin layer 13a. By forming the resin layer 13a in this manner, the end portions of the semiconductor substrate 9 and the connection terminal 8 having higher thermal conductivity than the resin of the resin layer 13a are exposed from the surface of the resin layer 13a. Improved heat dissipation characteristics.
　本発明は、配線基板の一方主面に半導体基板がフリップチップ実装された構成であれば、どのようなモジュールに対しても適用することができる。 The present invention can be applied to any module as long as the semiconductor substrate is flip-chip mounted on one main surface of the wiring board.
　１　モジュール搭載装置
　２　モジュール
　３　マザー基板
　５　グランド電極
　８　接続端子
　９　半導体基板
　１０　金属膜
　１１　配線基板
　１３ａ，１３ｂ　樹脂層 DESCRIPTION OF SYMBOLS 1 Module mounting apparatus 2 Module 3 Mother board 5 Ground electrode 8 Connection terminal 9 Semiconductor substrate 10 Metal film 11 Wiring board 13a, 13b Resin layer

Claims (6)

  1. 　配線基板と、
    　前記配線基板の一方主面に実装された半導体基板と、
    　前記半導体基板の前記配線基板と対向しない側の非対向主面が露出するように前記半導体基板を被覆する前記一方主面に形成された樹脂層とを備え、
    　前記半導体基板の前記非対向主面の少なくとも一部に金属膜が形成されている
    ことを特徴とするモジュール。     A wiring board;
    A semiconductor substrate mounted on one main surface of the wiring board;
    A resin layer formed on the one main surface that covers the semiconductor substrate so that the non-opposing main surface of the semiconductor substrate that does not face the wiring substrate is exposed;
    A module, wherein a metal film is formed on at least a part of the non-opposing main surface of the semiconductor substrate.
  2. 　前記金属膜の表面に凹凸が形成されていることを特徴とする請求項１に記載のモジュール。 The module according to claim 1, wherein irregularities are formed on the surface of the metal film.
  3. 　前記金属膜がめっきにより形成されていることを特徴とする請求項１または２に記載のモジュール。 The module according to claim 1 or 2, wherein the metal film is formed by plating.
  4. 　前記一方主面に立設された柱状の接続端子をさらに備え、
    　前記接続端子の先端面が、前記樹脂層の表面から露出していることを特徴とする請求項１ないし３のいずれかに記載のモジュール。     It further comprises a columnar connection terminal erected on the one main surface,
    4. The module according to claim 1, wherein a front end surface of the connection terminal is exposed from a surface of the resin layer. 5.
  5. 　請求項１ないし４のいずれかに記載のモジュールと、
    　前記モジュールの前記金属膜と接続されるマザー基板と
    　を備えることを特徴とするモジュール搭載装置。     A module according to any one of claims 1 to 4,
    A module mounting device comprising: a mother substrate connected to the metal film of the module.
  6. 　前記モジュールの前記金属膜が、前記マザー基板に形成された接地用のグランド電極と接続されていることを特徴とする請求項５に記載のモジュール搭載装置。 6. The module mounting apparatus according to claim 5, wherein the metal film of the module is connected to a ground electrode for grounding formed on the mother substrate.
PCT/JP2013/064618 2012-07-26 2013-05-27 Module, and device having module mounted thereon WO2014017160A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012165610 2012-07-26
JP2012-165610 2012-07-26

Publications (1)

Publication Number Publication Date
WO2014017160A1 true WO2014017160A1 (en) 2014-01-30

Family

ID=49996978

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/064618 WO2014017160A1 (en) 2012-07-26 2013-05-27 Module, and device having module mounted thereon

Country Status (2)

Country Link
TW (1) TWI521655B (en)
WO (1) WO2014017160A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019181761A1 (en) * 2018-03-20 2019-09-26 株式会社村田製作所 High frequency module
US11107782B2 (en) 2018-12-20 2021-08-31 Murata Manufacturing Co., Ltd. Radio frequency module and communication device
US11201633B2 (en) 2017-03-14 2021-12-14 Murata Manufacturing Co., Ltd. Radio frequency module
US12040755B2 (en) 2017-03-15 2024-07-16 Murata Manufacturing Co., Ltd. High-frequency module and communication device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003007931A (en) * 2001-06-20 2003-01-10 Sony Corp Semiconductor device and manufacturing method therefor
JP2005203633A (en) * 2004-01-16 2005-07-28 Matsushita Electric Ind Co Ltd Semiconductor device, semiconductor device mount and method for manufacturing the semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003007931A (en) * 2001-06-20 2003-01-10 Sony Corp Semiconductor device and manufacturing method therefor
JP2005203633A (en) * 2004-01-16 2005-07-28 Matsushita Electric Ind Co Ltd Semiconductor device, semiconductor device mount and method for manufacturing the semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11201633B2 (en) 2017-03-14 2021-12-14 Murata Manufacturing Co., Ltd. Radio frequency module
US12040755B2 (en) 2017-03-15 2024-07-16 Murata Manufacturing Co., Ltd. High-frequency module and communication device
WO2019181761A1 (en) * 2018-03-20 2019-09-26 株式会社村田製作所 High frequency module
JPWO2019181761A1 (en) * 2018-03-20 2021-01-07 株式会社村田製作所 High frequency module
US11270922B2 (en) 2018-03-20 2022-03-08 Murata Manufacturing Co., Ltd. Radio-frequency module
US11107782B2 (en) 2018-12-20 2021-08-31 Murata Manufacturing Co., Ltd. Radio frequency module and communication device

Also Published As

Publication number Publication date
TW201409630A (en) 2014-03-01
TWI521655B (en) 2016-02-11

Similar Documents

Publication Publication Date Title
US9293446B2 (en) Low profile semiconductor module with metal film support
JP6282589B2 (en) Module and manufacturing method thereof
JP5195903B2 (en) Electronic component module and method for manufacturing the electronic component module
US9226400B2 (en) Multilayer ceramic electronic device and method for manufacturing the same
JP4453702B2 (en) COMPOSITE ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF
US10362677B2 (en) Capacitor built-in multilayer wiring substrate and manufacturing method thereof
US9591747B2 (en) Module board
KR101740816B1 (en) Chip inductor
JP4986507B2 (en) Circuit module
JP2009266979A (en) Semiconductor device
US20120049368A1 (en) Semiconductor package
WO2014017160A1 (en) Module, and device having module mounted thereon
JP4821424B2 (en) Ceramic multilayer substrate and manufacturing method thereof
JP5066830B2 (en) Ceramic multilayer substrate
JP2007294829A (en) High-frequency circuit module, and method of manufacturing the same
US9961764B2 (en) Circuit module
JP2013110299A (en) Composite module
JP2013197564A (en) Composite module and manufacturing method of the same
WO2023021888A1 (en) Electronic component module
WO2023021887A1 (en) Electronic component module
WO2013099360A1 (en) Module and component equipped with module
TW201352128A (en) Electromagnetic interference shielding material, electromagnetic interference shielding device, electromagnetic interference shielding device manufacturing method, package modules and electronic products capable of shielding electromagnetic interference

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13822684

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13822684

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP