WO2013164887A1 - 信号同期システム、マルチプロセッサ、及びノード同期システム - Google Patents

信号同期システム、マルチプロセッサ、及びノード同期システム Download PDF

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Publication number
WO2013164887A1
WO2013164887A1 PCT/JP2012/061580 JP2012061580W WO2013164887A1 WO 2013164887 A1 WO2013164887 A1 WO 2013164887A1 JP 2012061580 W JP2012061580 W JP 2012061580W WO 2013164887 A1 WO2013164887 A1 WO 2013164887A1
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Prior art keywords
reference signal
value
synchronization
unit
node
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PCT/JP2012/061580
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English (en)
French (fr)
Japanese (ja)
Inventor
崇 光井
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富士電機株式会社
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Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to CN201280070128.4A priority Critical patent/CN104115450B/zh
Priority to PCT/JP2012/061580 priority patent/WO2013164887A1/ja
Priority to KR1020147022963A priority patent/KR101578751B1/ko
Priority to JP2014513325A priority patent/JP5850143B2/ja
Publication of WO2013164887A1 publication Critical patent/WO2013164887A1/ja
Priority to IN7649DEN2014 priority patent/IN2014DN07649A/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers

Definitions

  • the present invention relates to a signal synchronization system, a multiprocessor, and a node synchronization system for synchronizing predetermined signals.
  • a multiprocessor that executes processing using a plurality of processors for the purpose of dealing with large-scale processing, speeding up processing, load distribution, etc.
  • the system is known.
  • a multiprocessor in order to synchronize counters (timers) among a plurality of processors, an interrupt signal or the like that matches the main processor is generated from the main processor to the counter of the slave processor to synchronize the counter. .
  • each device has a virtual shared memory (common memory) and transmits its own node data to all nodes (stations) on the network at the update timing.
  • each received node updates its data and accesses an application, thereby realizing a data exchange method that guarantees real-time performance.
  • a method for realizing efficient broadcast communication (broadcast communication) on a network at the time of data exchange described above has been proposed (see, for example, Patent Document 1).
  • the time division multiple access method using the internal timer of each node and the internal timer correction of the slave node using the synchronization frame from the master node are used together.
  • the transmission path is configured as a network connected by a bus or a serial cable.
  • this counter is a counter that serves as an execution reference for a plurality of program processes that are internally performed. Therefore, if the counter is rewritten without permission, problems occur in other processes. Further, when the counter is built in a CPU (Central Processing Unit) of the slave processor, the counter of the slave processor cannot be reset directly from the master processor. Therefore, conventionally, an interrupt signal is once transmitted from the main processor to the slave processor, and the slave processor receives the signal and executes a counter reset process indirectly (in software) using predetermined software. .
  • CPU Central Processing Unit
  • the slave processor generates a delay time due to overhead or the like after receiving the interrupt signal from the main processor until executing the reset processing of its own counter corresponding to the signal. Therefore, conventionally, even if the reset process is performed, a counter synchronization error between the main processor and the slave processor remains.
  • a method of receiving a synchronization frame and clearing a timer can be considered.
  • an error occurs in the counter due to a delay time such as overhead.
  • the present invention has been devised in view of the above points, and an object thereof is to provide a signal synchronization system, a multiprocessor, and a node synchronization system for synchronizing a predetermined signal with high accuracy.
  • the present invention provides a first reference signal generation unit configured to generate a first reference signal when a reference value is set and a count value reaches the reference value in a signal synchronization system, A reference value is set, and when the count value reaches the reference value, a second reference signal generation unit that generates a second reference signal and the first reference signal generated by the first reference signal generation unit are received. And an arithmetic unit that executes predetermined processing.
  • the signal synchronization system is restarted upon receiving the first reference signal, and an overhead measuring unit that measures overhead until the predetermined processing is executed from the restart time point, and the passage of the overhead
  • a synchronization determination unit that determines that the first reference signal and the second reference signal are asynchronous.
  • the synchronization value is obtained by subtracting the count value acquired by the count value acquisition unit from the overhead value.
  • a signal synchronization system comprising: a synchronization correction unit that obtains a correction value and sets a value obtained by subtracting the obtained synchronization correction value from the reference value as a temporary reference value in the second reference signal generation unit.
  • a predetermined signal can be synchronized with high accuracy.
  • time chart figure (the 1) for demonstrating the counter synchronous example in 2nd Embodiment. It is a time chart figure (the 2) for explaining an example of counter synchronization in a 2nd embodiment. It is a time chart figure (the 3) for explaining an example of counter synchronization in a 2nd embodiment. It is a figure for demonstrating an example of the notification procedure of the transmission delay time in 2nd Embodiment. It is a figure which shows an example of schematic structure of the network transmission system containing the node synchronous system using the master node and slave node in 2nd Embodiment. It is a figure which shows the example of a schematic sequence of a node synchronous process.
  • ⁇ About the present invention for example, when counter (timer) synchronization is performed between devices in a master-slave relationship, an overhead value on the slave device side is obtained for an interrupt signal (counter reset signal) from the master device side. Further, according to the present invention, synchronous / asynchronous determination is performed based on the obtained overhead value and the counter on the slave device side, and if it is asynchronous, synchronous correction processing is performed.
  • a synchronous / asynchronous determination is performed in consideration of a delay time on a communication path (transmission delay time). Perform synchronization correction processing.
  • FIG. 1 is a diagram illustrating an example of a schematic configuration of a signal synchronization system according to the first embodiment.
  • the signal synchronization system 10 shown in FIG. 1 shows an example of a multiprocessor for performing counter synchronization between a plurality of processors (in the example of FIG. 1, the processors 11-1 to 11-3). Yes.
  • the signal synchronization system 10 shown in FIG. 1 includes a plurality of processors 11-1 to 11-3 (hereinafter referred to as “processor 11” as necessary), a transmission bus 12, and an I / O (input / output) module 13-. 1 to 13-4 (hereinafter referred to as “I / O module 13” if necessary), external devices 14-1 to 14-4 (hereinafter referred to as “external device 14” if necessary), and a programming device 15.
  • the processor 11-1 is a main (main) processor
  • the processors 11-2 and 11-3 are sub (sub) processors, and the main configuration as each processor.
  • the number of slave processors is not limited to this.
  • the present invention is not limited to this, and has the same configuration so that one processor can be both a main processor and a slave processor.
  • Each processor 11 is connected by a transmission bus 12. In the first embodiment, it is assumed that there is no delay time caused by the transmission bus 12.
  • the main processor 11-1 includes a first arithmetic unit (CPU) 21 and a storage unit 22.
  • the first reference signal generation unit 21-1 is incorporated in the first calculation unit 21, but the present invention is not limited to this.
  • the first calculation unit 21 and the first reference signal The generation unit 21-1 may be configured as a separate block.
  • the above-described built-in means that only the first calculation unit 21 can access the built-in first reference signal generation unit 21-1.
  • the slave processors 11-2 and 11-3 each include a second calculation unit (CPU) 31, a synchronization correction processing unit 32, and a storage unit 33.
  • the second reference signal generation unit 31-1 is built in the second calculation unit 31.
  • the present invention is not limited to this.
  • the second calculation unit 31 and the second reference signal The generation unit 31-1 may be configured as a separate block.
  • the synchronization correction processing unit 32 includes an overhead measurement unit 32-1, a count value acquisition unit 32-2, a synchronization determination unit 32-3, a synchronization correction unit 32-4, and a storage unit 33.
  • the first reference signal generator 21-1 generates the first reference signal when the count value reaches a preset reference value.
  • the first reference signal generation unit 21-1 includes a counter (hereinafter also referred to as “timer” as necessary).
  • the above-described count value is cyclically counted based on the reference value.
  • the first calculation unit 21 executes (calculates) a predetermined application program stored in the storage unit 22 in synchronization with the first reference signal generated by the first reference signal generation unit 21-1.
  • the first reference signal is also given (transmitted) to the slave processors 11-2 and 11-3 via the transmission bus 12.
  • the storage unit 22 stores a predetermined application program (sequence program) that is calculated by the first calculation unit 21.
  • the predetermined application program calculated by the first calculation unit 21 gives an instruction to, for example, the I / O module 13-1 connected to the main processor 11-1, and the I / O module 13-1 causes the external device 14- 1 is a process for controlling 1. Therefore, the storage unit 22 stores a program for executing predetermined processing mainly on the I / O module 13-1 and the external device 14-1 connected to the own processor.
  • the main processor 11-1 outputs a first reference signal at predetermined intervals, and the first calculation unit 21 executes (calculates) an application program (sequence program) to control a predetermined device, and The application program (sequence program) is executed cyclically.
  • slave processors 11-2 and 11-3 will be described. Since the slave processors 11-2 and 11-3 have the same configuration, the following description will be made using the slave processor 11-2.
  • the second reference signal generation unit 31-1 is set with the same reference value as the reference value set in the first reference signal generation unit 21-1, and the second reference signal generation unit 31-1 reaches the reference value by the count value reaching the second reference signal. Generate a signal.
  • the second reference signal generator 31-1 has a counter. The above-described count value is cyclically counted based on the reference value.
  • the counters of the first reference signal generation unit 21-1 and the second reference signal generation unit 31-1 are free running counters and are self-running.
  • the second calculation unit 31 executes (calculates) a predetermined application program or the like stored in the storage unit 33 in synchronization with the second reference signal generated by the second reference signal generation unit 31-1.
  • the second reference signal generation unit 31-1 is a counter that can be accessed only from the second calculation unit 31, for example, and is a counter (CPU built-in counter) built in the second calculation unit 31. That is, the second reference signal generation unit 31-1 is a counter that cannot be reset by hardware from outside the main processor 11-1.
  • the second arithmetic unit (CPU) 31 receives the first reference signal (synchronization reference signal) from the main processor 11-1 as an interrupt signal, and starts a synchronization correction process (predetermined process) described later.
  • the overhead measurement unit 32-1 measures an overhead value until the synchronization correction processing is executed, starting from the reception of the first reference signal described above.
  • the overhead measuring unit 32-1 includes a counter (timer) that receives and restarts the first reference signal, and a process of reading the value of this counter at the start of the synchronization correction process.
  • the overhead means a delay time from the occurrence of an event until the processing (software) for the event is actually executed.
  • the overhead measurement unit 32-1 is restarted.
  • the time from the start to the start of the predetermined process is not limited to this.
  • the count value acquisition unit 32-2 acquires the count value of the second reference signal generation unit 31-1 when the predetermined process is actually executed. That is, the count value acquisition unit 32-2 reads the count value of the second reference signal generation unit 31-1 at the start of the synchronization correction process.
  • the synchronization determination unit 32-3 when the count value acquired by the count value acquisition unit 32-2 is equal to the count value of the overhead value counted by the overhead measurement unit 32-1, It is determined that the signal is synchronized. In addition, the synchronization determination unit 32-3, when the count value acquired by the count value acquisition unit 32-2 is different from the count value of the overhead value described above, the first reference signal and the second reference signal described above are Judged to be asynchronous.
  • the synchronization determination unit 32-3 converts the count value acquired by the count value acquisition unit 32-2 and the count value of the overhead value measured by the overhead measurement unit 32-1, and when both times are equal. It can be determined that they are synchronized, and it can also be determined that they are asynchronous when their time is different. That is, in the first embodiment, there may be cases where the unit time per clock of each counter is not equal between the processors. Therefore, in such a case, each counter value is converted into time, and synchronous / asynchronous determination is performed at the converted time.
  • the synchronization correction unit 32-4 sets the reference value in the second reference signal generation unit 31-1.
  • the synchronization correction unit 32-4 calculates an overhead value from the count value acquired by the count value acquisition unit 32-2. Subtract the synchronization correction value.
  • the synchronization correction unit 32-4 subtracts the obtained synchronization correction value from the reference value, and sets the subtracted value as a new reference value in the second reference signal generation unit.
  • the new reference value is used when the synchronization determination unit 32-3 determines asynchronous with respect to the timer reference value (default reference value) used when the synchronization determination unit 32-3 determines synchronization. It is a timer reference value that is treated temporarily.
  • the synchronization correction unit 32-4 uses the default reference value described above for the second reference signal generation unit 31 each time the synchronization determination unit 32-3 determines the synchronization between the first reference signal and the second reference signal. Although it may be set to -1, if the synchronization is maintained, once the default reference value is set, nothing is required.
  • the storage unit 33 stores a predetermined application program (sequence program) that is calculated by the second calculation unit 31.
  • the predetermined application program calculated by the second calculation unit 31 gives instructions to the I / O modules 13-2 and 13-3 connected to the slave processor 12-2, for example, and the I / O modules 13-2 and 13-3.
  • 13-3 is a process for controlling the external devices 14-2 and 14-2 by 13-3. Therefore, a program for executing predetermined processing on the I / O modules 13-2 and 13-3 and the external devices 14-2 and 14-3 mainly connected to the own processor is stored in the storage unit 33. Is memorized.
  • the I / O module 13 performs input / output processing with the external device 14 and the like.
  • the I / O module 13 outputs (transmits) data or the like obtained from the connected external device 14 or the like to the processor 11, outputs the result of arithmetic processing by the processor 11 to the external device 14 or the like, Or remember. That is, the processor 11 controls the external device 14 by calculating the input data obtained from the I / O module 13 using an application program and giving the calculation result to the I / O module 13 as output data.
  • the external device 14 is, for example, various sensors, motors, recording media, or the like.
  • the external device 14 detects and drives data, inputs / outputs data, and the like based on a control signal from the I / O module 13.
  • the reference value may be set in advance for each of the processor 11-1, the processor 11-2, and the processor 11-3, and may also be set from the programming device 15 (setting device) externally connected thereto. Can do.
  • the programming device 15 can be realized by communicating with the processor 11 in a PC (Personal Computer) used by a user or the like and adding a function for setting a reference value, but is not limited to this, and a dedicated setting device It may be. Thereby, a reference value (processing cycle) can be arbitrarily adjusted for each user.
  • the signal synchronization system 10 includes a first reference signal generation unit 21-1, a second reference signal generation unit 31-1, The second calculation unit 31, the overhead measurement unit 32-1, the count value acquisition unit 32-2, the synchronization determination unit 32-3, and the synchronization correction unit 32-4 may be included.
  • the application example of the signal synchronization system 10 is not limited to a multiprocessor.
  • the main device side is a transmitting station that transmits a digital signal of date / time information by an atomic clock
  • the slave device side is a radio wave clock.
  • Application as a timer synchronization system is also possible.
  • FIG. 2 is a diagram illustrating an example of a hardware configuration of the processor.
  • the processor 11 shown in FIG. 2 includes an input unit 41, an output unit 42, a CPU 43, a memory 44, and an external interface 45, which are connected by a common bus B.
  • the input unit 41 inputs various operation signals such as execution of a program from a user or the like.
  • the input unit 41 may have a pointing device such as a keyboard or a mouse operated by a user or the like, and may have a voice input device when inputting by voice or the like.
  • the output unit 42 has a display for displaying various windows, data, and the like necessary for operating the processor that performs processing in the present embodiment, and displays the execution progress and results of the control program executed by the CPU 43.
  • the CPU 43 controls the entire processing of the processor 11 such as various operations and input / output of data with each hardware component based on a control program such as OS (Operating System) and an execution program stored in the memory 44. By doing so, each processing in the present embodiment is realized. Various information necessary during the program execution may be acquired from the memory 44 and the execution result or the like may be stored.
  • OS Operating System
  • the memory 44 stores an execution program read by the CPU 43 and the like.
  • the memory 44 includes a ROM (Read Only Memory), a RAM (Random Access Memory), and the like. Further, the memory 44 may have storage means such as a hard disk as an auxiliary storage device.
  • the memory 44 stores an execution program according to the present invention, a control program provided in the computer, and the like, and performs input / output as necessary. Note that the memory 44 corresponds to the storage units 22 and 33 described above.
  • the external interface 45 transmits and receives data and control signals to and from other processors via the transmission bus 12 and the like.
  • the external interface 45 also transmits / receives data and control signals to / from the connected I / O module 13.
  • the counter synchronization process according to the present invention can be executed by the hardware configuration described above. Also, by installing the execution program, the counter synchronization processing in the present embodiment can be easily realized by a general-purpose personal computer or the like.
  • ⁇ Counter synchronization example in the first embodiment> 3 to 5 are time charts (part 1 to part 3) for explaining an example of counter synchronization in the first embodiment.
  • the examples shown in FIGS. 3 to 5 show examples of counter value synchronization between the main side (main apparatus side) CPU (processor) and the sub side (subordinate apparatus side) CPU (processor).
  • the reference value (processing cycle) in the first embodiment is 1000 ⁇ s.
  • the present invention is not limited to this, and the setting can be changed as appropriate by the programming device 15 described above, for example.
  • the first reference signal output from the main processor 11-1 is described as the main synchronization reference, and the first reference signal generator 21-1 is described as the main CPU1 counter. Further, in the examples of FIGS. 3 to 5, the second reference signal generation unit 31-1 is described as the sub CPU2 counter 1, and the counter included in the overhead measurement unit 32-1 is described as the counter 2.
  • the main CPU1 counter of the main processor 11-1 outputs the first reference signal because the counter value has reached the reference value.
  • the slave processor 11-2 receives the first reference signal as an interrupt, and starts the synchronization correction process ((2) in FIG. 3).
  • the overhead measuring unit 32-1 of the slave processor 11-2 clears the counter value of the counter (counter 2) and restarts ((3) in FIG. 3).
  • the overhead measuring unit 32-1 refers to the value of the counter (counter 2) at the time (4) in FIG. 3, that is, at the start of the synchronization correction process, and sends the value to the synchronization determining unit 32-3.
  • the synchronization determination unit 32-3 converts the counter value given by the overhead measurement unit 32-1 into time, and obtains 200 ⁇ s. In this way, the first embodiment measures the overhead from when the interrupt starts until the synchronization correction process is executed.
  • the count value acquisition unit 32-2 refers to the counter value of the sub CPU 2 counter 1 and gives the value to the synchronization determination unit 32-3.
  • the synchronization determination unit 32-3 converts the counter value given by the count value acquisition unit 32-2 into time to obtain 200 ⁇ s.
  • the synchronization determination unit 32-3 compares the counter value (200 ⁇ s) obtained from the count value acquisition unit 32-2 with the overhead value (200 ⁇ s) described above. In this case, the synchronization determination unit 32-3 determines that the first reference signal and the second reference signal are synchronized because they are the same value.
  • the synchronization correction unit 32-4 sets the reference value 1000 ⁇ s in the sub CPU2 counter 1 (at this time, the sub CPU2 counter 1 has restarted). Absent). The sub CPU 2 counter 1 is restarted because the counter value has reached the reference value 1000 ⁇ s at the point (6) in FIG.
  • the sub CPU 2 counter 1 can be restarted at substantially the same timing as the output timing of the first reference signal in the next cycle with respect to the current cycle.
  • the counter value of the counter and the counter value of the sub CPU 2 counter 1 can be adjusted to substantially the same value.
  • the sub CPU 2 counter 1 is built in the CPU described above. However, in the present embodiment, the sub CPU 2 counter 1 is not limited to this and may be outside the CPU.
  • the program of the count value acquisition unit 32-2, the synchronization determination unit 32-3, the synchronization correction unit 32-4, and the overhead measurement unit 32-1 is included. Processing is included.
  • FIG. 4 shows a case where the counter of the slave processor 11-2 is delayed by 200 ⁇ s from the counter of the main processor 11-1.
  • the main CPU 1 counter of the main processor 11-1 outputs the first reference signal because the counter value has reached the reference value.
  • the slave processor 11-2 receives the first reference signal as an interrupt, and starts the synchronization correction process ((2) in FIG. 4).
  • the overhead measuring unit 32-1 of the slave processor 11-2 clears the counter value of the counter (counter 2) and restarts ((3) in FIG. 4).
  • the overhead measuring unit 32-1 refers to the value of the counter (counter 2) at the time (4) in FIG. 4, that is, at the start of the synchronization correction process, and sends the value to the synchronization determining unit 32-3.
  • the synchronization determination unit 32-3 converts the counter value given by the overhead measurement unit 32-1 into time, and obtains 200 ⁇ s.
  • the count value acquisition unit 32-2 refers to the counter value of the sub CPU 2 counter 1 and gives the value to the synchronization determination unit 32-3.
  • the synchronization determination unit 32-3 converts the counter value given by the count value acquisition unit 32-2 into time to obtain 0 ⁇ s.
  • the synchronization determination unit 32-3 compares the counter value (0 ⁇ s) obtained from the count value acquisition unit 32-2 with the overhead value (200 ⁇ s) described above. In this case, the synchronization determination unit 32-3 determines that the first reference signal and the second reference signal are asynchronous because they are different values.
  • the synchronization correction unit 32-4 sets a temporary reference value in the sub CPU2 counter 1. Specifically, the synchronization correction unit 32-4 sets the restart value (reset value) of “counter 1” using the formula “reference value (processing cycle) ⁇ (“ counter 2 ” ⁇ “ counter 1 ”)”. And the obtained counter value is set to “counter 1” as a temporary reference value.
  • the sub CPU 2 counter 1 is restarted because the counter value has reached the temporary reference value of 800 ⁇ s at the point (6) in FIG. Incidentally, the value of “Counter 2” ⁇ “Counter 1” is the synchronization correction value.
  • the output timing of the first reference signal in the next cycle is substantially the same as the current cycle (first cycle).
  • the sub CPU2 counter 1 can be restarted. Therefore, the first embodiment can synchronize the first reference signal and the second reference signal.
  • the synchronization correction unit 32-4 since the first reference signal and the second reference signal are synchronized in the second cycle, the synchronization correction unit 32-4 performs the processing as shown in FIG.
  • the original reference value 1000 ⁇ s is set in the sub CPU2 counter 1 (at this time, the sub CPU2 counter 1 has not been restarted). Then, the sub CPU 2 counter 1 is restarted when the counter value reaches the reference value 1000 ⁇ s.
  • FIG. 5 shows a case where the counter of the slave processor 11-2 is advanced by 200 ⁇ s from the counter of the main processor 11-1.
  • the main CPU 1 counter of the main processor 11-1 outputs the first reference signal because the counter value has reached the reference value.
  • the slave processor 11-2 receives the first reference signal as an interrupt, and starts the synchronization correction process ((2) in FIG. 5).
  • the overhead measuring unit 32-1 of the slave processor 11-2 clears the counter value of the counter (counter 2) and restarts ((3) in FIG. 5).
  • the overhead measuring unit 32-1 refers to the value of the counter (counter 2) at the time (4) in FIG. 5, that is, at the start of the synchronization correction process, and sends the value to the synchronization determining unit 32-3.
  • the synchronization determination unit 32-3 converts the counter value given by the overhead measurement unit 32-1 into time, and obtains 200 ⁇ s.
  • the count value acquisition unit 32-2 refers to the counter value of the sub CPU 2 counter 1 and gives the value to the synchronization determination unit 32-3.
  • the synchronization determination unit 32-3 converts the counter value given by the count value acquisition unit 32-2 into time, and obtains 400 ⁇ s.
  • the synchronization determination unit 32-3 compares the counter value (400 ⁇ s) obtained from the count value acquisition unit 32-2 with the overhead value (200 ⁇ s) described above. In this case, the synchronization determination unit 32-3 determines that the first reference signal and the second reference signal are asynchronous because the counter values are different from each other.
  • the synchronization correction unit 32-4 sets a temporary reference value in the sub CPU2 counter 1. Specifically, the synchronization correction unit 32-4 calculates in the same manner as described with reference to FIG. 4 to obtain a temporary reference value and sets it to “counter 1”.
  • the sub CPU 2 counter 1 is restarted because the counter value has reached the temporary reference value 1200 ⁇ s at the point (6) in FIG. Incidentally, the value of “Counter 2” ⁇ “Counter 1” is the synchronization correction value.
  • 1st Embodiment is sub-side at the substantially same timing as the output timing of the 1st reference signal of the following cycle (2nd cycle: middle cycle) with respect to the present cycle (1st cycle).
  • the CPU 2 counter 1 can be restarted. Therefore, the present invention can synchronize the first reference signal and the second reference signal.
  • the description of the second cycle in FIG. 5 is the same as that in FIG.
  • counter synchronization can be appropriately realized regardless of whether the counter (timer) of the slave processor is delayed or advanced with respect to the counter (timer) of the main processor. Note that the synchronization correction process described above may be performed in intermittent cycles or continuously in each cycle.
  • FIG. 6 is a diagram illustrating a schematic sequence example of counter synchronization processing.
  • synchronization using the main processor 11-1 and the slave processor 11-2 will be described.
  • the present invention is not limited to this, and one main processor is not limited to this. Can be synchronized with a plurality of slave processors.
  • the main processor 11-1 generates a first reference signal (S01), and the slave processor 11-2 generates a second reference signal (S02). This process is cyclically operated in terms of hardware.
  • the main processor 11-1 transmits the first reference signal obtained in the process of S01 (S03).
  • the first reference signal instructed to be transmitted is transmitted to the slave processor 11-1 via the transmission bus (S04).
  • the slave processor 11-2 When the slave processor 11-2 receives the first reference signal (S05), it measures the overhead (S06), performs the synchronization determination as described above (S07), and performs synchronization correction when it is asynchronous (S08). ).
  • FIG. 7 is a diagram illustrating an example of a schematic configuration of the node synchronization system according to the second embodiment.
  • the node synchronization system 50 shown in FIG. 7 is an example in which counter synchronization is performed between a plurality of nodes such as nodes 51-1 to 51-3.
  • the node synchronization system 50 includes a plurality of nodes 51-1 to 51-3 (hereinafter referred to as “node 51” as necessary), a communication network (communication path) 52, an I / O (input / output) module 53, And an external device 54 and a programming device 55. That is, the node synchronization system 50 includes a master node 51-1 including a first calculation unit (CPU) 61, a slave node 51-2, 51 including a second calculation unit (CPU) 71, and a synchronization correction processing unit 72. -3 is connected via a communication network 52 as a communication path.
  • the node 51-1 is a master node and the nodes 51-2 and 51-3 are slave nodes, and the configuration unique to each node will be described.
  • the present invention is not limited to this. Both the configurations are combined so that each node can be a master node or a slave node.
  • the master node 51-1 corresponds to the processor 11-1 in the first embodiment
  • the slave nodes 51-2 and 51-3 correspond to the processors 11-2 and 11-3 in the first embodiment.
  • the programming device 55 is the same as the programming device 15 in the first embodiment
  • the I / O modules 53-1 to 53-4 are the same as the I / O modules 13-1 to 13-1 in the first embodiment.
  • the external devices 54-1 to 54-4 are the same as the external devices 14-2 to 14-4 in the first embodiment. Therefore, in the following description, the description of the same configuration as in the first embodiment is omitted.
  • the master node 51-1 includes a first calculation unit 61 (corresponding to the first calculation unit 21 of the first embodiment), a storage unit 62 (corresponding to the storage unit 22 of the first embodiment), and a synchronization frame notification unit. 63 and a transmission delay time notification unit 64.
  • the first calculation unit 61 includes a first reference signal generation unit 61-1 (corresponding to the first reference signal generation unit 21-1 of the first embodiment).
  • the main difference between the master node 51-1 and the processor 11-1 in the first embodiment is that a synchronization frame notification unit 63 and a transmission delay time notification unit 64 are added. Therefore, in the following description, the main part of the second embodiment will be described, and the same movement as in the first embodiment will be omitted.
  • the transmission delay time notifying unit 64 of the master node 51-1 transmits a transmission delay time request frame in order to calculate the transmission delay time.
  • This frame is substantially the same as a synchronization frame to be described later, and data of a predetermined portion (for example, command portion) in the synchronization frame is changed and transmitted. That is, the transmission delay time request frame is transmitted in synchronization with the first reference signal generated by the first reference signal generation unit 61.
  • the transmission delay time notification unit 64 receives the reception completion frame from the slave node that responds to the transmission delay time request frame. Then, the transmission delay time notification unit 64 calculates the round trip transmission delay time between the master node and the slave node from the difference between the time when the response frame is received and the time when the transmission delay time request frame is transmitted. The transmission delay time notification unit 64 transmits a transmission delay time notification frame including the calculated round-trip transmission delay time to the slave node in synchronization with the next first reference signal, so that the delay through the communication path 52 is transmitted to the slave node. Notify time.
  • the master node 51-1 After notifying the round-trip transmission delay time, the master node 51-1 sends a prepared synchronization frame to the slave node via the communication path 52 based on the first reference signal (in synchronization with the first reference signal). Send to. This process is executed by the synchronization frame notification unit 63.
  • the synchronization frame is a synchronization reference signal for matching the counter value of the slave node with the counter value of the master node 51-1.
  • Each of the slave nodes 51-2 and 51-3 includes a second calculation unit 71, a synchronization correction processing unit 72, a storage unit 73, a reception completion notification unit 74, and a frame reception unit 75.
  • the second calculation unit 71 includes a second reference signal generation unit 71-1.
  • the synchronization correction processing unit 72 includes an overhead measuring unit 72-1, a count value acquisition unit 72-2, a synchronization determination unit 72-3, and a synchronization correction unit 72-4. Since the slave nodes 51-2 and 51-3 have the same configuration, the following description will be made using the slave node 51-2.
  • the main differences from the processor 11-2 of the first embodiment are that the synchronization determination unit 72-3 is different from the synchronization determination unit 32-3 of the first embodiment, that the reception completion notification unit 74 and the frame reception unit 75 are different.
  • the second reference signal generator 71-1 is the same as the second reference signal generator 31-1 in the first embodiment
  • the second calculator 71 is the second calculator in the first embodiment. This is the same as the unit 31.
  • the overhead measurement unit 72-1 is the same as the overhead measurement unit 32-1 in the first embodiment, and the count value acquisition unit 72-2 is the same as the count value acquisition unit 32-2 in the first embodiment.
  • the storage unit 73 is the same as the storage unit 33 in the first embodiment. Therefore, in the following description, the description of the same configuration as in the first embodiment is omitted.
  • the synchronization correction processing of the slave node 51-2 including the transmission delay time of the communication path 52 will be described.
  • the reception completion notifying unit 74 receives the transmission delay time request frame described above from the master node 51-1, thereby transmitting the reception completion frame to the master node 51-1.
  • the frame receiving unit 75 receives the above-described transmission delay time notification frame transmitted by the master node 51-1, and saves the round-trip transmission delay time (value) included in the frame in the above-described memory 44 or the like. In this way, the slave node obtains the round trip transmission delay time between the master node 51-1 and the slave node from the master node 51-1.
  • the slave node 51-2 which has obtained the round trip transmission delay time from the master node 51-1, receives the synchronization frame and causes the second arithmetic unit (CPU) 71 to generate an interrupt. Receiving the interrupt, the second computing unit 71 starts a synchronization correction process (predetermined process) described later. In the present invention, of course, even when a synchronization frame is received without obtaining a round trip transmission delay time, the synchronization correction processing (predetermined processing) may be started with the round trip transmission delay time set to zero (0). It is.
  • the synchronization frame reception means includes hardware such as FPGA (Field Programmable Gate Array). It is preferable to use logic.
  • the overhead measurement unit 72-1 measures the overhead value until the synchronization correction processing is executed, starting from the reception of the synchronization frame described above.
  • the overhead measuring unit 72-1 includes a counter (timer) that receives and restarts the synchronization frame, and a program process that reads the value of this counter at the start of the synchronization correction process. . That is, the overhead measuring unit 72-1 receives and restarts the synchronization frame, and measures the overhead until the above-described synchronization correction processing is executed, starting from the restart time.
  • the count value acquisition unit 72-2 acquires the count value of the second reference signal generation unit 71-1 at the time when the synchronization correction process is actually executed.
  • the synchronization determination unit 72-3 calculates the one-way transmission delay time of the communication path 52 by halving the above-described round-trip transmission delay time, and further calculates the total delay time obtained by adding the one-way transmission delay time and the above-described overhead. . Then, the synchronization determination unit 72-3 compares the obtained total delay time with the count value of the second reference signal generation unit acquired by the count value acquisition unit 72-2. As a result of the comparison, when both are equal, the synchronization determination unit 72-3 determines that the first reference signal and the second reference signal are synchronized, and when they are different, the first reference signal and the second reference signal It is determined that the reference signal is asynchronous.
  • the synchronization means that the counter value of the first reference signal generation unit is equal to the counter value of the second reference signal generation unit.
  • the synchronization determination unit 72-3 can also determine synchronization / asynchronization by converting the counter values of the counters into time and comparing them. Is possible.
  • the synchronization correction unit 72-4 sets the reference value in the second reference signal generation unit 71-1, and when asynchronous is determined. Then, the synchronization correction value is obtained by subtracting the total delay time value described above from the count value of the second reference signal generation unit acquired by the count value acquisition unit 72-2. Subsequently, the synchronization correction unit 72-4 subtracts the obtained synchronization correction value from the reference value, and sets the subtracted value as a new reference value in the second reference signal generation unit 71-1.
  • the new reference value is a timer of the second reference signal generation unit with respect to a reference value (default reference value) set in the second reference signal generation unit when the synchronization determination unit 72-3 determines synchronization. Temporarily set to correct the value (temporary reference value).
  • a default reference value may be set in the second reference signal generation unit 71-1, or may be set intermittently.
  • the present invention can perform the synchronization correction process considering the influence of the transmission delay time when the synchronization reference signal (synchronization frame) is notified via the communication path 52. That is, in the second embodiment, the counter value including the transmission delay time between the nodes and the overhead of the slave node can be corrected, and high-accuracy synchronization between the nodes can be realized.
  • FIGS. 8 to 10 are time charts (part 1 to part 3) for explaining examples of counter synchronization in the second embodiment.
  • the counter values between the master node 51-1 and the slave node 51-2 are shown in FIG. It is a synchronization example.
  • These figures show the state after the round-trip transmission delay time (600 ⁇ s, ie, the one-way transmission delay time is 300 ⁇ s) has already been calculated by the master node 51-1 and notified to the slave node 51-2.
  • a value synchronization process will be described.
  • the reference value (processing cycle) in the second embodiment is set to 1000 ⁇ s as in the first embodiment, and this reference value can be appropriately changed by the programming device 55.
  • the synchronization frame transmission timing of the master node 51-1 is described as “master station synchronization reference”, and the first reference signal generator 61-1 is described as “master counter”. .
  • the second reference signal generation unit 71-1 is described as “slave-side counter 1”, and the counter included in the overhead measurement unit 72-1 is described as “counter 2”.
  • the master node 51-1 transmits a synchronization frame because the counter value on the master side has reached the reference value. Then, at the time (2), the slave node 51-2 receives the synchronization frame transmitted at the time (1) via the one-way transmission delay time (300 ⁇ s) of the communication path 52, and activates the synchronization correction processing. Yes. With the reception of the synchronization frame, the counter (counter 2) of the overhead measuring unit 72-1 is cleared and restarted ((3) in FIG. 8).
  • the overhead measuring unit 72-1 refers to the value of the counter (counter 2) at the time when the synchronization correction process is started. In conversion, 200 ⁇ s is obtained. In this way, the overhead measuring unit 72-1 measures the overhead until the synchronization correction processing is executed (start time) with the reception of the synchronization frame as a starting point.
  • the count value acquisition unit 72-2 refers to the value of the counter 1 on the slave side, converts it to time, and acquires 500 ⁇ s.
  • the synchronization determination unit 72-3 obtains a one-way transmission delay time of 300 ⁇ s from the round-trip transmission delay time (600 ⁇ s), and adds the obtained transmission delay time and the above-described overhead of 200 ⁇ s to obtain a total delay time of 500 ⁇ s. Yes.
  • the synchronization determination unit 72-3 compares the total delay time 500 ⁇ s with the 500 ⁇ s acquired by the count value acquisition unit 72-2, and since both are equal, the first reference signal and the second reference signal are synchronized. It is determined.
  • the synchronization correction unit 72-4 sets the reference value 1000 ⁇ s in the counter 1 on the slave side. (The slave counter 1 has not been restarted at the time of setting). Then, the counter 1 on the slave side is restarted because the counter value has reached the reference value of 1000 ⁇ s at the time of (6) in FIG.
  • FIG. 9 shows a case where the counter of the slave node 51-2 is delayed by 200 ⁇ s from the counter of the master node 51-1.
  • the master node 51-1 transmits a synchronization frame because the counter value on the master side has reached the reference value. .
  • the slave node 51-2 receives the synchronization frame transmitted at the time (1) via the one-way transmission delay time (300 ⁇ s) of the communication path 52, and starts the synchronization correction processing.
  • the counter (counter 2) of the overhead measuring unit 72-1 is cleared and restarted ((3) in FIG. 9).
  • the overhead measuring unit 72-1 refers to the value of the counter (counter 2) at the time when the synchronization correction process is started. In conversion, 200 ⁇ s is obtained.
  • the count value acquisition unit 72-2 refers to the value of the counter 1 on the slave side, converts it to time, and acquires 300 ⁇ s.
  • the synchronization determination unit 72-3 obtains a one-way transmission delay time of 300 ⁇ s from the round-trip transmission delay time (600 ⁇ s), and adds the obtained transmission delay time and the above-described overhead of 200 ⁇ s to obtain a total delay time of 500 ⁇ s. Yes.
  • the synchronization determination unit 72-3 compares the total delay time of 500 ⁇ s with the 300 ⁇ s acquired by the count value acquisition unit 72-2, and since they are different, the first reference signal and the second reference signal are asynchronous. It is determined.
  • the synchronization correction unit 72-4 sets a temporary reference value in the counter 1 on the slave side. Specifically, the synchronization correction unit 72-4 restarts the “slave side counter 1” using the formula “reference value (processing cycle) ⁇ (“ counter 2 ” ⁇ “ slave side counter 1 ”)”. A value (reset value) is obtained, and the obtained counter value is set in “slave-side counter 1” as a temporary reference value.
  • FIG. 10 shows a case where the counter of the slave node 51-2 is advanced by 200 ⁇ s from the counter of the master node 51-1.
  • the master node 51-1 transmits a synchronization frame because the counter value on the master side has reached the reference value. .
  • the slave node 51-2 receives the synchronization frame transmitted at the time (1) via the one-way transmission delay time (300 ⁇ s) of the communication path 52, and activates the synchronization correction processing. Yes.
  • the counter (counter 2) of the overhead measuring unit 72-1 is cleared and restarted ((3) in FIG. 10).
  • the overhead measuring unit 72-1 refers to the value of the counter (counter 2) at the time of starting the synchronization correction process. In conversion, 200 ⁇ s is obtained.
  • the count value acquisition unit 72-2 refers to the value of the counter 1 on the slave side and converts it to time to acquire 700 ⁇ s.
  • the synchronization determination unit 72-3 obtains a one-way transmission delay time of 300 ⁇ s from the round-trip transmission delay time (600 ⁇ s), and adds the obtained one-way transmission delay time and the above-described overhead of 200 ⁇ s to obtain a total delay time of 500 ⁇ s. Seeking. Then, the synchronization determination unit 72-3 compares the total delay time 500 ⁇ s with the 700 ⁇ s acquired by the count value acquisition unit 72-2, and the two are different, so the first reference signal and the second reference signal are asynchronous. It is determined.
  • the synchronization correction unit 72-4 sets a temporary reference value in the counter 1 on the slave side.
  • the synchronization correction unit 72-4 The original reference value 1000 ⁇ s is set in the slave-side counter 1 by the processing shown in FIG. 8 described above (the slave-side counter 1 has not been restarted at the time of setting). Then, the slave-side counter 1 restarts when the counter value reaches the reference value 1000 ⁇ s. That is, in the second embodiment, since the slave counter 1 can be restarted at substantially the same timing as the master counter restart in the next cycle with respect to the current cycle, The value of the counter 1 on the slave side can be adjusted to a substantially equal value.
  • the synchronization correction processing includes program processing of the count value acquisition unit 72-2, the synchronization determination unit 72-3, the synchronization correction unit 72-4, and the overhead measurement unit 72-1. It is.
  • the slave-side counter 1 that is, the second reference signal generation unit 71-1
  • the present invention is not limited to this. That is, the second reference signal generation unit 71-1 can be realized even outside the CPU.
  • the second reference signal generation unit 71-1 since the second reference signal generation unit 71-1 is built in the CPU, the second reference signal generation unit 71-1 cannot be hardware reset with a predetermined signal generated outside the CPU. .
  • the second reference signal generation unit 71-1 is a counter whose operation is controlled through a program. Therefore, according to the present invention, the reset process (restart process) of the second reference signal generator 71-1 needs to be executed by a program, and the overhead leads to a synchronization error. Therefore, the present invention requires a configuration for measuring overhead (the same applies to the first embodiment).
  • the synchronization correction process is an interrupt process that is activated by receiving a synchronization frame.
  • the slave node 51-2 obtains and holds the round-trip transmission delay time from the master node 51-1, and uses the held round-trip transmission delay time in the synchronization correction processing.
  • the master node 51-1 includes the round trip transmission delay time in the synchronization frame and transmits it to the slave node 51-2, and the slave node 51-2 that has received this sends the round trip transmission time included in the synchronization frame.
  • the master node 51-1 can appropriately notify the slave node of the round trip transmission delay time according to the situation, so that the slave node can utilize the round trip transmission delay time according to the situation in a timely manner. .
  • the transmission delay time notification unit 64 may calculate the one-way transmission delay time by halving the calculated round-trip transmission delay time, and notify the slave node 51-2 of the calculated one-way transmission delay time.
  • the synchronization determination unit 72-3 of the slave node 51-2 may obtain the total delay time using the given one-way transmission delay time as it is.
  • the first reference signal and the second reference signal can be synchronized including the transmission delay time of the signal through the communication path.
  • FIG. 11 is a diagram for explaining an example of a transmission delay time notification procedure according to the second embodiment.
  • the master node 51-1 and the slave nodes 51-2 and 51-3 described above are included, and each node is connected in a state where signals can be transmitted and received via the communication path 52. It is assumed that Further, in the following description, an example is shown in which the master node 51-1 acquires a signal transmission delay time through the communication path 52 between the nodes.
  • the squares shown in FIG. 11 indicate frames, the squares on the line for each node indicate transmission frames, and the squares below the lines indicate reception frames.
  • the frame shown in FIG. 11 is a transmission delay time request frame 81 (“REQ S *” in FIG. 11 (* indicates a number assigned in advance to identify each slave node, for example)) , Reception completion frame 82 (“S *” in FIG. 11), transmission delay time notification frame 83 (“SET S *” in FIG. 11), and response frame 84 to transmission delay time notification frame 83 (“ANS” in FIG. 11) S * ").
  • the master node 51-1 broadcasts a transmission delay time request frame 81-1 (REQ S1) to the slave node 51-2 (S1) on the communication path 52 in accordance with the master node synchronization standard.
  • the transmission delay time request frame 81-1 includes information (target node information) indicating a transmission delay time request for the slave node 51-2.
  • the transmission delay time request frame 81-1 transmitted by broadcast is received by the slave nodes 51-2 and 51-3 via the communication path 52 after a predetermined transmission delay time.
  • the slave node 51-1 receives the transmission delay time request frame 81-1 with the delay time D1 from the master node synchronization reference, and the slave node 51-3 receives the delay time from the master node synchronization reference.
  • the transmission delay time request frame 81-1 is received at D2.
  • each of the slave nodes 51-2 and 51-3 confirms the above-mentioned target node information included in the transmission delay time request frame 81-1.
  • the transmission delay time request frame 81-1 is a request for the slave node 51-2
  • the slave node 51-2 receives the reception completion frame 82-1 (S1) from the master node 51-1. Broadcast.
  • the reception completion frame 82-1 includes information (target node information) indicating that it is a reception completion frame for the master node 51-1.
  • the received reception frame 82-1 is received by the master node 51-1 and the slave node 52-3 via the communication path 52.
  • the master node 51-1 and the slave node 51-3 confirm the target node information described above included in the reception completion frame 82-1.
  • the reception completion frame 82-1 is a frame for the master node 51-1. Therefore, the master node 51-1 determines the slave node 51 based on the time information from the transmission of the transmission delay time request frame 81-1 transmitted according to the master node synchronization reference until the reception completion frame 82-1 is received.
  • Set the transmission delay time for -2 may be a round trip transmission delay time in which a predetermined signal reciprocates between the master node 51-1 and the slave node 51-2 via the communication path 52, or a one-way transmission delay. It may be time.
  • the master node 51-1 creates a transmission delay time notification frame 83-1 (SET S1) for notifying the slave node 51-2 of the set transmission delay time, and the created transmission delay time notification frame 83- 1 is broadcast according to the master node synchronization standard.
  • the transmission delay time notification frame 83-1 includes the target node information described above.
  • the transmission delay time notification frame 83-1 transmitted by broadcast is transmitted by the slave nodes 51-2 and 51-3 after a predetermined transmission delay time via the communication path 52 in the same manner as the transmission delay time request frame 81-1 described above. Received.
  • the slave node 51-2 determines from the target node information of the received transmission delay time notification frame 83-1 that the information is for the own node, the transmission delay time included in the frame, the overhead time described above, and the like.
  • the synchronization correction process in the second embodiment including the above is performed.
  • the slave node 51-2 creates a response frame 84-1 (ANS S1) for the transmission delay time notification frame 83-1, and broadcasts the created response frame 84-1.
  • the response frame 84-1 includes information (target node information) indicating that the frame is for the master node 51-1, information indicating that the synchronization correction processing has been completed, and the like.
  • the transmitted response frame 84-1 is received by the master node 51-1 and the slave node 52-3 via the communication path 52 in the same manner as the reception completion frame 82-1 described above.
  • the master node 51-1 and the slave node 51-3 confirm the target node information described above included in the reception response frame 84-1.
  • the response frame 84-1 is a frame for the master node 51-1. Therefore, the master node 51-1 can grasp that the synchronization correction processing is completed from the response frame 84-1 from the slave node 51-2.
  • the slave node 51-3 includes a transmission delay time request frame 81-1 (REQ S1), a reception completion frame 82-1 (S1), a transmission delay time notification frame 83-1 (SET S1), and a response frame.
  • 84-1 (ANS S1) is received, but since none of them is a frame for the own node, the received frame is discarded.
  • the master node 51-1 similarly notifies the slave node 51-3 of the transmission delay time.
  • the master node 51-1 transmits the transmission delay time request frame 81-2 (REQ S2) to the slave node 51-3 (S2) on the communication path 52 in accordance with the master node synchronization standard. Broadcast to.
  • the transmission delay time request frame 81-2 transmitted by broadcast is received by each of the slave nodes 51-2 and 51-3 via the communication path 52 with a predetermined transmission delay time (D1, D2) as described above. .
  • the transmission delay time request frame 81-2 is a request for the slave node 51-3
  • only the slave node 51-3 broadcasts a reception completion frame 82-2 (S2) to the master node 51-1.
  • the transmitted reception completion frame 82-2 is received by the master node 51-1 and the slave node 52-2 via the communication path 52.
  • the reception completion frame 82-2 is a frame for the master node 51-1. Therefore, the master node 51-1 determines the slave node 51 based on the time information from the transmission of the transmission delay time request frame 81-2 transmitted according to the master node synchronization reference until the reception completion frame 82-2 is received.
  • Set the transmission delay time for -3 may be a round trip transmission delay time in which a predetermined signal reciprocates between the master node 51-1 and the slave node 51-3 via the communication path 52, or a one-way transmission delay. It may be time.
  • the master node 51-1 creates a transmission delay time notification frame 83-2 (SET S2) for notifying the slave node 51-3 of the set transmission delay time, and the created transmission delay time notification frame 83- 2 is broadcast according to the master node synchronization standard.
  • the transmission delay time notification frame 83-2 transmitted by broadcast is transmitted to each slave node 51-2 with a predetermined transmission delay time (D1, D2) via the communication path 52 in the same manner as the transmission delay time request frame 81-2 described above. , 51-3.
  • the slave node 51-3 determines that it is information for the own node from the target node information of the received transmission delay time notification frame 83-2, and the transmission delay time included in the frame, The synchronization correction process in the second embodiment including the overhead time described above is performed. Also, the slave node 51-3 creates a response frame 84-2 (ANS S2) for the transmission delay time notification frame 83-2, and broadcasts the created response frame 84-2. At this time, the response frame 84-2 includes information (target node information) indicating that the frame is for the master node 51-1, information indicating that the synchronization correction processing has been completed, and the like.
  • the transmitted response frame 84-2 is received by the master node 51-1 and the slave node 52-2 via the communication path 52 in the same manner as the reception completion frame 82-2 described above.
  • the master node 51-1 and the slave node 51-2 confirm the above-described target node information included in the response frame 84-2.
  • the response frame 84-2 is a frame for the master node 51-1. Therefore, the master node 51-1 can recognize that the synchronization correction processing has been completed from the response frame 84-2 from the slave node 51-3.
  • the slave node 51-2 includes a transmission delay time request frame 81-2 (REQ S2), a reception completion frame 82-2 (S2), a transmission delay time notification frame 83-2 (SET S2), and a response frame.
  • 84-2 (ANS S2) is received, but since none of them is a frame for the own node, the received frame is discarded.
  • the transmission delay time can be notified by sequentially performing the above-described processing on each slave node of the communication path 52.
  • the transmission delay time notification procedure is not limited to the procedure described above.
  • a send counter may be provided in each of the nodes described above, and control may be performed so that response frames are transmitted at different timings using the send counter.
  • the counter of each node is synchronized with the common memory network using the time division multiplex transmission method, and the entire apparatus is Synchronous control that matches the timing of control is possible.
  • the counter to be synchronized can be configured by using a counter inside the microcomputer or by using a counter in hardware such as an FPGA. Therefore, in the second embodiment, for example, a counter that is synchronized with the master node at the reception timing of the transmission / reception frame and a counter that measures the processing time in the microcomputer are configured by hardware such as FPGA, and the counter value Can be corrected by a microcomputer.
  • the node synchronization between the master and the slave has been described as an example of the node synchronization system 50.
  • the present invention is not limited to this, and for example, a sampling synchronization technique in a protection relay or the like. It can also be applied to.
  • FIG. 12 is a diagram illustrating an example of a schematic configuration of a network transmission system including a node synchronization system using a master node and a slave node in the second embodiment.
  • the network transmission system 90 shown in FIG. 12 includes a plurality of nodes 51 (nodes 51-1 to 51-3 in the example of FIG. 12) and a HUB 91 (one in FIG. 12) as one or more relay apparatuses.
  • HUB 91-1 to 91-5) are included. Note that the number and type of nodes and relay devices, and the connection method are not limited thereto.
  • the master node in FIG. 7, that is, the node 51-1 is the node A (master station), and the slave nodes in FIG. 7, that is, the nodes 51-2 and 51-3 are the node B and the node C (slave). Bureau).
  • the communication path of the network transmission system 90 is, for example, a star type having a relay device between the master node 51-1 and the slave node 51-2.
  • the relay apparatus uses HUB as an example, but the present invention is not limited to this, and for example, a router, a repeater, an optical converter, or the like can be used.
  • the master node and the slave node are, for example, programmable controllers (also referred to as a control device or PLC (Programmable Logic Controller)), and the communication path of the network transmission system 90 is a data exchange bus that exchanges data between these programmable controllers. is there.
  • Devices connected to the data exchange bus include, for example, a PC, a server, an I / O module, a drive device (for example, an inverter, a servo, etc.) in addition to the above-described programmable controller.
  • a node 51-1 and a node 51-3 are connected to the same HUB 12-1, and the node 51-2 is connected to a node via a 5-stage HUB (relay device). 51-1 and the node 51-3.
  • a general Ethernet HUB employs an interface method called store & forward.
  • all the sent frames are stored in the reception buffer in the HUB, and are transmitted after performing the HUB internal processing (for example, abnormality determination, destination determination, etc.).
  • FIG. 13 is a diagram illustrating a schematic sequence example of node synchronization processing.
  • synchronization using the master node 51-1 and the slave node 51-2 will be described.
  • the present invention is not limited to this, and one master node is not limited to this. Multiple slave nodes can be synchronized.
  • the master node 51-1 generates a first reference signal (S11), and the slave node 51-2 generates a second reference signal (S12). Further, this process is cyclically operated in terms of hardware.
  • the master node 51-1 in order to measure the transmission delay time, the master node 51-1 generates a transmission delay time request frame and notifies the slave node 51-2 (S13).
  • the transmission delay time request frame is a data obtained by changing only a predetermined portion of data included in the synchronization frame and can be called a synchronization frame.
  • the transmission delay time request frame is transmitted to the slave node 51-2 via the communication path 52 (S14).
  • the slave node 51-2 When receiving the transmission delay time request frame, the slave node 51-2 generates a reception completion notification and notifies the master node 51-1 (S15).
  • the reception completion notification is transmitted to the master node 51-1 via the communication path 52 (S16).
  • the master node 51-1 calculates, for example, a round trip transmission delay time (S17), generates a transmission delay time frame notification including the calculated round trip transmission delay time, etc. (S18), and generates the generated transmission.
  • the delay time frame notification is transmitted to the slave node 51-2 through the communication path 52 (S19).
  • the slave node 51-2 When receiving the transmission delay time frame (S20), the slave node 51-2 measures the overhead (S21), performs the synchronization determination as described above (S22), and calculates the total delay time when it is asynchronous. (S23).
  • the total delay time is, for example, a value obtained by adding a transmission delay time and an overhead value, but is not limited thereto.
  • the slave node 51-2 performs synchronization correction using the calculated total delay time (S24). In the process shown in FIG. 13, the slave node 51-2 may transmit a response frame indicating that the synchronization correction has been completed to the master node 51-1.
  • the master node 51-1 also performs node synchronization processing in accordance with the above-described procedure for slave nodes other than the slave node 51-2 connected to the communication path 52.
  • a program for causing a computer to function as each unit included in the above-described node 60 is generated, and the generated program is installed in the computer or the like, so that Node synchronization processing can be realized.
  • a predetermined signal can be synchronized with high accuracy.
  • stabilization of the data exchange cycle of each node can be realized.
  • a timer of each node is synchronized with a shared memory network using a time division multiplex transmission method, thereby improving transmission efficiency and data exchange. Efficiency and stabilization of the data exchange cycle can be realized.
  • this embodiment can be applied to a synchronization method when performing a series of operations in a large-scale facility such as a steel plant using a plurality of operations. It can be widely applied as a synchronization method.

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PCT/JP2012/061580 2012-05-01 2012-05-01 信号同期システム、マルチプロセッサ、及びノード同期システム WO2013164887A1 (ja)

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CN201280070128.4A CN104115450B (zh) 2012-05-01 2012-05-01 同步系统、多处理器及节点同步系统
PCT/JP2012/061580 WO2013164887A1 (ja) 2012-05-01 2012-05-01 信号同期システム、マルチプロセッサ、及びノード同期システム
KR1020147022963A KR101578751B1 (ko) 2012-05-01 2012-05-01 신호 동기화 시스템, 멀티 프로세서 및 노드 동기화 시스템
JP2014513325A JP5850143B2 (ja) 2012-05-01 2012-05-01 信号同期システム、マルチプロセッサ、及びノード同期システム
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KR101578751B1 (ko) 2015-12-18
IN2014DN07649A (ko) 2015-05-15
JP5850143B2 (ja) 2016-02-03
JPWO2013164887A1 (ja) 2015-12-24
KR20140121849A (ko) 2014-10-16
CN104115450A (zh) 2014-10-22

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