WO2013161420A1 - Vertical high-voltage semiconductor device and method for manufacturing same - Google Patents
Vertical high-voltage semiconductor device and method for manufacturing same Download PDFInfo
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- WO2013161420A1 WO2013161420A1 PCT/JP2013/057123 JP2013057123W WO2013161420A1 WO 2013161420 A1 WO2013161420 A1 WO 2013161420A1 JP 2013057123 W JP2013057123 W JP 2013057123W WO 2013161420 A1 WO2013161420 A1 WO 2013161420A1
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Definitions
- the present invention relates to a silicon carbide semiconductor device formed on a silicon carbide (SiC) substrate and a method for manufacturing the same, and a power semiconductor device capable of controlling a high breakdown voltage and a large current, particularly silicon carbide, which is one of wide band gap materials, as a semiconductor.
- the present invention relates to a vertical high voltage semiconductor device, an IGBT, and a manufacturing method thereof.
- a silicon single crystal is used as a material of a power semiconductor element that controls a high breakdown voltage and a large current.
- power semiconductor elements There are several types of power semiconductor elements, and the current situation is that they are properly used according to the application.
- bipolar transistors and IGBTs insulated gate bipolar transistors
- Bipolar transistors have several kHz
- IGBTs have a frequency of about 20 kHz.
- a power MOSFET cannot be used with a large current, but can be used at a high speed up to several MHz.
- FIG. 12 shows a cross-sectional structure of a conventional MOSFET.
- An n ⁇ drift layer 302 is provided on an n + substrate (sub) 301, a p base layer 303 is stacked on the n ⁇ drift layer 302, and an n + source layer 304 is selectively formed on the surface layer of the p base layer 303.
- a gate electrode 307 is formed on the n ⁇ drift layer 302, the p base layer 303, and the n + source layer 304 with a source electrode 305 and a gate insulating film 306 interposed therebetween.
- Reference numeral 308 denotes a drain electrode.
- SiC is a next-generation power semiconductor element that has a low on-voltage, high speed, Since it is an element excellent in high temperature characteristics, it has attracted particular attention recently. This is because SiC is a chemically very stable material, has a wide band gap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. This is also because the maximum electric field strength is one digit or more larger than that of silicon. Since SiC has a high possibility of exceeding the material limit in silicon, future growth is greatly expected in power semiconductor applications, particularly MOSFETs. In particular, the on-resistance is expected to be small, but a vertical SiC-MOSFET having a further low on-resistance while maintaining high breakdown voltage characteristics can be expected.
- a p base layer 303 is stacked on the n ⁇ drift layer 302, and an n + source layer 304 is selectively formed on the surface layer of the p base layer 303.
- the n ⁇ drift layer 302, the p base layer 303, and the n + source layer are formed.
- a gate electrode 307 is formed on 304 via a gate insulating film 306, and a drain electrode 308 is formed on the back surface of the substrate 301.
- the SiC-MOSFET formed in this way is expected to be used as a switching device in power converters such as inverters for motor control and uninterruptible power supplies (UPS) as elements capable of high-speed switching with low on-resistance.
- power converters such as inverters for motor control and uninterruptible power supplies (UPS) as elements capable of high-speed switching with low on-resistance.
- UPS uninterruptible power supplies
- the oxide film may be destroyed due to the SiC that does not become a problem because the breakdown electric field strength of silicon is reached before a large electric field is applied to the oxide film.
- a large electric field strength is applied to the gate oxide film of the SiC-MOSFET shown in FIG. 12, which may cause a serious problem in gate oxide film destruction and reliability. This is true not only for SiC-MOSFETs but also for SiC-IGBTs.
- FIG. 13 is a cross-sectional view of the unit cell.
- a low-concentration n-type drift layer 202 is deposited on a high-concentration n-type substrate 201, and a high-concentration p-type gate layer 231 is formed on the surface of the n-type drift layer 202 by ion implantation.
- a concentration p-type layer 232 is deposited.
- An n-type source layer 205 is selectively formed by ion implantation on the surface portion of the low-concentration p-type layer 232, a gate electrode 207 is interposed via a gate oxide film 206, and a source electrode 209 is further interposed via an interlayer insulating film 208. Are formed, and a channel region 211 is formed in the low-concentration p-type deposition layer 232 immediately below the gate oxide film 206.
- An n-type base layer 204 that penetrates the low-concentration p-type deposition layer 232 and reaches the n-type drift layer 202 is selectively formed as a reversal layer by ion implantation of n-type impurities from the surface.
- 210 is a drain electrode.
- the channel region 211 is formed in a low-concentration p-type deposition layer that is not ion-implanted, so that high mobility of conduction electrons can be obtained, and a vertical MOSFET with low on-resistance can be manufactured.
- the vertical channel portion 224 of the well is completely blocked at a low voltage by the depletion layer extending in the lateral direction from the high-concentration p-type gate layer 231 to the low-concentration n-type drift layer 202. This is characterized in that the electric field leakage to the gate oxide film or the like can be prevented and the source / drain withstand voltage can be increased.
- the impurity concentration of the strike back layer is low and thick.
- the thickness is thin, a portion of the well that is not closed by the depletion layer remains, the mobile charge reaches near the interface with the gate oxide film 206, and the gate interposed between the gate electrode 207 and the n-type base layer 204 There is a problem that a strong electric field is applied to the oxide film 206 to cause dielectric breakdown.
- SiC has characteristics that exceed the material limit of silicon, for example, it has a wide energy gap and is thermally stable, so that future growth is expected greatly in power semiconductor applications, especially MOSFETs.
- the on-resistance is expected to be small, but even when a high voltage is applied, the gate oxide film is required to have a low on-resistance characteristic without being destroyed or reliability deteriorated.
- An object of the present invention is to provide a vertical high-voltage semiconductor device having a low on-resistance characteristic and a method for manufacturing the same without destroying a gate oxide film or deteriorating reliability even when a high voltage is applied. is there.
- a further object of the present invention is to provide a vertical SiC-MOSFET having a low on-resistance characteristic and an IGBT and a method for manufacturing the same without destroying a gate oxide film or deteriorating reliability even when a high voltage is applied. There is to do.
- the well layer not closed by the depletion layer Means are provided to ensure that the depletion layer has no open space so that no part remains.
- the well portion facing the gate oxide film is completely closed by the depletion layer, so that the mobile charge does not reach the gate oxide film through the well portion that is not closed, and the electric field is concentrated on the gate oxide film. No breakdown occurs in the gate oxide film.
- a coupling portion including a second conductivity type region and a base region for protecting the gate oxide film is provided on the drift region.
- the coupling portion is integrally connected to a part of each of the second conductivity type region and the base region.
- the connecting portions of the base region in which the source region of each cell is formed and the second conductivity type region for protecting the gate oxide film facing the base region are arranged in a plane along the substrate surface. a) a point farthest and equidistant from the center of all opposing source regions, and (b) a point nearest and equidistant from the end farthest from the center of the source region Form.
- the coupling portion is integrally provided in a part of each of the second conductivity type region and the base region so as to include equidistant points (gap in the outline of the depletion layer).
- the coupling portion is integrally provided in a part of each of the second conductivity type region and the base region so as to include points that are close and equidistant.
- a first conductivity type (n-type) SiC layer 2 serving as a drift layer is epitaxially grown on a first conductivity type (n-type) SiC semiconductor substrate 1 to form the first
- the second conductivity type (P type) semiconductor layer 3 is formed by ion implantation of a predetermined region into the conductivity type (n type) SiC layer 2, and the first conductivity type (n type) SiC layer 2 and the second conductivity type (
- a base layer 4 of a second conductivity type (P type) semiconductor is epitaxially grown on the P type) semiconductor layer 3, and the second conductivity type (P type) semiconductor layer 3 and the base of the second conductivity type (P type) semiconductor are obtained.
- a first conductivity type (N-type) reversal layer is formed by ion-implanting into a part of the layer 4 so that a part of the coupling part (connected part) of the layer 3 and the layer 4 remains.
- Source region of (N type) source layer 7 and second conductivity type (P type) contact The auxiliary layer 6 is selectively formed in the second conductive type (P-type semiconductor) base layer 4.
- a source electrode (not shown) is provided on the source region 7 and the contact auxiliary layer 6.
- a drain electrode (not shown) is provided on the back surface of the semiconductor substrate 1.
- the coupling portion including the point closest to and equidistant from each other is integrally provided in a part of each of the second conductivity type region and the base region.
- the coupling portion is configured based on the configuration of the source region.
- the cell electrode (source electrode) is formed such that the outer shape of the surface along the substrate surface is the same as or similar to the outer shape of the surface of the source region. In particular, it is preferable that the outer shape of the cell electrode (source electrode) is formed in a similar and reduced shape that is slightly smaller than the outer shape of the source region.
- a vertical high-voltage semiconductor device includes a semiconductor substrate 1 of a first conductivity type, a semiconductor layer 2 of a first conductivity type formed on the semiconductor substrate 1 and having a lower concentration than the semiconductor substrate 1, and a semiconductor A high-concentration second conductivity type semiconductor layer 3 selectively formed on the surface of the layer 2, and a second conductivity type and relatively low concentration semiconductor layer (base) on the semiconductor layer 2 and the semiconductor layer 3.
- Layer) 4 a first conductivity type source region 7 selectively formed on the surface layer of the second conductivity type base layer 4, and the first conductivity type semiconductor through the second conductivity type base layer 4 from the surface.
- the first conductive type well region 20 formed so as to reach the second layer, and the exposed surface portion of the second conductive type base layer 4 sandwiched between the first conductive type source region 7 and the first conductive type well region 20 A gate electrode layer provided on at least a part of the gate insulating film via a gate insulating film; Vertical high-voltage semiconductor device having a source electrode 7 connected to the second conductivity type base layer 4 via a type auxiliary region 7 and a contact auxiliary layer, and a drain electrode provided on the back surface of the first conductivity type semiconductor substrate 1 Because In the plan view, a point that is the farthest and equidistant point from the center of all the opposing source regions, and the point that is the nearest and equidistant from the end farthest from the center of the source region is used as a coupling portion. In other words, each of the semiconductor layer 3 and the base layer 4 is coupled in place of the well region 20.
- a layer 7 is formed by epitaxial growth, a high-concentration second conductive semiconductor layer 3 selectively formed on the surface of the semiconductor layer 2 is formed by ion implantation, and the semiconductor layer 2 and the semiconductor layer 3 are further formed.
- a first conductivity type source formed on the surface layer of the second conductivity type base layer is formed by epitaxial growth on the semiconductor layer (base layer) 4 of the second conductivity type having a relatively low concentration.
- a region 5 and a first conductivity type well region 20 formed so as to penetrate the second conductivity type base layer from the surface and reach the first conductivity type semiconductor layer 2 are formed by an ion implantation method. To do.
- the semiconductor material is a semiconductor material having a band gap of 2.2 eV or more.
- Examples of SiC include 2H—SiC with a band gap of 3.33 eV, 3C—SiC with 2.23 eV, 4H—SiC with 3.26 eV, and 6H—SiC with 2.93 eV.
- the band gap of SiC is specified as 2.2 eV or more compared to 1.12 of Si.
- the crystallographic plane index of the first conductivity type semiconductor substrate is an arbitrary value within a range of 0 degrees to 10 degrees with respect to (000-1).
- the surface is inclined at an angle.
- the crystallographic plane index of the semiconductor substrate of the first conductivity type is at an arbitrary angle within a range of 0 degrees to 10 degrees with respect to (0001). It is characterized by an inclined surface.
- a vertical high voltage semiconductor device includes: A first conductivity type (n-type) semiconductor substrate 1; a first conductivity type (n-type) low impurity concentration semiconductor layer 2 formed on the first conductivity type (n-type) semiconductor substrate 1; A second conductive type (p-type) high impurity concentration semiconductor layer 3 selectively formed on the conductive type (n-type) semiconductor layer 2 and the surface of the second conductive type (p-type) semiconductor layer 3 and the exposed surface.
- a low-concentration second conductivity type (p-type) conductivity type base layer 4 is formed on the surface of the first conductivity type (n-type) semiconductor layer 2, and the second conductivity type (p-type) conductivity type base layer 4 is formed.
- the semiconductor device is a point farthest and equidistant from the center of all the opposing source regions, and the closest and equidistant from the end farthest from the center of the source region
- the coupling portion including these points is integrally provided in the second conductivity type region and the base region.
- the second conductive type (p-type) semiconductor layer 3 and the second conductive type (p-type conductive type) base layer 4 are partially extended in the shape of a coupling portion.
- a contact with the source electrode is formed on the source region 7 and the base layer 4, and a drain electrode is formed on the back surface of the n-type semiconductor substrate 1.
- the cell pattern is a hexagon.
- the coupling portions are respectively radial (cells of the cell) from the corners of the second conductivity type (p-type) semiconductor layer 3 and the second conductivity type (p-type) conductivity type base layer 4 constituting the cell pattern. And has a width that includes the outline gap of the depletion layer. The width is such that the well portion facing the gate oxide film is completely closed with a depletion layer, and the mobile charge does not reach the gate oxide film through the well portion that is not closed, and the electric field concentrates on the gate oxide film. It should be long enough to function so that nothing happens.
- the cell pattern has a stripe shape.
- the coupling portion is configured to include all gaps in the outline of the depletion layer.
- a first conductivity type (n-type) SiC layer 2 serving as a drift layer is epitaxially grown on a first conductivity type (n-type) SiC semiconductor substrate 1, and the first The second conductivity type (P type) semiconductor layer 3 is formed by ion implantation of a predetermined region into the conductivity type (n type) SiC layer 2, and the first conductivity type (n type) SiC layer 2 and the second conductivity type (
- a base layer 4 of a second conductivity type (P type) semiconductor is epitaxially grown on the P type) semiconductor layer 3, and the second conductivity type (P type) semiconductor layer 3 and the base of the second conductivity type (P type) semiconductor are obtained.
- a first conductivity type (N-type) reversal layer is formed by ion-implanting into a part of the layer 4 so that a part of the coupling part (connected part) of the layer 3 and the layer 4 remains.
- N type source layer and second conductivity type (P type) contact layer It is selectively formed in the two-conductivity type (P-type semiconductor) base layer 4.
- (22) In the manufacturing method of (21) above, when viewed in plan, it is a point farthest and equidistant from the center of all opposing source regions and the end farthest from the center of the source region
- the coupling portion including the point closest to and equidistant from the second conductive type region and the base region is integrally provided.
- the present invention can increase the impurity concentration of the n-type semiconductor layer 2 and the n-type semiconductor well region 20 to sufficiently reduce the on-resistance, or between the p-type semiconductor layers 3 and the p-type conductivity base layer. Even when the on-resistance is sufficiently lowered by widening the distance between the four, even when a high voltage is applied between the source and the drain (a source is applied with 0V and a + voltage is applied to the drain), the n-type semiconductor well region 20 A large electric field is not applied to the gate oxide film, and a sufficient device breakdown voltage can be maintained.
- the p-type semiconductor layer 3 and the p-type conductivity type base layer 4 are connected to each other, so that a depletion layer generated in the drift layer 2 easily spreads in the lateral direction along the P + layer 3. Because. As a result, even if the impurity concentration of the n-type semiconductor layer 2 and the n-type semiconductor well region 20 is set higher than that of the conventional MOSFET, the depletion layer tends to spread along the P + layer 3 in the lateral direction. The on-resistance can be reduced while increasing the distance between the semiconductor layers 3 and between the p-type conductivity type base layers 4 to maintain a sufficient element breakdown voltage.
- the base layer 4 of the present invention when the base layer 4 of the present invention is formed by the epitaxial growth method, it can be made flat so that there is almost no surface roughness, so that the mobility of the MOSFET portion on the surface becomes extremely high, and as a result, the on-resistance is further reduced. Can do.
- the crystallographic plane index of the n-type semiconductor substrate 1 is relative to a plane parallel to (000-1) due to the relationship between the off angle and flatness of the epitaxial layer.
- the off-angle can be made sufficiently small and the step can be made sufficiently small, the roughness is very good and the mobility is not deteriorated, so that the interface state density between the gate oxide film and the semiconductor interface can be reduced. Mobility can be further improved. As a result, the on-resistance can be made extremely small.
- the gate oxide film has a structure in which an electric field is not easily applied while maintaining a sufficient device breakdown voltage characteristic regardless of the crystal plane orientation of the substrate.
- a vertical SiC-MOSFET and an IGBT that have a low on-resistance, a large breakdown resistance, and capable of high-speed switching characteristics can be configured.
- the p + type semiconductor layer 3 is formed on the n type semiconductor layer 2 to be the drift layer so as to face each source region, and the p + type semiconductor layer 3 is formed.
- a p-type conductive base layer 4 is formed on the upper surface of the p-type semiconductor layer 3 so as to face the layer 3, and a coupling portion is integrally formed between the p + -type semiconductor layers 3 and between the p-type conductive base layers 4. Since it did in this way, when laminating
- the channel region 18 is formed as an N well region composed of the N-epitaxial layer 2 and the N returning layer 5, even if the N returning layer 5 can only be formed thin, the entire channel region 18 becomes thicker.
- the electric field applied to the gate oxide film can be lowered.
- a semiconductor material having a band gap of 2.2 eV or more all SiC having a band gap value of 2.2 eV or more, for example, 2H—SiC having a band gap of 3.33 eV, 3C—SiC having a band gap of 2.23 eV, 3C Targets are .26 eV 4H-SiC and 2.93 eV 6H-SiC.
- the band gap of SiC can be identified by specifying 2.2 eV or more compared to 1.12 of Si.
- the energy gap can be wide and thermally stable.
- the on-resistance can be reduced. Even when a high voltage is applied, a low on-resistance can be obtained without breaking the gate oxide film or deteriorating reliability. Further, by using such a semiconductor material, there is an effect that a manufacturing method peculiar to this material can be applied.
- FIG. 4 is an explanatory diagram of a well closed state of the SiC-MOSFET in Example 1 of the present invention. It is sectional drawing of the SiC-MOSFET manufacturing process in Example 1 of this invention (when a P + board
- FIG. 7 is a P + layer spacing-device breakdown voltage characteristic diagram of Example 1 of the present invention and a conventional SiC-MOSFET, and is a comparative evaluation result. It is a characteristic view of the load short circuit tolerance measurement result of SiC-MOSFET in Example 1 of the present invention. It is a characteristic view of the turn-off breakdown tolerance evaluation result of SiC-MOSFET in Example 1 of the present invention.
- FIG. 6 is an explanatory diagram of a well closed state when the SiC-MOSFET coupling portion in Example 1 of the present invention is omitted.
- FIG. 1A is a cross-sectional view taken along the line EF in FIG. 1B or FIG. 1C, and is a plan view in a state where the upper side is removed from the gate oxide film.
- FIG. 1B is a cross-sectional view taken along the line AB in FIG.
- FIG. 1C is a cross-sectional view taken along the line CD in FIG.
- FIG. 1D is a plan view of the gate electrode corresponding to FIG.
- FIG. 2 is a diagram illustrating the function of the coupling unit.
- the vertical planar gate MOSFET a silicon carbide is used as a semiconductor material, and a MOSFET having an element withstand voltage of 1200 V is shown.
- Example 1 of FIG. 1 shows the case of a hexagonal cell pattern.
- the vertical high breakdown voltage semiconductor device of FIG. particularly the vertical SiC-MOSFET, includes an n + type semiconductor substrate 1, an n ⁇ type epitaxial layer 2 as a drift layer epitaxially grown on the semiconductor substrate 1, and this n ⁇ type.
- a p + type semiconductor layer 3 selectively formed on the epitaxial layer 2 and a p ⁇ type semiconductor layer 4 are epitaxially grown on the surface of the p + type semiconductor layer 3 and selectively formed on the surface layer of the p ⁇ type semiconductor layer 4.
- n + type source region 7 is formed, an n type well region 20 is formed so as to penetrate the p ⁇ type semiconductor layer 4 from the surface to reach the n type semiconductor layer 2, and the n type source region 7 and the n type well region
- the gate electrode 9 is formed on the surface of the p-type semiconductor layer 4 sandwiched between the gate insulating film 8 and the gate electrode 9.
- the n-type well region 20 is composed of the N counter layer 5 and the n ⁇ -type epitaxial layer 2 and becomes the channel region 18.
- the region 6 becomes a contact auxiliary layer to the base region.
- Region 10 is an interlayer insulating film.
- a region 17 is a lower region of the connection portion in the N ⁇ epitaxial layer 2.
- a source electrode (not shown) is provided on the first conductivity type source region 7 and the contact auxiliary layer 6.
- a drain electrode (not shown) is provided on the back surface of the semiconductor substrate 1.
- the coupling portion 46 is composed of the coupling portion 15 of the P ⁇ epitaxial layer 4 and the coupling portion 16 of the P + layer 3 in FIG. 1C, and is provided immediately below the gate oxide film 8 and the gate electrode 9.
- the coupling portion 46 constitutes a means for ensuring that the depletion layer has no vacant space so that when the depletion layer has fully extended into the channel portion of the well, the portion of the well not closed by the depletion layer does not remain.
- the coupling portion 15 is provided integrally with each layer.
- the coupling portion is configured based on the configuration of the source region.
- the cell electrode (source electrode) is formed such that the outer shape of the surface along the substrate surface is the same as or similar to the outer shape of the surface of the source region.
- the outer shape of the cell electrode is formed in a similar and reduced shape that is slightly smaller than the outer shape of the source region.
- the coupling portion is integrally provided in the second conductivity type region 3 and the base region 4 so as to include the point (gap in the outline of the depletion layer).
- the depletion layer outline 19 remains in the channel until the channel region 18 of the well is completely blocked by the depletion layer 19 extending from the P + layer 3 to the channel region 18.
- the region 18 extends to the gate insulating film 8.
- the coupling portion 46 is continuously formed in the length direction of the P + layer 3, it is oxidized from the drift layer 2 immediately below the gate oxide film 8 and the gate electrode 9. Since the space to the film 8 is isolated, the outline 19 of the depletion layer does not approach the vicinity of the oxide film 8 and no gap between the outlines of the depletion layer is generated.
- FIG. 14 is an explanatory diagram when the connecting portion 46 is omitted from the first embodiment shown in FIGS. 1 and 2.
- 14A is a plan view taken along the line IJ in FIG. 14B
- FIG. 14B is a cross-sectional view taken along the line EF in FIG. 14A.
- Reference numerals 101 to 109 and 119 are obtained by adding 100 to the corresponding constituent elements of the first embodiment.
- a depletion layer is generally formed as indicated by an outline 119 with a dotted line.
- the outlines 119 of the opposing depletion layers are formed in contact with each other so that the well is completely closed.
- the outline 119 of the depletion layer is in contact as shown in the enlarged view surrounded by a circle in FIG.
- the gap 120 of the outline of the depletion layer that is not formed is formed.
- the center of the outline gap 120 of the depletion layer is a position where the lengths from the center points of the three adjacent hexagonal cell patterns are equal.
- the gap 120 in the outline of the depletion layer is substantially triangular in the plan view of FIG. 14A, substantially parallel in the cross-sectional view of FIG. 14B, and generally exhibits a substantially triangular prism. Note that when the cell pattern is different, the shape of the gap in the outline of the depletion layer is also different.
- the gap 120 of the outline of the depletion layer is formed as shown in the sectional view of FIG.
- the electric field may concentrate between the gate oxide film 108 and the gate oxide film 108 may break down.
- the coupling portion of the present invention can prevent the gate oxide film from being destroyed by the electric field concentration.
- FIG. 3 shows a manufacturing method of the vertical planar gate MOSFET shown in the first embodiment of the present invention.
- FIG. 3A is a cross-sectional view showing a process of manufacturing a portion where the P + layer 3 is not bonded, including the process in the left column of FIG.
- FIG. 3B is a cross-sectional view showing a process of manufacturing a portion where the P + layer 3 is bonded, including the process in the right column of FIG.
- Steps are: Step 1 (a1; b1): N-epi (epitaxial layer 2) growth, Step 2 (a2; b2): P + layer 3 implantation (ion implantation), Step 3 (a3; b3): P layer 4 epi Growth (base region 4 epitaxial growth), step 4 (a4;): N layer 5 backlash (ion implantation), step 5 (a5; b5): N + layer 7 (source region), P + layer 6 (contact to base region 4) Auxiliary layer) formation, Step 6 (a6; b6): Gate oxide film 8 and gate electrode 9 formation, Step 7 (a7; b7): Interlayer insulating film 10 and electrodes 12, 13 formation.
- Step 1 (a1; b1): First, an n-type SiC semiconductor substrate 1 is prepared.
- the low-resistance SiC semiconductor 1 containing about 2 ⁇ 10 19 cm ⁇ 3 of nitrogen as an impurity is used.
- An n-type SiC layer 2 containing about 1.8 ⁇ 10 16 cm ⁇ 3 of nitrogen is epitaxially grown to a thickness of 10 ⁇ m on a plane inclined by 4 ° with respect to (000-1) as the crystallographic plane index of the n-type semiconductor substrate 1.
- Step 2 (a2; b2): A P + layer 3 having a width of 13 ⁇ m and a depth of 0.5 ⁇ m is formed on the layer 2 by ion implantation. In this case, aluminum was used as the ion.
- the dose was set so that the impurity concentration was 1.0 * 10 18 cm ⁇ 3 .
- a part of the P + layer 3 is bonded to each other (see FIG. 1C). That is, as shown in FIG. 1 (b), the N + layer 5 and the N well region 20 are not formed, but the P + layer 3 and the P layer 4 are connected to each other as shown in FIG. 1 (c). It forms continuously (refer process (b2)). This connected portion becomes a coupling portion described later.
- a P + layer 3 having a predetermined shape is selectively formed on the layer 2 by an ion implantation method (see step (a2)).
- a hexagonal cell pattern is used, but there is no problem even with a square cell pattern.
- the distance between the P + layers 3 where they are not coupled (substantially the width of the N well 20) shown in FIG. Step 3 (a3; b3):
- a P base layer 4 is formed on the P + layer 3 and the n-type layer 2 to a thickness of 0.5 ⁇ m by epitaxial growth.
- the impurity at that time was aluminum, and the impurity concentration was set to 2.0 * 10 16 cm ⁇ 3 .
- the N-turnback layer 5 is formed by selectively injecting it so as to have a width of 1.5 ⁇ m and a width of 2.0 ⁇ m.
- Step 5 (a5; b5): Next, an N + source layer 7 and a P + contact layer 6 are selectively formed in the p base layer 4 by ion implantation.
- Step 6 (a6; b6): Thereafter, activation annealing is performed. The heat treatment temperature and time are 1620 ° C. and 2 minutes. Thereafter, a gate oxide film 8 is formed by thermal oxidation with a thickness of 100 nm and annealed at 1000 ° C. in a hydrogen atmosphere. A polycrystalline silicon layer doped with phosphorus is formed as the gate electrode 9 and patterned.
- FIG. 11 is a table of characteristics of Example 1-5 of the present invention and SiC-MOSFET and Si-IGBT of the prior art.
- the chip size is 3 mm square, the active area is 5.27 mm 2 , and the rated current is 25A.
- the on-resistance (RonA) has a sufficiently low value of 2.85 m ⁇ cm 2, and the initial device breakdown voltage is 1452 V, which is sufficiently good as a 1200 V device.
- the on-resistance showed a sufficiently low value of equivalent 2.8 m ⁇ cm 2 .
- 880 V was applied between the source and drain, the gate oxide film was destroyed. From this, it can be seen that the element of the present invention exhibits extremely low on-resistance while maintaining a sufficient element breakdown voltage.
- FIG. 6 is a P + layer spacing-device breakdown voltage characteristic diagram of Example 1 of the present invention and a conventional SiC-MOSFET, and is a comparative evaluation result.
- FIG. 6 shows the device breakdown voltage and N counterattack of the SiC-MOSFET in Example 1 of the present invention and the SiC-MOSFET in which the P base layer 204 and the P + layer 203 are not coupled at all in the SiC-MOSFET in Example 1 of the present invention. It is an actual measurement result when changing the layer (P + layer) width.
- the horizontal axis represents P + layer spacing (um), and the vertical axis represents device breakdown voltage (v).
- the characteristics of FIG. 6 are the elements in the SiC-MOSFET (A) in Example 1 of the present invention and the SiC-MOSFET (B) that does not couple the P base layer 204 and the P + layer 203 to each other for comparison. This is an actual measurement result when the breakdown voltage and the width of the N-turnback layer (P + layer) are changed.
- the concentration thickness of each layer of the element is as described above.
- the actual measurement result of the P + layer spacing-element breakdown voltage characteristic is illustrated by the following table.
- Example 1 of the present invention achieves a high breakdown voltage characteristic of 1400 V or higher, which is a sufficient breakdown voltage characteristic for a 1200 V device.
- the on-resistance at this time is the same for both conditions, and it has been found that making a cell under the gate pad is effective in reducing the on-resistance because the effective area in the element increases.
- the distance In order to satisfy the high breakdown voltage characteristic of 1400 V or higher equivalent to that of the first embodiment of the present invention in the SiC-MOSFET used for comparison, in order not to exceed the breakdown electric field of the gate oxide film, It has been found that the distance must be 1.0 ⁇ m or less and the N-backing layer concentration must be reduced to 1/5.
- the on-resistance at that time was an extremely high value of 10.8 m ⁇ cm 2 . In other words, the present invention can improve the on-resistance and the element breakdown voltage characteristics at the same time.
- a load short-circuit tolerance test was performed.
- the power supply voltage Vcc (Vds) 800 V, and the measured temperature (Tj) is 175 ° C.
- a schematic diagram of the measured waveform is shown in FIG.
- FIG. 7 is a characteristic diagram of the measurement results of the load short-circuit withstand capability of the SiC-MOSFET in Example 1 of the present invention.
- the horizontal axis represents time ( ⁇ s)
- the vertical axis represents voltage (V) and current (A).
- Ip 125 A
- FIG. 8 is a characteristic diagram of a turn-off breakdown resistance evaluation result of the SiC-MOSFET in Example 1 of the present invention.
- the horizontal axis represents time ( ⁇ s), and the vertical axis represents voltage (V) and current (A).
- Vdsclamp in FIG. 8 When the turn-off resistance was further evaluated, it was confirmed that the source-drain voltage Vds was clamped at 1630 V (Vdsclamp in FIG. 8), and 100 A (four times the rated current) could be turned off at 150 ° C. without destruction.
- the element of the present invention realizes a low on-resistance, and has an extremely large load short-circuit resistance and turn-off resistance.
- the withstand voltage of the conventional SiC-MOSFET prepared for comparison was evaluated, the withstand voltage of the device was not sufficient, and the load short circuit withstand capability and the turn-off withstand capability were significantly inferior to those of the device of Example 1 of the present invention (FIG. 11).
- the crystallographic plane index of the n-type semiconductor substrate 1 is an arbitrary angle of 0 ° or more and 10 ° or less with respect to (000-1), for example, 0 °, 2 °, 8 °, 10 °
- a device was similarly formed on the surface, and the fabricated device was evaluated. As a result, it was found that there was almost no change in characteristics. In addition, even when a prototype was made using GaN, a good effect was confirmed.
- FIG. 9 is a turn-off switching waveform diagram of the SiC-MOSFET in Example 1 of the present invention.
- FIG. 9A shows that the measured temperature is R.P.
- the characteristics of the drain-source voltage Vds, the gate-source voltage Vgs, and the drain-source current Ids at T (room temperature) are represented, the horizontal axis represents time, and the vertical axis represents voltage and current.
- FIG. 9B shows the characteristics of the drain-source voltage Vds, the gate-source voltage Vgs, and the drain-source current Ids at a measurement temperature of 200 ° C., where the horizontal axis represents time and the vertical axis represents voltage and current.
- FIG. 9B show a state after Vgs is switched from the ON state to the OFF state. Ids switches from 25A to 0A, and Vds switches from 0V to 600V. It converges quickly in about 100ns after switching.
- the characteristics shown in FIG. 9 are good in terms of breakdown voltage and resistance as a semiconductor element.
- FIG. 10 is a turn-on switching waveform diagram of the SiC-MOSFET in Example 1 of the present invention.
- FIG. 10 (a) shows that the measured temperature is R.P.
- the characteristics of the drain-source voltage Vds, the gate-source voltage Vgs, and the drain-source current Ids at T (room temperature) are represented, the horizontal axis represents time, and the vertical axis represents voltage and current.
- FIG. 10B shows the characteristics of the drain-source voltage Vds, the gate-source voltage Vgs, and the drain-source current Ids at a measurement temperature of 200 ° C., where the horizontal axis represents time and the vertical axis represents voltage and current.
- FIG. 10B show a state after Vgs is switched from the OFF state to the ON state. Ids switches from 0A to 25A, and Vds switches from 600V to 0V. It converges quickly in about 100ns after switching.
- the characteristics shown in FIG. 10 are good in terms of breakdown voltage and resistance as a semiconductor element.
- a vertical SiC-MOSFET having a specification of 1200 V and 25 A was manufactured by the same manufacturing process as in Example 1.
- the n-type SiC layer 202 containing about 1.8 ⁇ 10 16 cm ⁇ 3 of nitrogen is formed on the surface of the n-type semiconductor substrate 1 whose crystallographic plane index is inclined by 4 ° with respect to (0001).
- 10 ⁇ m epitaxial growth was performed.
- Other processes and the cell structure are exactly the same.
- the electrical property evaluation results of the fabricated elements are shown as Example 2 in Table 1 of FIG.
- the crystallographic plane index of the n-type semiconductor substrate 201 is an arbitrary angle of 0 ° to 10 ° designed with a stripe cell pattern with respect to (0001), for example, 0 °, 2 °, 8 °, 10 °.
- a film was formed in the same manner on the inclined surface, and the element was also evaluated. As a result, it was found that there was almost no change in characteristics.
- FIG. 4 is a diagram showing the arrangement of the P + layer 3 and the cell of the SiC-MOSFET in the third embodiment of the present invention.
- 4A is a plan view taken along the line EF in FIG. 4B or FIG. 4C (however, the gate oxide film or more is omitted), and
- FIG. 4B is a cross-sectional view taken along the line AB in FIG. 4A.
- FIG. 4C is a cross-sectional view taken along line CD of FIG.
- FIG. 5 is an explanatory diagram of the well closed state of the SiC-MOSFET in the third embodiment of the present invention.
- 5A is a plan view taken along the line EF of FIG. 5B or FIG. 5C, FIG.
- FIG. 5B is a cross-sectional view taken along the line AB of FIG. 5A
- FIG. 5A is a cross-sectional view taken along line CD
- FIG. 5D is a cross-sectional view taken along line GH in FIG. 5A
- FIG. 5E is a cross-sectional view taken along line GH in FIG. FIG.
- the vertical SiC-MOSFET having the stripe cell pattern shown in FIG. 4 includes an n + type semiconductor substrate 21, an n ⁇ type epitaxial layer 22 that becomes a drift layer epitaxially grown on the semiconductor substrate 21, and the n ⁇ type epitaxial layer 22.
- Region 26 serves as a contact auxiliary layer to the base region.
- Reference numeral 30 denotes a correlation insulating film.
- a source electrode (not shown) is provided on the region 27 and the region 26.
- a drain electrode (not shown) is provided on the back surface of the semiconductor substrate 21.
- the n-type well region 44 is composed of the N counter layer 25 and the n ⁇ -type epitaxial layer 22 and constitutes a channel region 38.
- the same divided region 41 as the P + layer 23 and the same divided region 40 as the P ⁇ epitaxial layer 24 are formed.
- Region 26 serves as a contact auxiliary layer to the base region.
- the region 30 is an interlayer insulating film.
- Region 37 is a lower region of the connection portion in N ⁇ epitaxial layer 2.
- the coupling portion 45 includes the coupling portion 35 of the P ⁇ epitaxial layer 24 and the coupling portion 36 of the P + layer 3 in FIG. 4C, and is provided immediately below the gate oxide film 28 and the gate electrode 29.
- Reference numeral 42 denotes a unit cell pattern. In practice, the required number of such cell patterns are arranged on a plane.
- the coupling portion 45 constitutes a means for ensuring that the depletion layer has no vacant space so that when the depletion layer reaches the channel portion of the well, the portion of the well not closed by the depletion layer does not remain.
- Each of the P + layers 23 (the second conductivity type region for protecting the gate oxide film) and the P ⁇ epitaxial layer 24 (the base region) have the coupling portions 35 including the nearest and equidistant points.
- the coupling portion is configured based on the configuration of the source region.
- the cell electrode (source electrode) is formed such that the outer shape of the surface along the substrate surface is the same as or similar to the outer shape of the surface of the source region.
- the outer shape of the cell electrode (source electrode) is formed in a similar and reduced shape that is slightly smaller than the outer shape of the source region.
- the stripe cell pattern when viewed in plan, it is farthest and equidistant from the centers of all the opposing source regions 27 and is nearest and equidistant from the end farthest from the center of the source regions.
- the coupling portion is integrally provided in the second conductivity type region and the base region so as to include the above points.
- the position of the coupling portion 45 is not directly above the outline gap 43 of the depletion layer 39.
- the coupling portion 45 causes the outline gap 43 of the depletion layer 39 to pass through the electric field directly below the gate electrode 29. Since it can be pushed to an external measurement sufficiently far so that the strength is weakened, the problem of dielectric breakdown due to electric field concentration of the gate oxide film 28 is eliminated.
- the depletion layer when the depletion layer is fully extended to the channel portion of the well, the depletion layer is ensured to have no free space so that the portion of the well not closed by the depletion layer does not remain.
- the depletion layer outline 39 extends the channel region 38 to the gate insulating film 28. spread.
- the coupling portion 45 is continuously formed in the length direction of the P + layer 23 as shown in FIG. 5C, from the drift layer 22 immediately below the gate oxide film 28 and the gate electrode 29. Since the space to the oxide film 28 is isolated, the outline 39 of the depletion layer is not pushed into the connection portion lower region 37 in the N ⁇ epitaxial layer 22 and extends to the gate oxide film 28.
- FIG. 5E is an explanatory diagram in the case where the coupling portion 45 that is a feature of the present invention is omitted from the third embodiment shown in FIG.
- the depletion layer is generally formed as shown by the outline 39 by a dotted line.
- the outlines 39 of the opposing depletion layers are formed in contact so that the well is completely closed (FIG. 5). (See (a)).
- the outline 39 of the depletion layer is the gate as shown by the circles c and d in FIG. 5 (e).
- a gap 43 (depicted by hatching in FIG. 5A) of the outline of the depletion layer in contact with the oxide film 28 is formed.
- the electric field may concentrate on the oxide film 28 via the gap 43 in the outline of the depletion layer, and dielectric breakdown may occur.
- the vertical SiC-MOSFET having the stripe cell pattern according to the present invention includes the coupling portion 36 of the P + layer 23 (second conductivity type region for protecting the gate oxide film) and Since the coupling portion 45 composed of the coupling portion 35 of the P ⁇ epitaxial layer 24 (base region) is provided across both ends of the opposing stripe cell region (in this example, the source region 27), the depletion layer outline 39 is As shown in FIG. 5D, the coupling portion 45 is bent so as to be farther away from the gate oxide film 28 than the example shown in FIG. For this reason, in the case of FIG.
- the gap 43 in the outline of the depletion layer has a longer distance to the gate oxide film 28 than in the case of FIG. 5E, the electric field concentration is relaxed, and the dielectric strength is improved.
- the coupling portion 45 since the coupling portion 45 is provided, it is possible to suppress the outline 39 of the depletion layer 39 from approaching the gate oxide film 28. This effect is achieved even if the coupling portion 45 is not provided continuously with the stripe cell region (in this example, the source region 27) or provided only in the gap 43 of the depletion layer outline.
- the gap 43 in the outline of the depletion layer formed by the coupling portion 45 so that the outline 39 of the depletion layer is in contact with the gate oxide film 28 is not provided as in the example in which the coupling portion 45 shown in FIG.
- the breakdown voltage can be improved because the dielectric breakdown due to the concentration of the electric field is not generated in the vicinity.
- the position of the coupling portion 45 is not directly above the outline gap 43 of the depletion layer 39, but the coupling portion 45 also allows the outline gap 43 of the depletion layer 39 to be directly below the gate electrode 29 in this structure. Since it can be pushed to an external measurement sufficiently far away so that the electric field strength is weakened, the problem of dielectric breakdown due to electric field concentration of the gate oxide film 28 is eliminated.
- Example 3 A method for manufacturing the element of Example 3 of the present invention will be described below.
- a SiC-MOSFET of the present invention having a specification of 1200 V and 25 A was manufactured by the same manufacturing process as in Example 1.
- An n-type SiC layer 22 containing about 1.8 ⁇ 10 16 cm ⁇ 3 of nitrogen is epitaxially grown by 10 ⁇ m on a surface inclined by 4 ° with respect to (000-1) as the crystallographic plane index of the n-type semiconductor substrate 21. .
- the stripe cell pattern is used.
- the P + layer 23 is arranged as shown in FIG. 4 in which the P base layer 24 and the P + layer 23 are coupled.
- the other steps are exactly the same as those in the first embodiment.
- the electrical characteristic evaluation results of the SiC-MOSFET designed with the stripe cell pattern of the present invention in FIG. 4 are shown as Example 3 in Table 1 of FIG. Although the on-resistance increases by about 10% with respect to the above-described embodiment, it can be seen that the on-resistance characteristics and the high breakdown voltage characteristics are sufficiently low with respect to a normal SiC-MOSFET.
- an n-type SiC semiconductor substrate 1 is prepared.
- the low-resistance SiC semiconductor 1 containing about 2 ⁇ 10 19 cm ⁇ 3 of nitrogen as an impurity is used.
- An n-type SiC layer 2 containing about 1.8 ⁇ 10 16 cm ⁇ 3 of nitrogen is epitaxially grown to a thickness of 10 ⁇ m on a plane inclined by 4 ° with respect to (000-1) as the crystallographic plane index of the n-type semiconductor substrate 1.
- a P + layer 3 having a width of 13 ⁇ m and a thickness of 0.5 ⁇ m is formed thereon by an epitaxial method.
- aluminum was used as impurity ions.
- the dose was set so that the impurity concentration was 1.0 * 10 18 cm ⁇ 3 .
- a part of the P + layers 3 is coupled to each other (see FIG. 3B2).
- a hexagonal cell pattern is used, but there is no problem with a quadrangular cell.
- the distance between the P + layers 3 that are not bonded is 2 ⁇ m (see FIG. 3A).
- a P base layer 4 is formed on the P + layer 3 and the n-type layer 2 to a thickness of 0.5 ⁇ m by an epitaxial growth method.
- the impurity at that time was aluminum, and the impurity concentration was set to 2.0 * 10 16 cm ⁇ 3 .
- nitrogen ions are selectively implanted as the N strike-back layer 5 so that a portion where the P base layer 4 and the P + layer 3 are connected remains and the gap of the electric field does not reach the gate oxide film 8. 7.
- a P + contact layer 6 is selectively formed in the P base layer 4.
- the concentration, thickness and width of the hitting layer 5 are the same as those in the first embodiment.
- activation annealing is performed.
- the heat treatment temperature and time are 1620 ° C. and 2 minutes.
- a gate oxide film 8 is formed to a thickness of 100 nm by thermal oxidation and annealed in the vicinity of 1000 ° C. in a hydrogen atmosphere.
- a polycrystalline silicon layer doped with phosphorus is formed as a gate electrode 9, patterned, a source electrode (not shown) is formed on the layers 7 and 6, and phosphorus glass is formed as an interlayer insulating film 10 to a thickness of 1.0 ⁇ m.
- the film was patterned and heat-treated, and aluminum 11 containing 1% silicon was formed on the surface with a thickness of 5 ⁇ m by sputtering.
- a film of nickel 12 was formed on the back surface of the device, heat-treated at 970 ° C., and then Ti / Ni / Au 13 was formed.
- the protective film 14 is added to the surface to complete the device.
- the measurement results of the electrical characteristics of the SiC-MOSFET thus produced are shown as Example 4 in Table 1 of FIG.
- the chip size is 3 mm square, the active area is 5.27 mm 2 , and the rated current is 25A.
- the on-resistance (RonA) is a sufficiently low value of 2.90 m ⁇ cm 2, and the initial device breakdown voltage is 1454 V, which is sufficiently good as a 1200 V device.
- the crystallographic plane index of the n-type semiconductor substrate 1 is an angle of 0 ° or more and 10 ° or less with respect to (000-1), for example, 0 °, 2 °, 8 ° or 10 °.
- a device was similarly formed on the surface, and when the device was evaluated, it was found that there was almost no change in characteristics.
- the crystallographic plane index of the n-type semiconductor substrate 1 is 10 ⁇ m of an n-type SiC layer 2 containing about 1.8 ⁇ 10 16 cm ⁇ 3 of nitrogen on a plane inclined by 4 ° with respect to (0001). Epitaxially grown. Other processes are exactly the same.
- Table 1 in FIG. 11 shows the electrical property evaluation results of the fabricated elements. Although the on-resistance increases by about 50% to 4.40 m ⁇ cm 2 with respect to Example 4, it can be seen that the on-resistance characteristics are sufficiently low for a normal SiC-MOSFET.
- the crystallographic plane index of the n-type semiconductor substrate 1 is the same on a surface inclined at an arbitrary angle of 0 ° or more and 10 ° or less with respect to (0001), for example, 0 °, 2 °, 8 °, or 10 °.
- the element evaluation was performed on the element formed and formed, the characteristics were hardly changed and the element was satisfactory.
- the switching loss evaluation of the SiC-MOSFETs prepared in Examples 1 to 4 was performed, as shown in FIG. 7, both the turn-on and turn-off losses were 60% or more with respect to the same rated Si-IGBT (1200V25A). It was confirmed that the reduction was achieved.
- the present invention can be applied to an IGBT using a semiconductor substrate having a conductivity type different from that of the MOSFET.
- the substrate 1 is a P + substrate, and the other configuration is similarly adopted, and is manufactured by the manufacturing method of FIG.
- the substrate 1 is a P + substrate.
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Abstract
Description
図13はその単位セルの断面図である。
この構造では、高濃度n型基板201上に低濃度n型ドリフト層202が堆積され、n型ドリフト層202の表面にイオン注入によって高濃度p型ゲート層231が形成され、さらにその上に低濃度p型層232が堆積されている。この低濃度p型層232の表面部分にはイオン注入によって選択的にn型ソース層205が形成され、ゲート酸化膜206を介してゲート電極207が、さらに層間絶縁膜208を介してソース電極209がそれぞれ形成され、チャネル領域211がゲート酸化膜206直下の低濃度p型堆積層232内に形成される。低濃度p型堆積層232を貫通してn型ドリフト層202に達するn型ベース層204が表面からのn型不純物のイオン注入による打ち返し層として選択的に形成されている。210はドレイン電極。 The above problem will be described in detail in another example of FIG. 13 related to the structure of FIG.
FIG. 13 is a cross-sectional view of the unit cell.
In this structure, a low-concentration n-
本発明のさらなる目的は、高電圧印加時においても、ゲート酸化膜が破壊したり、信頼性が劣化することなく、低オン抵抗特性を有する縦型SiC-MOSFETならびにIGBTおよびそれらの製造方法を提供することにある。 An object of the present invention is to provide a vertical high-voltage semiconductor device having a low on-resistance characteristic and a method for manufacturing the same without destroying a gate oxide film or deteriorating reliability even when a high voltage is applied. is there.
A further object of the present invention is to provide a vertical SiC-MOSFET having a low on-resistance characteristic and an IGBT and a method for manufacturing the same without destroying a gate oxide film or deteriorating reliability even when a high voltage is applied. There is to do.
(1) チャネルを構成する打ち返し層の不純物濃度が低く、厚さが薄い縦型高耐圧半導体装置において、空乏層がウェルのチャネル部分に広がりきったときに、空乏層によって閉じられていないウェルの部分が残らないように、空乏層の空き空間のない広がりを確保する手段を設ける。
これにより、ゲート酸化膜に対向するウェル部分は空乏層で完全に閉じられるので、可動電荷が閉じられていないウェル部分を介してゲート酸化膜まで到達することが無くなり、ゲート酸化膜に電界が集中することが無く、ゲート酸化膜の絶縁破壊が発生しない。換言すると、チャネルを構成する打ち返し層の不純物濃度が低く、厚さが薄い縦型高耐圧半導体装置において、空乏層がウェルのチャネル部分に広がりきったあとも、空乏層によって閉じられていないウェルの部分が残り、可動電荷がゲート酸化膜との界面付近に到達し、ゲート酸化膜に強い電界がかかり、絶縁破壊を引き起こすという問題を防止することができる。 To achieve the above objective,
(1) In a vertical type high breakdown voltage semiconductor device in which the impurity concentration of the striking layer constituting the channel is low and the thickness is small, when the depletion layer has spread over the channel portion of the well, the well layer not closed by the depletion layer Means are provided to ensure that the depletion layer has no open space so that no part remains.
As a result, the well portion facing the gate oxide film is completely closed by the depletion layer, so that the mobile charge does not reach the gate oxide film through the well portion that is not closed, and the electric field is concentrated on the gate oxide film. No breakdown occurs in the gate oxide film. In other words, in a vertical type high breakdown voltage semiconductor device in which the impurity concentration of the striking layer constituting the channel is low and thin, even after the depletion layer has spread over the channel portion of the well, the well layer that is not closed by the depletion layer It is possible to prevent the problem that the portion remains, the mobile charge reaches near the interface with the gate oxide film, a strong electric field is applied to the gate oxide film, and dielectric breakdown is caused.
ドリフト領域に発生する空乏層をこのドリフト領域に押し込めるように、ドリフト領域上にゲート酸化膜保護のための第2導電型領域およびベース領域からなる結合部を設ける。結合部は第2導電型領域およびベース領域のそれぞれの一部に一体に連設する。 (2) As a means for ensuring the expansion of the depletion layer (1) without a free space,
In order to push the depletion layer generated in the drift region into the drift region, a coupling portion including a second conductivity type region and a base region for protecting the gate oxide film is provided on the drift region. The coupling portion is integrally connected to a part of each of the second conductivity type region and the base region.
基板面に沿う方向の面内における(平面図示における)、
(a)相対向するすべてのソース領域の中心から最も遠く且つ等距離の点であって、且つ、
(b)ソース領域の中心から最も離れた端部から最も近く且つ等距離の点
を含む結合部を第2導電型領域およびベース領域のそれぞれの一部に一体に設ける。
結合部はソース領域の構成を基準にして構成する。セル電極(ソース電極)は、基板面に沿う面の外形形状が、ソース領域の前記面の外形形状と同形または相似形且つ縮小形の電極形状に形成される。特には、セル電極(ソース電極)の上記外形形状は、ソース領域の外形形状よりも少し小さい相似形且つ縮小形に形成されることが好ましい。 (3) As a means for ensuring the expansion of the depletion layer in (1) without a vacant space,
In a plane along the substrate surface (in the plan view),
(A) a point farthest and equidistant from the center of all opposing source regions, and
(B) A coupling portion including a point closest to and equidistant from the end portion farthest from the center of the source region is integrally provided in a part of each of the second conductivity type region and the base region.
The coupling portion is configured based on the configuration of the source region. The cell electrode (source electrode) is formed such that the outer shape of the surface along the substrate surface has the same shape as or similar to the outer shape of the surface of the source region. In particular, it is preferable that the outer shape of the cell electrode (source electrode) is formed in a similar and reduced shape that is slightly smaller than the outer shape of the source region.
基板面に沿う方向の面内における(平面図示したとき)、
(a)相対向するすべてのソース領域の中心から最も遠く且つ等距離の点であって、且つ、
(b)ソース領域の中心から最も離れた端部から最も近く且つ等距離の点を含む結合部を第2導電型領域およびベース領域それぞれの一部に一体に設ける。 (7) As a means for ensuring that the depletion layer has no open space so that the well portion not closed by the depletion layer does not remain when the depletion layer has fully spread in the channel portion of the well,
In a plane along the substrate surface (when the plan view is shown),
(A) a point farthest and equidistant from the center of all opposing source regions, and
(B) A coupling portion including a point closest to and equidistant from the end portion farthest from the center of the source region is integrally provided in a part of each of the second conductivity type region and the base region.
ソース領域7とコンタクト補助層6の上にソース電極(図示省略)を設ける。半導体基板1の裏面にドレイン電極(図示省略)を設ける。 (8) As a method for manufacturing a vertical high breakdown voltage semiconductor device, a first conductivity type (n-type)
A source electrode (not shown) is provided on the
結合部はソース領域の構成を基準にして構成する。セル電極(ソース電極)は、基板面に沿う面の外形形状が、ソース領域の前記面の外形形状と同形または相似形且つ縮小形の電極形状に形成される。特には、セル電極(ソース電極)の上記外形形状は、ソース領域の外形形状よりも少し小さい相似形且つ縮小形に形成されることが好ましい。 (9) In the manufacturing method of the above (8), when viewed from above, an end that is the farthest and equidistant point from the centers of all the opposing source regions and the farthest from the center of the source regions The coupling portion including the point closest to and equidistant from each other is integrally provided in a part of each of the second conductivity type region and the base region.
The coupling portion is configured based on the configuration of the source region. The cell electrode (source electrode) is formed such that the outer shape of the surface along the substrate surface is the same as or similar to the outer shape of the surface of the source region. In particular, it is preferable that the outer shape of the cell electrode (source electrode) is formed in a similar and reduced shape that is slightly smaller than the outer shape of the source region.
(10) 縦型高耐圧半導体装置は、第1導電型の半導体基板1と、前記半導体基板1上に形成された第1導電型で前記半導体基板1よりも低濃度な半導体層2と、半導体層2の表面に選択的に形成された高濃度の第2導電型半導体層3と、前記半導体層2ならびに前記半導体層3の上に、第2導電型で比較的低濃度の半導体層(ベース層)4と、その第2導電型ベース層4の表面層に選択的に形成された第1導電型ソース領域7と、表面から第2導電型ベース層4を貫通して第1導電型半導体層2層に達するように形成された第1導電型ウェル領域20と、第1導電型ソース領域7と第1導電型ウェル領域20とに挟まれた第2導電型ベース層4の表面露出部上の少なくとも一部にゲート絶縁膜を介して設けられたゲート電極層と、第1導電型ソース領域7とコンタクト補助層を介して第2導電型ベース層4に接続するソース電極7と、第1導電型の半導体基板1の裏面に設けられたドレイン電極を有する縦型高耐圧半導体装置であって、
平面図示したとき、相対向するすべてのソース領域の中心から最も遠く且つ等距離の点であって、且つ、ソース領域の中心から最も離れた端部から最も近く且つ等距離の点を結合部として含むように、ウェル領域20の代わりに半導体層3及びベース層4それぞれが結合されていることを特徴とする。 The specific configuration is as in the following example.
(10) A vertical high-voltage semiconductor device includes a
In the plan view, a point that is the farthest and equidistant point from the center of all the opposing source regions, and the point that is the nearest and equidistant from the end farthest from the center of the source region is used as a coupling portion. In other words, each of the
SiCとしては、バンドギャップが3.33eVの2H-SiC、2.23eVの3C-SiC、3.26eVの4H-SiC、2.93eVの6H-SiCが対象となる。このSiCのバンドギャップは、Siの1.12に比べ2.2eV以上と特定される。 (12) In the vertical high voltage semiconductor device according to (10) or (11), the semiconductor material is a semiconductor material having a band gap of 2.2 eV or more.
Examples of SiC include 2H—SiC with a band gap of 3.33 eV, 3C—SiC with 2.23 eV, 4H—SiC with 3.26 eV, and 6H—SiC with 2.93 eV. The band gap of SiC is specified as 2.2 eV or more compared to 1.12 of Si.
(14) 上記(13)記載の縦型高耐圧半導体装置において、上記第1導電型の半導体基板の結晶学的面指数は(000-1)に対して0度以上で10度以内の任意の角度に傾いた面であることを特徴とする。
(15) 上記(13)記載の縦型高耐圧半導体装置において、上記第1導電型の半導体基板の結晶学的面指数は(0001)に対して0度以上で10度以内の任意の角度に傾いた面であることを特徴とする。 (13) The vertical high voltage semiconductor device according to (10) or (11) above, wherein the semiconductor material is silicon carbide.
(14) In the vertical high breakdown voltage semiconductor device according to (13), the crystallographic plane index of the first conductivity type semiconductor substrate is an arbitrary value within a range of 0 degrees to 10 degrees with respect to (000-1). The surface is inclined at an angle.
(15) In the vertical high breakdown voltage semiconductor device according to (13), the crystallographic plane index of the semiconductor substrate of the first conductivity type is at an arbitrary angle within a range of 0 degrees to 10 degrees with respect to (0001). It is characterized by an inclined surface.
第1導電型(n型)半導体基板1と、前記第1導電型(n型)半導体基板1上に形成された第1導電型(n型)低不純物濃度の半導体層2と、前記第1導電型(n型)半導体層2に選択的に形成された第2導電型(p型)高不純物濃度の半導体層3と、前記第2導電型(p型)半導体層3の表面および露出する前記第1導電型(n型)半導体層2の表面に低濃度の第2導電型(p型)導電型ベース層4を形成し、その第2導電型(p型)導電型ベース層4の表面層に選択的に形成された第1導電型(n型)導電型ソース領域7と、表面から第2導電型(p型)導電型ベース層4を貫通して第1導電型(n型導電型)半導体層2層に達するように形成された第1導電型(n型導電型)ウェル領域20と、第1導電型(n型導電型)ソース領域7と第1導電型(n型導電型)ウェル領域20とに挟まれた第2導電型(p型導電型)ベース層4の表面にゲート絶縁膜8を介して形成された制御電極9とを備えた半導体装置であって、平面図示における、相対向するすべてのソース領域の中心から最も遠く且つ等距離の点であって、且つ、ソース領域の中心から最も離れた端部から最も近く且つ等距離の点を含む結合部を第2導電型領域およびベース領域に一体に設ける。
第2導電型(p型)半導体層3及び第2導電型(p型導電型)ベース層4はその一部をそれぞれ結合部の形状で延設している。
上記ソース領域7ならびにベース層4上にソース電極とのコンタクトが形成され、また、n型半導体基板1の裏面にドレイン電極が形成されている。 (16) A vertical high voltage semiconductor device according to the present invention includes:
A first conductivity type (n-type)
The second conductive type (p-type)
A contact with the source electrode is formed on the
6角形セルパターンの場合、結合部は、セルパターンを構成する第2導電型(p型)半導体層3及び第2導電型(p型)導電型ベース層4の角部からそれぞれ放射状(セルの中心からの放射線の延長上)に延びていて、上記空乏層のアウトラインの隙間を含む幅を有する。上記幅は、ゲート酸化膜に対向するウェル部分を空乏層で完全に閉じて、可動電荷が閉じられていないウェル部分を介してゲート酸化膜まで到達することが無くなり、ゲート酸化膜に電界が集中することが無くなるように機能する程度の長さとする。
(18) 上記(16)記載の縦型SiC-MOSFETにおいて、上記セルパターンをストライプ状としたことを特徴とする。
(19) 上記(16)記載の縦型SiC-MOSFETにおいて、上記結合部は、上記空乏層のアウトラインの隙間をすべて含むように構成したことを特徴とする。 (17) In the vertical SiC-MOSFET described in (16) above, the cell pattern is a hexagon.
In the case of the hexagonal cell pattern, the coupling portions are respectively radial (cells of the cell) from the corners of the second conductivity type (p-type)
(18) In the vertical SiC-MOSFET described in (16) above, the cell pattern has a stripe shape.
(19) In the vertical SiC-MOSFET described in (16), the coupling portion is configured to include all gaps in the outline of the depletion layer.
(21) 縦型高耐圧半導体装置の製造方法として、第1導電型(n型)SiC半導体基板1上にドリフト層となる第1導電型(n型)SiC層2をエピタキシャル成長させ、前記第1導電型(n型)SiC層2に所定領域イオン注入して第2導電型(P型)半導体層3を形成し、前記第1導電型(n型)SiC層2および前記第2導電型(P型)半導体層3上に第2導電型(P型)半導体のベース層4をエピタキシャル成長させ、前記第2導電型(P型)半導体層3および前記第2導電型(P型)半導体のベース層4の一部にイオン注入して前記層3および前記層4それぞれの結合部(つながった部分)が一部残るように第1導電型(N型)打ち返し層を形成し、第1導電型(N型)ソース層および第2導電型(P型)コンタクト層を前記第2導電型(P型半導体の)ベース層4内に選択的に形成する。 (20) The IGBT according to any one of (16) to (19) above, wherein the conductivity type of the semiconductor substrate in the vertical high-voltage semiconductor device is P-type.
(21) As a method for manufacturing a vertical type high breakdown voltage semiconductor device, a first conductivity type (n-type)
更に、本発明のベース層4をエピタキシャル成長法によって形成した場合、表面荒れがほとんどないくらいに平坦にできるため、表面のMOSFET部分の移動度が極めて大きくなり、その結果、オン抵抗をさらに小さくすることができる。 This is because the p-
Furthermore, when the
また、本発明の装置の製造方法によれば、ドリフト層となるn型半導体層2の上に、それぞれのソース領域に対向してそれぞれp+型半導体層3を形成し、前記p+型半導体層3の上に該層3に対向してp型導電型ベース層4を形成し、それぞれのp+型半導体層3相互間およびそれぞれのp型導電型ベース層4相互間に結合部分を一体に形成するようにしたので、それぞれの層を積層するときに結合部も同時に積層形成できる利点があり、簡単な積層手順でそれぞれの結合部分を形成できる。 Further, as exemplified by the (0001) plane system and the (000-1) plane system, the gate oxide film has a structure in which an electric field is not easily applied while maintaining a sufficient device breakdown voltage characteristic regardless of the crystal plane orientation of the substrate. In addition, a vertical SiC-MOSFET and an IGBT that have a low on-resistance, a large breakdown resistance, and capable of high-speed switching characteristics can be configured.
Further, according to the method for manufacturing the device of the present invention, the p +
バンドギャップ2.2eV以上の半導体材料とすることにより、バンドギャップの値が2.2eV以上のすべてのSiC、例えば、バンドギャップが3.33eVの2H-SiC、2.23eVの3C-SiC、3.26eVの4H-SiC、2.93eVの6H-SiCを対象とする。このSiCのバンドギャップは、Siの1.12に比べ2.2eV以上と特定することで識別できる。このような半導体材料を用いることにより、エネルギーギャップが広く熱的にも安定である特性を有することができる。特にそのオン抵抗が小さくできる。高電圧印加時においても、ゲート酸化膜が破壊したり、信頼性が劣化することなく低オン抵抗を有することができる。また、このような半導体材料を用いることにより、この材料特有の製造方法を適用することができる効果がある。 Since the
By using a semiconductor material having a band gap of 2.2 eV or more, all SiC having a band gap value of 2.2 eV or more, for example, 2H—SiC having a band gap of 3.33 eV, 3C—SiC having a band gap of 2.23 eV, 3C Targets are .26 eV 4H-SiC and 2.93 eV 6H-SiC. The band gap of SiC can be identified by specifying 2.2 eV or more compared to 1.12 of Si. By using such a semiconductor material, the energy gap can be wide and thermally stable. In particular, the on-resistance can be reduced. Even when a high voltage is applied, a low on-resistance can be obtained without breaking the gate oxide film or deteriorating reliability. Further, by using such a semiconductor material, there is an effect that a manufacturing method peculiar to this material can be applied.
なお、本実施例は縦型プレーナーゲートMOSFETとして、半導体材料として炭化ケイ素を用い、素子耐圧1200VのMOSFETを示した。 Hereinafter, the form of Example 1 of this invention is demonstrated with reference to FIG. FIG. 1A is a cross-sectional view taken along the line EF in FIG. 1B or FIG. 1C, and is a plan view in a state where the upper side is removed from the gate oxide film. FIG. 1B is a cross-sectional view taken along the line AB in FIG. FIG. 1C is a cross-sectional view taken along the line CD in FIG. FIG. 1D is a plan view of the gate electrode corresponding to FIG. FIG. 2 is a diagram illustrating the function of the coupling unit.
In the present embodiment, as the vertical planar gate MOSFET, a silicon carbide is used as a semiconductor material, and a MOSFET having an element withstand voltage of 1200 V is shown.
図1の縦型高耐圧半導体装置、特に縦型SiC-MOSFETは、n+型半導体基板1と、この半導体基板1上にエピタキシャル成長されたドリフト層となるn-型エピタキシャル層2と、このn-型エピタキシャル層2に選択的に形成されたp+型半導体層3と、このp+型半導体層3の表面にp-型半導体層4をエピタキシャル成長させ、そのp-型半導体層4の表面層に選択的にn+型ソース領域7を形成し、表面からp-型半導体層4を貫通してn型半導体層2層に達するようにn型ウェル領域20を形成し、n型ソース領域7とn型ウェル領域20とに挟まれたp型半導体層4の表面にゲート絶縁膜8を介してゲート電極9を形成して、構成される。n型ウェル領域20は、N打ち返し層5とn-型エピタキシャル層2からなり、チャネル領域18になる。領域6はベース領域へのコンタクト補助層となる。領域10は層間絶縁膜である。領域17はN-エピタキシャル層2中の連結部下部領域である。
第1導電型ソース領域7とコンタクト補助層6の上にソース電極(図示省略)が設けられる。半導体基板1の裏面にドレイン電極(図示省略)が設けられる。 Example 1 of FIG. 1 shows the case of a hexagonal cell pattern.
The vertical high breakdown voltage semiconductor device of FIG. 1, particularly the vertical SiC-MOSFET, includes an n +
A source electrode (not shown) is provided on the first conductivity
結合部46は、空乏層がウェルのチャネル部分に広がりきったときに、空乏層によって閉じられていないウェルの部分が残らないように、空乏層の空き空間のない広がりを確保する手段を構成し、基板面に沿う方向の面内における(平面図示における)、相対向するすべてのソース領域の中心から最も遠く且つ等距離の点であって、且つ、ソース領域の中心から最も離れた端部から最も近く且つ等距離の点(空乏層のアウトラインの隙間)を含み、P+層3(ゲート酸化膜保護のための第2導電型領域)の結合部16およびP-エピタキシャル層4(ベース領域)の結合部15からなり、それぞれの層と一体に設けられる。
結合部はソース領域の構成を基準にして構成する。セル電極(ソース電極)は、基板面に沿う面の外形形状が、ソース領域の前記面の外形形状と同形または相似形且つ縮小形の電極形状に形成される。特には、セル電極(ソース電極)の上記外形形状は、ソース領域の外形形状よりも少し小さい相似形且つ縮小形に形成されることが好ましい。
6角形セルパターンの場合、平面図示したときに、相対向するすべてのソース領域の中心から最も遠く且つ等距離であって、且つ、ソース領域の中心から最も離れた端部から最も近く且つ等距離の点(空乏層のアウトラインの隙間)を含むように、結合部を第2導電型領域3およびベース領域4に一体に設ける。 The
The
The coupling portion is configured based on the configuration of the source region. The cell electrode (source electrode) is formed such that the outer shape of the surface along the substrate surface is the same as or similar to the outer shape of the surface of the source region. In particular, it is preferable that the outer shape of the cell electrode (source electrode) is formed in a similar and reduced shape that is slightly smaller than the outer shape of the source region.
In the case of a hexagonal cell pattern, when viewed in plan, it is farthest and equidistant from the centers of all opposing source regions, and is nearest and equidistant from the end farthest from the center of the source regions. The coupling portion is integrally provided in the second
この例では、空乏層のアウトラインの隙間120は、図14(a)の平面図で略三角形、図14(b)の断面図で略平行で、全体的には略三角柱を呈する。なお、セルパターンが異なると空乏層のアウトラインの隙間の形状も異なる。
この空乏層のアウトラインの隙間120は、断面図では、図14(b)の断面図に示すように形成される。
このため、空乏層のアウトライン119とゲート電極109側のゲート絶縁膜108が接する○印の部分aと、n型ソース領域107とゲート電極109側のゲート絶縁膜108とが接する○印の部分bとの間に電界が集中し、ゲート酸化膜108が絶縁破壊することがある。
本発明の結合部は上記電界集中によるゲート酸化膜の破壊を防止することができる。 The center of the
In this example, the
The
Therefore, a circled portion a where the
The coupling portion of the present invention can prevent the gate oxide film from being destroyed by the electric field concentration.
図3(a)は、図3の左側列の工程を含み、P+層3の結合していない部分を製造する工程を示す断面図である。図3(b)は、図3の右側列の工程を含み、P+層3の結合している部分を製造する工程を示す断面図である。工程は、工程1(a1;b1):N-エピ(エピタキシャル層2)成長、工程2(a2;b2):P+層3インプラ(イオン注入)、工程3(a3;b3):P層4エピ成長(ベース領域4エピタキシャル成長)、工程4(a4;):N層5打ち返し(イオン注入)、工程5(a5;b5):N+層7(ソース領域)、P+層6(ベース領域4へのコンタクト補助層)形成、工程6(a6;b6):ゲート酸化膜8・ゲート電極9形成、工程7(a7;b7):層間絶縁膜10・電極12,13形成 からなる。 FIG. 3 shows a manufacturing method of the vertical planar gate MOSFET shown in the first embodiment of the present invention.
FIG. 3A is a cross-sectional view showing a process of manufacturing a portion where the P +
まず、n型SiC半導体基板1を用意する。ここでは、不純物として窒素を2x1019cm-3程度含む低抵抗SiC半導体1とした。前記n型半導体基板1の結晶学的面指数は(000-1)に対して4°傾いた面の上に窒素を1.8x1016cm-3程度含むn型SiC層2を10μmエピタキシャル成長させる。
工程2(a2;b2):
その層2上に幅13μmで深さ0.5μmのP+層3をイオン注入法で形成する。その際のイオンはアルミニウムを用いた。また不純物濃度は、1.0*1018cm-3となるようにドーズ量を設定した。その際、後で述べるように、P+層3の一部をたがいに結合するようにする(図1(c)参照)。すなわち、図1(b)に示すように、N打ち返し層5、Nウェル領域20を形成せずに、図1(c)に示すように、P+層3およびP層4をそれぞれつながった形状に連続して形成する(工程(b2)参照)。このつながった部分が後述する結合部になる。それ以外の部分は、その層2上に所定形状のP+層3をイオン注入法で選択的に形成する(工程(a2)参照)。 Step 1 (a1; b1):
First, an n-type
Step 2 (a2; b2):
A P +
工程3(a3;b3):
次に、Pベース層4をエピタキシャル成長法により0.5μm厚で前記P+層3ならびに前記n型層2上に形成する。その際の不純物はアルミニウムとし、不純物濃度は2.0*1016cm-3となるようにした。
工程4(a4):
その後、Pベース層4及びP+層3がつながった部分(結合部となる部分:b(3)工程参照)が一部残るように、窒素イオンが5.0*1016cm-3で深さ1.5μm、幅2.0μmになるように選択的に注入し、N打ち返し層5を形成する。 In this embodiment, a hexagonal cell pattern is used, but there is no problem even with a square cell pattern. Further, the distance between the P + layers 3 where they are not coupled (substantially the width of the N well 20) shown in FIG.
Step 3 (a3; b3):
Next, a
Step 4 (a4):
Thereafter, the nitrogen ions are deep at 5.0 * 10 16 cm −3 so that a part of the part where the
次に、イオン注入により、N+ソース層7、P+コンタクト層6をpベース層4内に選択的に形成する。
工程6(a6;b6):
その後活性化アニールを実施する。熱処理温度・時間は1620℃・2分である。その後、ゲート酸化膜8を100nmの厚さ熱酸化で形成し、水素雰囲気中にて1000℃でアニールする。リンがドープされた多結晶シリコン層をゲート電極9として形成し、パターニングする。
工程7(a7;b7):
その後、ゲート電極9およびN+ソース層7と層6に接して設けたソース電極(図示省略)の上に層間絶縁膜10としてリンガラスを1.0μm厚で成膜し、パターニングし、熱処理し、1%シリコンを含んだアルミニウム11を表面にスパッタ法にて厚さ5μmで成膜する。素子裏面にはニッケル12を成膜し970℃で熱処理後、Ti/Ni/Au13を成膜する。ニッケル成膜層およびTi/Ni/Au成膜層はドレイン電極を構成する。
最後に保護膜14を表面に付加して素子は完成する。
上記方法は、一連の手順を実行して所期の半導体素子を作成する限りにおいて、膜厚、温度、不純物濃度、添加剤の種類等のパラメータを適宜変更することができる。 Step 5 (a5; b5):
Next, an N +
Step 6 (a6; b6):
Thereafter, activation annealing is performed. The heat treatment temperature and time are 1620 ° C. and 2 minutes. Thereafter, a
Step 7 (a7; b7):
Thereafter, a phosphor glass is formed in a thickness of 1.0 μm as an
Finally, a
In the above method, parameters such as film thickness, temperature, impurity concentration, additive type, and the like can be appropriately changed as long as a desired semiconductor element is formed by executing a series of procedures.
チップサイズは3mm角であり、活性面積は5.27mm2であり、定格電流は25Aである。実施例1の場合、オン抵抗(RonA)は2.85mΩcm2と十分低い値を示し、初期の素子耐圧も1452Vと、1200V素子として十分良好な特性を示している。比較のために、前記Pベース層204及びP+層203をまったく結合させないようにして作成した従来例のSiC-MOSFETを測定したところ、オン抵抗は同等の2.8mΩcm2と十分低い値を示したがソース・ドレイン間に880V印加したところで、ゲート酸化膜が破壊してしまった。このことから本発明素子は十分な素子耐圧を維持しながら、極めて小さいオン抵抗を示していることが分かる。 The measurement results of the electrical characteristics of the SiC-MOSFET of the present invention thus prepared are shown in Table 1 of FIG. FIG. 11 is a table of characteristics of Example 1-5 of the present invention and SiC-MOSFET and Si-IGBT of the prior art.
The chip size is 3 mm square, the active area is 5.27 mm 2 , and the rated current is 25A. In the case of Example 1, the on-resistance (RonA) has a sufficiently low value of 2.85 mΩcm 2, and the initial device breakdown voltage is 1452 V, which is sufficiently good as a 1200 V device. For comparison, when a conventional SiC-MOSFET fabricated so that the
図6は、本発明の実施例1におけるSiC-MOSFETと、本発明の実施例1におけるSiC-MOSFETにおいてPベース層204相互及びP+層203相互を全く結合させないSiC-MOSFETの素子耐圧とN打ち返し層(P+層)幅を変えた時の実測結果である。横軸はP+層間隔(um)、縦軸は素子耐圧(v)。 FIG. 6 is a P + layer spacing-device breakdown voltage characteristic diagram of Example 1 of the present invention and a conventional SiC-MOSFET, and is a comparative evaluation result.
FIG. 6 shows the device breakdown voltage and N counterattack of the SiC-MOSFET in Example 1 of the present invention and the SiC-MOSFET in which the
P+層間隔-素子耐圧特性の実測結果を以下の表により例示する。
The actual measurement result of the P + layer spacing-element breakdown voltage characteristic is illustrated by the following table.
その結果、最大電流が素子定格の5倍である125A(Ip)を導通しても破壊せず、さらに15μsecでも破壊しないという十分な特性を示した。 FIG. 7 is a characteristic diagram of the measurement results of the load short-circuit withstand capability of the SiC-MOSFET in Example 1 of the present invention. In FIG. 7, the horizontal axis represents time (μs), and the vertical axis represents voltage (V) and current (A). In the characteristic diagram, a large amount of current flows at the ON position.
As a result, it showed sufficient characteristics that it does not break even when 125 A (Ip) whose maximum current is five times the element rating is conducted, and does not break even after 15 μsec.
さらにターンオフ耐量を評価したところ、ソース・ドレイン間電圧Vdsは1630Vにクランプされ(図8中のVdsclamp)、破壊することなく100A(定格電流の4倍)を150℃にてオフできることを確認した。 FIG. 8 is a characteristic diagram of a turn-off breakdown resistance evaluation result of the SiC-MOSFET in Example 1 of the present invention. In FIG. 8, the horizontal axis represents time (μs), and the vertical axis represents voltage (V) and current (A).
When the turn-off resistance was further evaluated, it was confirmed that the source-drain voltage Vds was clamped at 1630 V (Vdsclamp in FIG. 8), and 100 A (four times the rated current) could be turned off at 150 ° C. without destruction.
なお、前記n型半導体基板1の結晶学的面指数は(000-1)に対して0°以上10°以下の任意の角度、例えば0°、2°、8°、10°傾いた面の面上で同様に成膜し、作成した素子についても素子評価を行ったところ、特性の変化はほとんどなく良好であった。またGaNを用いて試作した場合にても同様に良好な効果を確認した。 From this, it can be said that the element of the present invention realizes a low on-resistance, and has an extremely large load short-circuit resistance and turn-off resistance. When the withstand voltage of the conventional SiC-MOSFET prepared for comparison was evaluated, the withstand voltage of the device was not sufficient, and the load short circuit withstand capability and the turn-off withstand capability were significantly inferior to those of the device of Example 1 of the present invention (FIG. 11). (See Table 1).
The crystallographic plane index of the n-
図9(a)および図9(b)は、VgsがON状態からOFF状態に切り替わったあとの状態を示している。Idsは25Aから0Aへ切り替わり、Vdsは0Vから600Vへ切り替わる。切り替わった後100ns程度で速やかに収束している。
図9の特性は半導体素子として耐圧および抵抗値に関し良好になっている。 FIG. 9 is a turn-off switching waveform diagram of the SiC-MOSFET in Example 1 of the present invention. FIG. 9A shows that the measured temperature is R.P. The characteristics of the drain-source voltage Vds, the gate-source voltage Vgs, and the drain-source current Ids at T (room temperature) are represented, the horizontal axis represents time, and the vertical axis represents voltage and current. FIG. 9B shows the characteristics of the drain-source voltage Vds, the gate-source voltage Vgs, and the drain-source current Ids at a measurement temperature of 200 ° C., where the horizontal axis represents time and the vertical axis represents voltage and current.
FIG. 9A and FIG. 9B show a state after Vgs is switched from the ON state to the OFF state. Ids switches from 25A to 0A, and Vds switches from 0V to 600V. It converges quickly in about 100ns after switching.
The characteristics shown in FIG. 9 are good in terms of breakdown voltage and resistance as a semiconductor element.
図10(a)は測定温度がR.T(室温)におけるドレイン-ソース電圧Vds、ゲート-ソース電圧Vgs、ドレイン-ソース電流Idsの特性を表し、横軸は時間、縦軸は電圧、電流を表す。図10(b)は測定温度が200℃におけるドレイン-ソース電圧Vds、ゲート-ソース電圧Vgs、ドレイン-ソース電流Idsの特性を表し、横軸は時間、縦軸は電圧、電流を表す。
図10(a)および図10(b)は、VgsがOFF状態からON状態に切り替わったあとの状態を示している。Idsは0Aから25Aへ切り替わり、Vdsは600Vから0Vへ切り替わる。切り替わった後100ns程度で速やかに収束している。
図10の特性は半導体素子として耐圧および抵抗値に関し良好になっている。 FIG. 10 is a turn-on switching waveform diagram of the SiC-MOSFET in Example 1 of the present invention.
FIG. 10 (a) shows that the measured temperature is R.P. The characteristics of the drain-source voltage Vds, the gate-source voltage Vgs, and the drain-source current Ids at T (room temperature) are represented, the horizontal axis represents time, and the vertical axis represents voltage and current. FIG. 10B shows the characteristics of the drain-source voltage Vds, the gate-source voltage Vgs, and the drain-source current Ids at a measurement temperature of 200 ° C., where the horizontal axis represents time and the vertical axis represents voltage and current.
FIG. 10A and FIG. 10B show a state after Vgs is switched from the OFF state to the ON state. Ids switches from 0A to 25A, and Vds switches from 600V to 0V. It converges quickly in about 100ns after switching.
The characteristics shown in FIG. 10 are good in terms of breakdown voltage and resistance as a semiconductor element.
作製した素子の電気特性評価結果を図11の第1表に実施例2として示す。オン抵抗は4.27mΩcm2と前記実施例に対し50%ほど増加するものの、通常のSiC-MOSFETに対しては十分低いオン抵抗特性を示していることがわかる。
なお、前記n型半導体基板201の結晶学的面指数は(0001)に対してストライプセルパターンで設計した0°以上10°以下の任意の角度、例えば0°、2°、8°、10°傾いた面の面上に同様に成膜し、作成した素子についても素子評価を行ったところ、特性の変化はほとんどなく良好であった。 A vertical SiC-MOSFET having a specification of 1200 V and 25 A was manufactured by the same manufacturing process as in Example 1. However, in this embodiment, the n-
The electrical property evaluation results of the fabricated elements are shown as Example 2 in Table 1 of FIG. Although the on-resistance is 4.27 mΩcm 2 which is about 50% higher than that of the above example, it can be seen that the on-resistance characteristic is sufficiently low for a normal SiC-MOSFET.
The crystallographic plane index of the n-
図5は、本発明の実施例3におけるSiC-MOSFETのウェル閉塞状態説明図である。図5(a)は図5(b)又は図5(c)のE-F平面図、図5(b)は図5(a)のA-B断面図、図5(c)は図5(a)のC―D断面図、図5(d)は図5(a)のG-H断面図、図5(e)は結合部無しの場合の図5(a)のG-H断面図である。 FIG. 4 is a diagram showing the arrangement of the P +
FIG. 5 is an explanatory diagram of the well closed state of the SiC-MOSFET in the third embodiment of the present invention. 5A is a plan view taken along the line EF of FIG. 5B or FIG. 5C, FIG. 5B is a cross-sectional view taken along the line AB of FIG. 5A, and FIG. 5A is a cross-sectional view taken along line CD, FIG. 5D is a cross-sectional view taken along line GH in FIG. 5A, and FIG. 5E is a cross-sectional view taken along line GH in FIG. FIG.
結合部45は、図4(c)におけるP-エピタキシャル層24の結合部35とP+層3の結合部36からなり、ゲート酸化膜28およびゲート電極29の直下に設けられている。42は単位セルパターンを表す。実用上は、このようなセルパターンが平面上に必要数配置される。 The n-
The
結合部はソース領域の構成を基準にして構成する。セル電極(ソース電極)は、基板面に沿う面の外形形状が、ソース領域の前記面の外形形状と同形または相似形且つ縮小形の電極形状に形成される。特には、セル電極(ソース電極)の上記外形形状は、ソース領域の外形形状よりも少し小さい相似形且つ縮小形に形成されることが好ましい。
ストライプセルパターンの場合、平面図示したときに、相対向するすべてのソース領域27の中心から最も遠く且つ等距離であって、且つ、ソース領域の中心から最も離れた端部から最も近く且つ等距離の点を含むように、結合部を第2導電型領域およびベース領域に一体に設ける。
なお、この実施例3では、結合部45の位置は空乏層39のアウトラインの隙間43の直上ではないが、結合部45はこの構造でも空乏層39のアウトラインの隙間43をゲート電極29直下から電界強度が弱まるように十分離れた外測へ押しやれるので、ゲート酸化膜28の電界集中による絶縁破壊の問題は無くなる。 The
The coupling portion is configured based on the configuration of the source region. The cell electrode (source electrode) is formed such that the outer shape of the surface along the substrate surface is the same as or similar to the outer shape of the surface of the source region. In particular, it is preferable that the outer shape of the cell electrode (source electrode) is formed in a similar and reduced shape that is slightly smaller than the outer shape of the source region.
In the case of the stripe cell pattern, when viewed in plan, it is farthest and equidistant from the centers of all the opposing
In the third embodiment, the position of the
空乏層によるウェル閉塞状態のとき、一般に点線でアウトライン39を示すように空乏層が形成される。対向するストライプセルの中心点間を直線(図5(a)参照)で結ぶ線上では、完全にウェルが閉塞するように、対向する互いの空乏層のアウトライン39は接して形成される(図5(a)参照)。しかし、対向するストライプセルの中心点間を線分G-Hのように結ぶ線上では、図5(e)に○印cおよび○印dで囲んで示すように、空乏層のアウトライン39がゲート酸化膜28に接する空乏層のアウトラインの隙間43(図5(a)では斜線で示す例示あり)ができてしまう。この結果、この空乏層のアウトラインの隙間43を介して酸化膜28に電界が集中して絶縁破壊が発生することがある。 Functions and effects of the
When the well is closed by the depletion layer, the depletion layer is generally formed as shown by the
前記実施例1と同様の製造工程にて1200V、25A仕様の本発明のSiC-MOSFETを作製した。前記n型半導体基板21の結晶学的面指数は(000-1)に対して4°傾いた面の上に窒素を1.8x1016cm-3程度含むn型SiC層22を10μmエピタキシャル成長させた。また本実施例3ではストライプセルパターンで設計した。そのため、P+層23の配置は図4に示すような構造でPベース層24及びP+層23を結合させている。その他の工程は実施例1の工程と全く同一である。 A method for manufacturing the element of Example 3 of the present invention will be described below.
A SiC-MOSFET of the present invention having a specification of 1200 V and 25 A was manufactured by the same manufacturing process as in Example 1. An n-
まず、n型SiC半導体基板1を用意する。ここでは、不純物として窒素を2x1019cm-3程度含む低抵抗SiC半導体1とした。前記n型半導体基板1の結晶学的面指数は(000-1)に対して4°傾いた面の上に窒素を1.8x1016cm-3程度含むn型SiC層2を10μmエピタキシャル成長させる。その上に幅13μmで厚さ0.5μmのP+層3をエピタキシャル法で形成する。その際の不純物イオンはアルミニウムを用いた。また不純物濃度は、1.0*1018cm-3となるようにドーズ量を設定した。その際、前記実施例1と同様、P+層3相互の一部をたがいに結合するようにする(図3(b2)参照)。 A method for manufacturing the element of Example 4 will be described with reference to FIG.
First, an n-type
作製した素子の電気特性評価結果を図11の表1に示す。オン抵抗は前記実施例4に対し4.40mΩcm2と、50%ほど増加するものの、通常のSiC-MOSFETに対しては十分低いオン抵抗特性を示していることがわかる。 In the same manufacturing process as in Example 4, a 1200 V25A specification MOSFET was manufactured. However, in this embodiment, the crystallographic plane index of the n-
Table 1 in FIG. 11 shows the electrical property evaluation results of the fabricated elements. Although the on-resistance increases by about 50% to 4.40 mΩcm 2 with respect to Example 4, it can be seen that the on-resistance characteristics are sufficiently low for a normal SiC-MOSFET.
また、実施例1~4で作成したSiC-MOSFETのスイッチング損失評価を行ったところ、図7に示すようにターンオン、ターンオフ損失とも、同一定格のSi-IGBT(1200V25A)に対し、60%以上もの低減が図られていることを確認した。
なお、実施例には示さなかったが本発明はMOSFETとは異なる導電型の半導体基板を用いたIGBTにも適用されることは自明である。
IGBTの場合は、図3において、基板1をP+基板とし、その他の構成を同じく採用した構成を有し、図3の製造方法により製造される。IGBTの場合は、実施例1から実施例5において、基板1をP+基板とした構成をとる。これにより、先に記載した所期の目的および効果を奏する。
Note that the crystallographic plane index of the n-
Further, when the switching loss evaluation of the SiC-MOSFETs prepared in Examples 1 to 4 was performed, as shown in FIG. 7, both the turn-on and turn-off losses were 60% or more with respect to the same rated Si-IGBT (1200V25A). It was confirmed that the reduction was achieved.
Although not shown in the embodiments, it is obvious that the present invention can be applied to an IGBT using a semiconductor substrate having a conductivity type different from that of the MOSFET.
In the case of the IGBT, in FIG. 3, the
2 N-エピタキシャル層(ドリフト層)
3 P+層(ゲート酸化膜保護のための第2導電型領域)
4 P-エピタキシャル層(ベース層)
5 N打ち返し層
6 (P+)ベース領域へのコンタクト補助層
7 (N+)ソース領域
8 ゲート酸化膜
9 ゲート電極(多結晶Si層)
10 層間絶縁膜
11 Al成膜層
12 Ni成膜層
13 Ti/Ni/Au成膜層
14 保護膜
15 (P-エピタキシャル層4)結合部
16 (P+層3)結合部
17 (N-エピタキシャル層2)結合部下部
18 チャネル領域
19 空乏層のアウトライン
20 Nウエル層
21 N+基板/P+基板
22 N-エピタキシャル層(ドリフト層)
23 P+層(ゲート酸化膜保護のための第2導電型領域)
24 P-エピタキシャル層
25 N打ち返し層
26 (P+)ベース領域へのコンタクト補助層
27 (N+)ソース領域
28 ゲート酸化膜
29 ゲート電極(多結晶Si層)
30 層間絶縁膜
31 Al成膜層
32 Ni成膜層
33 Ti/Ni/Au成膜層
34 保護膜
35 (P-エピタキシャル層4)結合部
36 (P+層3)結合部
37 (N-エピタキシャル層2)結合部下部
38 チャネル領域
39 空乏層のアウトライン
40 分割領域(ベース領域4の)
41 分割領域(P+層3の)
42 セル単位
43 空乏層のアウトラインの隙間
44 Nウェル層
45 結合部(ストライプセル)
46 結合部(6画セル)
1 N + substrate / P + substrate 2 N-epitaxial layer (drift layer)
3 P + layer (second conductivity type region for gate oxide protection)
4 P-epitaxial layer (base layer)
5 N strike back layer 6 (P +) Contact
DESCRIPTION OF
23 P + layer (second conductivity type region for protecting gate oxide film)
24 P-epitaxial layer 25 N return layer 26 (P +) contact
30 Interlayer insulation film 31 Al film formation layer 32 Ni film formation layer 33 Ti / Ni / Au film formation layer 34 Protective film 35 (P-epitaxial layer 4) coupling part 36 (P + layer 3) coupling part 37 (N-epitaxial layer 2) Coupling
41 Divided area (P + layer 3)
42
46 Joint (6 stroke cell)
Claims (8)
- 第1導電型の半導体基板と、前記半導体基板上に形成された第1導電型で前記半導体基板よりも低濃度な半導体層と、前記半導体層の表面に選択的に形成された高濃度の第2導電型半導体層と、前記第1導電型半導体層ならびに前記第2導電型半導体層の上に形成された第2導電型で比較的低濃度の半導体のベース層と、その第2導電型ベース層の表面層に選択的に形成された第1導電型ソース領域と、表面から前記第2導電型ベース層を貫通して前記第1導電型半導体層に達するように形成された第1導電型ウェル領域と、前記第1導電型ソース領域と前記第1導電型ウェル領域とに挟まれた前記第2導電型ベース層の表面露出部上の少なくとも一部にゲート絶縁膜を介して設けられたゲート電極層と、前記第1導電型ソース領域とコンタクト補助層を介して前記第2導電型ベース層に接続するソース電極と、前記第1導電型の半導体基板1の裏面に設けられたドレイン電極を有する縦型高耐圧半導体装置において、
平面図示したとき、相対向するすべての前記ソース領域の中心から最も遠く且つ等距離の点であって、且つ、前記ソース領域の中心から最も離れた端部から最も近く且つ等距離の点を結合部として含むように、前記ウェル領域の代わりに前記高濃度の第2導電型半導体層及び前記第2導電型ベース層がその一部において結合されていることを特徴とする縦型高耐圧半導体装置。 A first conductivity type semiconductor substrate; a first conductivity type semiconductor layer formed on the semiconductor substrate and having a lower concentration than the semiconductor substrate; and a high concentration first layer selectively formed on the surface of the semiconductor layer. A second conductivity type semiconductor layer; a second conductivity type relatively low-concentration semiconductor base layer formed on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; and a second conductivity type base thereof A first conductivity type source region selectively formed on a surface layer of the layer, and a first conductivity type formed so as to penetrate the second conductivity type base layer from the surface to reach the first conductivity type semiconductor layer Provided at least partially on the surface exposed portion of the second conductivity type base layer sandwiched between the well region, the first conductivity type source region, and the first conductivity type well region via a gate insulating film A gate electrode layer, and a first conductive type source region and a contour In the vertical high-voltage semiconductor device having a source electrode through a preparative auxiliary layer connected to the second conductivity type base layer, a drain electrode provided on the back surface of the semiconductor substrate 1 of the first conductivity type,
When viewed from above, the points that are farthest and equidistant from the centers of all of the opposing source regions and that are closest and equidistant from the end farthest from the center of the source regions A vertical type high withstand voltage semiconductor device characterized in that, instead of the well region, the high-concentration second conductive type semiconductor layer and the second conductive type base layer are coupled in part thereof so as to be included as a part . - 第1導電型の半導体基板と、前記半導体基板上に形成された第1導電型で前記半導体基板よりも低濃度な半導体層がエピタキシャル成長で形成され、前記半導体層の表面に選択的に高濃度の第2導電型半導体層がイオン注入法で形成され、前記第1導電型半導体層ならびに前記第2導電型半導体層の上に、第2導電型で比較的低濃度のベース層がエピタキシャル成長法で形成され、その第2導電型ベース層の表面層に選択的に第1導電型ソース領域が形成され、表面から前記第2導電型ベース層を貫通して前記第1導電型半導体層に達するように第1導電型ウェル領域がイオン注入法で形成されたことを特徴とする請求項1記載の縦型高耐圧半導体装置。 A semiconductor substrate having a first conductivity type and a first conductivity type semiconductor layer having a lower concentration than the semiconductor substrate formed on the semiconductor substrate are formed by epitaxial growth, and a selectively high concentration is formed on the surface of the semiconductor layer. A second conductivity type semiconductor layer is formed by ion implantation, and a second conductivity type and a relatively low concentration base layer is formed by epitaxial growth on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. The first conductivity type source region is selectively formed on the surface layer of the second conductivity type base layer, and penetrates the second conductivity type base layer from the surface to reach the first conductivity type semiconductor layer. 2. The vertical high voltage semiconductor device according to claim 1, wherein the first conductivity type well region is formed by an ion implantation method.
- 前記半導体材料がバンドギャップ2.2eV以上の半導体材料であることを特徴とする請求項1又は2記載の縦型高耐圧半導体装置。 3. A vertical high voltage semiconductor device according to claim 1, wherein the semiconductor material is a semiconductor material having a band gap of 2.2 eV or more.
- 前記半導体材料が炭化珪素であることを特徴とする請求項1又は2記載の縦型高耐圧半導体装置。 3. A vertical high voltage semiconductor device according to claim 1, wherein the semiconductor material is silicon carbide.
- 前記第1導電型の半導体基板の結晶学的面指数が(000-1)に対して0度以上で10度以内の任意の角度に傾いた面であることを特徴とする請求項4記載の縦型高耐圧半導体装置。 The crystallographic plane index of the semiconductor substrate of the first conductivity type is a plane inclined at an arbitrary angle within a range of 0 degrees to 10 degrees with respect to (000-1). Vertical high-voltage semiconductor device.
- 前記第1導電型の半導体基板の結晶学的面指数が(0001)に対して0度以上で10度以内の任意の角度に傾いた面であることを特徴とする請求項4記載の縦型高耐圧半導体装置。 5. The vertical type according to claim 4, wherein the first conductivity type semiconductor substrate has a crystallographic plane index inclined at an arbitrary angle of not less than 0 degrees and not more than 10 degrees with respect to (0001). High voltage semiconductor device.
- 第1導電型SiC半導体基板上にドリフト層となる第1導電型SiC層をエピタキシャル成長させ、前記第1導電型SiC層に所定領域イオン注入して第2導電型半導体層を形成し、前記第1導電型SiC層および前記第2導電型半導体層上に第2導電型半導体のベース層をエピタキシャル成長させ、前記第2導電型半導体層および前記第2導電型半導体のベース層の一部にイオン注入して前記第2導電型半導体層および前記第2導電型半導体のベース層それぞれの結合部が一部残るように第1導電型打ち返し層を形成し、第1導電型ソース層のソース領域および第2導電型コンタクト層を前記第2導電型ベース層内に選択的に形成することを特徴とする縦型高耐圧半導体装置の製造方法。 A first conductivity type SiC layer serving as a drift layer is epitaxially grown on the first conductivity type SiC semiconductor substrate, a predetermined region ion is implanted into the first conductivity type SiC layer to form a second conductivity type semiconductor layer, and the first conductivity type SiC layer is formed. A base layer of a second conductivity type semiconductor is epitaxially grown on the conductivity type SiC layer and the second conductivity type semiconductor layer, and ions are implanted into a part of the second conductivity type semiconductor layer and the base layer of the second conductivity type semiconductor. Forming a first conductivity-type striking layer so that a part of the coupling portion between each of the second conductivity-type semiconductor layer and the base layer of the second conductivity-type semiconductor remains, and the source region of the first conductivity-type source layer and the second region A method of manufacturing a vertical type high breakdown voltage semiconductor device, wherein a conductive contact layer is selectively formed in the second conductive type base layer.
- 平面図示したとき、相対向するすべての前記ソース領域の中心から最も遠く且つ等距離の点であって、且つ、前記ソース領域の中心から最も離れた端部から最も近く且つ等距離の点を含む結合部を第2導電型半導体層およびベース層それぞれに一体に設けることを特徴とする請求項7記載の縦型高耐圧半導体装置の製造方法。
When viewed in plan, includes points that are farthest and equidistant from the centers of all of the opposing source regions and that are closest and equidistant from the end farthest from the center of the source regions 8. The method of manufacturing a vertical type high withstand voltage semiconductor device according to claim 7, wherein the coupling portion is provided integrally with each of the second conductive type semiconductor layer and the base layer.
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JP2015191923A (en) * | 2014-03-27 | 2015-11-02 | 住友電気工業株式会社 | Silicon carbide semiconductor device and manufacturing method of the same |
JP2016058530A (en) * | 2014-09-09 | 2016-04-21 | 住友電気工業株式会社 | Silicon carbide semiconductor device manufacturing method |
JP2019517150A (en) * | 2016-05-23 | 2019-06-20 | ゼネラル・エレクトリック・カンパニイ | Electric field shielding in silicon carbide metal oxide semiconductor (MOS) device cells using body region extensions |
JP2019517149A (en) * | 2016-05-23 | 2019-06-20 | ゼネラル・エレクトリック・カンパニイ | Electric field shielding in silicon carbide metal oxide semiconductor (MOS) device cells using channel region extensions |
JP7102048B2 (en) | 2016-05-23 | 2022-07-19 | ゼネラル・エレクトリック・カンパニイ | Electric Field Shield in Silicon Carbide Metal Oxide Semiconductor (MOS) Device Cell with Channel Region Expansion |
JP2020119939A (en) * | 2019-01-21 | 2020-08-06 | 株式会社デンソー | Semiconductor device |
JP7180402B2 (en) | 2019-01-21 | 2022-11-30 | 株式会社デンソー | semiconductor equipment |
JP2022537452A (en) * | 2019-06-21 | 2022-08-25 | ウルフスピード インコーポレイテッド | Device design for short circuit protection of transistors |
JP7362790B2 (en) | 2019-06-21 | 2023-10-17 | ウルフスピード インコーポレイテッド | Device design for transistor short circuit protection |
Also Published As
Publication number | Publication date |
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DE112013002178T5 (en) | 2014-12-31 |
US20150076521A1 (en) | 2015-03-19 |
CN104303312B (en) | 2018-03-20 |
CN104303312A (en) | 2015-01-21 |
US9362392B2 (en) | 2016-06-07 |
JPWO2013161420A1 (en) | 2015-12-24 |
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