WO2013140713A1 - Image display device drive method, image display device, and image display system - Google Patents

Abstract

An objective of the present invention is to stably generate electricity discharges. To this end, provided is an image display device drive method wherein: a field is generated comprising a plurality of image display subfields, a y-coordinate detection subfield, and an x-coordinate detection subfield, and either the y-coordinate detection subfield or the x-coordinate detection subfield is generated at the end of the field. The image display subfield further comprises a preservation period in which a rising oblique waveform voltage, which rises to a first voltage after the generation of a preservation pulse, is applied to a scanning electrode. Either the y-coordinate detection subfield or the x-coordinate detection subfield which is generated at the end of the field further comprises a deletion period in which a rising oblique waveform voltage, which rises to a second voltage which is greater than the first voltage, and a falling oblique waveform voltage, are applied to the scanning electrode.

Description

Image display device driving method, image display device, and image display system

The present invention relates to a driving method of an image display apparatus that displays an image in an image display area by combining binary control of light emission and non-light emission in a plurality of light emitting elements constituting a pixel, an image display apparatus, and an image using a light pen. The present invention relates to an image display system capable of handwritten input of characters and drawings on a display device.

A plasma display panel (hereinafter abbreviated as “panel”) is a typical image display device that displays an image in an image display area by combining binary control of light emission and non-light emission in each of a plurality of light emitting elements constituting a pixel. There is).

In the panel, a large number of discharge cells, which are light-emitting elements constituting pixels, are formed between a front substrate and a rear substrate that are arranged to face each other.

In the front substrate, a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate. The back substrate has a plurality of parallel data electrodes formed on a glass substrate on the back side.

Each discharge cell is coated with one of red (R), green (G), and blue (B) phosphors, and a discharge gas is enclosed therein. In each discharge cell, an ultraviolet ray is generated by causing a gas discharge, and the phosphor is excited to emit light by the ultraviolet ray.

A subfield method is generally used as a method of displaying an image in an image display area of a panel by combining binary control of light emission and non-light emission in a light emitting element.

In the subfield method, one field is divided into a plurality of subfields having different emission luminances. In each discharge cell, light emission / non-light emission of each subfield is controlled by a combination according to the gradation value to be displayed. As a result, each discharge cell emits light with brightness corresponding to the gradation value to be displayed, and a color image composed of various combinations of gradation values is displayed in the image display area of the panel.

Some of such image display apparatuses have a function of allowing handwriting input of characters and drawings on a panel using a pointing device called “light pen”.

In order to realize a handwriting input function using a light pen, a technique for detecting the position of the light pen in an image display area is disclosed. Hereinafter, the coordinates representing the position of the light pen in the image display area are referred to as “position coordinates”.

For example, in the plasma display device described in Patent Document 1, an abscissa detection subfield for displaying an abscissa detection pattern is provided in one field. Then, the light emission of this abscissa detection subfield is detected by the light pen, and the position (abscissa) of the light pen is detected based on the timing at which the light emission is detected.

In the plasma display device described in Patent Document 2, a position detection period for generating a light signal for detecting position coordinates is provided in one field only when detecting the position coordinates of the light pen. Then, this light signal is detected by the light pen, and the position coordinates of the light pen are detected based on the timing at which the light signal is detected.

JP 50-108838 A JP 2001-318765 A

An image display device according to the present disclosure includes an image display unit having a plurality of scan electrodes, sustain electrodes, and a plurality of data electrodes, and a drive circuit configured to form one field by a plurality of subfields and drive the image display unit. . In this image display device, the drive circuit generates a field having an image display subfield, a y-coordinate detection subfield, and an x-coordinate detection subfield, and the y-coordinate detection subfield or the x-coordinate detection subfield is set in the field. It happens last. In the sustain period of the image display subfield, the drive circuit applies an upward ramp waveform voltage that rises to the first voltage after alternately applying a sustain pulse to the scan electrode and the sustain electrode, to the scan electrode. In addition, the driving circuit scans an up-slope waveform voltage and a down-slope waveform voltage that rise to a second voltage higher than the first voltage in the y-coordinate detection subfield or the x-coordinate detection subfield generated at the end of the field. An erasing period to be applied to the electrode is provided.

This makes it possible to generate a stable discharge and detect the position coordinates of the light pen with high accuracy.

An image display system according to the present disclosure includes the above-described image display device, a light pen, a coordinate calculation circuit, and a drawing circuit. The light pen has a light receiving element, and receives light emission generated in the image display unit in the y coordinate detection subfield and light emission generated in the image display unit in the x coordinate detection subfield, and outputs a light reception signal. The coordinate calculation circuit, based on the light reception signal, coordinates indicating the position of light emission received by the light pen in the light emission generated in the image display unit in the y coordinate detection subfield, and light emission generated in the image display unit in the x coordinate detection subfield. The coordinates representing the light emission position received by the light pen are calculated. The drawing circuit creates a drawing signal for displaying an image based on the coordinates calculated by the coordinate calculation circuit on the image display unit. Then, the image display device displays an image based on the drawing signal on the image display unit.

This makes it possible to generate a stable discharge and detect the position coordinates of the light pen with high accuracy.

FIG. 1 is an exploded perspective view showing an example of the structure of a panel used in the plasma display device in accordance with the exemplary embodiment of the present invention. FIG. 2 is a diagram showing an example of the electrode arrangement of the panel used in the plasma display device in accordance with the exemplary embodiment of the present invention. FIG. 3 is a diagram schematically showing an example of a drive voltage waveform applied to each electrode of the panel in the subfields SF1 to SF3 of the image display subfield in the embodiment of the present invention. FIG. 4 is a diagram schematically showing an example of a drive voltage waveform applied to each electrode of the panel in the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx in the embodiment of the present invention. is there. FIG. 5 is a diagram schematically showing an example of a circuit block and a plasma display system constituting the plasma display device in the embodiment of the present invention. FIG. 6 is a circuit diagram schematically showing a configuration example of the scan electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention. FIG. 7 is a circuit diagram schematically showing a configuration example of the sustain electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention. FIG. 8 is a circuit diagram schematically showing a configuration example of the data electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention. FIG. 9 is a diagram schematically showing an example of the operation when detecting the position coordinates of the light pen in the plasma display system according to the embodiment of the present invention. FIG. 10 is a diagram schematically showing an example of a drive voltage waveform when detecting the position coordinates of the light pen in the plasma display system according to the embodiment of the present invention. FIG. 11 is a diagram schematically showing an example of an operation when performing handwriting input with a light pen in the plasma display system according to the embodiment of the present invention.

Hereinafter, an image display device and an image display system according to embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a plasma display device having a plasma display panel and a plasma display system will be described as an example of an image display device and an image display system.

(Embodiment)
FIG. 1 is an exploded perspective view showing an example of the structure of a panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.

A plurality of display electrode pairs 14 each including a scanning electrode 12 and a sustaining electrode 13 are formed on a glass front substrate 11. A dielectric layer 15 is formed so as to cover the display electrode pair 14, and a protective layer 16 is formed on the dielectric layer 15. The front substrate 11 serves as an image display surface on which an image is displayed.

A plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is further formed thereon. The phosphor layer 25R that emits red (R), the phosphor layer 25G that emits green (G), and the phosphor layer that emits blue (B) are formed on the side surfaces of the barrier ribs 24 and the surface of the dielectric layer 23. 25B is provided. Hereinafter, the phosphor layer 25R, the phosphor layer 25G, and the phosphor layer 25B are collectively referred to as a phosphor layer 25.

The front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 intersect each other with a minute space therebetween, and a discharge space is provided in the gap between the front substrate 11 and the rear substrate 21. . And the outer peripheral part is sealed with sealing materials, such as glass frit. For example, a mixed gas of neon and xenon is sealed in the discharge space as a discharge gas.

The discharge space is partitioned into a plurality of sections by the barrier ribs 24, and discharge cells, which are light-emitting elements constituting the pixels, are formed at the intersections between the display electrode pairs 14 and the data electrodes 22.

Then, discharge is generated in these discharge cells, and the phosphor layer 25 emits light (discharge cells are turned on), thereby displaying a color image on the panel 10.

In the panel 10, one pixel is composed of three consecutive discharge cells arranged in the direction in which the display electrode pair 14 extends. The three discharge cells are a discharge cell having a phosphor layer 25R and emitting red (R) light (hereinafter referred to as “red discharge cell” or “red pixel”), and a phosphor layer 25G. Discharge cells (hereinafter referred to as “green discharge cells” or “green pixels”) having a green color (G), and discharge cells (hereinafter referred to as “green pixels”) having a phosphor layer 25B. , “Blue discharge cells” or “blue pixels”).

Note that the structure of the panel 10 is not limited to the above-described structure, and may be, for example, provided with a stripe-shaped partition wall.

FIG. 2 is a diagram showing an example of the electrode arrangement of the panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.

In the panel 10, n scan electrodes SC1 to SCn (scan electrode 12 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 13 in FIG. 1) extended in the first direction are arranged. The m data electrodes D1 to Dm (data electrode 22 in FIG. 1) extended in the second direction intersecting the first direction are arranged.

Hereinafter, the first direction is referred to as a row direction (or horizontal direction or line direction), and the second direction is referred to as a column direction (or vertical direction).

One discharge cell as a light emitting element is formed in a region where a pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects with one data electrode Dj (j = 1 to m). . In other words, m discharge cells are formed on one pair of display electrodes 14 and m / 3 pixels are formed. Then, m × n discharge cells are formed in the discharge space, and an area where m × n discharge cells are formed becomes an image display area of the panel 10. For example, in a panel having 1920 × 1080 pixels, m = 1920 × 3 = 5760 and n = 1080.

For example, a red phosphor is applied as a phosphor layer 25R to a discharge cell having a data electrode Dp (p = 3 × q−2: q is a positive integer of m / 3 or less). It becomes a red discharge cell. The discharge cell having the data electrode Dp + 1 is coated with a green phosphor as the phosphor layer 25G, and this discharge cell becomes a green discharge cell. A blue phosphor is applied as a phosphor layer 25B to the discharge cell having the data electrode Dp + 2, and this discharge cell becomes a blue discharge cell. A red discharge cell, a green discharge cell, and a blue discharge cell adjacent to each other constitute a set to constitute one pixel.

Next, driving voltage waveforms generated in the plasma display device according to the present embodiment will be described with reference to FIGS.

In this embodiment, one field includes a plurality of image display subfields for displaying an image on the panel 10, a timing detection subfield SFo, a y coordinate detection subfield SFy, and an x coordinate detection subfield SFx. Hereinafter, the image display subfield is also simply referred to as a subfield.

Each image display subfield has an initialization period, an address period, and a sustain period.

In the initialization period, initialization discharge is generated in each discharge cell, and wall charges necessary for the subsequent address operation are formed in the discharge cell. In addition, priming particles (charged particles that assist the generation of discharge) necessary for the address operation are generated in the discharge cell. In the address period, an address discharge is generated in the discharge cells that should emit light. In the sustain period, sustain pulses are alternately applied to the scan electrodes and the sustain electrodes, and a sustain discharge is generated in the discharge cells that have generated the address discharge.

The initialization operation in the initialization period includes “forced initialization operation” and “selective initialization operation”, and generated drive voltage waveforms are different from each other. In the forced initializing operation, an initializing discharge is forcibly generated in the discharge cells regardless of the presence or absence of discharge in the immediately preceding subfield. In the selective initializing operation, initializing discharge is selectively generated only in the discharge cells that have generated address discharge in the address period of the immediately preceding subfield.

In the present embodiment, among the plurality of subfields included in one field, the first subfield (for example, subfield SF1) is set as a subfield (forced initialization subfield) for performing a forced initialization operation, and other subfields are included. An example will be described in which a field (for example, a subfield after subfield SF2) is used as a subfield (selective initialization subfield) for performing a selective initialization operation.

Also, in the image display subfield, a luminance weight is set for each subfield. In the present embodiment, as an example, one field has eight subfields (subfields SF1 to SF8), and each subfield has a luminance of (1, 34, 21, 13, 8, 5, 3, 2). An example of setting a weight is given.

The position of the light pen in the image display area is represented by the x coordinate and the y coordinate. The x-coordinate detection subfield SFx and the y-coordinate detection subfield SFy are subfields for detecting the x-coordinate and y-coordinate of the position (position coordinate) of the light pen in the image display area.

The light pen is provided in the plasma display system, and is used by a user to input characters and drawings on the panel by handwriting. Details of the light pen will be described later.

In the plasma display system in this embodiment, wireless communication is performed between the light pen and the plasma display device. The light pen calculates the position coordinates of the light pen inside the light pen, and transmits data of the calculated position coordinates from the light pen to the plasma display device by wireless communication.

When calculating the position coordinates of the light pen inside the light pen, it is necessary for the light pen to accurately grasp the timing at which the y coordinate detection subfield SFy and the x coordinate detection subfield SFx occur in the plasma display device. .

The timing detection subfield SFo of the present embodiment is for enabling the light pen itself to generate a signal (coordinate reference signal) serving as a reference for detecting position coordinates with high accuracy.

In this embodiment, in one field, a plurality of image display subfields (for example, subfields SF1 to SF8), a timing detection subfield SFo, a y coordinate detection subfield SFy, and an x coordinate detection subfield SFx are arranged in this order. An example in which each subfield occurs will be described, but the generation order of each subfield is not limited to this order.

Also, the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx are not necessarily provided in each field. For example, the timing detection subfield SFo, the y-coordinate detection subfield SFy, and the x-coordinate detection subfield SFx may be generated at a rate of once per a plurality of fields in accordance with the video signal, the usage state of the plasma display device, and the like. .

FIG. 3 schematically shows an example of a drive voltage waveform applied to each electrode of panel 10 in subfields SF1 to SF3 of the image display subfield in the embodiment of the present invention.

FIG. 3 shows sustain electrodes SU1 to SUn, scan electrode SC1 that performs the address operation first in the address period, scan electrode SCn that performs the address operation last in the address period (for example, scan electrode SC1080), and data electrode D1 to data electrode. The drive voltage waveform applied to each of Dm (for example, data electrode D5760) is shown. Scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected based on image data (data indicating light emission / non-light emission for each subfield) from among the electrodes.

It should be noted that each subfield after subfield SF3 generates a drive voltage waveform substantially similar to that of subfield SF2, except for the number of sustain pulses.

First, the subfield SF1, which is a forced initialization subfield, will be described. Here, the initialization period Pia1 of the subfield SF1 is divided into four periods of a first period Pi1, a second period Pi2, a third period Pi3, and a fourth period Pi4, and each period will be described.

In the first period Pi1 of the initialization period Pia1 of the subfield SF1 in which the forced initialization operation is performed, the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn, and the voltage 0 (V) is applied to the data electrodes D1 to Dm. A high impedance state is set later.

A scan waveform SC1 to SCn is applied with voltage Vi1 after voltage 0 (V) is applied, and a ramp waveform voltage (hereinafter referred to as “upward ramp waveform voltage”) that gradually rises from voltage Vi1 to voltage Vi2. Apply.

The voltage Vi1 is set to a voltage lower than the discharge start voltage for the sustain electrodes SU1 to SUn, and the voltage Vi2 is set to a voltage exceeding the discharge start voltage for the sustain electrodes SU1 to SUn.

While the rising ramp waveform voltage rises, it is weak between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn, and between the scan electrodes SC1 to SCn and the data electrodes D1 to Dm, respectively. Initializing discharge is generated continuously.

Then, negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Furthermore, priming particles that assist the generation of the subsequent discharge are generated in the discharge cell. The wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

Since the data electrodes D1 to Dm are in a high impedance state after the voltage 0 (V) is applied, as the voltage applied to the scan electrodes SC1 to SCn rises, the voltage of the data electrodes D1 to Dm also increases. It gradually rises from 0 (V) in the positive direction.

Thus, discharge between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn occurs before discharge between scan electrodes SC1 to SCn and data electrodes D1 to Dm. As a result, the initialization discharge is stably generated. This is due to the following reason.

The protective layer 16 is formed of a material mainly composed of magnesium oxide (MgO) having a large secondary electron emission coefficient and excellent durability in order to lower the discharge start voltage in the discharge cell. On the other hand, the phosphor layer 25 has a smaller secondary electron emission coefficient than the protective layer 16.

Therefore, discharge between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, which are relatively likely to generate discharge, is first generated, and scan electrodes SC1 to SCn and data electrodes are generated using priming particles generated by the discharge. By generating the discharge between D1 and Dm, the initialization discharge can be generated stably.

When the voltage applied to scan electrodes SC1 to SCn reaches voltage Vi2, the voltage of scan electrodes SC1 to SCn is once lowered to voltage Vi3 lower than voltage Vi2, and then lowered to voltage 0 (V). The voltage Vi3 is set to a voltage lower than the voltage Vi2 and lower than the discharge start voltage with respect to the sustain electrodes SU1 to SUn. Although an example in which the voltage Vi3 is about 200 (V) is shown in this embodiment, the voltage Vi3 may be a voltage that does not cause discharge in the discharge cells. Further, the voltage may be sharply decreased from the voltage Vi2 to the voltage 0 (V).

In the second period Pi2 of the initialization period Pia1 of the subfield SF1, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the positive voltage Ve is applied to the sustain electrodes SU1 to SUn.

As shown in FIG. 3, the sustain electrodes SU1 to SUn may be in a high impedance state after the voltage Ve is applied. For example, the voltage Ve may be kept applied to the sustain electrodes SU1 to SUn.

The scan electrodes SC1 to SCn have a ramp waveform voltage that gradually falls from a voltage that is less than the discharge start voltage (eg, voltage 0 (V)) to a negative voltage Vi4 (hereinafter also simply referred to as “down ramp waveform voltage”). Is applied. Voltage Vi4 is set to a voltage exceeding the discharge start voltage with respect to sustain electrodes SU1 to SUn.

While this downward ramp waveform voltage is applied to scan electrodes SC1 to SCn, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn of each discharge cell, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm. In the meantime, weak initializing discharges are continuously generated. As a result, the negative wall voltage on scan electrodes SC1 to SCn and the positive wall voltage on sustain electrodes SU1 to SUn are weakened, and the positive wall voltage on data electrodes D1 to Dm remains in the subsequent writing period Pw1. The voltage is adjusted to a voltage suitable for the write operation. Further, priming particles are generated in the discharge cell.

When the downward ramp waveform voltage reaches the voltage Vi4, the voltage applied to the scan electrodes SC1 to SCn is set to voltage 0 (V).

In the third period Pi3 of the initialization period Pia1 of the subfield SF1, the voltage 0 (V) is applied to the scan electrodes SC1 to SCn while the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn and the data electrodes D1 to Dm. An upward ramp waveform voltage that gradually rises to Vr is applied.

In the discharge cell in which the wall voltage is not properly adjusted in the second period Pi2 and abnormal wall charges remain, a discharge is generated while the upward ramp waveform voltage is applied to the scan electrodes SC1 to SCn. Wall charges are erased.

On the other hand, no discharge occurs in the discharge cell in which the wall voltage is appropriately adjusted in the second period Pi2.

When the rising ramp waveform voltage reaches the voltage Vr, the voltage applied to the scan electrodes SC1 to SCn is lowered to the voltage 0 (V).

In the fourth period Pi4 of the initialization period Pia1 of the subfield SF1, as in the second period Pi2, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the positive voltage Ve is applied to the sustain electrodes SU1 to SUn. To do.

As shown in FIG. 3, the sustain electrodes SU1 to SUn may be in a high impedance state after the voltage Ve is applied. For example, the voltage Ve may be applied to the sustain electrodes SU1 to SUn.

The downward ramp waveform voltage that gently falls from the voltage 0 (V) to the negative voltage Vi4 is applied to the scan electrodes SC1 to SCn.

In the discharge cell where the wall voltage is not properly adjusted in the second period Pi2 and abnormal wall charges remain and discharge occurs in the third period Pi3, the downward ramp waveform voltage is applied to the scan electrodes SC1 to SCn. Discharge occurs. As a result, abnormal wall charges are erased, and the wall voltage in the discharge cell is adjusted to a value suitable for the address operation in the subsequent address period Pw1.

On the other hand, no discharge occurs in the discharge cells in which the wall voltage is appropriately adjusted in the second period Pi2 and no discharge occurs in the third period Pi3.

When the descending ramp waveform voltage reaches the voltage Vi4, the voltage applied to the scan electrodes SC1 to SCn is set to the voltage Vc.

The above-mentioned drive voltage waveform generated in the initialization period Pia1 is a forced initialization waveform (first forced initialization waveform). By this forced initializing operation, the wall voltage of each discharge cell in which the initializing discharge has occurred can be made substantially uniform.

In the present embodiment, the forced initializing operation is described as an initializing operation for forcibly generating an initializing discharge in all the discharge cells in the image display area of the panel. It is not limited to. In the present embodiment, for example, an operation for applying a forced initialization waveform only to a part of the discharge cells in the image display area of the panel is also a forced initialization operation, and a subfield for performing the forced initialization operation is forcibly initialized. Subfield. For example, in the odd-field subfield SF1, the forced initializing waveform is applied only to the odd-numbered scan electrodes SC (2N-1) (N is an integer of 1 or more), and the other scan electrodes SC (2N) are described later. A selective initialization waveform is applied. In the even-field subfield SF1, a forced initialization waveform is applied only to the even-numbered scan electrode SC (2N), and a selective initialization waveform is applied to the other scan electrode SC (2N-1). For example, the scan electrodes SC1 to SCn to which the forced initialization waveform is applied may be changed for each field. The same applies to all subfields that perform the forced initialization operation in the following description.

In address period Pw1 of subfield SF1, voltage 0 (V) is applied to data electrodes D1 to Dm, voltage Ve is applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn. .

Next, a negative scan pulse having a negative voltage Va is applied to the scan electrode SC1 in the first row. Then, a positive address pulse of a positive voltage Vd is applied to the data electrode Dk of the discharge cell that should emit light in the first row of the data electrodes D1 to Dm.

In this embodiment, the time from the end of the initialization period Pia1 to the generation of the first address pulse in the address period Pw1 (the first scan pulse is applied after the voltage Vc is applied to the scan electrode SC1). Tw0, and the time for applying the scan pulse to each of the scan electrodes SC1 to SCn (the width of the scan pulse, and the width of the write pulse applied to the data electrode Dk is substantially equal to this) Tw1 And In the present embodiment, the period Tw0 is about 50 μsec, for example, and Tw1 is about 1 μsec, for example.

In the discharge cell at the intersection of the data electrode Dk to which the address pulse voltage Vd is applied and the scan electrode SC1 to which the scan pulse voltage Va is applied, a discharge occurs between the data electrode Dk and the scan electrode SC1, and is maintained. A discharge is also generated between the electrode SU1 and the scan electrode SC1. Thus, address discharge is generated in the discharge cells (discharge cells to emit light) to which the scan pulse voltage Va and the address pulse voltage Vd are simultaneously applied.

In the discharge cell in which the address discharge has occurred, positive wall voltage is accumulated on scan electrode SC1, negative wall voltage is accumulated on sustain electrode SU1, and negative wall voltage is also accumulated on data electrode Dk. Is done.

In a discharge cell to which no address pulse is applied, the voltage at the intersection of data electrode Dh (data electrode Dh is data electrode D1-Dm excluding data electrode Dk) and scan electrode SC1 is the discharge start voltage. Therefore, the address discharge does not occur.

The voltages of the scan pulse and the address pulse are adjusted so that the address discharge is weaker than the sustain discharge. Therefore, the light emission due to the address discharge has lower luminance than the light emission due to the sustain discharge. This is to prevent light emission due to the address discharge from hindering display of an image on the panel 10.

Next, a scan pulse of voltage Va is applied to scan electrode SC2 in the second row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light in the second row. As a result, address discharge occurs in the discharge cells in the second row to which the scan pulse and address pulse are simultaneously applied. Address discharge does not occur in the discharge cells to which no address pulse is applied. Thus, the address operation in the discharge cells in the second row is performed.

The same addressing operation is sequentially performed in the order of scan electrode SC3, scan electrode SC4,..., Scan electrode SCn up to the discharge cell in the n-th row, and the address period Pw1 of subfield SF1 ends. As described above, in the address period Pw1, address discharge is selectively generated in the discharge cells to emit light, and wall charges for sustain discharge are formed in the discharge cells.

In the present invention, the order in which the scan pulses are applied to the scan electrodes SC1 to SCn is not limited to the order described above. The order in which the scan pulses are applied to the scan electrodes SC1 to SCn may be arbitrarily set according to the specifications of the image display device.

In the sustain period Ps1 of the subfield SF1, voltage 0 (V) is applied to the data electrodes D1 to Dm. Then, a sustain pulse of positive voltage Vs is applied to scan electrodes SC1 to SCn, and voltage 0 (V) is applied to sustain electrodes SU1 to SUn.

By applying the sustain pulse, a sustain discharge is generated between the scan electrode SCi and the sustain electrode SUi in the discharge cell that has generated the address discharge in the immediately preceding address period Pw1. The phosphor layer 25 of the discharge cell emits light due to the ultraviolet rays generated by the sustain discharge.

Also, due to the sustain discharge, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is also accumulated on the data electrode Dk. However, the sustain discharge does not occur in the discharge cells in which the address discharge has not occurred in the immediately preceding address period Pw1, and the wall voltage at the end of the initialization period Pia1 is maintained.

Subsequently, voltage 0 (V) is applied to scan electrodes SC1 to SCn, and a sustain pulse of voltage Vs is applied to sustain electrodes SU1 to SUn. In the discharge cell that has generated a sustain discharge immediately before, a sustain discharge occurs again, and a negative wall voltage is accumulated on the sustain electrode SUi, and a positive wall voltage is accumulated on the scan electrode SCi.

Thereafter, similarly, the number of sustain pulses obtained by multiplying the brightness weight by a predetermined brightness multiple is alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. In this way, the discharge cells that have generated the address discharge in the immediately preceding address period Pw1 generate the sustain discharge the number of times corresponding to the luminance weight, and emit light with the luminance corresponding to the luminance weight.

After the sustain pulse is generated (after the sustain operation is completed in sustain period Ps1), voltage 0 (V) is applied to sustain electrodes SU1 to SUn and data electrodes D1 to Dm, and applied to scan electrodes SC1 to SCn. An upward ramp waveform voltage that gradually rises from the voltage 0 (V) to the positive voltage Vr that is the first voltage is applied. Hereinafter, this upward ramp waveform voltage is referred to as a “first ramp waveform voltage”.

In the discharge cells that have generated the sustain discharge, the negative wall voltage is accumulated on the sustain electrode SUi and the positive wall voltage is accumulated on the scan electrode SCi, so that the discharge start voltage of those discharge cells is exceeded. The voltage Vr is set as the voltage. As a result, a weak discharge (erase discharge) is generated between sustain electrode SUi and scan electrode SCi of the discharge cell in which the sustain discharge is generated while applying the first ramp waveform voltage to scan electrodes SC1 to SCn. It occurs continuously.

Thereby, the wall voltage on the scan electrode SCi and the wall voltage on the sustain electrode SUi are weakened while leaving the positive wall voltage on the data electrode Dk, and unnecessary wall charges in the discharge cell are erased.

Note that the voltage Vr as the first voltage is preferably a voltage value approximate to the voltage Vs, and in this embodiment, the voltage Vr is set to a voltage value equal to the voltage Vs.

When the first ramp waveform voltage reaches the voltage Vr, the voltage applied to the scan electrodes SC1 to SCn is lowered to the voltage 0 (V). Thus, the erase operation performed at the end of sustain period Ps1 ends, and subfield SF1 ends.

Next, the selective initialization subfield will be described by taking the subfield SF2 as an example. In the present embodiment, in the initialization periods Pib3 to Pib8 after the subfield SF3, the same drive voltage waveform as that in the initialization period Pib2 of the subfield SF2 is applied to each electrode to perform the selective initialization operation. .

In the initialization period Pib2 of the subfield SF2, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the positive voltage Ve is applied to the sustain electrodes SU1 to SUn.

A downward ramp waveform voltage that drops from a voltage that is lower than the discharge start voltage (for example, voltage 0 (V)) to a negative voltage Vi4 is applied to scan electrodes SC1 to SCn. The downward ramp waveform voltage has substantially the same waveform shape as the downward ramp waveform voltage generated in the second period Pi2 and the fourth period Pi4 of the initialization period Pia1.

While applying this downward ramp waveform voltage to scan electrodes SC1 to SCn, a weak initializing discharge is generated in the discharge cell that has generated a sustain discharge in sustain period Ps1 of immediately preceding subfield SF1.

This initialization discharge weakens the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. In addition, the positive wall voltage accumulated on the data electrode Dk by the last sustain discharge is adjusted to a wall voltage suitable for the address operation by discharging an excessive portion.

On the other hand, in the discharge cells that did not generate the sustain discharge in the sustain period Ps1 of the immediately preceding subfield SF1, the initialization discharge does not occur, and the wall voltage at the end of the initialization period Pia1 of the subfield SF1 is maintained.

When the descending ramp waveform voltage reaches the voltage Vi4, the voltage applied to the scan electrodes SC1 to SCn is set to the voltage Vc.

As described above, in the initialization period Pib2 of the subfield SF2, the initializing discharge is performed on the discharge cell that has performed the address operation in the address period Pw1 of the immediately preceding subfield SF1 (that is, the discharge cell that has performed the sustain operation in the sustain period Ps1). Select initialization operation that generates Thereby, the wall voltage in the discharge cell is adjusted to a wall voltage suitable for the address operation in the subsequent address period Pw2. Further, priming particles that assist the generation of the address discharge are generated in the discharge cell.

The above-mentioned drive voltage waveform generated in the initialization period Pib2 is a selective initialization waveform.

The voltage Vi4 and the voltage Ve are set to voltage values that satisfy the above-described operation according to the characteristics of the panel 10, the specifications of the plasma display device 100, and the like.

In the address period Pw2 and the sustain period Ps2 in the subfield SF2, the drive voltage waveforms similar to those in the address period Pw1 and the sustain period Ps1 in the subfield SF1 are applied to the respective electrodes, except for the number of sustain pulses generated, and thus the description thereof is omitted.

In each subfield after subfield SF3, the drive voltage waveform similar to that in subfield SF2 is applied to each electrode except for the number of sustain pulses, and the description thereof is omitted.

In the present embodiment, an example has been described in which the subfield for performing the forced initialization operation is the subfield SF1, but the present invention is not limited to this configuration. The subfield in which the forced initialization operation is performed may be a subfield after subfield SF2.

In the present embodiment, the example in which the forced initialization operation is performed once per field has been described, but the present invention is not limited to this configuration. The number of times of performing the forced initialization operation may be once in a plurality of fields.

Next, the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx will be described. The coordinate detection subfield is a generic name for the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx.

FIG. 4 schematically shows an example of a drive voltage waveform applied to each electrode of panel 10 in timing detection subfield SFo, y coordinate detection subfield SFy, and x coordinate detection subfield SFx in the embodiment of the present invention. It is.

FIG. 4 shows drive voltages applied to sustain electrodes SU1 to SUn, scan electrodes SC1 to SCn, and data electrodes D1 to Dm in timing detection subfield SFo, y coordinate detection subfield SFy, and x coordinate detection subfield SFx. Waveform is shown. FIG. 4 also shows a part of the sustain period Ps8 of the subfield SF8 immediately before the timing detection subfield SFo and a part of the subfield SF1.

The timing detection subfield SFo has an initialization period Pico, an address period Pwo, and a timing detection period Po.

In the initialization period Pico, a forced initialization operation is performed. In the initialization period Pico, a driving voltage waveform different from that in the initialization period Pia1 of the subfield SF1 of the image display subfield is applied to each electrode. Here, the initialization period Pico is divided into two periods of a sixth period Pi6 and a seventh period Pi7, and each period will be described.

In the sixth period Pi6 of the initialization period Pico, the same drive voltage waveform as that in the first period Pi1 of the initialization period Pia1 is applied to each electrode.

That is, the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn, and the data electrodes D1 to Dm are set to the high impedance state after the voltage 0 (V) is applied. A voltage Vi1 is applied to scan electrodes SC1 to SCn after voltage 0 (V) is applied, and an upward ramp waveform voltage that gradually rises from voltage Vi1 to voltage Vi2 is applied. Voltage Vi1 is set to a voltage lower than the discharge start voltage with respect to sustain electrodes SU1 to SUn. Voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrodes SU1 to SUn.

The upslope waveform voltage has substantially the same waveform shape as the upslope waveform voltage generated in the first period Pi1 of the initialization period Pia1.

While the rising ramp waveform voltage rises, it is weak between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn, and between the scan electrodes SC1 to SCn and the data electrodes D1 to Dm, respectively. Initializing discharge is generated continuously.

At this time, since the data electrodes D1 to Dm are in a high impedance state, the discharge between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn is caused to occur between the scan electrodes SC1 to SCn as in the initialization period Pia1 of the subfield SF1. It occurs before the discharge between the data electrodes D1 to Dm. Therefore, this initialization discharge is generated stably.

Then, negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Furthermore, priming particles that assist the generation of the subsequent address discharge are generated in the discharge cell.

When the voltage applied to scan electrodes SC1 to SCn reaches voltage Vi2, the voltage of scan electrodes SC1 to SCn is once lowered to voltage Vi3 lower than voltage Vi2, and then lowered to voltage 0 (V). However, the present invention is not limited to this configuration. For example, the voltage may be sharply decreased from voltage Vi2 to voltage 0 (V).

In the seventh period Pi7 of the initialization period Pico, the same drive voltage waveform as that in the initialization period Pib2 of the subfield SF2 is applied to each electrode.

That is, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the positive voltage Ve is applied to the sustain electrodes SU1 to SUn. A downward ramp waveform voltage that falls from a voltage (for example, voltage 0 (V)) that is lower than the discharge start voltage to a negative voltage Vi4 is applied to scan electrodes SC1 to SCn. This downward ramp waveform voltage has substantially the same waveform shape as the downward ramp waveform voltage generated in the initialization period Pib2.

While applying this downward ramp waveform voltage to scan electrodes SC1 to SCn, a weak initializing discharge is generated between scan electrodes SC1 to SCn and data electrodes D1 to Dm, and between scan electrode SCi and sustain electrode SUi. appear.

This initialization discharge weakens the wall voltage on scan electrodes SC1 to SCn and the wall voltage on sustain electrodes SU1 to SUn, and the positive wall voltage accumulated on data electrodes D1 to Dm has an excessive portion. It is discharged and adjusted to a wall voltage suitable for the subsequent address operation.

When the descending ramp waveform voltage reaches the voltage Vi4, the voltage applied to the scan electrodes SC1 to SCn is set to the voltage Vc.

The above-mentioned drive voltage waveform generated in the initialization period Pico is a forced initialization waveform (second forced initialization waveform). In this initialization period Pico, initialization discharge is forcibly generated in all the discharge cells in the image display area of panel 10. Although the wall voltage varies between the discharge cells depending on the discharge history, the wall voltage of each discharge cell can be made substantially uniform by this forced initialization operation. The wall voltage in each discharge cell is adjusted to a wall voltage suitable for the address operation in the subsequent address period Pwo, and priming particles that assist the generation of the address discharge are generated in the discharge cell.

In the address period Pwo of the timing detection subfield SFo, the voltage 0 (V) is applied to the data electrodes D1 to Dm, the voltage Ve is applied to the sustain electrodes SU1 to SUn, and the voltage Vc is applied to the scan electrodes SC1 to SCn. Apply.

Next, an address pulse of the voltage Vd is applied to the data electrodes D1 to Dm and a scan pulse of the voltage Va is applied to the scan electrodes SC1 to SCn to generate an address discharge in each discharge cell.

In the present embodiment, as shown in FIG. 4, the scan pulse is sequentially applied to each of the electrodes from the scan electrode SC1 to the scan electrode SCn while applying the write pulse to all the data electrodes D1 to Dm. It is also possible to apply a scan pulse to all the scan electrodes SC1 to SCn at a time and generate an address discharge in all the discharge cells in the image display area of the panel 10 at the same time.

After completing the address discharge in all the discharge cells in the image display area of the panel 10, the voltage 0 (V) is applied to the data electrodes D1 to Dm. Further, voltage Vc is applied to scan electrodes SC1 to SCn, and then voltage 0 (V) is applied. Further, the voltage applied to sustain electrodes SU1 to SUn is changed from voltage Ve to voltage 0 (V). In the present embodiment, this state is maintained from time to0 to time To0. Therefore, during this period, after the last address discharge occurs in the discharge cells, a state in which no discharge occurs is maintained. Time to0 is the time when the scan pulse for generating the last address discharge is applied to scan electrode SCn.

In this embodiment, the time To0 is set to a time longer than any of the time To1, the time To2, and the time To3 described later. In the present embodiment, the time To0 is about 50 μsec, for example.

Next, in the timing detection period Po of the timing detection subfield SFo, the panel 10 is caused to emit a plurality of times of light emission (light emission for timing detection) as a reference when calculating the position coordinates of the light pen. That is, light emission for timing detection is emitted to all the discharge cells in the image display area of the panel 10 at a predetermined time interval (in this embodiment, for example, time To1, time To2, and time To3 in this embodiment). The timing detection discharge to be generated is generated a plurality of times (in this embodiment, for example, four times).

Specifically, at time to1 after time To0 has elapsed from time to0, voltage 0 (V) is applied to sustain electrodes SU1 to SUn, and timing detection pulse V1 of voltage Vso is applied to scan electrodes SC1 to SCn. . As a result, the first timing detection discharge is generated in all the discharge cells in the image display area of the panel 10, and the entire image display surface of the panel 10 emits light (first timing detection light emission).

Note that this timing detection discharge is a stronger discharge than the address discharge, similarly to the sustain discharge.

Next, at time to2 after time To1 has elapsed from time to1, voltage 0 (V) is applied to scan electrodes SC1 to SCn and timing detection pulse V2 of voltage Vso is applied to sustain electrodes SU1 to SUn. Thereby, the second timing detection discharge is generated in all the discharge cells in the image display area of the panel 10, and the entire image display surface of the panel 10 emits light (second timing detection light emission).

Next, at time to3 after time To2 has elapsed from time to2, voltage 0 (V) is applied to sustain electrodes SU1 to SUn, and timing detection pulse V3 of voltage Vso is applied to scan electrodes SC1 to SCn. As a result, the third timing detection discharge is generated in all the discharge cells in the image display region of the panel 10, and the entire image display surface of the panel 10 emits light (third timing detection light emission).

Next, at time to4 after time To3 has elapsed from time to3, voltage 0 (V) is applied to scan electrodes SC1 to SCn, and timing detection pulse V4 of voltage Vso is applied to sustain electrodes SU1 to SUn. As a result, the fourth timing detection discharge is generated in all the discharge cells in the image display area of the panel 10, and the entire image display surface of the panel 10 emits light (fourth timing detection light emission).

Thus, in the timing detection subfield SFo, a predetermined time interval (in the present embodiment, for example, time To1, time To2, and time To3 in this embodiment) is multiple times (in this embodiment, for example, 4 Timing detection discharge is generated, and the entire image display surface of the panel 10 is caused to emit light a plurality of times (for example, four times) at predetermined time intervals (for example, time To1, time To2, and time To3). Then, the light pen receives this light emission and creates a coordinate reference signal (a signal that becomes a reference when calculating the position coordinates (x coordinate, y coordinate) of the light pen).

In the timing detection subfield SFo, the entire surface of the image display surface of the panel 10 shines at the same timing, so that the light pen is at the same timing no matter where the tip of the light pen is in the image display area of the panel 10. This light emission can be received.

In this embodiment, for example, the time To1 is about 40 μsec, the time To2 is about 20 μsec, and the time To3 is about 30 μsec. However, the present invention is not limited to the numerical values described above for the times To0 to To3, and each time may be set appropriately according to the specifications of the plasma display system.

The light pen generates a coordinate reference signal when it detects a plurality of times (for example, four times) of light emission occurring at a predetermined time interval (for example, time To1, time To2, and time To3).

In the timing detection period Po of the timing detection subfield SFo, after the generation of the timing detection pulse V4 (the end of the timing detection period Po), an erase operation similar to the erase operation performed at the end of the sustain period Ps1 of the subfield SF1 is performed. . In other words, the scan electrodes SC1 to SCn gradually increase from the voltage 0 (V) to the first voltage (voltage Vr) while the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn and the data electrodes D1 to Dm. A ramp waveform voltage of 1 is applied. When the first ramp waveform voltage reaches the voltage Vr, the voltage applied to the scan electrodes SC1 to SCn is lowered to the voltage 0 (V). Thereby, a weak erasure discharge is generated in all the discharge cells in the image display area of the panel 10.

In this embodiment, the voltage Vso is set to a voltage equal to the voltage Vs. For example, the voltage Vso is about 205 (V). However, the voltage Vso may be a voltage different from the voltage Vs. The voltage Vso may be any voltage that generates timing detection discharge.

Subsequently, a y-coordinate detection subfield SFy and an x-coordinate detection subfield SFx are generated.

The y coordinate detection subfield SFy has an initialization period Piby, a y coordinate detection period Py, and an erase period Peby.

In the initialization period Piby, a drive voltage waveform similar to that in the initialization period Pib2 of the subfield SF2 of the image display subfield is applied to each electrode to perform the same selective initialization operation, and thus description thereof is omitted.

In the timing detection period Po of the timing detection subfield SFo immediately before the initialization period Piby, timing detection discharges are generated in all the discharge cells in the image display area of the panel 10, and therefore in the initialization period Piby A weak initializing discharge is generated in all discharge cells. Thereby, the wall voltage of all the discharge cells in the image display area of the panel 10 is adjusted to the wall voltage suitable for the y coordinate detection pattern display operation in the subsequent y coordinate detection period Py. Furthermore, priming particles that assist the generation of discharge in the y-coordinate detection period Py are generated in the discharge cell.

Next, in the y coordinate detection period Py of the y coordinate detection subfield SFy, the voltage Ve is applied to the sustain electrodes SU1 to SUn, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the scan electrodes SC1 to SCn are applied. A voltage Vc is applied. Then, this state is maintained during the period Ty0. This period Ty0 is longer than the above-described period Tw0, and is set to about 700 μsec, for example.

Next, at time ty0 after period Ty0, positive y coordinate detection voltage Vdy is applied to data electrodes D1 to Dm, and negative y coordinate detection pulse of voltage Vay is applied to scan electrode SC1 in the first row. To do. The y coordinate detection voltage Vdy is a voltage higher than the voltage 0 (V), and the voltage Vay of the y coordinate detection pulse is a negative voltage lower than the voltage Vc. In FIG. 4, the pulse width of the y coordinate detection pulse is shown as Ty1.

In the discharge cell in the first row at the intersection of the data electrodes D1 to Dm to which the y coordinate detection voltage Vdy is applied and the scan electrode SC1 to which the y coordinate detection pulse of the voltage Vay is applied, the data electrodes D1 to Dm and the scan electrodes The voltage difference at the intersection with SC1 exceeds the discharge start voltage, and discharge occurs between data electrodes D1 to Dm and scan electrode SC1, and between sustain electrode SU1 and scan electrode SC1.

This discharge is as strong as the address discharge and is weaker than the sustain discharge.

Thus, discharge occurs in all the discharge cells constituting the first row, and these discharge cells emit light all at once. For example, if the image display area of the panel 10 is composed of m × n discharge cells, m = 1920 × 3 = 5760, and n = 1080 (that is, the number of pixels in the image display area is 1920 × 1080). The 5760 discharge cells (1920 pixels) constituting the first row emit light all at once. And this light emission becomes light emission for y coordinate detection.

Hereinafter, an aggregate of discharge cells constituting one row is referred to as “discharge cell row”, and an aggregate of pixels constituting one row is referred to as “pixel row”. In this embodiment, the discharge cell row and the pixel row are substantially the same, and in the above operation, the first pixel row (first discharge cell row) emits light all at once.

In the discharge cell in which this discharge has occurred, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also formed on data electrodes D1 to Dm. Is accumulated.

Next, with the y coordinate detection voltage Vdy applied to the data electrodes D1 to Dm, a y coordinate detection pulse of the voltage Vay is applied to the scan electrode SC2 in the second row. As a result, light emission for y coordinate detection occurs in the second pixel row (second discharge cell row).

The same operation is performed in the order of scan electrode SC3, scan electrode SC4,..., Scan electrode SCn with the y coordinate detection voltage Vdy being applied to the data electrodes D1 to Dm until the discharge cell in the n-th row is reached. Then, light emission for y coordinate detection is sequentially generated in each pixel row (discharge cell row) from the third row to the nth row (for example, 1080th row).

As a result, in the y coordinate detection period Py of the y coordinate detection subfield SFy, one horizontal line that emits light (that is, one pixel row that emits light) corresponds to the upper end portion (pixels in the first row) of the image display area of the panel 10. A pattern (y-coordinate detection pattern) that sequentially moves one line at a time from the lower line to the lower end (nth pixel line) is displayed. That is, the y-coordinate detection pattern is a pattern in which each pixel row from the first row to the n-th row of the image display area sequentially emits light for each row.

When the y-coordinate detection pattern is displayed on the panel 10, each pixel row from the first row to the n-th row of the image display region emits light sequentially for each row, so that the tip of the light pen is the image display region of the panel 10 The timing at which the light pen receives this light emission varies depending on where the light pen is. The y coordinate of the position (x coordinate, y coordinate) of the light pen in the image display area is detected by detecting the light reception timing when the light emission is received by the light pen.

Note that the period during which the y-coordinate detection pattern is displayed on the panel 10 is very short. Therefore, the possibility that the y-coordinate detection pattern is recognized by the user is low, and even if it is recognized by the user, it is only a slight change in luminance.

In this embodiment, the time for applying the y-coordinate detection pulse to each of the scan electrodes SC1 to SCn is Ty1. This Ty1 is, for example, about 1 μsec. Therefore, for example, if n = 1080 and the period Ty0 from the end of the initialization period Piby to the generation of the first y coordinate detection pulse is about 700 μsec, the time of the y coordinate detection period Py is Ty0 + Ty1 × 1080 = about 1780 μsec.

In the erasing period Peby of the y coordinate detection subfield SFy, the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn, and the data electrodes D1 to Dm are set to the high impedance state after the voltage 0 (V) is applied.

The upward ramp waveform voltage that gently rises from the voltage 0 (V) to the first voltage (voltage Vr) is applied to the scan electrodes SC1 to SCn. When the rising ramp waveform voltage reaches voltage Vr, the voltages of scan electrodes SC1 to SCn are once lowered to voltage 0 (V). Next, a voltage Vi1 lower than the voltage Vr is applied to the scan electrodes SC1 to SCn, and an upward ramp waveform voltage that gradually rises from the voltage Vi1 to a second voltage (voltage Vi2) higher than the first voltage is applied. . Voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrodes SU1 to SUn.

While the rising ramp waveform voltage rises, a weak erasing discharge is generated between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm. To do.

At this time, since the data electrodes D1 to Dm are in the high impedance state, the discharge between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn is caused to occur between the scan electrodes SC1 to SCn, as in the initialization period Pia1 of the subfield SF1. It occurs before the discharge between the data electrodes D1 to Dm. Therefore, this erasing discharge is generated stably.

Thus, the wall voltage of all the discharge cells in the image display area of panel 10 is adjusted to the wall voltage suitable for the initialization operation in the subsequent x coordinate detection subfield SFx. Furthermore, priming particles that assist the generation of discharge in the x-coordinate detection subfield SFx are generated in the discharge cell.

FIG. 4 shows an example in which the rising ramp waveform voltage that rises in two steps from the voltage 0 (V) to the positive voltage Vi2 is applied to the scan electrodes SC1 to SCn. In order to prevent a strong discharge from occurring when a waveform voltage is applied to the discharge cell, as shown in FIG. 4, the start voltage of the second rising ramp voltage is equal to or lower than the maximum voltage of the first rising ramp voltage. It is desirable to set it to a value.

Further, in the present embodiment, the upward ramp waveform voltage is not limited to a configuration that is generated in two steps, and the upward ramp waveform voltage is continuous from voltage 0 (V) to voltage Vi2. It may be a waveform shape that rises. Hereinafter, this upward ramp waveform voltage is referred to as a “second ramp waveform voltage”. Therefore, the second up-ramp waveform voltage shown in FIG. 4 has a waveform shape that rises in two steps from voltage 0 (V) to voltage Vi2, but rises continuously from voltage 0 (V) to voltage Vi2. A waveform having a waveform shape is also included in the second ramp waveform voltage.

When the second ramp waveform voltage reaches the voltage Vi2, the voltage applied to the scan electrodes SC1 to SCn is once lowered to the voltage Vi3 lower than the voltage Vi2, and then set to the voltage 0 (V). However, the present invention is not limited to this configuration. For example, the voltage may be sharply decreased from voltage Vi2 to voltage 0 (V).

The subsequent x-coordinate detection subfield SFx has an initialization period Pidx, an x-coordinate detection period Px, and an erase period Pedx.

In the initialization period Pidx, a drive voltage waveform similar to that in the initialization period Piby of the y coordinate detection subfield SFy is applied to each electrode, and a selective initialization operation similar to that in the initialization period Piby is performed. However, in the initialization period Pidx, a downward ramp waveform voltage having a larger amplitude than that of the downward ramp waveform voltage generated in the initialization period Piby is applied to the scan electrodes SC to SCn.

In the initialization period Pidx, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the voltage Ve is applied to the sustain electrodes SU1 to SUn. Then, a downward ramp waveform voltage that falls from a voltage (for example, voltage 0 (V)) that is lower than the discharge start voltage to a negative voltage Va is applied to scan electrodes SC1 to SCn.

The negative voltage Va has a lower voltage value than the negative voltage Vi4. That is, the absolute value of the voltage Va is larger than the absolute value of the voltage Vi4. In the present embodiment, the voltage Va is about −200 (V), for example, and the voltage Vi4 is about −175 (V), for example.

In the y-coordinate detection subfield SFy immediately before the initialization period Pidx, the discharge and erasure discharge for detecting the y-coordinate occur in all the discharge cells in the image display area of the panel 10, and therefore, in the initialization period Pidx However, a weak initializing discharge is generated in all the discharge cells. Thereby, the wall voltage of all the discharge cells in the image display area of the panel 10 is adjusted to the wall voltage suitable for the x coordinate detection pattern display operation in the subsequent x coordinate detection period Px. Furthermore, priming particles that assist the generation of discharge in the x-coordinate detection period Px are generated in the discharge cell.

In the present embodiment, the arrival potential of the downward ramp waveform voltage generated in the initialization period Pidx of the x-coordinate detection subfield SFx is set to the voltage Va lower than the voltage Vi4 (larger absolute value), and the data electrodes D1 to The positive wall voltage remaining on Dm is applied to the data electrodes D1 to D1 at the end of the initialization periods Pia1, Pib2 to Pib8 of the subfields SF1 to SF8 of the image display subfield (or at the end of the initialization periods Pico and Piby). It is adjusted to a value lower than the positive wall voltage remaining on Dm.

By reducing the wall voltage in this way, it is possible to suppress the dark current that flows when the voltage Vax is applied to the scan electrodes SC1 to SCn in the x coordinate detection period Px of the x coordinate detection subfield SFx. Since the decrease in wall charge can be suppressed by suppressing the dark current, the decrease in wall charge in the x coordinate detection period Px can thereby be suppressed.

Next, in the x coordinate detection period Px of the x coordinate detection subfield SFx, first, the voltage 0 (V) is applied to the data electrodes D1 to Dm, the voltage Ve is applied to the sustain electrodes SU1 to SUn, and the scan electrodes SC1 to SCn are applied. A voltage Vc is applied to SCn. Then, this state is maintained during the period Tx0.

This period Tx0 is set to be longer than the period Tw0 described above. The period Tx0 is desirably set between 200 μsec and 1 msec, and is set to about 700 μsec in the present embodiment, for example.

Next, at the time tx0 after the elapse of the period Tx0, the negative x-coordinate detection voltage Vax is applied to the scan electrodes SC1 to SCn, and the voltage applied to the scan electrodes SC1 to SCn reaches the x-coordinate detection voltage Vax. A positive x coordinate detection pulse of voltage Vdx is applied to data electrodes D1 to D3 in the first to third columns. The voltage Vdx of the x coordinate detection pulse is higher than the voltage 0 (V), and the x coordinate detection voltage Vax is a negative voltage lower than the voltage Vc. In FIG. 4, the pulse width of the x-coordinate detection pulse is shown as Tx1, and the drive voltage waveform applied to scan electrodes SC1 to SCn is a drive voltage waveform in which the voltage drops relatively slowly from voltage Vc to voltage Vax. As shown.

The data electrodes D1 to D3 correspond to a red discharge cell, a green discharge cell, and a blue discharge cell constituting one pixel, and the pixel is a pixel arranged at the left end of the image display area, for example. It is.

In the discharge cell at the intersection of the data electrodes D1 to D3 to which the x coordinate detection pulse of the voltage Vdx is applied and the scan electrodes SC1 to SCn to which the x coordinate detection voltage Vax is applied, the data electrodes D1 to D3 and the scan electrodes SC1 to SC1 The voltage difference at the intersection with SCn exceeds the discharge start voltage, and discharge occurs between data electrodes D1 to D3 and scan electrodes SC1 to SCn and between sustain electrodes SU1 to SUn and scan electrodes SC1 to SCn. .

This discharge is the same as or weaker than the address discharge, and is weaker than the sustain discharge.

In this way, discharge occurs in all the pixels constituting the first column, and these pixels emit light all at once. For example, if the image display area of the panel 10 is composed of m × n discharge cells, m = 1920 × 3 = 5760, and n = 1080 (that is, the number of pixels in the image display area is 1920 × 1080). The 1080 pixels (3 columns × 1080 discharge cells) constituting the first column emit light all at once. And this light emission becomes light emission for x coordinate detection.

Hereinafter, an assembly of discharge cells constituting one column is referred to as a “discharge cell column”. Further, an assembly of discharge cells (pixel column) composed of three adjacent discharge cell columns is referred to as a “pixel column”. In the above-described operation, the first pixel column (that is, the first, second, and third discharge cell columns) emits light all at once.

In the discharge cell in which this discharge has occurred, positive wall voltage is accumulated on scan electrodes SC1 to SCn, negative wall voltage is accumulated on sustain electrodes SU1 to SUn, and negative electrodes are also formed on data electrodes D1 to D3. Sex wall voltage is accumulated.

Next, with the x coordinate detection voltage Vax being applied to the scan electrodes SC1 to SCn, the x coordinate detection pulse of the voltage Vdx is applied to the data electrodes D4 to D6 in the fourth column to the sixth column. As a result, light emission for x coordinate detection occurs in the second pixel column (fourth, fifth, and sixth discharge cell columns).

Similar operations are performed adjacent to each other in the order of data electrodes D7 to D9, data electrodes D10 to D12,..., Data electrodes Dm-2 to Dm, with the x coordinate detection voltage Vax being applied to scan electrodes SC1 to SCn. Each of the three data electrodes 22 is sequentially performed until reaching the m-th discharge cell, and light emission for x coordinate detection is performed on each pixel column from the third column to the last column (for example, 1920 column). Generate sequentially.

As a result, in the x coordinate detection period Px of the x coordinate detection subfield SFx, one vertical line that emits light (that is, one pixel column that emits light) corresponds to the left end (first column) of the image display area of the panel 10. A pattern (x-coordinate detection pattern) that sequentially moves one column at a time from the pixel column) to the right end (m / 3th pixel column) is displayed. That is, the x coordinate detection pattern is a pattern in which each pixel column from the first column to the last column in the image display area sequentially emits light for each column. In other words, the x-coordinate detection pattern is a pattern in which three discharge cell columns adjacent to each other sequentially emit light by three columns from the left end (first column) to the right end (m column) of the image display area. is there.

When the x-coordinate detection pattern is displayed on the panel 10, each pixel column from the first column to the last column in the image display region sequentially emits light for each column, so that the tip of the light pen is the image display region of the panel 10. The timing at which the light pen receives this light emission varies depending on where the light pen is. By detecting the light reception timing when this light emission is received by the light pen, the x coordinate of the position (x coordinate, y coordinate) of the light pen in the image display area is detected.

Note that the period during which the x-coordinate detection pattern is displayed on the panel 10 is very short. Therefore, the possibility that the x coordinate detection pattern is recognized by the user is low, and even if it is recognized by the user, it is only a slight change in luminance.

In this embodiment, the time for applying the x-coordinate detection pulse to each of the data electrodes D1 to Dm is Tx1. This Tx1 is about 1 μsec, for example. Therefore, for example, if m = 1920 × 3 and the period Tx0 from the end of the initialization period Pidx to the generation of the first x-coordinate detection pulse is about 700 μsec, the time of the x-coordinate detection period Px is Tx0 + Tx1 × 1920 = about 2620 μsec.

In the erasing period Pedx of the x-coordinate detection subfield SFx, the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn, and the data electrodes D1 to Dm are set to the high impedance state after the voltage 0 (V) is applied.

The second ramp waveform voltage is applied to the scan electrodes SC1 to SCn in the same manner as the erase period Peby of the y coordinate detection subfield SFy. That is, when an upward ramp waveform voltage that gradually rises from the voltage 0 (V) to the first voltage (voltage Vr) is applied and the upward ramp waveform voltage reaches the voltage Vr, the voltages of the scan electrodes SC1 to SCn are temporarily set to voltages. Reduce to 0 (V). Next, a voltage Vi1 lower than the voltage Vr is applied to the scan electrodes SC1 to SCn, and an upward ramp waveform voltage that gradually rises from the voltage Vi1 to a second voltage (voltage Vi2) higher than the first voltage is applied. . Voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrodes SU1 to SUn.

While the second ramp waveform voltage rises, weak erase discharges are generated between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm, respectively. Will occur.

At this time, since the data electrodes D1 to Dm are in the high impedance state, the discharge between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn is caused to occur between the scan electrodes SC1 to SCn, as in the initialization period Pia1 of the subfield SF1. It occurs before the discharge between the data electrodes D1 to Dm. Therefore, this erasing discharge is generated stably.

Thus, in all the discharge cells in the image display area of panel 10, negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive polarity is applied to data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Wall voltage is accumulated.

When the second ramp waveform voltage reaches the voltage Vi2, the voltage applied to the scan electrodes SC1 to SCn is once lowered to the voltage Vi3 lower than the voltage Vi2, and then set to the voltage 0 (V). However, the present invention is not limited to this configuration. For example, the voltage may be sharply decreased from voltage Vi2 to voltage 0 (V).

Next, a voltage 0 (V) is applied to the data electrodes D1 to Dm, and a voltage Vs higher than the voltage Ve is applied to the sustain electrodes SU1 to SUn. Then, a downward ramp waveform voltage that drops from a voltage (for example, voltage 0 (V)) that is lower than the discharge start voltage to a negative voltage Vi4 is applied to scan electrodes SC1 to SCn. Hereinafter, this downward ramp waveform voltage is referred to as a “third ramp waveform voltage”.

While this third ramp waveform voltage is applied to scan electrodes SC1 to SCn, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm. In this case, a weak erasing discharge is generated.

Thereby, the wall voltage on scan electrodes SC1 to SCn and the wall voltage on sustain electrodes SU1 to SUn are weakened, and the positive wall voltage accumulated on data electrodes D1 to Dm is also weakened.

Thus, the wall voltage of all the discharge cells in the image display area of panel 10 is adjusted to the wall voltage suitable for the initialization operation in subfield SF1 of the subsequent image display subfield. Furthermore, priming particles that assist the generation of the subsequent initializing discharge are generated in the discharge cell.

When the third ramp waveform voltage reaches the voltage Vi4, the voltage applied to the scan electrodes SC1 to SCn is set to the voltage Vc. Further, the voltage applied to sustain electrodes SU1 to SUn is changed from voltage Vs to voltage Ve. Then, this state (pause state) is maintained until the subfield SF1 of the next field starts. FIG. 4 shows this dormant state as a dormant period BLK.

Note that, in the erase period Peby of the y-coordinate detection subfield SFy and the erase period Pedx of the x-coordinate detection subfield SFx in the present embodiment, the scan electrodes SC1 to SCn are supplied with the first voltage (voltage) from the voltage 0 (V). The second ramp waveform voltage rising to the second voltage (voltage Vi2) higher than Vr) is applied for the following reason.

In the sustain periods Ps1 to Ps8 of the subfields SF1 to SF8 that are image display subfields, the erase operation is performed after the sustain discharge, which is a relatively strong discharge, is completed. Similarly, in the timing detection period Po of the timing detection subfield SFo, similarly to the sustain discharge, the erase operation is performed after the timing detection discharge, which is a relatively strong discharge, is completed. Therefore, in these subfields, the wall charge sufficient to generate an erasing discharge is sufficient for the erasing operation even in the first erasing lamp that rises from the voltage 0 (V) to the first voltage (voltage Vr). Accumulated in the discharge cell immediately before.

On the other hand, in the y-coordinate detection subfield SFy and the x-coordinate detection subfield SFx, the erase operation is performed after the discharge for y-coordinate detection and the discharge for x-coordinate detection, which are weaker discharges than the sustain discharge, are completed. .

Therefore, the wall charges stored in the discharge cells immediately before these erasing operations are less than the wall charges stored in the discharge cells after the sustain operation is completed, and the first charge (voltage Vr) is reached. In the first erase lamp that only rises, there is a possibility that the erase discharge does not occur stably.

Therefore, in the present embodiment, in order to generate an erasing discharge stably, in the erasing period Peby of the y-coordinate detection subfield SFy and the erasing period Pedx of the x-coordinate detection subfield SFx, the first voltage (voltage Vr) is used. The erase operation is performed using the second ramp waveform voltage that rises to a higher second voltage (voltage Vi2).

In the erasing period Pedx of the x-coordinate detection subfield SFx in the present embodiment, the third voltage that drops from the voltage 0 (V) to the negative voltage Vi4 is applied to the scan electrodes SC1 to SCn following the second ramp waveform voltage. The ramp waveform voltage is applied for the following reason.

The rest period BLK from the end of the x coordinate detection subfield SFx to the start of the subfield SF1 of the next field is a period in which a rest state in which no discharge occurs is maintained. For example, in a configuration in which the luminance multiple is changed according to the image signal, the length of the pause period BLK is also changed because the number of sustain pulses generated is changed according to the image signal.

In this rest period BLK, since no discharge occurs, the priming particles decrease with the passage of time, and the state of the wall charge in the discharge cell also changes. Therefore, if the pause period BLK is long, the discharge generated at the beginning of the next field may become unstable.

Therefore, in this embodiment, in order to further generate priming particles and further weaken the wall charge in the discharge cell to suppress the change in the state of the wall charge, in the erasing period Pedx of the x coordinate detection subfield SFx, After the erase discharge is generated by the ramp waveform voltage of 2, the third ramp waveform voltage that drops to the voltage Vi4 is applied to the scan electrodes SC1 to SCn to further generate the erase discharge.

Thereby, immediately before the start of the subfield SF1 of the next field, sufficient priming particles remain in the discharge cell, and the wall charge state in the discharge cell can be kept more stable. Therefore, it is possible to generate the initialization discharge of subfield SF1 more stably.

Note that if the erase operation after the relatively strong discharge is generated by the second ramp waveform voltage, the erase operation becomes excessive, which is not desirable. Therefore, in the present embodiment, the erasing operation is performed with the first ramp waveform voltage at the end of the sustain periods Ps1 to Ps8 and at the end of the timing detection period Po.

The above is the outline of the drive voltage waveforms of the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx.

FIG. 4 shows an example in which the x coordinate detection subfield SFx is generated after the y coordinate detection subfield SFy. For example, the y coordinate detection subfield SFy is generated after the x coordinate detection subfield SFx. Also good. However, in this configuration, the drive voltage waveform generated during the erasing period Pedx of the x-coordinate detection subfield SFx shown in FIG. 4 is generated during the erasing period Peby of the y-coordinate detection subfield SFy, and the y-coordinate detection shown in FIG. It is assumed that the drive voltage waveform generated in the erase period Peby of the subfield SFy is generated in the erase period Pedx of the x coordinate detection subfield SFx.

Note that the voltage values applied to the electrodes in this embodiment are, for example, the voltage Vi1 = 150 (V), the voltage Vi2 = 350 (V), the voltage Vi3 = 200 (V), and the voltage Vi4 = −175 (V). , Voltage Va = voltage Vay = voltage Vax = −200 (V), voltage Vc = −50 (V), voltage Vs = voltage Vso = 205 (V), voltage Vr = 205 (V), voltage Ve = 155 (V ), Voltage Vd = voltage Vdy = voltage Vdx = 55 (V).

In this embodiment, the voltage Va, the voltage Vay, and the voltage Vax are set to be equal to each other, and the voltage Vd, the voltage Vdy, and the voltage Vdx are set to be equal to each other. Different voltages may be used.

In the present embodiment, an upward ramp waveform voltage voltage Vi2 generated in the initialization period Pia1 of the subfield SF1, an upward ramp waveform voltage voltage Vi2 generated in the initialization period Pico of the timing detection subfield SFo, and The voltage Vi2 of the second ramp waveform voltage generated in the erase period Peby of the y-coordinate detection subfield SFy and the erase period Pedx of the x-coordinate detection subfield SFx is set to be equal to each other, but the voltages Vi2 are different from each other. It may be set.

In addition, an upward ramp waveform voltage generated in the initialization period Pia1 of the subfield SF1, the initialization period Pico of the timing detection subfield SFo, the erase period Peby of the y coordinate detection subfield SFy, and the erase period Pedx of the x coordinate detection subfield SFx. The slope of is about 1.5 (V / μsec). Also, the initialization periods Pia1, Pib2 to Pib8 of the image display subfield (subfields SF1 to SF8), the initialization period Pico of the timing detection subfield SFo, the initialization period Piby of the y coordinate detection subfield SFy, and the x coordinate The gradient of the falling ramp waveform voltage generated in the initialization period Pidx of the detection subfield SFx is about −2.5 (V / μsec). The gradient of the first ramp waveform voltage generated at the end of each sustain period Ps1 to Ps8 of the image display subfield (subfields SF1 to SF8) and at the end of the timing detection period Po of the timing detection subfield SFo is about 10 ( V / μsec).

In the present embodiment, the specific numerical values such as the voltage value and the gradient described above are merely examples, and the present invention is not limited to the numerical values described above for each voltage value and the gradient. Each voltage value, gradient, and the like are preferably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device.

In the present embodiment, the reason why the timing detection subfield SFo is provided in one field and each drive voltage waveform of the timing detection subfield SFo is generated with the waveform shape shown in FIG. 4 is as follows.

In this embodiment, wireless communication is performed between the plasma display device and the light pen. Therefore, in the present embodiment, the light pen itself can generate a coordinate reference signal (a signal indicating the generation timing of the y-coordinate detection period Py and the x-coordinate detection period Px), and the timing detection subfield in one field. SFo is provided. In the timing detection subfield SFo, the light pen detects light emission generated at a specific time interval on the panel 10 by timing detection discharge, and generates a coordinate reference signal. Based on this coordinate reference signal, the light pen calculates the position coordinates of the light pen itself.

Further, in this embodiment, in order to increase the accuracy of generating the coordinate reference signal in the light pen, each drive voltage waveform of the timing detection subfield SFo is generated with the waveform shape shown in FIG. 4, and the time To0 is set to the time To1. Set to a longer time. Desirably, the time To0 is set to a time longer than any of the time To1, the time To2, and the time To3. This is due to the following reasons.

The light receiving element of the light pen also detects light emission generated by address discharge. Therefore, depending on the set value of time To0, the light pen may misrecognize the light emission generated by the address discharge in the address period Pwo of the timing detection subfield SFo as the light emission by the timing detection discharge.

However, if the time To0 is set to a time longer than the time To1, no matter where the light pen is in the image display area, the time from the time when the light pen detects light emission due to the write discharge to the time to1 The interval is longer than time To1. Thereby, it is possible to prevent the light pen from erroneously recognizing light emission due to the address discharge generated in the address period Pwo of the timing detection subfield SFo as light emission due to the timing detection discharge. If the time To0 is set to a time longer than any of the time To1, the time To2, and the time To3, the erroneous recognition can be prevented with higher accuracy, and the write in the image display area can be prevented. It becomes possible to detect the position (position coordinates) of the pen more accurately.

As described above, the image display device according to the present embodiment detects the position (positional coordinates) of the light pen in the image display area while displaying an image corresponding to the image signal on the panel 10 by the above-described operation. Discharge can be generated stably, and the position coordinates of the light pen can be calculated with high accuracy.

Next, the configuration of the image display system in the present embodiment will be described. In the following, a plasma display system using a plasma display device as an image display device will be described as an example of the image display system in this embodiment, and the configuration thereof will be described.

FIG. 5 is a diagram schematically showing an example of a circuit block and a plasma display system 30 constituting the plasma display device 100 according to the embodiment of the present invention.

The plasma display system 30 shown in the present embodiment includes a plasma display device 100 and a light pen 50 as components.

The plasma display device 100 includes a panel 10 and a driving circuit that drives the panel 10 with a plurality of subfields in one field. The drive circuit supplies power necessary for the image signal processing circuit 31, the data electrode drive circuit 32, the scan electrode drive circuit 33, the sustain electrode drive circuit 34, the timing generation circuit 35, the drawing circuit 44, the reception circuit 46, and each circuit block. A power supply circuit (not shown) for supplying is provided.

The image signal processing circuit 31 receives an image signal, a drawing signal output from the drawing circuit 44, and a timing signal supplied from the timing generation circuit 35. The image signal processing circuit 31 combines the image signal and the drawing signal in order to display an image obtained by combining the image signal and the drawing signal on the panel 10, and applies red, green to each discharge cell based on the combined signal. , Blue gradation values (gradation values expressed by one field) are set. Then, the image signal processing circuit 31 uses the red, green, and blue gradation values set for each discharge cell as image data indicating lighting / non-lighting for each subfield (light emission / non-light emission is “1” of the digital signal). , Data corresponding to “0”), and output the image data (red image data, green image data, and blue image data).

The timing generation circuit 35 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal. The generated timing signal is supplied to each circuit block (data electrode drive circuit 32, scan electrode drive circuit 33, sustain electrode drive circuit 34, image signal processing circuit 31, etc.).

Based on the image data output from the image signal processing circuit 31 and the timing signal supplied from the timing generation circuit 35, the data electrode driving circuit 32 performs the writing periods Pw1 to Pw1 of the subfields SF1 to SF8 which are image display subfields. In the writing period Pwo of Pw8 and the timing detection subfield SFo, the writing pulse of the voltage Vd is used, in the y coordinate detection period Py of the y coordinate detection subfield SFy, the y coordinate detection voltage Vdy is used, and in the x coordinate detection subfield SFx, the x coordinate detection period. In Px, an x-coordinate detection pulse of voltage Vdx is applied to each data electrode D1 to Dm.

Sustain electrode drive circuit 34 includes a sustain pulse generation circuit and a circuit (not shown in FIG. 5) for generating voltage Ve, and generates each drive voltage waveform based on the timing signal supplied from timing generation circuit 35. The voltage is applied to each of the sustain electrodes SU1 to SUn. In the sustain periods Ps1 to Ps8 of the subfields SF1 to SF8, which are image display subfields, the sustain pulse of the voltage Vs is used. In the timing detection period Po of the timing detection subfield SFo, the voltage Vso (equal to the voltage Vs in the present embodiment). ) Of the timing detection pulses V2 and V4, the voltage Vs in the erasing period Pedx of the x-coordinate detection subfield SFx, the initialization periods Pia1, Pib2 to Pib8 and the writing periods of the subfields SF1 to SF8 which are image display subfields. Pw1 to Pw8, timing detection subfield SFo initialization period Pico and writing period Pwo, y coordinate detection subfield SFy initialization period Piby and y coordinate detection period Py, and x coordinate detection subfield SFx initialization period Pidx x coordinate detection period A voltage Ve at x, it is applied to sustain electrodes SU1 ~ SUn.

Scan electrode drive circuit 33 includes a ramp waveform voltage generation circuit, a sustain pulse generation circuit, and a scan pulse generation circuit (not shown in FIG. 5), and each drive voltage waveform is based on a timing signal supplied from timing generation circuit 35. Is applied to each of scan electrodes SC1 to SCn. The ramp waveform voltage generating circuit, based on the timing signal, initializes the initialization periods Pia1, Pib2 to Pib8 and the sustain periods Pw1 to Pw8 of the subfields SF1 to SF8, which are image display subfields, and the initialization period of the timing detection subfield SFo. In Pico, the timing detection period Po, the initialization period Piby and the erasure period Peby of the y coordinate detection subfield SFy, and the initialization period Pidx and the erasure period Pedx of the x coordinate detection subfield SFx, the ramp waveform voltage is applied to the scan electrodes SC1 to SCn. Apply to. Based on the timing signal, the sustain pulse generating circuit generates sustain pulses in the sustain periods Ps1 to Ps8 of the subfields SF1 to SF8 that are image display subfields, and the voltage Vso (this implementation) in the timing detection period Po of the timing detection subfield SFo. In this embodiment, timing detection pulses V1 and V3 equal to the voltage Vs) are applied to the scan electrodes SC1 to SCn. The scan pulse generation circuit includes a plurality of scan electrode driving ICs (scan ICs), and based on the timing signal, the writing periods Pw1 to Pw8 of the subfields SF1 to SF8 that are image display subfields and the timing detection subfield Sfo In the writing period Pwo, scanning pulses of the voltage Vc and the voltage Va are used, in the y coordinate detection period Py of the y coordinate detection subfield SFy, the y coordinate detection pulse of the voltage Vc and voltage Vay is used, and the x coordinate detection period of the x coordinate detection subfield SFx. In Px, voltage Vc and x-coordinate detection voltage Vax are applied to scan electrodes SC1 to SCn.

The light pen 50 is used when the user inputs characters, drawings and the like in the image display area of the panel 10 by handwriting. The light pen 50 is formed in a rod shape and includes a light receiving element 52, a timing detection circuit 54, a coordinate calculation circuit 56, and a transmission circuit 58.

Although not shown in FIG. 5, the light pen 50 has a contact switch. The contact switch is provided at the tip of the light pen 50 and detects the contact when the light pen 50 contacts the front substrate 11 of the panel 10 (the image display surface of the panel 10).

The light receiving element 52 receives light emitted from the image display surface of the panel 10 and converts it into an electric signal (light receiving signal). Then, the light reception signal is output to the timing detection circuit 54 and the coordinate calculation circuit 56. In the present embodiment, the position coordinates (x, y) of the light pen 50 are positions where the light receiving element 52 receives light emitted from the image display surface.

The timing detection circuit 54, the coordinate calculation circuit 56, and the transmission circuit 58 have a period during which the contact switch detects contact (for example, a period during which the manual switch is turned on in a non-contact type light pen without a contact switch). The following operations are performed.

The timing detection circuit 54 detects light emission for timing detection (light emission generated by the timing detection discharge) generated in the timing detection period Po of the timing detection subfield SFo based on the light reception signal. Specifically, the timing detection circuit 54 measures a time interval of a plurality of (for example, five times) emission using a timer (not shown in FIG. 5) included in the timing detection circuit 54. Then, whether or not the time interval matches a predetermined time interval (for example, time To0, time To1, time To2, time To3) is determined by a plurality of threshold values (set in the timing detection circuit 54). For example, the determination is made by comparing the measured time interval with a threshold value corresponding to time To0, time To1, time To2, and time To3.

Then, the timing detection circuit 54 generates a coordinate reference signal based on one of the continuous plural times (for example, five times) of light emission. For example, in the example illustrated in FIG. 4, the coordinate reference signal is generated based on the light emission generated at the time to1 in the timing detection period Po of the timing detection subfield SFo.

The time to1 is the time when the first timing detection pulse V1 is applied to the scan electrodes SC1 to SCn in the timing detection period Po of the timing detection subfield SFo.

The coordinate reference signal is not shown in FIG. 4, but is, for example, a signal having rising edges at time ty0 and time tx0. Time ty0 is a time at which a y-coordinate detection pulse is applied to scan electrode SC1 in the first row in y-coordinate detection period Py of y-coordinate detection subfield SFy. Time tx0 is a time at which an x-coordinate detection pulse is applied to the data electrodes D1 to D3 corresponding to the first pixel column in the x-coordinate detection period Px of the x-coordinate detection subfield SFx.

Therefore, if the time to1 is known, a coordinate reference signal having rising edges at each of the time ty0 and the time tx0 can be generated.

Then, the timing detection circuit 54 outputs the coordinate reference signal to the coordinate calculation circuit 56.

In this embodiment, an example in which a coordinate reference signal is generated with reference to time to1 has been described, but the present invention is not limited to this configuration. The coordinate reference signal may be generated on the basis of the time to2 at which the second timing detection pulse V2 is generated, or the time to3 at which the third timing detection pulse V3 is generated or the fourth timing detection pulse V4. You may generate | occur | produce on the basis of the time to4 etc. which generate | occur | produce.

Also, the coordinate reference signal is not limited to a signal having rising edges at time ty0 and time tx0. The coordinate reference signal may be any signal that can be used as a reference for specifying the time when the light receiving element 52 receives light emission by the y coordinate detection pattern and light emission by the x coordinate detection pattern.

The coordinate calculation circuit 56 includes a counter that measures the length of time and an arithmetic circuit that performs an operation on the output of the counter (not shown in FIG. 5).

Then, based on the coordinate reference signal and the light reception signal, the coordinate calculation circuit 56 selectively extracts a signal indicating the light emission of the y coordinate detection pattern and a signal indicating the light emission of the x coordinate detection pattern from the light reception signal, and writes the light in the image display area. The position (x coordinate, y coordinate) of the pen 50 is calculated.

Specifically, the coordinate calculation circuit 56 counts the time (time Tyy) from time ty0 to the time (time tyy) from which light is first received by the light receiving element 52 after time ty0 based on the coordinate reference signal. Measure with Then, the time Tyy is divided by the time Ty1 (pulse width of the y coordinate detection pulse) in the arithmetic circuit. In this way, the y coordinate of the position of the light pen 50 in the image display area is calculated.

Next, the coordinate calculation circuit 56 measures, based on the coordinate reference signal, a time (time Txx) from time tx0 to time (time txx) when light is first received by the light receiving element 52 after time tx0. To do. Then, the time Txx is divided by the time Tx1 (pulse width of the x coordinate detection pulse) in the arithmetic circuit. In this way, the x coordinate of the position of the light pen 50 in the image display area is calculated.

The time tyy is the time when the light receiving element 52 of the light pen 50 receives light emitted from the panel 10 by the y coordinate detection pattern, and the time txx is the time when the light receiving element 52 of the light pen 50 receives the panel 10 by the x coordinate detection pattern. It is the time when the light emission generated in

The coordinate calculation circuit 56 outputs the position coordinates (x, y) of the light pen 50 calculated in this way to the transmission circuit 58.

The transmission circuit 58 has a transmission circuit that encodes an electric signal and converts the encoded signal into a radio signal such as infrared rays and transmits the signal (not shown in FIG. 5). Then, a signal representing the position (coordinates (x, y)) of the light pen 50 calculated by the coordinate calculation circuit 56 is encoded, converted into a wireless signal, and wirelessly transmitted to the reception circuit 46 of the plasma display device 100.

The light pen 50 is configured to perform the above-described operation even during a period in which the contact switch does not detect contact (in a non-contact type light pen without a contact switch, for example, a period in which the manual switch is turned off). May be.

The reception circuit 46 includes a conversion circuit that receives a wireless signal wirelessly transmitted from the transmission circuit 58 of the light pen 50, decodes the received signal, and converts it into an electrical signal (not shown in FIG. 5). The wireless signal wirelessly transmitted from the transmission circuit 58 is converted into a signal representing the position (x coordinate, y coordinate) of the light pen 50 and output to the drawing circuit 44.

The drawing circuit 44 includes an image memory 47 (referred to as memory in FIG. 5). The drawing circuit 44 generates a drawing signal for indicating the locus of the light pen 50 in the image display area of the panel 10 based on the signal received by the receiving circuit 46 (x coordinate and y coordinate calculated by the coordinate calculation circuit 56). To do. The drawing signal is a signal for displaying on the panel 10 an image or the like handwritten by the user, and is substantially the same as the image signal. The drawing signal is stored in the image memory 47. As a result, a drawing signal obtained by adding the current position coordinates of the light pen 50 to the past locus of the light pen 50 is accumulated in the image memory 47. The drawing circuit 44 outputs the drawing signal accumulated in the image memory 47 to the image signal processing circuit 31.

As described above, the image signal processing circuit 31 synthesizes the drawing signal output from the drawing circuit 44 and the image signal, converts the image signal into image data, and outputs the image data to a subsequent circuit. In this way, the graphic input handwritten by the light pen 50 is combined with the image based on the image signal and displayed on the panel 10.

In addition, in order to erase the locus of the light pen 50 shown on the panel 10, the light pen 50 may be provided with a switch for switching between the “drawing” mode and the “erasing” mode. When the light pen 50 is in the “erase” mode, the trace of the light pen 50 shown on the panel 10 is traced with the light pen 50 again, so that the drawing signal stored in the image memory 47 can be partially or totally. To erase. For example, the light pen may be configured in this way.

The light pen 50 is configured so that the light receiving element 52 converts the received light emission into a light reception signal and outputs it to a subsequent circuit only when the tip of the light pen 50 is in contact with the image display surface of the panel 10. It may be.

Next, the scan electrode drive circuit 33, the sustain electrode drive circuit 34, and the data electrode drive circuit 32 of the plasma display apparatus 100 will be described.

FIG. 6 is a circuit diagram schematically showing a configuration example of the scan electrode driving circuit 33 of the plasma display device 100 according to the embodiment of the present invention.

The scan electrode drive circuit 33 includes a sustain pulse generation circuit 55, a ramp waveform voltage generation circuit 60, and a scan pulse generation circuit 70. Each circuit block operates based on the timing signal supplied from the timing generation circuit 35, but details of the timing signal path are omitted in FIG. Hereinafter, the voltage input to the scan pulse generation circuit 70 is referred to as “reference potential A”.

Sustain pulse generation circuit 55 has power recovery circuit 51, switching element Q55, switching element Q56, and switching element Q59. The power recovery circuit 51 includes a power recovery capacitor C10, a switching element Q11, a switching element Q12, a backflow prevention diode Di11, a diode Di12, a resonance inductor L11, and an inductor L12.

The power recovery circuit 51 recovers the power stored in the panel 10 from the panel 10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L12, and stores it in the capacitor C10. Then, the recovered power is supplied to the panel 10 again from the capacitor C10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L11, and reused as power when driving the scan electrodes SC1 to SCn.

Switching element Q55 clamps scan electrodes SC1 to SCn to voltage Vs, and switching element Q56 clamps scan electrodes SC1 to SCn to voltage 0 (V). The switching element Q59 is a separation switch, and prevents a current from flowing back through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 33.

Scan pulse generation circuit 70 has switching elements Q71H1 to Q71Hn, switching elements Q71L1 to Q71Ln, switching element Q72, a power supply for generating negative voltage Va, and a power supply E71 for generating voltage Vp. Then, a voltage Vp (Vc = Va + Vp) is generated by superimposing the voltage Vp on the reference potential A of the scan pulse generating circuit 70, and applied to the scan electrodes SC1 to SCn while switching between the voltage Va and the voltage Vc. Is generated. For example, if the voltage Va = −200 (V) and the voltage Vp = 150 (V), the voltage Vc = −50 (V).

The scan pulse generation circuit 70 sequentially applies scan pulses to the scan electrodes SC1 to SCn at the timings shown in FIGS. Scan pulse generation circuit 70 outputs the output voltage of sustain pulse generation circuit 55 as it is during the sustain period. That is, the reference potential A is output to scan electrodes SC1 to SCn.

Further, the scan pulse generation circuit 70 generates y coordinate detection pulses of the voltage Vc and the voltage Vay (= voltage Va) in the y coordinate detection period Py of the y coordinate detection subfield SFy at the timing shown in FIG. In the x-coordinate detection period Px of the coordinate detection subfield SFx, a voltage Vc and an x-coordinate detection voltage Vax (= voltage Va) are generated and applied to the scan electrodes SC1 to SCn.

The ramp waveform voltage generation circuit 60 includes a Miller integration circuit 61, a Miller integration circuit 62, and a Miller integration circuit 63, and generates the ramp waveform voltage shown in FIGS.

Miller integrating circuit 61 includes transistor Q61, capacitor C61, and resistor R61. Then, by applying a constant voltage to the input terminal IN61 (giving a constant voltage difference between two circles illustrated as the input terminal IN61), the voltage gradually rises toward the voltage Vt (= voltage Vi2). Up-slope waveform voltage (initialization period Pia1 of subfield SF1, which is an image display subfield, initialization period Pico of timing detection subfield SFo, erase period Peby of y coordinate detection subfield SFy, and x coordinate detection subfield SFx The rising ramp waveform voltage generated in each period of the erasing period Pedx) is generated.

Alternatively, the voltage Vt may be set so that a voltage obtained by superimposing the voltage Vp on the voltage Vt is equal to the voltage Vi2. In this configuration, when Miller integrating circuit 61 is operated, switching element Q72 and switching elements Q71L1 to Q71Ln are turned off, switching elements Q71H1 to Q71Hn are turned on, and the rising ramp waveform voltage generated in Miller integrating circuit 61 is turned on. The up slope waveform voltage for the initialization operation can be generated by superimposing the voltage Vp of the power source E71 on the top.

Miller integrating circuit 62 includes transistor Q62, capacitor C62, resistor R62, and diode Di62 for preventing backflow. Then, by applying a constant voltage to the input terminal IN62 (giving a constant voltage difference between two circles shown as the input terminal IN62), an up-slope waveform voltage that gradually rises toward the voltage Vr ( The initialization period Pia1 of the subfield SF1, which is an image display subfield, the end of the sustain periods Ps1 to Ps8 of the subfields SF1 to SF8, the end of the timing detection period Po of the timing detection subfield SFo, and the y coordinate detection subfield SFy An upward ramp waveform voltage generated in each period of the erasing period Peby and the erasing period Pedx of the x-coordinate detection subfield SFx is generated.

Miller integrating circuit 63 includes transistor Q63, capacitor C63, and resistor R63. Then, by applying a constant voltage to the input terminal IN63 (giving a constant voltage difference between two circles shown as the input terminal IN63), a downward ramp waveform voltage (gradiently decreasing toward the voltage Vi4 ( Initialization periods Pia1, Pib2 to Pib8 of the subfields SF1 to SF8 which are image display subfields, an initialization period Pico of the timing detection subfield SFo, an initialization period Piby of the y coordinate detection subfield SFy, and an x coordinate detection sub A downward ramp waveform voltage generated in each period of the initialization period Pidx of the field SFx).

Note that the switching element Q69 is a separation switch, and prevents a current from flowing back through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 33.

Note that these switching elements and transistors can be configured using generally known semiconductor elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the respective switching elements and transistors generated by the timing generation circuit 35.

FIG. 7 is a circuit diagram schematically showing a configuration example of the sustain electrode drive circuit 34 of the plasma display apparatus 100 according to the embodiment of the present invention.

The sustain electrode driving circuit 34 includes a sustain pulse generating circuit 80 and a constant voltage generating circuit 85. Each circuit block operates based on the timing signal supplied from the timing generation circuit 35, but details of the timing signal path are omitted in FIG.

Sustain pulse generation circuit 80 has a power recovery circuit 81, a switching element Q83, and a switching element Q84. The power recovery circuit 81 includes a power recovery capacitor C20, a switching element Q21, a switching element Q22, a backflow prevention diode Di21, a diode Di22, a resonance inductor L21, and an inductor L22.

The power recovery circuit 81 recovers the power stored in the panel 10 from the panel 10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L22, and stores it in the capacitor C20. Then, the recovered power is supplied to the panel 10 again from the capacitor C20 by LC resonance between the interelectrode capacitance of the panel 10 and the inductor L21, and is reused as power when driving the sustain electrodes SU1 to SUn.

Switching element Q83 clamps sustain electrodes SU1 to SUn to voltage Vs, and switching element Q84 clamps sustain electrodes SU1 to SUn to voltage 0 (V).

Thus, sustain pulse generating circuit 80 generates a sustain pulse of voltage Vs and applies it to sustain electrodes SU1 to SUn. Further, the timing detection pulses V2 and V4 are applied to the sustain electrodes SU1 to SUn in the timing detection period Po of the timing detection subfield SFo, and the voltage Vs is applied in the erasure period Pedx of the x coordinate detection subfield SFx.

The constant voltage generation circuit 85 includes a switching element Q86 and a switching element Q87. Then, the constant voltage generation circuit 85 writes the initialization periods Pia1, Pib2 to Pib8 and the writing periods Pw1 to Pw8 of the subfields SF1 to SF8, which are image display subfields, and the initialization period Pico and the writing of the timing detection subfield SFo. During the period Pwo, the initialization period Pby and y coordinate detection period Py of the y coordinate detection subfield SFy, and the initialization period Pidx and x coordinate detection period Px of the x coordinate detection subfield SFx, the voltage Ve is applied to the sustain electrodes SU1 to SUn. Apply.

It should be noted that all of these switching elements of sustain electrode drive circuit 34 may be turned off in order to set sustain electrodes SU1 to SUn to a high impedance state.

In addition, these switching elements can be configured using generally known elements such as MOSFETs and IGBTs. These switching elements are controlled by timing signals corresponding to the respective switching elements generated by the timing generation circuit 35.

FIG. 8 is a circuit diagram schematically showing a configuration example of the data electrode driving circuit 32 of the plasma display device 100 according to the embodiment of the present invention.

The data electrode drive circuit 32 operates based on the image data supplied from the image signal processing circuit 31 and the timing signal supplied from the timing generation circuit 35. In FIG. 8, details of the paths of these signals are omitted. To do.

The data electrode drive circuit 32 includes switching elements Q91H1 to Q91Hm and switching elements Q91L1 to Q91Lm. Then, voltage 0 (V) is applied to data electrode Dj by turning on switching element Q91Lj, and voltage Vd is applied to data electrode Dj by turning on switching element Q91Hj. In this way, the data electrode driving circuit 32 applies the write pulse of the voltage Vd to the write period Pwo of the subfields SF1 to SF8 which are image display subfields and the write period Pwo of the timing detection subfield SFo. In the y-coordinate detection period Py of SFy, the y-coordinate detection voltage Vdy (= voltage Vd) is used, and in the x-coordinate detection period Px of the x-coordinate detection subfield SFx, the x-coordinate detection pulse of the voltage Vdx (= voltage Vd) is used. Applied to D1 to Dm.

It should be noted that in order to set the data electrodes D1 to Dm in a high impedance state, all of these switching elements included in the data electrode driving circuit 32 may be turned off.

Next, the operation of the plasma display system 30 which is an example of the image display system in the present embodiment will be described.

FIG. 9 is a diagram schematically showing an example of the operation when detecting the position coordinates of the light pen 50 in the plasma display system 30 according to the embodiment of the present invention. In FIG. 9, the image display area is indicated by a broken line, but this broken line is not actually displayed on the panel 10.

FIG. 10 is a diagram schematically showing an example of a driving voltage waveform when the position coordinates of the light pen 50 are detected in the plasma display system 30 according to the embodiment of the present invention.

FIG. 10 shows scan electrode SC1, scan electrode SCn, data electrode D1, and data in timing detection subfield SFo, y-coordinate detection subfield SFy, and x-coordinate detection subfield SFx following image display subfield SF8. A driving voltage waveform applied to each of the electrodes Dm, a coordinate reference signal input to the coordinate calculation circuit 56, and a light reception signal output from the light receiving element 52 are shown. In FIG. 10, the drive voltage waveforms applied to sustain electrodes SU1 to SUn are omitted, but the drive voltage waveforms shown in FIG. 10 are the same as the drive voltage waveforms shown in FIGS.

In plasma display device 100 in the present embodiment, time Toy from time to1 to time ty0 is determined in advance, and time Tox from time to1 to time tx0 is determined in advance.

Therefore, when the time to1 can be specified, the timing detection circuit 54 can generate a coordinate reference signal having rising edges at each of the time ty0 and the time tx0 and output it to the coordinate calculation circuit 56 as shown in FIG. it can.

At time to1, as described above, the timing detection circuit 54 emits light of five consecutive times in which the intervals of light emission are time To0, time To1, time To2, and time To3 (output from the light receiving element 52 based on these light emission). Is detected by detecting the received light signal).

In the y-coordinate detection period Py of the y-coordinate detection subfield SFy, a y-coordinate detection pattern in which linear light emission extended in the first direction (row direction) sequentially moves in the second direction (column direction) is displayed on the panel 10. To display. Accordingly, as shown in FIG. 9, one horizontal line Ly that sequentially moves from the upper end (first row) to the lower end (nth row) of the image display region is displayed in the image display region of the panel 10. Is done.

If the tip of the light pen 50 is in contact with (or close to) the “coordinates (x, y)” of the image display surface of the panel 10, at the time tyy when the horizontal line Ly passes the coordinates (x, y), the light The light receiving element 52 of the pen 50 receives the light emission of the horizontal line Ly. Thereby, as shown in FIG. 10, the light pen 50 outputs a light reception signal indicating that the light receiving element 52 has received the light emission of the horizontal line Ly at time tyy.

In the subsequent x-coordinate detection period Px of the x-coordinate detection subfield SFx, an x-coordinate detection pattern in which linear light emission extended in the second direction (column direction) sequentially moves in the first direction (row direction) is displayed on the panel. 10 is displayed. Accordingly, as shown in FIG. 9, the image display area of the panel 10 is sequentially moved from the left end portion (first pixel column) to the right end portion (m / 3 pixel row) of the image display area. One vertical line Lx is displayed.

If the tip of the light pen 50 is in contact with (or close to) the “coordinate (x, y)” of the image display surface of the panel 10, at the time txx when the vertical line Lx passes the coordinate (x, y), The light receiving element 52 of the light pen 50 receives the light emission of the vertical line Lx. Accordingly, as shown in FIG. 10, the light pen 50 outputs a light reception signal indicating that the light receiving element 52 has received the light emission of the vertical line Lx at time txx.

The coordinate calculation circuit 56 shown in FIG. 5 is based on the coordinate reference signal output from the timing detection circuit 54 and the light reception signal output from the light receiving element 52 in the y coordinate detection period Py of the y coordinate detection subfield SFy. The time Tyy from the time ty0 to the time tyy is measured using the counter provided for. The time Tyy is divided by the time Ty1 in the arithmetic circuit provided inside. The division result is the y coordinate of the position of the light pen 50 in the image display area.

The coordinate calculation circuit 56 is provided internally based on the coordinate reference signal output from the timing detection circuit 54 and the light reception signal output from the light receiving element 52 in the x coordinate detection period Px of the x coordinate detection subfield SFx. A time Txx from time tx0 to time txx is measured using a counter. Then, the time Txx is divided by the time Tx1 in the arithmetic circuit provided inside. This division result is the x coordinate of the position of the light pen 50 in the image display area.

In this way, the coordinate calculation circuit 56 in the present embodiment calculates the position (coordinates (x, y)) of the light pen 50 in the image display area.

FIG. 11 is a diagram schematically showing an example of an operation when handwriting input is performed with the light pen 50 in the plasma display system 30 according to the embodiment of the present invention. In FIG. 11, the image display area is indicated by a broken line, but this broken line is not actually displayed on the panel 10.

The drawing circuit 44 outputs a drawing signal of a drawing pattern (for example, a pattern such as a white circle) having a predetermined color and size around a pixel corresponding to the coordinates (x, y) calculated by the coordinate calculation circuit 56. Write to memory 47.

When the user moves the light pen 50 while the tip of the light pen 50 is in contact with the image display surface of the panel 10, the coordinates (x, y) calculated by the coordinate calculation circuit 56 also correspond to the movement of the light pen 50. Change.

The drawing circuit 44 sequentially writes a drawing signal corresponding to the drawing pattern whose position has changed in the image memory 47 while changing the position of the drawing pattern in accordance with the changing coordinates (x, y).

In this way, the drawing signal indicating the locus of the light pen 50 is accumulated in the image memory 47 of the drawing circuit 44. The drawing signal stored in the image memory 47 is read for each field and output to the image signal processing circuit 31.

The image signal processing circuit 31 combines the drawing signal output from the drawing circuit 44 and the image signal, and generates image data based on the combined signal. Thus, as shown in FIG. 11, the panel 10 displays an image in which an image indicating the locus of the light pen 50 (a graphic input by handwriting using the light pen 50) is superimposed on the image signal.

As described above, since the image display system (for example, the plasma display system 30) in the present embodiment can generate a stable discharge, the y coordinate detection pattern and the x coordinate detection pattern with high accuracy are displayed on the panel 10. Can be displayed.

Thereby, the light pen 50 can calculate the position coordinates (x coordinate, y coordinate) with higher accuracy. Therefore, in the plasma display system 30 in the present embodiment, the locus of the light pen 50 can be drawn based on accurate position coordinates.

In the present embodiment, an example has been described in which the timing detection discharge is generated four times at predetermined time intervals (for example, time To1, time To2, and time To3) in the timing detection subfield SFo. The number of timing detection discharges may be two or more.

In the present embodiment, it is desirable to set the time intervals for generating the timing detection discharge a plurality of times in order to easily identify the first timing detection discharge.

In the present embodiment, the configuration in which the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx are provided in each field has been described. However, the present invention is not limited to this configuration. Absent. For example, the configuration may be such that those subfields are generated at a rate of once in a plurality of fields.

In this embodiment, an example in which wireless communication is performed between the plasma display device and the light pen has been described, but the present invention is not limited to this configuration. For example, the plasma display device and the light pen may be electrically connected by an electric cable or the like, and a signal may be transmitted and received between the light pen and the plasma display device via the electric cable. In that case, the timing detection subfield SFo may not be provided.

In the embodiment of the present invention, each operation has been described by taking a plasma display device using a plasma display panel as an image display unit as an example of the image display device. However, in the present invention, the image display device is not limited to the plasma display device. For example, even in an image display device using a liquid crystal panel, an organic EL panel, an LED panel, or the like, the same effect as that described above can be obtained by applying the same configuration as that described above.

In the embodiment of the present invention, a configuration in which one field has a plurality of image display subfields and a subfield for detecting position coordinates has been described. However, the present invention is not limited to this configuration. is not. For example, when the user does not use the light pen, one field may be composed of only the image display subfield.

In the embodiment of the present invention, the forced initializing operation has been described as an initializing operation that forcibly generates initializing discharge in all the discharge cells in the image display area of the panel. It is not limited to this configuration. In the embodiment of the present invention, the forced initializing waveform is applied only to some discharge cells in the image display area of the panel and the initializing discharge is forcibly generated only in the discharge cells. It shall be included in the conversion operation.

In the embodiment of the present invention, a configuration in which the drawing circuit 44 is provided in the plasma display device is shown, but the present invention is not limited to this configuration. For example, a computer connected to the plasma display device may have a function corresponding to the drawing circuit 44, and a drawing signal may be generated using the computer.

In this embodiment, an example in which a contact-type light pen capable of handwriting input only when touching the panel is used in the image display system is described, but the present invention is not limited to this configuration. Even in an image display system using a non-contact type light pen capable of handwriting input even when not touching the panel, the same configuration as the above-described configuration can be applied, and the same effect as the above-described effect can be obtained. be able to.

The drive voltage waveforms shown in FIGS. 3, 4, and 10 are merely examples in the embodiment of the present invention, and the present invention is not limited to these drive voltage waveforms.

Further, the circuit configurations shown in FIGS. 5, 6, 7, and 8 are merely examples in the embodiment of the present invention, and the present invention is not limited to these circuit configurations. .

Each circuit block shown in the embodiment of the present invention may be configured as an electric circuit that performs each operation shown in the embodiment, or substantially the same as each operation shown in the embodiment. A microcomputer or a computer programmed to operate may be used.

The specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the panel 10 having a screen size of 50 inches and the number of display electrode pairs 14 of 1024. It is just an example. The present invention is not limited to these numerical values, and each numerical value is desirably set optimally in accordance with panel specifications, panel characteristics, plasma display device specifications, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.

Since the present invention can stably generate a discharge for detecting the position coordinates of the light pen and accurately detect the position coordinates of the light pen, the driving method of the image display apparatus, the image display apparatus, and the image display Useful as a system.

DESCRIPTION OF SYMBOLS 10 Panel 11 Front substrate 12 Scan electrode 13 Sustain electrode 14 Display electrode pair 15, 23 Dielectric layer 16 Protective layer 21 Back substrate 22 Data electrode 24 Partition 25, 25R, 25G, 25B Phosphor layer 30 Plasma display system 31 Image signal processing Circuit 32 Data electrode drive circuit 33 Scan electrode drive circuit 34 Sustain electrode drive circuit 35 Timing generation circuit 44 Drawing circuit 46 Reception circuit 47 Image memory 50 Light pen 51, 81 Power recovery circuit 52 Light receiving element 54 Timing detection circuit 55, 80 Sustain pulse Generation circuit 56 Coordinate calculation circuit 58 Transmission circuit 60 Ramp waveform voltage generation circuit 61, 62, 63 Miller integration circuit 70 Scanning pulse generation circuit 85 Constant voltage generation circuit 100 Plasma display device Lx Vertical line Ly Horizontal Di11, Di12, Di21, Di22, Di62 Diodes L11, L12, L21, L22 Inductors Q11, Q12, Q21, Q22, Q55, Q56, Q59, Q69, Q72, Q83, Q84, Q86, Q87, Q71H1 to Q71Hn, Q71L1 to Q71Ln, Q91H1 to Q91Hm, Q91L1 to Q91Lm Switching element C10, C20, C61, C62, C63 Capacitor R61, R62, R63 Resistor Q61, Q62, Q63 Transistor IN61, IN62, IN63 Input terminal E71 Power supply SFx x Coordinate detection subfield SFy y Coordinate detection subfield SFo Timing detection subfield SF1 to SF8 Image display subfield

Claims (10)

1. A method of driving an image display device including an image display unit having a plurality of scan electrodes and sustain electrodes and a plurality of data electrodes,
   Generating a field having an image display subfield, a y-coordinate detection subfield, and an x-coordinate detection subfield, and making the y-coordinate detection subfield or the x-coordinate detection subfield a subfield generated at the end of the field;
   The image display subfield has a sustain period in which an upward ramp waveform voltage rising to a first voltage is applied to the scan electrode after alternately applying a sustain pulse to the scan electrode and the sustain electrode;
   The y-coordinate detection subfield or the x-coordinate detection subfield generated at the end of the field generates an up-slope waveform voltage and a down-slope waveform voltage that rise to a second voltage that is higher than the first voltage. A driving method of an image display device, characterized by having an erasing period applied to the display.
2. 2. The image according to claim 1, wherein the y-coordinate detection subfield and the x-coordinate detection subfield have an erasing period in which an upward ramp waveform voltage that rises to the second voltage is applied to the scan electrode. A driving method of a display device.
3. 2. The image display according to claim 1, wherein the x coordinate detection subfield is generated immediately after the y coordinate detection subfield, and the x coordinate detection subfield is a subfield generated at the end of the field. Device driving method.
4. 2. The image display device according to claim 1, wherein in the erasing period, the data electrode is set in a high impedance state while an upward ramp waveform voltage rising to the second voltage is applied to the scan electrode. Driving method.
5. The rising ramp waveform voltage rising to the second voltage in the erasing period includes an rising ramp waveform voltage rising to the first voltage, and an rising ramp waveform voltage rising from the voltage lower than the first voltage to the second voltage. 2. The driving method of an image display device according to claim 1, wherein the driving method has a waveform shape including two rising ramp waveform voltages of the ramp waveform voltage.
6. 3. The method of driving an image display device according to claim 2, wherein the erasing period is generated at the end of the y-coordinate detection subfield, and the erasing period is generated at the end of the x-coordinate detection subfield.
7. An image display device comprising: an image display unit having a plurality of scan electrodes, sustain electrodes, and a plurality of data electrodes; and a drive circuit configured to drive one of the plurality of subfields to drive the image display unit. ,
   The drive circuit is
   Generating a field having an image display subfield, a y-coordinate detection subfield, and an x-coordinate detection subfield, and generating the y-coordinate detection subfield or the x-coordinate detection subfield at the end of the field;
   In the sustain period of the image display subfield, an upward ramp waveform voltage that rises to a first voltage after applying a sustain pulse alternately to the scan electrode and the sustain electrode is applied to the scan electrode,
   Ascending ramp waveform voltage and descending ramp waveform voltage rising to a second voltage higher than the first voltage are applied to the scan electrode in the y coordinate detection subfield or the x coordinate detection subfield generated at the end of the field. An image display device characterized by providing an erasing period to be applied to the display.
8. The drive circuit is
   8. The image according to claim 7, wherein an erasing period in which an ascending waveform voltage rising to the second voltage is applied to the scan electrode is provided in the y coordinate detection subfield and the x coordinate detection subfield. 9. Display device.
9. The drive circuit is
   The image display according to claim 7, wherein the x-coordinate detection subfield is generated immediately after the y-coordinate detection subfield, and the x-coordinate detection subfield is a subfield generated at the end of the field. apparatus.
10. An image display system including an image display device having an image display unit having a plurality of scan electrodes and sustain electrodes and a plurality of data electrodes, a light pen, a coordinate calculation circuit, and a drawing circuit,
    The image display device includes:
    Generating a field having an image display subfield, a y-coordinate detection subfield, and an x-coordinate detection subfield, and generating the y-coordinate detection subfield or the x-coordinate detection subfield at the end of the field;
    In the sustain period of the image display subfield, an upward ramp waveform voltage that rises to a first voltage after applying a sustain pulse alternately to the scan electrode and the sustain electrode is applied to the scan electrode,
    Ascending ramp waveform voltage and descending ramp waveform voltage rising to a second voltage higher than the first voltage are applied to the scan electrode in the y coordinate detection subfield or the x coordinate detection subfield generated at the end of the field. An erasing period to be applied to
    The light pen receives light emission generated in the image display unit in the y coordinate detection subfield and light emission generated in the image display unit in the x coordinate detection subfield, and outputs a light reception signal,
    The coordinate calculation circuit is configured to, based on the light reception signal, a coordinate indicating a light emission position received by the light pen among light emission generated in the image display unit in the y coordinate detection subfield, and in the x coordinate detection subfield. Calculate coordinates indicating the position of light emission received by the light pen among the light emission generated in the image display unit,
    The drawing circuit creates a drawing signal for displaying an image based on the coordinates calculated by the coordinate calculation circuit on the image display unit,
    The image display system displays an image based on the drawing signal on the image display unit.

Images