WO2013139128A1 - Transistor en couches minces de type n (n-tft) du type à grille supérieure, plaque de base de réseau, procédé de fabrication de celui-ci et unité d'affichage - Google Patents

Transistor en couches minces de type n (n-tft) du type à grille supérieure, plaque de base de réseau, procédé de fabrication de celui-ci et unité d'affichage Download PDF

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Publication number
WO2013139128A1
WO2013139128A1 PCT/CN2012/084118 CN2012084118W WO2013139128A1 WO 2013139128 A1 WO2013139128 A1 WO 2013139128A1 CN 2012084118 W CN2012084118 W CN 2012084118W WO 2013139128 A1 WO2013139128 A1 WO 2013139128A1
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Prior art keywords
tft
gate
region
photoresist
thickness
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PCT/CN2012/084118
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English (en)
Chinese (zh)
Inventor
胡理科
祁小敬
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2013139128A1 publication Critical patent/WO2013139128A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors

Definitions

  • Embodiments of the present invention relate to a top gate type N-TFT, an array substrate, a method of fabricating the same, and a display device. Background technique
  • Liquid crystal display technologies include amorphous silicon thin film transistor liquid crystal displays (a-Si TFT LCDs) and low temperature polysilicon liquid crystal displays (Low temperature Polysilicon LTPS LCDs).
  • a-Si TFT LCDs amorphous silicon thin film transistor liquid crystal displays
  • Low temperature Polysilicon LTPS LCDs Low temperature Polysilicon LTPS LCDs
  • amorphous silicon thin film transistor liquid crystal displays are difficult to meet the requirements of lightness, power saving and high image quality; while low temperature polycrystalline silicon liquid crystal displays have fast picture refreshing speed and high brightness. High definition and other advantages. Therefore, low-temperature polysilicon liquid crystal displays are increasingly becoming mainstream products of liquid crystal displays.
  • the preparation process of the array substrate in the low-temperature polysilicon liquid crystal display is complicated, and usually requires 8-10 patterning processes to complete, and when the channel region and the lightly doped region of the N-TFT are doped, two steps are required. Doping process, complex process. These reduce the yield and production efficiency of the array substrate and also increase the production cost. Summary of the invention
  • One aspect of the present invention provides a top gate type N-type thin film transistor (N-TFT) including a microdoped N-TFT channel region, a gate thickness of the top gate type N-TFT, and a gate insulating layer The thickness allows the gate and gate insulating layers to block the partially doped ions while performing the doping process to obtain the N-TFT lightly doped regions to obtain a microdoped N-TFT channel region.
  • N-TFT top gate type N-type thin film transistor
  • the material of the gate of the top gate type N-TFT is aluminum, germanium or aluminum germanium alloy, and the thickness of the top gate type N-TFT is 30 to 50 nm.
  • the gate insulating layer material is a SiNx layer, a SiO 2 layer, or a composite layer of SiNx and SiO 2 , and the gate insulating layer has a thickness of 10 to 100 nm.
  • the array substrate further includes a top gate type P-type thin film crystal A tube (P-TFT) having a thickness of a gate of the P-TFT greater than a thickness of the gate of the N-TFT.
  • P-TFT top gate type P-type thin film crystal A tube
  • the array substrate further includes a top gate type P-TFT,
  • the thickness of the gate of the P-TFT is the same as the thickness of the gate of the N-TFT.
  • Still another aspect of the invention provides a display device comprising the array substrate of any of the above.
  • a further aspect of the present invention provides a method for fabricating a top gate type N-TFT, comprising: step S1, forming an N-TFT heavily doped region;
  • Step S2 forming a gate insulating layer, a gate, and then forming a N-TFT lightly doped region and a microdoped N-TFT channel region by a doping process, wherein the gate thickness and the thickness of the gate insulating layer enable The doping process is performed to obtain an N-TFT lightly doped region while blocking a portion of the doped ions to obtain a microdoped N-TFT channel region.
  • the method for preparing the top gate type N-TFT further includes: Step S3, forming an interlayer insulating layer;
  • Step S4 forming a source/drain electrode.
  • Still another aspect of the invention provides a method of fabricating an array substrate, comprising the method of preparing an N-TFT according to any of the above.
  • the method for fabricating the array substrate further includes: S5, forming a passivation layer and a pixel electrode on the substrate on which the N-TFT is formed.
  • the array substrate includes a top gate type P-TFT
  • the gate electrode is formed by a halftone mask or a gray scale mask process in the S2 step, and is light on the N-TFT
  • the photoresist covering the gate of the N-TFT is completely removed, and the photoresist covering the gate of the P-TFT is left, for the N-TFT
  • the gate is etched to reduce the thickness of the N-TFT gate, and then the photoresist covering the gate of the P-TFT is completely removed, and then the N-TFT lightly doped region and the N-TFT channel region are performed. Doping.
  • the array substrate includes a top gate type P-TFT, and a halftone mask or a gray scale mask process is formed when the gate is formed in the step S2, and the N-TFT lightly doped region and the N-TFT are used.
  • the channel region is doped, the photoresist covering the gate of the N-TFT is completely removed, and the photoresist covering the gate of the P-TFT is left, and the overlying layer is removed after the doping process is completed.
  • the method for preparing the array substrate further includes: forming a buffer layer on the substrate before performing the S1 step.
  • Array substrate provided by embodiment of the present invention, manufacturing method thereof and display device thereof
  • the thickness of the N-TFT gate and the gate insulating layer is achieved by using a one-step doping process to simultaneously obtain the lightly doped region and the channel region of the N-TFT, and a halftone or grayscale mask process is employed in the patterning process.
  • the preparation of the array substrate can be realized by using seven patterning processes, which simplifies the process flow and improves the production efficiency.
  • FIG. 1 is a schematic structural view of a top gate type N-TFT provided by the present invention.
  • FIG. 2 is a schematic structural view of an array substrate provided by the present invention.
  • FIG. 5 is a flow chart of a method for preparing an array substrate provided by the present invention.
  • Figure 6.1 to Figure 6.11 are schematic cross-sectional views showing respective steps in the method of fabricating the array substrate provided by the present invention. detailed description
  • FIG. 1 is a schematic structural diagram of a top gate type N-type thin film transistor (N-TFT) according to an embodiment of the present invention.
  • the top gate type N-TFT includes an N-TFT heavily doped region 306, an N-TFT lightly doped region 308, a microdoped N-TFT channel region 309, and a gate 311 of the N-TFT.
  • the thickness of the gate 311 of the N-TFT and the gate insulation of the N-TFT are set.
  • the thickness of the layer 60 is such that the gate 311 of the N-TFT and the gate insulating layer 60 of the N-TFT block a portion of the dopant ions from entering the N-TFT channel region 309, thereby doping the N-TFT lightly doped region 308.
  • the micro-doping of the N-TFT channel region 309 is achieved at the same time.
  • the N-TFT channel region 309 can be realized by changing the thickness of the gate and the gate insulating layer without changing the power and concentration of the doping device. Partial occlusion of the doped ions, the doping concentration of the microdoped N-TFT channel region 309 is different from that of the N-TFT lightly doped region 308 in the one-step doping process, and the N-TFT lightly doped region 308 is obtained. And a microdoped N-TFT channel region 309.
  • the gate thickness of the N-TFT is 30 to 50 nm.
  • the thickness of the gate electrode can be selected to be 35 ⁇ , 40 nm or 45 nm.
  • the gate insulating layer is preferably a SiNx layer, a SiO 2 layer or a composite layer formed of SiNx and SiO 2 ; preferably, the gate insulating layer has a thickness of 10 to 100 nm.
  • the thickness of the gate insulating layer may be selected from 50 nm, 70 ⁇ , and 90 nm.
  • the gate of the N-TFT may be thinned by etching or the like during the preparation process to achieve partial doping ions into the N.
  • - TFT channel region 309 reaches the desired doping concentration.
  • FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • the array substrate includes a base substrate 10, and a buffer layer 20 and a top gate type N-TFT which are sequentially formed on the base substrate 10.
  • the top gate type N-TFT in this embodiment uses a top gate type N-TFT as shown in FIG.
  • the gate 311 of the N-TFT and the gate insulating layer 60 of the N-TFT block a part of the doping ions from entering N- TFT channel region 309, thereby achieving doping of N-TFT lightly doped region 308 Micro-doping of the N-TFT channel region 309.
  • the array substrate of the embodiment of the present invention may further include a P-type thin film transistor (P-TFT), a storage capacitor, a passivation layer 90, and a pixel electrode 302.
  • P-TFT P-type thin film transistor
  • a storage capacitor a storage capacitor
  • a passivation layer 90 a passivation layer
  • the P-TFT includes a P-TFT heavily doped region 304, a channel region 307 of the P-TFT, a gate 312 of the P-TFT, a source 317 of the P-TFT, and a drain 318 of the P-TFT.
  • a gate electrode such as aluminum, Niobium or its alloy.
  • the thickness of the gate of the N-TFT and the gate of the P-TFT are set to be the same, a halftone mask or a gray-scale mask process can be used in the preparation of the gate, thereby being in a lightly doped region of the N-TFT.
  • the gate metal layer of the gate of the P-TFT and the storage capacitor is covered with a photoresist to block the doping ions from entering the channel region and the storage capacitor of the P-TFT. Heavy doped area.
  • the N-TFT gate 311 may be thinned by etching or the like to enable partial doping ions to enter the N-TFT channel.
  • the region 309 reaches the desired doping concentration, and the gate 312 of the P-TFT maintains the original thickness to effectively block the doping ions from entering the P-TFT channel region 307.
  • the one-step doping process is simultaneously used to obtain the lightly doped region and the microdoped channel region of the N-TFT, thereby simplifying the preparation process and improving Production efficiency.
  • the array substrate may include a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel units arranged in a matrix, each of the pixel units including a thin film transistor as a switching element and a liquid crystal for controlling Arranged pixel electrodes.
  • the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode.
  • An example of the display device is a liquid crystal display device in which the array substrate and the opposite substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, colored Membrane substrate.
  • the pixel electrode of each pixel unit of the array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display device further includes a backlight that provides backlighting for the array substrate.
  • Another example of the display device is an organic electroluminescence display device in which the array substrate performs a display operation.
  • FIG. 3 is a flow chart of a method for fabricating a top gate type N-TFT according to an embodiment of the present invention
  • FIG. 4.1 to FIG. 4.8 are top gate type N-TFTs in each step of the method for fabricating the top gate type N-TFT. Sectional view.
  • the method for preparing the top gate type N-TFT provided in this embodiment includes the following steps.
  • Step S1 forming a heavily doped region 306 of the N-TFT.
  • This step includes, for example, the following operations.
  • a polysilicon layer is formed on the base substrate, and the method of forming the polysilicon layer may be performed by directly forming a polysilicon layer on the base substrate, or by forming an amorphous silicon (a-Si) layer on the base substrate, and then The amorphous silicon is crystallized to obtain a polysilicon layer.
  • a buffer layer 20 may be selectively formed on the base substrate, and a polysilicon layer 30 is formed on the buffer layer, as shown in FIG.
  • the base substrate is, for example, a glass substrate, a quartz substrate or a plastic substrate.
  • a heavily doped region 306 of the N-TFT is formed by a patterning process on the base substrate on which the polysilicon layer is formed.
  • the patterning process includes, for example, the following operations.
  • a photoresist is coated on the substrate on which the polysilicon layer is formed, and the photoresist is exposed by a mask process to form a photoresist completely reserved region and a photoresist non-reserved region, and the photoresist in the non-retained region is removed by a developing process.
  • the exposed polysilicon layer is doped using the photoresist pattern as a mask to form a heavily doped region 306 of the N-TFT, as shown in FIG.
  • the gate thickness and the thickness of the gate insulating layer enable partial doping of ions to be obtained while performing a doping operation to obtain an N-TFT lightly doped region to obtain a microdoped N-TFT channel region.
  • This step includes, for example, the following operations.
  • the gate insulating layer 60 is formed on the base substrate subjected to the step S1, and as shown in Fig. 4.3, the method of forming the gate insulating layer can be prepared by spin coating or the like.
  • Forming a gate metal layer on the substrate on which the gate insulating layer 60 is formed which may be sputtered or vapor deposited Method preparation.
  • a patterning process is performed on the base substrate on which the gate metal layer is formed to form a gate electrode 311 of the N-TFT, as shown in Fig. 4.4.
  • a photoresist is coated on the formed gate metal layer, and the photoresist is exposed by a mask process to form a photoresist retention region and a photoresist non-retention region, and the non-retention region is removed by development.
  • Glue to obtain a photoresist pattern; then, the exposed gate metal layer is removed by etching using the obtained photoresist pattern as an etch mask to form a gate 311 of the N-TFT; finally, the photoresist of the remaining region is removed.
  • the gate 311 region of the N-TFT is a photoresist retention region, and the other regions are photoresist non-retention regions.
  • a doping process is performed on the substrate on which the N-TFT gate 311 is formed to form a lightly doped region 308 of the N-TFT and a heavily doped channel region 309, as shown in FIG. Since the channel region 309 of the N-TFT is covered with the gate electrode 311 and the gate insulating layer 60, and the lightly doped region 308 of the N-TFT is covered only with the gate insulating layer 60, the gates 311 and N- of the N-TFT are provided.
  • the gate insulating layer 60 of the TFT blocks a portion of the dopant ions from entering the N-TFT channel region 309.
  • the lightly doped region 308 and the microdoped channel region 309 of the N-TFT can be simultaneously formed by only one doping process.
  • a material having a small blocking effect on the dopant ions as a gate material of the N-TFT, such as aluminum, germanium or an alloy thereof.
  • the gate thickness of the N-TFT is 30 to 50 ⁇ .
  • the thickness of the gate electrode may be selected from 35 ⁇ , 40 nm or 45 nm; the gate insulating layer is preferably a SiNx layer, a SiO 2 layer or a composite layer formed of SiNx and SiO 2 , preferably the gate insulating layer has a thickness of 10 to 100 nm, such as a gate electrode.
  • the thickness of the insulating layer can be selected from 50 nm, 70 nm, and 90 nm.
  • the gate of the N-TFT may be thinned by etching or the like during the preparation process to achieve partial doping ions into the N. - TFT channel region 309, to achieve the desired doping concentration.
  • the interlayer insulating layer 80 is formed on the substrate subjected to the above steps, and as shown in Fig. 4.6, the method of forming the interlayer insulating layer can be prepared by spin coating or the like.
  • a source/drain electrode is formed by a patterning process on the substrate on which the interlayer insulating layer 80 is formed. For example, a photoresist is coated on the base substrate on which the interlayer insulating layer 80 is formed, and the photoresist is exposed by a mask process to form a photoresist retention region and a photoresist non-retention region; The photoresist is obtained as a photoresist pattern; then, the exposed interlayer insulating layer and the gate insulating layer are removed by etching using the obtained photoresist pattern to form a first via 314, as shown in FIG.
  • the source/drain electrodes are formed on the base substrate on which the first via holes 314 are formed, and can be performed, for example, as follows.
  • a source/drain metal layer is formed on the base substrate on which the first via hole 314 is formed, and a method of forming the source/drain metal layer can be prepared by a method such as sputtering or vapor deposition.
  • Coating on a substrate forming an active metal leakage layer a photoresist exposing the photoresist to a photoresist retention region and a photoresist non-retention region by using a mask process; developing a photoresist that removes the non-retained region to obtain a photoresist pattern; and then using the obtained
  • the photoresist pattern is removed by etching to remove the exposed source and drain metal layers to form source-drain electrodes 315 and 316 of the N-TFT; finally, the photoresist in the remaining region is removed, as shown in FIG.
  • FIG. 5 is a flow chart of a method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 6 is a cross-sectional view of the array substrate in each step of the method for fabricating the array substrate.
  • the flow of the method for preparing an array substrate provided by the embodiment specifically includes the following steps.
  • Step S1 forming a heavily doped region 306 of the N-TFT.
  • This step may include, for example, the following sub-steps Sl l-S13.
  • Step S1 a polysilicon layer 30 is formed on the base substrate 10.
  • the method of forming a polysilicon layer may be performed by directly forming a polysilicon layer on a base substrate, or by forming an amorphous silicon (a-Si) layer on the substrate and then on the amorphous silicon. A crystallization treatment is performed to obtain a polysilicon layer. Further, in this step, a buffer layer 20 may be selectively formed on the base substrate 10, and a polysilicon layer 30 may be formed on the buffer layer.
  • a-Si amorphous silicon
  • Step S12 forming a heavily doped region of the P-TFT by using a patterning process for the polysilicon layer formed in the step S11, and simultaneously forming a heavily doped region of the storage capacitor.
  • the patterning process in this step is performed, for example, as follows. First, a photoresist is coated on the polysilicon layer 30, and a photoresist complete retention region, a photoresist partial retention region, and a photoresist complete are formed on the polysilicon layer 30 by a halftone mask process or a grayscale mask process.
  • the polysilicon layer is doped to form a heavily doped region 304 of the P-TFT and a heavily doped region 305 of the storage capacitor, as shown in Figure 6.2.
  • the heavily doped region 305 of the storage capacitor acts as one of the electrodes of the storage capacitor.
  • the region 401 is a photoresist completely reserved region
  • the region 402 is a photoresist non-reserved region
  • the heavily doped region 304 of the P-TFT and the heavily doped region 305 of the storage capacitor are partial reserved regions of the photoresist. Note that the storage capacitor may not be formed in this embodiment.
  • Step S13 forming a heavily doped region of the N-TFT by performing a patterning process through step S12.
  • the patterning process in this step is performed, for example, as follows.
  • the photoresist is coated on the substrate subjected to the step S12, and after exposure, a photoresist retention region and a photoresist complete removal region are formed, and the photoresist in the completely removed region is developed to be removed, as shown in FIG.
  • the polysilicon layer in the completely removed area is exposed. Row doping forms a heavily doped region 306 of the N-TFT, as shown in Figure 6.4.
  • Step S2 forming a gate insulating layer and a gate, and then forming a N-TFT lightly doped region and a microdoped N-TFT channel region by a doping process.
  • the gate thickness and the thickness of the gate insulating layer enable a portion of the doped ions to be blocked to obtain a doped N-TFT channel region while performing a doping operation to obtain an N-TFT lightly doped region.
  • This step S2 may include the following sub-steps S21-S23.
  • Step S21 forming a gate insulating layer.
  • This step is to form the gate insulating layer 60 on the base substrate which has passed through the step S1, and can be prepared, for example, by spin coating or the like.
  • Step S22 forming a gate. This step may further include the following sub-steps.
  • Step S221 forming a gate metal layer on the base substrate passing through S21.
  • This step is, for example, to form a gate metal layer by sputtering, vapor deposition or the like on the base substrate of S21.
  • Step S222 forming a gate electrode by forming a gate metal layer, and forming another electrode of the storage capacitor.
  • the patterning process in this step is performed, for example, as follows. Coating a photoresist on the base substrate on which the gate metal layer is formed, and exposing the photoresist by a halftone mask process or a gray scale mask process to form a photoresist completely removed region, and the photoresist portion is retained.
  • the region and the photoresist are completely reserved, developed to obtain a photoresist pattern, wherein the photoresist in the completely removed region is removed, and the photoresist in the partial remaining region is partially removed, and the obtained photoresist pattern is used as an etching
  • the mask is etched to remove the exposed gate metal layer to form gates 311, 312 covered with photoresist of different thicknesses and electrodes 313 for storage capacitance, as shown in FIG.
  • the gate 311 region of the top gate type N-TFT is a photoresist partial retention region, the gate 312 of the P-TFT and the electrode 313 region of the storage capacitor are completely reserved regions of the photoresist, and the remaining regions are complete photoresist removal regions. .
  • Step S23 forming an N-TFT lightly doped region and a microdoped N-TFT channel region.
  • the step includes the following operations.
  • the photoresist in the portion of the remaining region (the gate 311 region of the N-TFT) is removed by an ashing process on the electrode 313 which is formed by the step S222 to form the photoresist-covered gates 311, 312 and the storage capacitor, for N-
  • the TFT lightly doped region 308 and the N-TFT channel region 309 are doped as shown in Figure 6.6.
  • the one-step doping process can be realized.
  • the N-TFT lightly doped region 308 and the microdoped N-TFT channel region 309 are doped at different ion concentrations.
  • the gate 312 of the P-TFT is covered with a photoresist, doping of the lightly doped region and the channel region of the N-TFT does not affect the performance of the P-TFT.
  • the photoresist of a portion of the remaining region is removed by an ashing process, and the gate 311 of the exposed N-TFT is etched to reduce the thickness of the gate of the N-TFT.
  • a portion of the doping ions can pass through the N-TFT gate 311 and the gate insulating layer 60 into the N-TFT channel region, thereby achieving a lightly doped region 308 and a microdoping of the N-TFT by using a single doping process.
  • the channel region 309 of the N-TFT is included in this step.
  • the doping ions can be effectively blocked from entering the channel region 307 of the P-TFT, as shown in Fig. 6.7.
  • Step S3 forming an interlayer insulating layer 80.
  • This step is to form an interlayer insulating layer 80 on the base substrate which has passed through step S2, and can be prepared by spin coating or the like.
  • Step S4 forming a source/drain electrode.
  • This step may, for example, include the following sub-steps S41-S42.
  • Step S41 forming a first via 314 by patterning on the base substrate subjected to step S3.
  • the patterning process in this step includes, for example, the following operations.
  • Step S42 forming a source/drain electrode by patterning on the substrate subjected to step S41.
  • the patterning process in this step includes, for example, the following operations.
  • a source/drain metal layer is prepared on the base substrate on which the via hole is formed by sputtering, vapor deposition, etc., and a photoresist is coated on the substrate on which the source/drain metal layer is formed, and the photoresist is completely removed after exposure.
  • the photoresist forms source and drain electrodes 315 and 316 of the N-TFT, source and drain electrodes 317 and 318 of the P-TFT, and an electrode 319 of the storage capacitor, as shown in FIG.
  • Step S5 forming a passivation layer 90 and a pixel electrode 321 .
  • This step may, for example, include sub-steps S51-S53 as follows.
  • Step S51 forming a passivation layer on the base substrate on which the active drain electrode is formed.
  • a passivation layer is formed on the base substrate on which the active and drain electrodes are formed by spin coating or the like.
  • Step S52 forming a second via hole by using a patterning process on the formed passivation layer.
  • the patterning process in this step includes, for example, the following operations. Coating a photoresist on the substrate on which the passivation layer 90 is formed, after exposing to form a photoresist complete removal region and a photoresist retention region, and developing the photoresist without removing the region to obtain a photoresist pattern; then, The exposed passivation layer is removed by etching using the resulting photoresist pattern to form a second via 320, and finally the photoresist in the completely remaining region is removed, as shown in Figure 6.10.
  • Step S53 forming a pixel electrode 321 by a patterning process.
  • the patterning process in this step includes, for example, the following operations. Forming a transparent conductive layer on the substrate forming the second via 320, coating a photoresist on the substrate forming the transparent conductive layer, and forming a photoresist completely removed region and a photoresist completely reserved region by exposure; the development removal is not retained The photoresist of the region obtains a photoresist pattern; then, the exposed transparent conductive layer is removed by etching using the obtained photoresist pattern to form a pixel electrode 321 , and finally the photoresist in the completely reserved region is removed, as shown in FIG. 6.11. Show.
  • the channel region of the micro-doped N-TFT and the light-doped region of the N-TFT are simultaneously obtained by a single doping process, and at the same time, halftone or gray scale is used in the patterning process.
  • the mask process can realize the preparation of the array substrate by using seven patterning processes, simplifying the process flow and improving the production efficiency.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

L'invention concerne un transistor en couches minces dopé de type N (N-TFT) du type à grille supérieure et un procédé de fabrication de celui-ci. Le N-TFT comprend une microrégion de canal dopée de N-TFT (309), l'épaisseur de la grille (311) et celle de la couche d'isolation de grille (60) étant formées de manière à obtenir une région légèrement dopée de N-TFT (308) et une partie de blocage d'ions dopés simultanément pendant le processus de dopage, de façon à obtenir la microrégion de canal dopée de N-TFT (309). Le procédé de fabrication permet de réaliser une procédure de dopage pour obtenir une région légèrement dopée de N-TFT et la microrégion de canal dopée de N-TFT simultanément. Il est également envisagé d'appliquer des plaques de masquage tramées ou des plaques de masquage en nuances de gris et sept passes de gravure pour fabriquer les plaques de base de réseau.
PCT/CN2012/084118 2012-03-22 2012-11-06 Transistor en couches minces de type n (n-tft) du type à grille supérieure, plaque de base de réseau, procédé de fabrication de celui-ci et unité d'affichage WO2013139128A1 (fr)

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CN104300002B (zh) * 2013-07-15 2017-05-31 信利半导体有限公司 一种薄膜晶体管及其制造方法、光刻工艺
CN104103584A (zh) * 2014-06-25 2014-10-15 京东方科技集团股份有限公司 阵列基板制作方法
CN104701254B (zh) * 2015-03-16 2017-10-03 深圳市华星光电技术有限公司 一种低温多晶硅薄膜晶体管阵列基板的制作方法
CN105206568B (zh) * 2015-10-16 2018-06-05 京东方科技集团股份有限公司 一种低温多晶硅tft阵列基板的制备方法及其阵列基板
CN105679705B (zh) * 2016-01-29 2018-10-26 武汉华星光电技术有限公司 阵列基板的制作方法
CN105552027B (zh) * 2016-02-14 2018-08-14 武汉华星光电技术有限公司 阵列基板的制作方法及阵列基板
CN107046003B (zh) * 2017-06-02 2019-05-03 武汉华星光电技术有限公司 低温多晶硅tft基板及其制作方法
CN107464849B (zh) * 2017-07-28 2021-03-26 京东方科技集团股份有限公司 薄膜晶体管及制备方法、显示基板、显示装置
CN108461520A (zh) * 2018-01-09 2018-08-28 深圳市华星光电半导体显示技术有限公司 一种oled背板及其制备方法

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