WO2013131312A1 - SiGe-HBT晶体管及其制备方法 - Google Patents

SiGe-HBT晶体管及其制备方法 Download PDF

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WO2013131312A1
WO2013131312A1 PCT/CN2012/074801 CN2012074801W WO2013131312A1 WO 2013131312 A1 WO2013131312 A1 WO 2013131312A1 CN 2012074801 W CN2012074801 W CN 2012074801W WO 2013131312 A1 WO2013131312 A1 WO 2013131312A1
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layer
region
sige
collector
doping concentration
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PCT/CN2012/074801
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English (en)
French (fr)
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陈静
余涛
罗杰馨
柴展
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中国科学院上海微系统与信息技术研究所
伍青青
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Publication of WO2013131312A1 publication Critical patent/WO2013131312A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H01L29/7378—Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors

Definitions

  • the present invention relates to the field of microelectronics and solid state electronics, and more particularly to a SiGe heterojunction bipolar transistor (SiGe-HBT) and a method of fabricating the same.
  • SiGe-HBT SiGe heterojunction bipolar transistor
  • Heterojunction bipolar transistor fundamentally overcomes the inherent contradiction between the conventional Bipolar Junction Transistor (BJT) by using energy band engineering, that is, the contradiction between increasing the amplification factor and increasing the characteristic frequency. HBT can achieve ultra-high frequency and ultra-high speed. Moreover, SiGe technology is fully compatible with advanced CMOS technology, so SiGe-BiCMOS technology has been formed, which has driven the rapid development of microwave and RF communication technologies.
  • HBT devices due to the many physical properties affecting HBT devices: Early effects (and bias correlation), high injection effects, epitaxial layer resistance and its carrier saturation effects, base charge recombination, Kirk effect, weak nonlinearity of the base region Current, avalanche breakdown effect, charge storage, substrate effect, base-set and base-emitter junction dissipation capacitance, base resistance current density increase and conductivity modulation effect, intrinsic baseband high frequency distribution effect (skin and Superphase shifting), self-heating, thermal noise, shotgun noise, 1/f noise and various parasitic effects in extrinsic regions, and various effects caused by the distribution of Ge components, etc., and various parts of the HBT device (emitter, The design rules for the base and collector are quite large. This undoubtedly brings great challenges to the optimization of HBT device structure. How to choose and balance between many performances has always been a hot spot.
  • the microwave power tube In order to obtain a large power output, the microwave power tube must have a high operating voltage and a large collector alternating current. To obtain a high breakdown voltage and a large collector current, the material parameters of the collector epitaxial layer are selected. It is exactly the opposite. To obtain higher power gain, the device must have a higher characteristic frequency f T . For a microwave power transistor in a narrow base region, its characteristic frequency is mainly determined by the collector space charge region transit time, so the set is satisfied. On the premise of the breakdown voltage of the electrode base, a thin epitaxial layer is selected as much as possible and the space charge region is completely consumed.
  • the leakage formed by the junction terminal is larger and less used. Therefore, current bipolar devices, especially bipolar RF power transistors, mainly use diffusion protection rings, floating field limiting rings and field plate technology, but diffusion protection rings, floating field limiting rings increase the junction area and increase the current collection.
  • the junction capacitance and leakage current limit the cutoff frequency of the RF power tube and reduce the power gain. This contradiction is not adjustable by increasing the breakdown voltage.
  • the current collector region is generally set. It is calculated as a two-layer structure in which a low-doped layer is interposed between the highly doped collector region and the base region.
  • An example of a SiGe transistor and its manufacturing method for doping a collector region is shown in CN101937846A.
  • the specific structure of the device is shown in FIG. 1.
  • the invention is entitled “A SiGe transistor and a method for fabricating the same", and the disclosed collector region is disclosed.
  • the doping step includes: a first ion implantation step for forming a first collector region C1 of a first doping concentration; and a second ion implantation step for forming a second collector region C2 having a second doping concentration
  • the first collector region C1 and the second collector region C2 are arranged to overlap to form a collector region, and the second collector region C2 is formed over the first collector region C1, and the second doping concentration is greater than the first Doping concentration.
  • the main disadvantage of the invention is that when the collector region is completely depleted, the wider low-doped collector region increases the time during which the carrier transits the space charge region, resulting in a decrease in the characteristic frequency.
  • an object of the present invention is to provide a SiGe-HBT transistor and a method for fabricating the same, which are used to solve the problem of reducing the characteristic frequency when the base-collector breakdown voltage is increased in the prior art. , or the problem of deterioration of breakdown voltage caused by increasing the doping concentration of the collector region, increasing the characteristic frequency, and increasing the transit time of the space charge region.
  • the present invention provides a method of fabricating a SiGe-HBT transistor, including:
  • a base region including an intrinsic SiGe layer, a base region P-SiGe:C layer, and a heavily doped P+ polysilicon outer base layer on the collector region to contact the collector region and the base region Forming a collector-base junction space charge region, and preparing an emitter cap layer and an emitter region on the P+ polysilicon outer base layer;
  • a base contact, an emitter contact, and a collector contact are respectively prepared on the base region, the emitter region, and the sub-collector region.
  • the ions implanted in the P+ layer are phosphorus or arsenic.
  • the ions implanted in the N+ layer are boron.
  • the doping concentration value ranges from
  • the doping concentration value has a Gaussian distribution.
  • the doping concentration value of the P+ layer or the N+ layer is smaller than the doping concentration value of the P-SiGe:C layer of the base region.
  • the doping concentration value of the P+ layer or the N+ layer is greater than the doping concentration value of the collector region.
  • the method for fabricating the SiGe-HBT transistor is characterized in that the thickness of the P+ layer and the N+ layer is 10 nm to 90 nm.
  • Another object of the present invention is to provide a SiGe heterojunction two-transistor structure comprising:
  • a base region formed over the collector region, comprising an intrinsic SiGe layer, a heavily doped P+ polysilicon outer base layer, and a layer of the intrinsic SiGe layer and the heavily doped P+ polysilicon outer base layer a base region P-SiGe: C layer, a contact interface of the collector region and the base region forms a collector-base junction space charge region, and the heavily doped P+ polysilicon outer base region layer is formed Base contact
  • An emitter region is formed on the P+ polysilicon outer base layer and the emitter cap layer, and an emitter contact is formed; and the P+ layer having the same doping concentration is formed in the overlap region of the collector region and the space charge region A stack of N+ layers.
  • ions implanted in the P+ layer are phosphorus or arsenic.
  • ions implanted in the N+ layer are boron.
  • the P+ layer and the N+ layer have a doping concentration value ranging from 10 17 cm 3 to 10 18 cm 3 , and the doping concentration value is Gaussian.
  • the doping concentration value of the P+ layer or the N+ layer is smaller than the doping concentration value of the P-SiGe:C layer of the base region.
  • the doping concentration value of the P+ layer or the N+ layer is greater than the doping concentration value of the collector region.
  • the P+ layer or the N+ layer has a thickness of 10 nm to 90 nm.
  • a SiGe heterojunction dual transistor of the present invention and a method of fabricating the same have the following advantageous effects:
  • the present invention forms a P+ layer having an equal doping concentration in the overlap region of the collector region and the space charge region.
  • the laminated value composed of the N+ layer can not only change the electric field value of the local barrier region, but also change the electric field distribution in the barrier region. Due to the electron velocity saturation effect, as long as the electrons reach the maximum kinetic energy before reaching the peak of the electric field in the barrier region, even if the electric field strength is increased, the velocity does not change substantially.
  • This structure can push the electric field peak after the maximum electron kinetic energy. That is, the electron is already saturated at the peak of the electric field, so it does not change depending on the electric field strength, thus significantly reducing the probability of ionization collision, thereby increasing the base avalanche breakdown voltage of the base. From another angle, when the breakdown voltage is kept constant, the doping concentration of the collector region is appropriately increased, and the high doping narrows the space charge region, thereby increasing the characteristic frequency f T and the thin collector potential.
  • the barrier zone can also inhibit the avalanche breakdown effect, thus forming a virtuous circle.
  • Fig. 1 is a schematic view showing the structure of a SiGe-HBT transistor in the prior art.
  • FIG. 2a-2c are schematic views showing the structure formed in the different steps of preparing a SiGe-HB T transistor of the present invention.
  • FIG. 3 is a view showing the position of a space charge region of a collector junction in a SiGe-HB T transistor to be prepared according to the present invention.
  • FIG. 2a The structure shown in Figure 2a is prepared using conventional processing techniques well known to those skilled in the art, which are also conventional materials well known to those skilled in the art.
  • a general SiGe heterojunction dual transistor is fabricated on a semiconductor substrate (not shown), and the substrate material is selected from one of Si, Ge, GeSi, but is not limited to these materials.
  • the substrate can be either an N-type or a P-type substrate, depending on the type of device being fabricated.
  • the structure in Fig. 2a includes a sub-collector region 11 formed on a semiconductor substrate (not shown), and the sub-collector region 11 is formed by a conventional ion implantation or epitaxial growth process, and then in the A shallow trench isolation region 13 is formed on the collector region 11 and the deep trench isolation 12.
  • the collector region 14 is formed between the bipolar device regions, i.e., the two shallow trench isolation regions 13, by ion implantation or activation annealing.
  • the process of forming the deep trench isolation region 12 for isolating the sub-collector region 11 and the shallow trench isolation region 13 for isolating the collector region 14 formed on the semiconductor substrate (not shown) is conventional. Lithography, etching and trench isolation fill.
  • the collector contact 20 is then formed on the sub-collector 11 .
  • the width of the space charge region and its position in the collector region are first determined according to the predetermined doping concentration of the collector region and the base region.
  • the collector region 14 is an n-type region with uniform donor impurities.
  • the degree N D the base region 16 is a p-type region, and has a uniform acceptor impurity concentration N A .
  • N fl represents the donor impurity concentration
  • ⁇ represents the space charge region width
  • X n represents the space charge region width of the n-type region as can be seen from the above formula: (1) The contact potential difference of the unilateral abrupt junction ⁇ with low doping The impurity concentration on the side of the impurity increases. (2) The space charge region width of the unilateral abrupt junction decreases as the impurity concentration increases. The space charge region is almost entirely on the lightly doped side, so band bending occurs mainly in this region.
  • N A is much larger than N D
  • X n is much larger than X p , that is, the base region
  • the charge density in 16 is large, and the diffusion of the space charge region occurs almost in the collector region 14, thus introducing X D X n .
  • the width of the space charge region and the position in the collector region are as shown in FIG.
  • FIG. 2b The next step in the preparation of the SiGe heterojunction two-transistor of the present invention is shown in Figure 2b.
  • the ⁇ + layer 17 and the P+ having the same doping concentration are formed in the overlap region of the collector region 14 and the space charge region 15 by the ion implantation technique.
  • a stack of layers 18 is formed, and the order of the ⁇ + layer 17 and the P+ layer 18 in the stack is interchangeable.
  • the ions implanted in the P+ layer 18 are phosphorus or arsenic, the ions implanted in the ⁇ + layer 17 are boron, and the doping concentration values of the P+ layer 18 and the ⁇ + layer 17 are in the range of 10 17 cm - 3 . ⁇ 10 18 cm- 3 , and the doping concentration value is Gaussian.
  • the thickness of the P+ layer 18 and the ⁇ + layer 17 can be adjusted according to the width of the space charge region 15, ranging from 10 nm to 90 nm.
  • the structure not only changing the electric field value of the local barrier region, but also Can change the electric field of the barrier zone Distribution. Due to the electron velocity saturation effect, as long as the electrons reach the maximum kinetic energy before reaching the peak of the electric field in the barrier region, even if the electric field strength is increased, the speed does not substantially change. Therefore, the solution of the present invention can push the electric field peak to the maximum electron.
  • the doping concentration of the collector region 14 is appropriately increased, and the high doping narrows the space charge region 15 to increase the characteristic frequency f T , and the thin space charge region 15 is further The avalanche breakdown effect can be suppressed, thereby forming a virtuous cycle.
  • the next step in the preparation of the SiGe heterojunction two-transistor of the present invention is shown in Figure 2c.
  • the intrinsic SiGe layer 160 is prepared on the collector region 14 (since the thickness of the intrinsic SiGe layer 160 is thin, the researchers generally ignore the existence of the intrinsic layer when quantitatively analyzing and analyzing characteristics such as SiGe HBT frequency), a base region P-SiGe: a C layer 161, and a base region 16 of the heavily doped P+ polysilicon outer base layer 162, and a base contact 21 is formed on the P+ polysilicon outer base layer 162; wherein, due to the base region 16 is heavily doped, and the heat treatment process causes ions in the base region 16, such as B (boron), to diffuse to the collector region 14, causing the heterojunction and the pn junction to not coincide, and the device performance is seriously degraded, in order to suppress the occurrence of this situation.
  • B boron
  • the method commonly used by researchers is to add a thin intrinsic SiGe layer 160 at the interface of the heterogeneous collector junction, which can effectively block the diffusion of boron ions from the base region 16 to the collector region 14.
  • the intrinsic SiGe layer 160 is incorporated into the structure of the present invention using conventional techniques of the prior art, such as ultra high vacuum chemical weather deposition (UHV / CVD).
  • UHV / CVD ultra high vacuum chemical weather deposition
  • an emitter cap layer 19 is also incorporated into the structure of the present invention for controlling lateral erosion of the emitter region 22.
  • An emitter region 22 and an emitter contact 23 are then formed on the emitter cap layer 19, and a spatial isolation region 24 is formed between the emitter region 22 and the base region 16, and the structure of the emitter region 22 is formed by conventional photolithography and etching processes, such as Figure 2c shows.
  • the doping concentration value of the N+ layer 17 or the P+ layer 18 is smaller than the doping concentration value of the base region P-SiGe: C layer 161, and the N+ layer
  • the doping concentration value of the 17 or P+ layer 18 is greater than the doping concentration value of the collector region 14.
  • the present invention also provides a SiGe-HBT transistor structure, as shown in Figure 2c, comprising:
  • a base region 16 is formed over the collector region 14 and includes an intrinsic SiGe layer 160 and a heavily doped P+ polysilicon external base. a region layer 162 and a base region P-SiGe: C layer 161 between the intrinsic SiGe layer 160 and the heavily doped P+ polysilicon outer region layer 162, the contact between the collector region 14 and the base region 16 A collector-base junction space charge region 15 is formed on the interface, and a base contact 21 is formed on the P+ polysilicon outer base layer 162 layer.
  • An emitter region 22 is formed over the P+ polysilicon outer base layer 162 and the emitter cap layer 19, and is formed with an emitter contact 23.
  • the ions implanted in the P+ layer 18 are phosphorus or arsenic, and the ions implanted in the N+ layer 17 are boron; the doping concentration values of the N+ layer 17 and the P+ layer 18 range from 10 17 to 10 18 Cm- 3 , and the doping concentration value is Gaussian; the doping concentration value of the N+ layer 17 or the P+ layer 18 is smaller than the doping concentration value of the base region P-SiGe: C layer 161; the N+ layer 17 Or the doping concentration value of the P+ layer 18 is greater than the doping concentration value of the collector region 14. Further specifically, the thickness of the N+ layer 17 or the P+ layer 18 may be adjusted according to the width of the space charge region 15 distributed in the collector region 14, ranging from 10 nm to 90 nm.
  • the laminated structure composed of the P+ layer or the N+ layer can not only change the electric field value of the local barrier region, but also change the distribution of the electric field in the barrier region, ensuring that the transit time, the cutoff frequency, and the maximum oscillation frequency are not sacrificed.
  • the base-collector breakdown voltage is increased, or the doping concentration of the collector region is increased, and the space charge region transit time and the cutoff frequency are increased while ensuring that the breakdown voltage is not deteriorated.
  • the present invention forms an N+ layer 17 by implanting boron in a space charge region by using an ion implantation technique, and the concentration is in the range of 10 17 cm - 3 to 10 18 cm - 3 , and the thickness is in the range of ten to several tens of nanometers.
  • the specific thickness is adjusted according to the width of the space charge region), and the doping concentration value is Gaussian; then phosphorus or arsenic is implanted above the N+ layer 17 to form a P+ layer 18, and the concentration is also 10 17 cm - 3 ⁇ 10 18 cm - Within the range of 3 , and the P+ layer 18 concentration value is the same as the N+ layer 17 concentration value, and has a Gaussian distribution with a thickness of ten to several tens of nanometers (the specific thickness is adjusted according to the width of the depletion layer).
  • the solution of the present invention can push the electric field peak to the maximum electron. After kinetic energy, that is, the electrons are already saturated at the peak of the electric field, so it does not change depending on the electric field strength, which is significant.
  • the probability of ionization collision is reduced, thereby increasing the avalanche breakdown voltage of the base-collector junction, or increasing the doping concentration of the collector region 14 while maintaining the voltage across the well, and the high doping makes the space charge
  • the narrowing of the region 15 increases the characteristic frequency f T , and the thinner space charge region 15 suppresses the avalanche breakdown effect, thereby forming a virtuous cycle.

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Abstract

本发明提供一种SiGe-HBT晶体管及其制备方法，属于微电子与固体电子领域。该SiGe异质结双晶体管的制备方法通过采用离子注入技术，在集电区与空间电荷区重叠区域中形成掺杂浓度相等的P+层与N+层组成的叠层，所述P+层或N+层的掺杂浓度值呈高斯分布，且其浓度值小于基区的掺杂浓度值，大于集电区的掺杂浓度值。本发明的方案不仅可以改变局部势垒区电场值大小，还可以改变势垒区电场的分布情况，在保证不牺牲渡越时间、截止频率以及最大振荡频率的情况下，提高基极-集电极击穿电压，或者在保证击穿电压不恶化的情况下，增加集电区掺杂浓度，提高空间电荷区渡越时间和截止频率。

Description

SiGe-HBT晶体管及其制备方法
技术领域
本发明涉及微电子与固体电子学技术领域， 特别是涉及一种 SiGe 异质结双极型晶体管 (SiGe-HBT) 及其制备方法。 背景技术
异质结双极型晶体管 （HBT ) 利用能带工程从根本上克服了常规双极结型晶体管 (Bipolar Junction Transistor, BJT) 所存在的内在矛盾， 即提高放大系数与提高特征频率的矛 盾， 因此 HBT 可以实现超高频率和超高速。 而且 SiGe 技术与先进的 CMOS 工艺完全兼 容， 所以就形成了 SiGe-BiCMOS技术， 这相应地推动着微波、 射频通信技术的快速发展。
然而， 由于影响 HBT器件的物理特性非常之多： Early效应 （和偏置相关） 、 高注入效 应、 外延层电阻及其载流子饱和效应、 基区电荷复合、 Kirk效应、 基区弱非线性电流、 雪崩 击穿效应、 电荷存储、 基底效应、 基 -集和基-射结耗散电容、 基区电阻电流密度升高和电导 率调制效应、 本征基区高频分布效应 （趋肤和超相移） 、 自热、 热噪声、 散弹噪声、 1/f 噪 声和非本征区的各种寄生效应以及 Ge 组分分布引起的各种效应等， 而且 HBT器件各部分 (发射极、 基极、 集电极） 的设计规则相当之多。 这无疑给 HBT器件结构的优化带来了巨 大挑战， 如何在众多性能之间取舍、 权衡一直是人们关注的热点。
微波功率管要获得较大的功率输出， 必须具有较高的工作电压和较大的集电极交流电 流， 要得到高的击穿电压和大的集电极电流， 对于集电极外延层材料参数的选取恰恰是相反 的。 要获得较高的功率增益要求器件必须具有较高的特征频率 fT， 对于微波功率晶体管在窄 基区时， 它的特征频率主要由集电极空间电荷区渡越时间所决定， 所以在满足集电极基极击 穿电压的前提下， 尽可能选取薄外延层并使空间电荷区全部耗。
双极器件中常用扩散保护环， 浮空场限环， 场板， 腐蚀成形结终端扩展技术来提高电 压， 但腐蚀成型需精密控制腐蚀的深度及其在平面结中的位置， 因此比较难形成， 而结终端 扩展形成的漏电较大， 也较少使用。 因此， 目前双极器件， 尤其是双极射频功率晶体管中主 要采用扩散保护环， 浮空场限环以及场板技术， 但扩散保护环， 浮空场限环增加了结面积， 增大了集电结电容和漏电流， 限制了射频功率管的截止频率， 减小了功率增益， 这个矛盾与 提高击穿电压是不可调和的。
在现有技术中， 为了使 SiGe 晶体管能稳定的工作及提高其击穿电压， 一般将集电区设 计成两层结构， 即在高掺杂集电区和基区之间插入一层低掺杂层。 一种 SiGe 晶体管及其制 造方法对集电极区域进行掺杂的实例见于 CN101937846A, 器件具体结构如图 1所示， 发明 名称为 "一种 SiGe晶体管及其制造方法"， 公开的对集电极区域进行掺杂的步骤包括： 第一 离子注入步骤， 用于形成第一掺杂浓度的第一集电极区域 C1 ; 以及第二离子注入步骤用于 形成具有第二掺杂浓度的第二集电极区域 C2; 且第一集电极区域 C1和第二集电极区域 C2 重叠布置以构成集电极区域， 并且第二集电极区域 C2形成在第一集电极区域 C1 之上， 并 且第二掺杂浓度大于第一掺杂浓度。 但是， 该发明存在的主要缺点为： 当集电区完全耗尽 时， 较宽的低掺杂集电区会使载流子渡越空间电荷区的时间增大， 从而导致特征频率降低。
鉴于此， 怎样在保证不牺牲渡越时间、 截止频率以及最大振荡频率的情况下， 提高基 极 -集电极击穿电压， 或者在保证击穿电压不恶化的情况下， 增加集电区掺杂浓度， 怎样提 高空间电荷区渡越时间和截止频率， 实已成为本领域从业者亟待解决的技术问题。 发明内容
鉴于以上所述现有技术的缺点， 本发明的目的在于提供一种 SiGe-HBT晶体管及其制备 方法， 用于解决现有技术中， 在提高基极 -集电极击穿电压时导致特征频率降低， 或在增加 集电区掺杂浓度、 提高特征频率以及提高空间电荷区渡越时间时导致的击穿电压恶化的问 题。
为实现上述目的及其他相关目的， 本发明提供一种 SiGe-HBT 晶体管的制备方法， 包 括：
提供一半导体衬底， 在该衬底上制备出次集电区， 并在所述次集电区上形成藉由浅槽隔 离区隔离出的集电区；
依据预设的集电区和基区的掺杂浓度确定出空间电荷区的宽度及其在所述集电区中的位 置；
利用离子注入技术在所述的集电区和空间电荷区重叠区域中形成掺杂浓度相等的 P+层与 N+层组成的叠层；
在所述集电区上制备包括本征 SiGe层、 基区 P-SiGe:C层、 以及重掺杂的 P+多晶硅外基 区层的基区， 以在所述集电区和基区的接触界面形成一集电极-基极结空间电荷区， 且在所 述 P+多晶硅外基区层上制备出发射极盖帽层和发射区；
分别在所述的基区、 发射区、 次集电区分别上制备出基极接触、 发射极接触、 集电极接 触。 可选地， 所述的 SiGe-HBT晶体管的制备方法中， 所述 P+层中注入的离子为磷或砷。 可选地， 所述的 SiGe-HBT晶体管的制备方法中， 所述 N+层中注入的离子为硼。
可选地， 所述的 SiGe-HBT晶体管的制备方法中， 其特征在于， 所述掺杂浓度值范围为
1017 cm-3 ~1018cm-3， 且所述掺杂浓度值呈高斯分布。
可选地， 所述的 SiGe-HBT 晶体管的制备方法中， 所述 P+层或 N+层的掺杂浓度值小于 基区 P-SiGe:C层的掺杂浓度值。
可选地， 所述的 SiGe-HBT 晶体管的制备方法中， 所述 P+层或 N+层的掺杂浓度值大于 集电区的掺杂浓度值。
可选地， 所述的 SiGe-HBT 晶体管的制备方法， 其特征在于， 所述 P+层和 N+层的厚度 为 10nm~90nm。
本发明的另一个目的是提供一种 SiGe异质结双晶体管结构， 包括：
次集电区及形成于所述次集电区上且由浅槽隔离区隔离出的集电区， 且所述次集电区上 形成有集电极接触；
基区， 形成于所述集电区之上， 包括本征 SiGe层、 重掺杂的 P+多晶硅外基区层以及位 于所述的本征 SiGe层和重掺杂的 P+多晶硅外基区层之间的基区 P-SiGe:C层， 所述集电区和 基区的接触界面形成有一集电极-基极结空间电荷区， 且所述重掺杂的 P+多晶硅外基区层上 形成有基极接触；
发射区， 形成于所述 P+多晶硅外基区层和发射极盖帽层上， 且形成有发射极接触； 所述的集电区和空间电荷区重叠区域中形成有掺杂浓度相等的 P+层与 N+层组成的叠 层。
可选地， 所述 SiGe-HBT晶体管集电区中， 所述 P+层中注入的离子为磷或砷。
可选地， 所述 SiGe-HBT晶体管集电区中， 所述 N+层中注入的离子为硼。
可选地， 所述 P+层与 N+层的掺杂浓度值范围为 1017cm- 3~1018cm- 3， 且所述掺杂浓度值 呈高斯分布。
可选地， 所述的 SiGe-HBT晶体管的制备方法中， 所述 P+层或 N+层的掺杂浓度值小于 基区 P-SiGe:C层的掺杂浓度值。
可选地， 所述的 SiGe-HBT晶体管的制备方法中， 所述 P+层或 N+层的掺杂浓度值大于 集电区的掺杂浓度值。
可选地， 所述的 SiGe-HBT晶体管的制备方法中， 所述 P+层或 N+层的厚度为 10nm ~ 90nm。 如上所述， 本发明的一种 SiGe异质结双晶体管及其制备方法， 具有以下有益效果： 本发明通过在所述的集电区和空间电荷区重叠区域中形成掺杂浓度相等的 P+层与 N+层 组成的叠层值， 不仅可以改变局部势垒区电场值大小， 还可以改变势垒区电场的分布情况。 由于电子速度饱和效应， 只要电子在到达势垒区电场峰值之前， 已经到达最大动能， 即便是 在增加电场强度， 其速度也基本不改变， 此结构可以将电场峰值推在最大电子动能之后。 即 电子在到达电场峰值时就已经速度饱和， 所以它不在依赖电场强度而变化， 这样就显著减少 了电离碰撞的几率， 从而提升基极一集电极雪崩击穿电压。 换个角度， 在保持击穿电压不变 的情况下， 适当增加集电区掺杂浓度， 高的掺杂使空间电荷区变窄， 即可提高特征频率 fT， 而且较薄的集电结势垒区又可抑制雪崩击穿效应， 由此形成了良性循环。 附图说明
图 1显示为现有技术中的一种 SiGe-HBT晶体管结构示意图。
图 2a-2c显示为本发明制备 SiGe-HB T晶体管的不同步骤中所形成的结构示意图。 图 3显示为本发明所要制备的 SiGe-HB T晶体管中集电结空间电荷区的位置示意图。 元件标号说明
11 次集电区
12 深槽隔离区
13 浅槽隔离区
14 集电区
15 集电极 -基极结空间电荷区
16 基区
160 本征 SiGe层
161 基区 P-SiGe:C
162 重掺杂的 P+多晶硅外基区
17 N+-Si层
18 P+-Si层
19 发射极盖帽层
20 集电极接触
21 基极接触 22 发射区
23 发射极接触
24 空间隔离区 具体实施方式
以下通过特定的具体实例说明本发明的实施方式， 本领域技术人员可由本说明书所揭露 的内容轻易地了解本发明的其他优点与功效。 本发明还可以通过另外不同的具体实施方式加 以实施或应用， 本说明书中的各项细节也可以基于不同观点与应用， 在没有背离本发明的精 神下进行各种修饰或改变。
请参阅图 1至图 3。 需要说明的是， 本实施例中所提供的图示仅以示意方式说明本发明 的基本构想， 遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、 形状 及尺寸绘制， 其实际实施时各组件的型态、 数量及比例可为一种随意的改变， 且其组件布局 型态也可能更为复杂。
下面结合说明书附图进一步说明本发明提供的一种 SiGe-HBT晶体管及其制备方法， 为 了示出的方便附图并未按照比例绘制， 特此述明。
实施例一
对照附图 2a-2c对本发明提供的一种 SiGe-HBT晶体管的制备方法做进一步的解释和说 明。
如图 2a所示的结构是使用本领域技术人员所熟知的常规工艺手段来制备的， 所述的材 料也是本领域技术人员所熟知的常规材料。 例如， 一般 SiGe 异质结双晶体管制作在半导体 衬底上 （图中未示出）， 衬底材料选自 Si、 Ge、 GeSi中的一种， 但不限于这些材料。 衬底可 以选用 N型或 P型衬底， 这取决于制作的器件的类型。
在图 2a中的结构包括在半导体衬底 （图中未示出） 上形成的次集电区 11， 次集电区 11 采用常规的离子注入或外延生长的工艺以形成， 然后在所述次集电区 11和深槽隔离 12上形 成浅槽隔离区 13。 在浅槽隔离区 13形成后， 采用离子注入或激活退火方法在双极器件区即 两个浅槽隔离区 13之间形成集电区 14。 其中， 在半导体衬底 （图中未示出） 上形成的用来 隔离次集电区 11 的深槽隔离区 12和用来隔离集电区 14的浅槽隔离区 13 所采用的工艺是 常规的光刻、 腐蚀和沟槽隔离填充。 接着在次集电区 11上制备集电极接触 20。
在进行本发明的下一个步骤前， 首先依据预设的集电区及基区的掺杂浓度确定出空间电 荷区的宽度及其在集电区中的位置。 如图 3所示， 集电区 14为 n型区， 有均匀施主杂质浓 度 ND， 基区 16 为 p型区， 有均匀受主杂质浓度 NA。 集电极 -基极结空间电荷区 15 (也称 作势垒区） 的宽度为 XD = Xn + Xp， ^为 n型区的空间电荷区宽度， Xp为 p 型区空间电 荷区宽度， 且由于半导体满足电中性条件， 空间电荷区内正负电荷总量相等， 即 NA x Xp = ND x Xn , 可以看到空间电荷区的宽度与其所在区的杂质浓度成反比。 杂质浓度高 的一边空间电荷区宽度小， 杂质浓度低的一边空间电荷区宽度大。 依据以下公式计算出空间 电荷区的宽度： 最大电场强度： ^ ( 1 )
ε0 接触电势差： Vz3 (2) 空间电荷区宽度： ( 3 )
Figure imgf000008_0001
其中， 电荷量 q =1.6xlO—19C， 真空介电常数 = 8.85x10— 14 F/cm， 硅的介电常数
=11.9， Nfl表示施主杂质浓度， ^表示空间电荷区宽度， Xn表示 n型区的空间电荷区宽 从上式可以看出： （1 ) 单边突变结的接触电势差^随着低掺杂一边的杂质浓度的增加 而增高。 （2) 单边突变结的空间电荷区宽度随杂质浓度增大而下降。 空间电荷区几乎全部在 轻掺杂的一边， 因而能带弯曲主要发生于这一区域。
本发明中涉及到的基极-集电极 p+n 突变结， NA远大于 ND , 则 Xn远大于 Xp， 即基区
16中电荷密度很大， 使空间电荷区的扩散几乎都发生在集电区 14中， 因而推出 XD Xn。 空间电荷区的宽度及在集电区的位置如图 3所示。
本发明 SiGe异质结双晶体管的制备过程的下一步如图 2b所示。 根据上一步所确定的空 间电荷区 15在集电区 14的位置， 利用离子注入技术在所述的集电区 14和空间电荷区 15重 叠区域中形成掺杂浓度相等的 Ν+层 17与 P+层 18组成的叠层， 且所述叠层中 Ν+层 17与 P+ 层 18的顺序可以互换。 所述 P+层 18中注入的离子为磷或砷， 所述 Ν+层 17中注入的离子为 硼， 并且所述 P+层 18和 Ν+层 17的掺杂浓度值范围为 1017 cm-3 ~1018 cm-3， 且掺杂浓度值呈 高斯分布。 根据空间电荷区 15 的宽度可以调节 P+层 18 和 Ν+层 17 的厚度， 范围为 10nm~90nm。
在所述的集电区 14和空间电荷区 15重叠区域中形成掺杂浓度相等的 Ν+层 17与 P+层 18 组成的叠层， 这种结构不仅可以改变局部势垒区电场值大小， 还可以改变势垒区电场的 分布情况。 由于电子速度饱和效应， 只要电子在到达势垒区电场峰值之前， 已经到达最大动 能， 即便是在增加电场强度， 其速度也基本不改变， 因此， 本发明的方案可以将电场峰值推 在最大电子动能之后， 也即电子在到达电场峰值时就已经速度饱和， 所以它不在依赖电场强 度而变化， 这样就显著减少了电离碰撞的几率， 从而提升基极-集电极结的雪崩击穿电压， 或在保持穿电压不变的情况下， 适当增加集电区 14的掺杂浓度， 高的掺杂使空间电荷区 15 变窄， 即可提高特征频率 fT， 而且较薄的空间电荷区 15 又可抑制雪崩击穿效应， 由此形成 了良性循环。
本发明的 SiGe异质结双晶体管的制备过程的下一步如图 2c所示。 在所述集电区 14上 制备包括本征 SiGe层 160 (由于本征 SiGe层 160的厚度较薄,一般研究者在定量研究、 分析 SiGe HBT频率等特性时均忽略本征层的存在)、 基区 P-SiGe:C层 161、 以及重掺杂的 P+多晶 硅外基区层 162的基区 16， 且在所述 P+多晶硅外基区层 162上制备基极接触 21 ; 其中， 由 于基区 16是重掺杂， 热处理过程会引起基区 16中的离子例如 B (硼)向集电区 14扩散， 导致 异质结和 pn 结不重合， 器件性能严重退化， 为了抑制这种情况的发生， 研究人员普遍采用 的方法是在异质集电结界面添加一层薄的本征 SiGe层 160， 所述本征 SiGe层 160能有效地 阻挡基区 16硼离子向集电区 14的扩散。 本发明结构中引入本征 SiGe层 160， 采用现有技 术中常规工艺， 例如超高真空化学气象淀积 （UHV / CVD)。 此外， 本发明结构中还引入了 发射极盖帽层 19， 用来控制发射区 22 的侧向腐蚀。 然后在发射极盖帽层 19上形成发射区 22和发射极接触 23， 且发射区 22与基区 16之间形成空间隔离区域 24， 采用常规的光刻和 腐蚀工艺形成发射区 22的结构， 如图 2c所示。
具体地， 所述的 SiGe-HBT晶体管的制备方法中， 所述 N+层 17或 P+层 18的掺杂浓度 值小于基区 P-SiGe： C层 161的掺杂浓度值， 且所述 N+层 17或 P+层 18的掺杂浓度值大于集 电区 14的掺杂浓度值。
本领域技术人员可以理解的是， 在本实施例中以 NPN型 SiGe-HBT 晶体管为示例说明 了本发明的制备方法， 但是本发明的方案同样适用于 PNP型 SiGe-HBT晶体管。 实施例二
本发明还提供一种 SiGe-HBT晶体管结构， 如图 2c所示， 包括：
由深槽隔离 12隔离出的次集电区 11， 及形成于所述次集电区 11上且由浅槽隔离区 13 隔离出的集电区 14， 且所述次集电区上形成有集电极接触 20。
基区 16， 形成于所述集电区 14之上， 包括本征 SiGe层 160、 重掺杂的 P+多晶硅外基 区层 162以及位于所述的本征 SiGe层 160和重掺杂的 P+多晶硅外基区层 162之间的基区 P- SiGe： C层 161， 所述集电区 14和基区 16的接触界面形成有一集电极 -基极结空间电荷区 15， 且所述 P+多晶硅外基区层 162层上形成有基极接触 21。
发射区 22， 形成于所述 P+多晶硅外基区层 162和发射极盖帽层 19之上， 且形成有发射 极接触 23。
具体地， 所述 P+层 18中注入的离子为磷或砷， 所述 N+层 17中注入的离子为硼； 所述 N+层 17和 P+层 18的掺杂浓度值范围为 1017~1018cm- 3， 且所述掺杂浓度值呈高斯分布； 所 述 N+层 17或 P+层 18的掺杂浓度值小于基区 P-SiGe： C层 161的掺杂浓度值； 所述 N+层 17 或 P+层 18的掺杂浓度值大于集电区 14的掺杂浓度值。 进一步具体地， 根据分布在集电区 14中的空间电荷区 15的宽度可以调节所述 N+层 17或 P+层 18的厚度， 范围为 10nm到 90nm。
所述 P+层或 N+层组成的叠层结构不仅可以改变局部势垒区电场值大小， 还可以改变势 垒区电场的分布情况， 在保证不牺牲渡越时间、 截止频率以及最大振荡频率的情况下， 提高 基极 -集电极击穿电压， 或者在保证击穿电压不恶化的情况下， 增加集电区掺杂浓度， 提高 空间电荷区渡越时间和截止频率。 本领域技术人员可以理解的是， 在本实施例中以 NPN型 SiGe- HBT晶体管为示例说明了本发明的结构， 但是本发明的方案同样适用于 PNP型 SiGe- HBT晶体管。
综上所述， 本发明通过采用离子注入技术， 在空间电荷区域中先注入硼形成一道 N+层 17， 浓度在 1017cm- 3 ~1018cm- 3范围内， 厚度在十到几十纳米 （具体厚度根据空间电荷区的宽 度调节）， 且掺杂浓度值呈高斯分布； 然后在 N+层 17上方注入磷或砷形成一道 P+层 18， 浓 度也在 1017cm- 3 ~1018cm- 3范围内， 且 P+层 18浓度值与 N+层 17浓度值相同， 且呈高斯分 布， 厚度在十到几十纳米 （具体厚度根据耗尽层宽度调节）。 由于增加一个薄的 P+层 18， 可 以降低局部电场强度， 且不改变势垒区电场方向。 但与此同时， 引入了一部分空穴， 势必增 加基区 16电流， 导致放大系数减小， 所以我们需要加入一层含等电量电子的 N+层 17来抵 消引入的空穴， 使得空间电荷区的宽度 15 不变。 对于不同功能的器件可根据实际情况加入 不同厚度和数量的 P+层 18和 N+层 17， 而且 N+层 17与 P+层 18的上下顺序可以互换。 这种 结构不仅可以改变局部势垒区电场值大小， 还可以改变势垒区电场的分布情况。 由于电子速 度饱和效应， 只要电子在到达势垒区电场峰值之前， 已经到达最大动能， 即便是在增加电场 强度， 其速度也基本不改变， 因此， 本发明的方案可以将电场峰值推在最大电子动能之后， 也即电子在到达电场峰值时就已经速度饱和， 所以它不在依赖电场强度而变化， 这样就显著 减少了电离碰撞的几率， 从而提升基极-集电极结的雪崩击穿电压， 或在保持穿电压不变的 情况下， 适当增加集电区 14的掺杂浓度， 高的掺杂使空间电荷区 15变窄， 即可提高特征频 率 fT， 而且较薄的空间电荷区 15又可抑制雪崩击穿效应， 由此形成了良性循环。
上述实施例仅例示性说明本发明的原理及其功效， 而非用于限制本发明。 任何熟悉此技术 的人士皆可在不违背本发明的精神及范畴下， 对上述实施例进行修饰或改变。 因此， 举凡所 属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效 修饰或改变， 仍应由本发明的权利要求所涵盖。

Claims

权利要求书
1. 一种 SiGe-HBT晶体管的制备方法， 其特征在于， 包括：
提供一半导体衬底， 在该衬底上制备出次集电区， 并在所述次集电区上形成藉由 浅槽隔离区隔离出的集电区；
依据预设的集电区和基区的掺杂浓度确定出空间电荷区的宽度及其在所述集电区 中的位置；
利用离子注入技术在所述的集电区和空间电荷区重叠区域中形成掺杂浓度相等的 P+层与 N+层组成的叠层；
在所述集电区上制备包括本征 SiGe层、 基区 P-SiGe:C层、 以及重掺杂的 P+多晶 硅外基区层的基区， 以在所述集电区和基区的接触界面形成一集电极-基极结空间电荷 区， 且在所述 P+多晶硅外基区层上制备出发射极盖帽层和发射区；
分别在所述的基区、 发射区、 次集电区分别上制备出基极接触、 发射极接触、 集 电极接触。
2. 根据权利要求 1所述的 SiGe-HBT晶体管的制备方法， 其特征在于， 所述 P+层中注入的 离子为磷或砷。
3. 根据权利要求 1所述的 SiGe-HBT晶体管的制备方法， 其特征在于， 所述 N+层中注入的 离子为硼。
4. 根据权利要求 1 所述的 SiGe-HBT 晶体管的制备方法， 其特征在于， 所述掺杂浓度值范 围为 1017cm- 3~1018cm- 3， 且所述掺杂浓度值呈高斯分布。
5. 根据权利要求 1所述的 SiGe-HBT晶体管的制备方法， 其特征在于， 所述 P+层或 N+层的 掺杂浓度值小于基区 P-SiGe:C层的掺杂浓度值。
6. 根据权利要求 1所述的 SiGe-HBT晶体管的制备方法， 其特征在于， 所述 P+层或 N+层的 掺杂浓度值大于集电区的掺杂浓度值。
7. 根据权利要求 1所述的 SiGe-HBT晶体管的制备方法， 其特征在于， 所述 P+层和 N+层的 厚度为 10nm~90nm。
8. 一种 SiGe-HBT晶体管， 其特征在于， 包括：
次集电区及形成于所述次集电区上且由浅槽隔离区隔离出的集电区， 且所述次集电 区上形成有集电极接触；
基区， 形成于所述集电区之上， 包括本征 SiGe 层、 重掺杂的 P+多晶硅外基区层以 及位于所述的本征 SiGe层和重掺杂的 P+多晶硅外基区层之间的基区 P-SiGe:C层， 所述 集电区和基区的接触界面形成有一集电极-基极结空间电荷区， 且所述重掺杂的 P+多晶硅 外基区层上形成有基极接触；
发射区， 形成于所述 P+多晶硅外基区层和发射极盖帽层上， 且形成有发射极接触； 所述的集电区和空间电荷区重叠区域中形成有掺杂浓度相等的 P+层与 N+层组成的叠 层。
9. 根据权利要求 8所述的 SiGe-HBT晶体管， 其特征在于， 所述 P+层中注入的离子为磷或 砷。
10.根据权利要求 8所述的 SiGe-HBT晶体管， 其特征在于， 所述 N+层中注入的离子为硼。
11.根据权利要求 8所述的 SiGe-HBT晶体管， 其特征在于， 所述 P+层和 N+层的掺杂浓度值 范围为 1017 cm- 3 ~1018cm- 3， 且所述掺杂浓度值呈高斯分布。
12.根据权利要求 8所述的 SiGe-HBT晶体管， 其特征在于， 所述 P+层或 N+层的掺杂浓度值 小于基区 P-SiGe:C层的掺杂浓度值。
13.根据权利要求 8所述的 SiGe-HBT晶体管， 其特征在于， 所述 P+层或 N+层的掺杂浓度值 大于集电区的掺杂浓度值。
14.根据权利要求 8 所述的 SiGe-HBT 晶体管， 其特征在于， 所述 P+层或 N+层的厚度为 10nm〜90nm。
PCT/CN2012/074801 2012-03-09 2012-04-27 SiGe-HBT晶体管及其制备方法 WO2013131312A1 (zh)

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