WO2013118323A1 - 表示装置および表示方法 - Google Patents
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- WO2013118323A1 WO2013118323A1 PCT/JP2012/067477 JP2012067477W WO2013118323A1 WO 2013118323 A1 WO2013118323 A1 WO 2013118323A1 JP 2012067477 W JP2012067477 W JP 2012067477W WO 2013118323 A1 WO2013118323 A1 WO 2013118323A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0224—Details of interlacing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
Definitions
- the present invention relates to a display device, and more particularly to an active matrix display device and a display method in which the scanning order is changed.
- a drive method (frame inversion drive method) is known in which the polarity of the voltage applied to the liquid crystal is inverted every frame.
- display defects such as flicker are likely to occur at the time of display.
- the positive / negative polarity of the applied voltage is inverted for each frame while the polarity of the applied voltage is inverted for each horizontal scanning line.
- Driving method (referred to as “line inversion driving method”) or a driving method (“dot inversion”) that inverts the positive / negative polarity of the applied voltage for each frame while inverting the positive / negative polarity of the applied voltage for each pixel adjacent in the vertical and horizontal directions. This is called “driving system”.
- the video signal potential may change greatly depending on the image to be displayed.
- the voltage amplitude increases and the power consumption tends to increase.
- Japanese Patent Application Laid-Open No. 7-64512 discloses a liquid crystal driving device that determines the order in which scanning signal lines are selected so that the number of charge / discharge cycles of a liquid crystal is minimized in a configuration that uses binary digital video signals.
- a configuration is disclosed. With this configuration, the power consumption required for charging and discharging the liquid crystal is minimized, so that the power consumption of the entire apparatus is reduced.
- an object of the present invention is to provide a display device and a display method capable of reducing the total amount of potential change of video signal lines in a display device using analog data.
- a first aspect of the present invention is to form a plurality of pixels arranged along a plurality of video signal lines for transmitting a plurality of video signals and a plurality of scanning signal lines intersecting with the plurality of video signal lines.
- a display device for displaying an image by a unit, A video signal line driving circuit for driving the plurality of video signal lines based on an image signal representing the image; A scanning signal line driving circuit for selectively driving the plurality of scanning signal lines; When the plurality of scanning signal lines are selected in the arrangement order, the plurality of scanning signal lines are driven such that the plurality of video signal lines are driven with power smaller than the power required for driving the plurality of video signal lines.
- a scanning order determining circuit for determining the order of selection based on the image signal.
- the scanning order determination circuit has a value obtained by integrating the absolute values of potential fluctuation amounts in at least some of the plurality of video signal lines generated each time the scanning signal line selected by the scanning signal line driving circuit is switched. It is characterized in that at least a part of the order is determined so as to be smaller.
- the scanning order determining circuit determines a scanning signal line that minimizes a value obtained by integrating the absolute value of the potential fluctuation amount when it is selected next, and when the scanning signal line is selected after the scanning signal line is selected.
- the scanning signal line having the smallest value obtained by integrating the absolute value of the potential fluctuation amount is determined.
- the scanning order determining circuit is selected next to display the image after the scanning signal line to be selected last to display the image displayed immediately before the image is displayed is selected. Then, the scanning signal line having the smallest value obtained by integrating the absolute value of the potential fluctuation amount is the scanning signal line to be selected first among the plurality of scanning signal lines.
- the scanning order determination circuit selects a scanning signal line having the smallest integrated value of absolute values of differences between a predetermined potential and potentials in the plurality of video signal lines as the first of the plurality of scanning signal lines.
- a scanning signal line to be selected is used.
- the scanning order determination circuit is characterized in that a scanning signal line selected for displaying the first row of the image is a scanning signal line to be selected first among the plurality of scanning signal lines.
- the scanning order determination circuit is configured to calculate the integrated value based on a predetermined number of upper bits in digital gradation data indicating the potential to be applied to the plurality of video signal lines, which is gradation data included in the image signal. Is calculated.
- the scanning order determining circuit fixes the order determined until a predetermined waiting time elapses or a predetermined start time after determining the order.
- a ninth aspect of the present invention is the eighth aspect of the present invention.
- the scanning order determination circuit sets the time point when the change of the image is detected as the start time point, or when it is determined that the image is a still image, than when the image is determined to be a moving image.
- a long time is defined as the waiting time.
- the scanning order determining circuit groups the plurality of video signal lines for every predetermined number of adjacent scanning signal lines, and determines the order for each group.
- An eleventh aspect of the present invention is the tenth aspect of the present invention.
- the image processing apparatus further includes a memory having a size for storing digital gradation data indicating potentials to be applied to a plurality of video signal lines included in one of the groups.
- the scanning order determining circuit integrates absolute values of potential fluctuation amounts in the video signal lines every predetermined integer multiple of 2 or more among the plurality of video signal lines.
- the scanning signal line driving circuit is an address decoder
- the scanning order determination circuit is characterized in that an address corresponding to the order is given to the scanning signal line driving circuit.
- the scanning signal line drive circuits are respectively disposed at positions on both ends of the plurality of scanning signal lines so as to give a signal to at least one end of the plurality of scanning signal lines.
- a fifteenth aspect of the present invention is the formation of a plurality of pixels disposed along a plurality of video signal lines for transmitting a plurality of video signals and a plurality of scanning signal lines intersecting with the plurality of video signal lines.
- a method for displaying an image on a screen A video signal line driving step for driving the plurality of video signal lines based on an image signal representing the image; A scanning signal line driving step for selectively driving the plurality of scanning signal lines; When the plurality of scanning signal lines are selected in the arrangement order, the plurality of scanning signal lines are driven such that the plurality of video signal lines are driven with power smaller than the power required for driving the plurality of video signal lines.
- a scanning order determining step for determining the order of selection based on the image signal.
- the selection of the plurality of scanning signal lines is performed such that the plurality of video signal lines are driven with lower power than when the plurality of scanning signal lines are selected in the arrangement order. Since the order is determined, the power consumption for driving the video signal lines can be reduced.
- the second aspect of the present invention in order so that the value obtained by integrating the absolute values of the potential fluctuation amounts in at least some of the plurality of video signal lines generated each time the scanning signal line is switched is minimized. Since at least a part is determined, power consumption for driving the video signal line can be reduced.
- the scanning signal line that minimizes the value obtained by integrating the absolute value of the potential fluctuation amount is determined, and after the scanning signal line is selected, When selected, the scanning signal line having the smallest value obtained by integrating the absolute value of the potential fluctuation amount is determined, so that the power consumption for driving the video signal line can be reduced.
- the next display is performed to display the image.
- the scanning signal line having the smallest value obtained by integrating the absolute value of the potential fluctuation amount is selected as the scanning signal line to be selected first among the plurality of scanning signal lines.
- the integrated value of the potential fluctuation amount in the video signal line can be minimized even when the image is switched. Therefore, power consumption for driving the video signal line can be greatly reduced.
- the scanning signal line having the smallest integrated value of the absolute values of the differences between the predetermined potential and the potentials of the plurality of video signal lines is selected from the plurality of scanning signal lines. Since the scanning signal line to be selected first is used, for example, when a specific potential is applied to the video signal line at the time of device start-up, power-on, standby, or vertical blanking period, the video signal line The power consumption for driving can be reduced.
- the scanning signal line selected for displaying the first line of the image is the scanning signal line to be selected first among the plurality of scanning signal lines.
- the potential of the video signal line is indefinite, such as in a vertical blanking period, power consumption for driving the video signal line can be reduced with a simple configuration.
- the integrated value is calculated based on a predetermined number of high-order bits in the digital gradation data, the calculation can be simplified, the overall speed of the calculation is improved, and Power consumption used for calculation can be reduced.
- the predetermined standby time elapses or the order determined until the predetermined start time is fixed.
- the power consumption used can be reduced.
- the time point when the change of the image is detected is set as the start time point, or when the image is determined to be a moving image when the image is determined to be a still image. Since the long time is set as the standby time, the number of calculations can be appropriately reduced in accordance with the change of the image, and the power consumption used for the calculations can be reduced.
- the display quality can be kept good.
- a memory having a size for storing digital gradation data indicating potentials to be applied to a plurality of video signal lines included in one of the groups is typically provided.
- the absolute value of the potential fluctuation amount in each of the video signal lines of every two or more predetermined integer multiples of the video signal lines is integrated.
- the amount can be reduced, and the power consumption used for calculation can be reduced.
- a device by using a general address decoder as a scanning signal line driving circuit, a device can be manufactured with a simple configuration, and the scanning signal line can be manufactured with a simple configuration.
- the selection order can be changed freely.
- the scanning signal line drive circuit is disposed at each of the positions on both ends of the plurality of scanning signal lines, the scale (size) of one (end side) circuit is provided. Can be reduced. Further, when the scanning signal is given from both ends, the scanning signal is not distorted, so that the scanning line can be selected with high speed and reliability.
- the same effects as those of the first aspect of the present invention can be achieved in the display method.
- FIG. 1 is a block diagram showing an overall configuration of an active matrix liquid crystal display device according to a first embodiment of the present invention. It is a circuit diagram which shows the equivalent circuit of the pixel formation part in the said embodiment. It is a block diagram which shows the structure of the display control circuit in the said embodiment. It is a flowchart which shows the flow of the process which calculates the order of row selection in the scanning order calculation part in the said embodiment. It is a figure which shows the selection order of four scanning signal lines in the simple structural example in the 1st structural example of the said embodiment, and the voltage value applied to a video signal line. It is a wave form diagram of each signal in the simple structural example in the said embodiment.
- FIG. 15 is a waveform diagram showing a change in potential of each scanning signal line when selected in the selection order shown in FIG. 14.
- FIG. 14 it is a figure which shows the example which divided the display screen into six blocks.
- FIG. 14 it is a figure which shows partially the electric potential change of each scanning signal line in six blocks.
- FIG. 1 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to a first embodiment of the present invention.
- the liquid crystal display device includes a display control circuit 200, a video signal line drive circuit (source driver) 300, a drive control unit including a scanning signal line drive circuit (gate driver) 400, and a display unit 500.
- the display unit 500 includes a plurality (M) of video signal lines SL (1) to SL (M), a plurality (N) of scanning signal lines GL (1) to GL (N), and a plurality of these.
- FIG. 2 shows an equivalent circuit of the pixel formation portion P (m, n) in the display portion 500 of the present embodiment.
- each pixel forming portion P (m, n) has a video signal line SL (m) passing through the intersection and a gate signal connected to the scanning signal line GL (n) or adjacent thereto.
- a common liquid crystal layer is provided between the pixel electrode Epix and the common electrode Ecom.
- each pixel formation portion P (m, n) a liquid crystal capacitance (also referred to as “pixel capacitance”) Clc is formed by the pixel electrode Epix and the common electrode Ecom opposed thereto with the liquid crystal layer interposed therebetween.
- Each pixel electrode Epix is provided with two video signal lines SL (m) and SL (m + 1) so as to sandwich the pixel electrode Epix, and one of these two video signal lines is connected to the pixel electrode via the TFT 10. It is connected to the pixel electrode Epix.
- the TFT 10 uses amorphous silicon that can be easily and inexpensively manufactured as a semiconductor layer.
- amorphous silicon that can be easily and inexpensively manufactured as a semiconductor layer.
- other well-known materials such as In-Ga-Zn-O (IGZO) -based oxides and the like can be used.
- continuous grain boundary silicon can be used.
- IGZO In—Ga—Zn—O
- the response is fast and the current leakage is very small, so that low frequency driving (intermittent driving), etc.
- a driving mode with low power consumption can be realized. From this, in addition to the effect of this embodiment, power consumption can be further reduced.
- the display control circuit 200 receives a display data signal DAT and a timing control signal TS sent from the outside, and controls the digital image signal DV and the timing for displaying an image on the display unit 500.
- the display data signal DAT from the outside includes, for example, a total of 18-bit parallel data composed of red display data, green display data, and blue display data, each of which is 6-bit data to be supplied to one pixel formation unit. Contains. These data are given to the video signal line corresponding to each color.
- the video signal line driving circuit 300 receives the digital image signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200 and receives each pixel forming unit P in the display unit 500.
- Driving video signals S (1) to S (M) are applied to the video signal lines SL (1) to SL (M) in order to charge the pixel capacitance Clc (and auxiliary capacitance) of (m, n).
- the digital image signal DV indicating the voltage to be applied to each of the video signal lines SL (1) to SL (M) is sequentially supplied at the timing when the pulse of the source clock signal SCK is generated. Retained.
- the held digital image signal DV is converted to an analog voltage at the timing when the pulse of the latch strobe signal LS is generated.
- These analog voltages are applied simultaneously to all the video signal lines SL (1) to SL (M) as drive video signals. That is, in the present embodiment, the line sequential driving method is adopted as the driving method of the video signal lines SL (1) to SL (M).
- a line inversion driving method which is a driving method for inverting the positive / negative polarity of the voltage applied to the pixel liquid crystal every frame.
- the line inversion driving method which is a driving method for inverting the image for each row in the display unit 500 and for each frame, may be employed, or the dot inversion driving method described above may be employed.
- the scanning signal line driving circuit 400 Based on the gate address signal GA output from the display control circuit 200, the scanning signal line driving circuit 400 performs the corresponding active scanning with respect to one of the scanning signal lines GL (1) to GL (N). One of the signals G (1) to G (N) is applied. Specifically, the scanning signal line driving circuit 400 is an address decoder, and is one of the scanning signal lines GL (1) to GL (N) according to the address included in the received gate address signal GA. And an active scanning signal is applied to the selected scanning signal line. Hereinafter, such an operation is also expressed as selecting a row (which is a display row corresponding to the selected scanning signal line).
- the scanning signal line driver circuit 400 is configured to apply the scanning signal only from one end of the scanning signal lines GL (1) to GL (N).
- the structure provided in the both right and left sides of 500 may be sufficient. Then, the scale (size) of one (end side) circuit can be reduced.
- scanning signals can be quickly applied to the scanning signal lines GL (1) to GL (N), and the scanning signals are not distorted. It can be carried out.
- the display control circuit 200 scans the signal lines GL (1) to GL (N) so that the total amount (integrated value) of potential fluctuations of the video signal lines SL (1) to SL (M) is minimized. ) Are selected one by one, and the addresses are sequentially determined so that all are finally selected, and the gate address signal GA is output.
- a common electrode driving circuit (not shown) that inverts the common voltage Vcom, which is a voltage to be applied to the common electrode of the liquid crystal, for each frame is provided.
- Vcom common voltage
- the common electrode driving circuit generates a voltage that switches between two types of reference voltages for each row and for each frame in accordance with the polarity inversion signal from the display control circuit 200, and this is used as the common voltage Vcom. It supplies to the common electrode of the display part 500.
- the driving video signals are applied to the video signal lines SL (1) to SL (M), and the scanning signals are applied to the scanning signal lines GL (1) to GL (N) in the order described later. As a result, an image is displayed on the display unit 500.
- the configuration and operation of the display control circuit 200 having a feature in calculating the scanning order of the scanning signal lines will be described with reference to FIG.
- FIG. 3 is a block diagram showing a configuration of the display control circuit 200 in the present embodiment.
- the display control circuit 200 includes an input frame memory 21, an output frame memory 22, a scanning order calculation unit 23, a scanning order setting unit 24, a timing control unit 25, and an address output unit 26. .
- the timing control unit 25 receives a timing control signal TS sent from the outside, and controls to control the operations of the input frame memory 21, the output frame memory 22, the scanning order calculation unit 23, and the scanning order setting unit 24.
- a signal CT and a source start pulse signal SSP, a source clock signal SCK, and a latch strobe signal LS for controlling the timing of displaying an image on the display unit 500 are output. Further, the timing control unit 25 gives a timing control signal TS to the address output unit 26.
- the input frame memory 22 stores an external display data signal DAT for one frame.
- the frame memory 22 supplies the stored display data signal DAT for one frame to the output frame memory 22 and the scanning order calculation unit 23 at an appropriate timing based on the control signal CT from the timing control unit 25. Thereafter, the input frame memory 22 stores the display data signal DAT for the next one frame that is subsequently sent from the outside. Therefore, the display data signal DAT stored in the output frame memory 22 is data one frame before when viewed from the display data signal DAT stored in the input frame memory 21.
- the input frame memory 22 may be incorporated in a host controller (not shown) that provides the display data signal DAT to the display control circuit 200.
- the scanning order calculation unit 23 selects a certain reference row (that is, after one horizontal scanning period) on the basis of the display data signal DAT from the outside, and then selects which row the video signal line SL (1). Calculate whether the total amount (integrated value) of potential fluctuations of SL (M) is the smallest. Since the potential fluctuation of the video signal line causes charge / discharge with respect to the capacitance including the parasitic capacitance of the video signal line, the power consumption increases as the total amount of the potential fluctuation increases.
- the scanning order calculation unit 23 calculates this appropriate order by the processing procedure shown in FIG.
- FIG. 4 is a flowchart showing a flow of processing for calculating the row selection order in the scanning order calculation unit 23.
- the scanning order calculation unit 23 sets the first reference row to be selected to the first row.
- this reference row is a row serving as a reference for calculating the total amount (integrated value) of the potential fluctuation of the video signal line that should occur when another row is selected next.
- the process of setting the first row as the first row to be selected in one frame is simple, and the potentials of the video signal lines SL (1) to SL (M) are indefinite in the vertical blanking period.
- This configuration is suitable in some cases (that is, when a specific potential is not applied). This configuration is referred to as a first configuration.
- a specific potential may be applied to the video signal lines SL (1) to SL (M) when the apparatus is turned on, on standby, or in the vertical blanking period.
- the first row is always selected first as in the first configuration, the potential of the video signal line generated when the first row is selected from the specific potential.
- the total amount of variation may be large. Therefore, in this case, the total amount (integrated value) of potential fluctuations of the video signal lines SL (1) to SL (M) is minimized with reference to the specific potential instead of the processing in step S10.
- a configuration in which a row is selected as the first reference row is preferred. This configuration is referred to as a second configuration.
- the specific potential is not applied as described above, but the potential applied in the row selected at the end of one frame is directly applied to the video signal lines SL (1) to SL (M ) May be maintained. Also in this case, if the first row is always selected first as in the first configuration, the total amount of potential fluctuation of the video signal line that occurs when the first row is selected becomes large. In some cases. Therefore, in this case, instead of the processing in step S10, the potentials of the video signal lines SL (1) to SL (M) are based on the potential applied in the last selected row of the one frame. A configuration in which the row with the smallest potential fluctuation total amount (integrated value) is selected as the first reference row is preferable. This configuration is referred to as a third configuration.
- the potential fluctuation amount of the video signal line may increase depending on the operation mode of the apparatus. If the 2nd or 3rd structure is employ
- the scanning order calculation unit 23 calculates, for each row, the total amount (integrated value) of potential fluctuations of the video signal line that should occur when the next row is selected (step S20). . That is, which line is selected from the reference lines, the total amount of potential fluctuations of the video signal lines SL (1) to SL (M) is the smallest. Usually, the total amount of potential fluctuations for each row is not calculated. I can't judge. Therefore, the total amount of potential fluctuation shown in the following equation (1) is calculated for each row.
- a represents a reference row (initial value is 1)
- i represents a video signal line number (column number)
- j represents a scanning signal line number, that is, a row number.
- Vji indicates the potential applied to the i-th video signal line (i-th column) when the j-th row (j-th scanning signal line) is selected.
- the potential fluctuation amount of the video signal line is calculated based on the gradation data corresponding to the video signal to be applied to the video signal line. Specifically, the gradation data corresponding to each column (each video signal line) of the reference row and the row to be calculated is read from the input frame memory 21, and the potential is calculated based on the above equation (1). Calculate the total amount of fluctuation (integrated value).
- the scanning order calculation unit 23 calculates the gradation value (for example, 0 to 255) indicated by the display data corresponding to the driving video signal to be given to a certain video signal line and the voltage value of the driving video signal.
- a table hereinafter, referred to as “grayscale voltage table” indicating the correspondence relationship is included.
- the scanning order calculation unit 23 sets the next line as a reference line (step S40), determines whether all the lines have been determined as the next line (step S50), and if not determined ( In the case of No in step S50, the process returns to step S20, and the process is repeated until all the rows are determined (S50 ⁇ S20 ⁇ ... ⁇ S50), and when all the rows are determined (in step S50). In the case of Yes), the processing for one frame is completed. Thereafter, the display data signal DAT for the next frame is supplied to the input frame memory 21, and the same operation is performed.
- the scanning order calculation unit 23 generates scanning order data Dso indicating the selection order, and supplies it to the scanning order setting unit 24.
- the scanning order setting unit 24 supplies the received scanning order data Dso to the address output unit 26, and outputs the digital image signal DV in a data order corresponding to the order indicated by the scanning order data Dso.
- a sequence control signal Co for controlling the output 22 is supplied to the output frame memory 22.
- the output frame memory 22 receives and stores the display data signal DAT for one frame from the input frame memory 21.
- the display data signal DAT is grayscale data on the assumption that the scanning signal lines are selected in the arrangement order. Are arranged.
- the scanning order setting unit 24 controls the output frame memory 22 so as to output in the above order by changing (rearranging) or rearranging the arrangement order.
- the address output unit 26 supplies an address indicating the corresponding scanning line as the gate address signal GA to the scanning signal line driving circuit 400 which is an address decoder in accordance with the received scanning order data Dso.
- the scanning signal line driving circuit 400 selects one of the scanning signal lines GL (1) to GL (N) according to the address included in the received gate address signal GA.
- the display control circuit 200 selects the scanning signal lines GL (1) to GL (N) in the above order, and the driving video signals S (1) to S (1) to be given when the row is selected.
- S (M) is applied to the corresponding video signal lines SL (1) to SL (M). In this way, the total amount of potential fluctuation of the video signal line can be minimized. This will be described with reference to FIGS. 5 and 6 using a simple specific example.
- FIG. 5 is a diagram showing the selection order of the four scanning signal lines and the voltage value applied to the video signal lines in the first configuration example described above.
- the next selection order in the next frame is also shown. As described in the first configuration, the scanning signal line SL ( Since 1) is selected, the result is the same selection order as the selection order of the previous frame.
- FIG. 6 is a waveform diagram of each signal in the display device as such a simple example.
- the scanning signal line GL (1) becomes active from time t1 to t2.
- the scanning signal line GL (3) becomes active from time t2 to t3
- the scanning signal line GL (2) becomes active from time t3 to t4
- the scanning signal line GL (4) becomes active from time t4 to t5.
- the corresponding driving video signal voltages V11 to V41 are applied to the video signal line SL (1).
- the potential change of the video signal line SL (1) is gentle and the total amount of potential change is the smallest.
- the driving video signal voltages V11 to V41 corresponding to the arrangement order of the scanning signal lines are applied, the voltage V11 greatly changes from the voltage V11 to the voltage V21 at the time t2, and the voltage V31 to the voltage at the time t4.
- the total amount of potential change of the video signal line SL becomes much larger than in the case shown in FIG.
- FIG. 7 is a diagram showing the selection order of the four scanning signal lines and the voltage value applied to the video signal lines in the third configuration.
- the display device assumed in FIG. 7 is the same as the above-described simple display device assumed in FIG. 5, and the driving video signal voltage Vj1 (V11 to V41) is also the same.
- the row corresponding to the scanning signal line selected at the beginning of each frame is applied in the row corresponding to the scanning signal line selected at the end of the previous frame. Based on the potential, the row with the smallest total amount (integrated value) of potential fluctuations of the video signal lines SL (1) to SL (M) is selected. Therefore, as shown in FIG.
- the first row of the next frame is the scanning signal line SL (4) corresponding to the same fourth row as the last row of the previous frame. Then, with the fourth row as a reference, the total amount of potential fluctuation is the smallest in the second row. Similarly, the third row is selected next, and the first row is selected last. Is done. As described above, when the scanning signal lines are selected in the order in which the total amount of potential fluctuation of the video signal lines is made smaller than in the case where the scanning signal lines are selected in the arrangement order of the scanning signal lines, the video signal lines are driven. Therefore, power consumption can be reduced.
- the row with the smallest amount of potential fluctuation from the initially set reference row is selected as the next row, the selected next row is set as the next reference row, and the next row is set as the next reference row.
- the selection order for all rows is determined, and the scanning signal lines are selected in this order.
- FIG. 8 is a partial block diagram showing display data signals input to the input frame memory and the scanning order calculation unit.
- the input frame memory 21 receives the display data signal DAT from the outside.
- the display data signal DAT includes 6-bit gradation data for each pixel (RGB pixels), and there are no bits to be masked.
- the symbol [5: 0] indicating the data content is attached to the display data signal DAT.
- the display data signal DATm given from the input frame memory 21 to the scanning order calculation unit 23 is the same signal as the display data signal DAT, but the lower 3 bits of the 6-bit gradation data are masked. Yes.
- a symbol [5: 3] indicating the data content is attached to the display data signal DATm.
- the upper 3 bits of data that are not masked are referred to as determination data.
- FIG. 9 is a diagram showing the selection order of the four scanning signal lines, the voltage value applied to the video signal lines, and the corresponding input data and determination data, similar to FIG. As shown in FIG. 7, here, in the same simple display device as in FIG. 5, the level corresponding to the drive video signal voltage Vj1 (V11 to V41) applied to the video signal line SL (1).
- the input data indicating the key data value and the 6-bit input data for example, “1111010”
- the upper 3 bits of data for example, “111” are set as the determination data.
- step S30 shown in FIG. 4 described above the scanning order calculation unit 23 sequentially calculates the total amount of variation represented by the above equation (1) for each row, but is applied to the video signal line as in the above embodiment.
- the upper 3 bits by masking the lower 3 bits
- this 3-bit data is referred to as determination data here.
- the determination data is the total potential fluctuation amount as it is, but in actuality, it is an integrated value of the potential fluctuation amounts of a plurality of video signal lines.
- the amount indicated by the lower bits is discarded, making it impossible to calculate an accurate amount of potential fluctuation.
- the amount of calculation can be reduced, and the calculation speed is sufficiently high. If not, it is a suitable configuration. In addition, even if the calculation speed is sufficient, it is preferable in that power consumption by calculation can be reduced.
- the upper bits are not limited to 3 bits as long as the potential fluctuation amount can be calculated, and may be any number of upper bits that is smaller than the number of bits of the entire input data.
- the configuration of the first modification is applied to the configuration of the second modification, power consumption can be further reduced.
- the order determination method may be partially applied.
- FIG. 10 is a block diagram showing the configuration of the display control circuit in the second embodiment of the present invention.
- the display control circuit 210 shown in FIG. 10 performs the same operation with the same configuration except that a display switching detection unit 28 is newly provided, as can be seen by comparison with the display control circuit 200 shown in FIG. Therefore, the same components are denoted by the same reference numerals and the description thereof is omitted, and the operation of the newly provided display switching detection unit 28 will be described.
- the display switching detection unit 28 shown in FIG. 10 receives a display data signal DAT given from the outside, and detects a change in the displayed image. For example, when the same still image such as wallpaper is continuously displayed, the order in which the total amount of potential fluctuation of the video signal lines calculated by the scanning order calculation unit 23 is smaller should not change. Therefore, it is not preferable to repeatedly perform the same calculation from the viewpoint of reducing power consumption. Therefore, the display switching detection unit 28 monitors the content of the image for each frame (for example, the integrated value of the pixel gradation value), and when the change is detected, the update control signal Cr is sent to the scanning order calculation unit 23. give.
- the scanning order calculation unit 23 calculates the selection order for all (that is, one frame) rows as in the first embodiment. . Subsequent operations such as selection of the scanning signal line are the same as those in the first embodiment.
- the selection order is calculated by the scanning order calculation unit 23 only when the display change detection unit 28 detects a change in the image.
- the number of calculations in the scanning order calculation unit 23 can be reduced, and power consumption due to the calculations can be reduced.
- FIG. 11 is a block diagram showing a configuration of a display control circuit in a modification of the second embodiment of the present invention.
- the display control circuit 220 shown in FIG. 11 is the same as the display control circuit 210 shown in FIG. 10 except that a change frequency setting unit 29 is provided instead of the display switching detection unit 28. Since the same operation is performed in the configuration, the same components are denoted by the same reference numerals and the description thereof is omitted, and the operation of the change frequency setting unit 29 will be described.
- the change frequency setting unit 29 shown in FIG. 11 receives a display data signal DAT given from the outside, detects whether the displayed image is a still image or a moving image, and if it is a still image, it is a moving image.
- the update control signal Cr is output with a longer period (less frequently) than the case. For example, when a still image is displayed, the order in which the total amount of potential fluctuation amount of the video signal line calculated by the change frequency setting unit 29 is smaller than that when a moving image is displayed is frequently Should not change. Therefore, it is not preferable to perform the same or similar calculation repeatedly (with high frequency) in a short cycle from the viewpoint of reducing power consumption.
- the change frequency setting unit 29 monitors the content of the image for each frame (for example, the integrated value of the pixel gradation value), and determines that the image is a still image at a long cycle (for example, one second). Times), the update control signal Cr is supplied to the scanning order calculation unit 23, and when it is determined to be a moving image, the update control signal Cr is supplied to the scanning order calculation unit 23 in a short cycle (for example, every frame).
- FIG. 12 is a block diagram showing a configuration of a display control circuit in a further modification of the second embodiment of the present invention. Unlike the operation of the change frequency setting unit 29 shown in FIG. 11, the change frequency setting unit 29 shown in FIG. 12 determines whether the image represented by the display data signal DAT is a moving image or a still image. Is received from the outside (for example, a host controller), based on the received image content information Di, the same determination as in the above modification is performed, and the update control signal Cr is calculated in the corresponding cycle (frequency). Part 23 is given.
- the scanning order calculation unit 23 illustrated in FIG. 11 or FIG. 12 When receiving the update control signal Cr from the change frequency setting unit 29, the scanning order calculation unit 23 illustrated in FIG. 11 or FIG. 12 performs all (that is, one frame) as in the case of the first embodiment. Calculate the order of selection for rows. Subsequent operations such as selection of scanning signal lines are the same as those in the first or second embodiment.
- the change frequency setting unit 29 detects whether the image is a still image or a moving image.
- the selection order is calculated by the scanning order calculation unit 23 in a long cycle (less frequently).
- the configuration of this modification example updates the calculation contents even if the frequency is low. Even when the voltage gradually changes, the total amount of potential fluctuation of the video signal line can be reduced, and the power consumption can be further reduced.
- FIG. 13 is a block diagram showing a configuration of a display control circuit according to the third embodiment of the present invention.
- the display control circuit 230 shown in FIG. 13 is provided with an output line memory 32 in place of the output frame memory 22, as can be seen from comparison with the display control circuit 200 shown in FIG. Since the same operation is performed with the same configuration except that an intra-block scanning order calculation unit 33 is provided instead of 23 and an intra-block scanning order setting unit 34 is provided instead of the scanning order setting unit 24, the same configuration is performed. Elements are denoted by the same reference numerals and description thereof is omitted.
- the display control circuit 230 in this embodiment can avoid the problems that may occur in the case of the first embodiment. Hereinafter, this problem will be described with reference to FIGS.
- FIG. 14 is a diagram illustrating the selection order of the scanning signal lines for two consecutive frames of the simple display device according to the first embodiment
- FIG. 15 is a diagram illustrating the selection order in the selection order shown in FIG. It is a wave form diagram which shows the electric potential change of a scanning signal line.
- the F-th frame is an arbitrary integer
- the scanning signal line GL (4) selected last in the “F-frame” is the (F + 1) -th frame
- the scanning signal line selected first in the following hereinafter referred to as “(F + 1) frame”.
- the display period of the pixel selected by the scanning signal line GL (4) in the F frame is until the scanning signal line GL (4) is selected in the next (F + 1) frame.
- This period Td is substantially equal to the length of the vertical blanking period, and is a period that is very short compared to one frame period, which is the average value of the pixel display periods.
- the screen may be collapsed, which may cause a serious problem in display quality.
- the configuration of this embodiment can avoid this problem by performing the selection order of the scanning signal lines for each preset block.
- the selection method for each block will be described with reference to FIGS. 16 and 17.
- FIG. 16 is a diagram showing an example in which the display screen is divided into six blocks
- FIG. 17 is a diagram partially showing the potential change of each scanning signal line in the six blocks.
- the display screen represented by the display unit 500 is divided into six blocks from the first block to the sixth block.
- the first block starts from the first row (N / 6) Scanning signal lines corresponding to the first row are grouped.
- the scanning signal lines GL (1) to GL (N / 6) grouped in the first block are selected in the same order as in the first embodiment.
- the same processing is repeated until the sixth block is selected. If the scanning signal line is selected in this way, for example, the scanning signal line that is selected last in the first block of the F frame is almost the same even if the scanning signal line is selected first in the first block of the (F + 1) frame. Since the length of one frame period (more precisely, about 5/6 frame period) is at least open, the problem that the display period becomes very short as described above does not occur. Accordingly, it is possible to prevent display quality from being deteriorated. Next, operations of the intra-block scanning order calculation unit 33 and the intra-block scanning order setting unit 34 will be described with reference to FIGS. 18 and 19 using a simple specific example.
- FIG. 18 is a diagram showing the selection order of the six scanning signal lines and the voltage values applied to the video signal lines.
- FIG. 18 here, as a simple example, in a display device having six scanning signal lines GL (1) to GL (6) and one video signal line SL (1), scanning is performed.
- the selection order is determined for each block.
- This block is defined by grouping a plurality (three in this case) of adjacent scanning signal lines. That is, the first block includes three scanning signal lines GL (1) to GL (3), and the second block includes three scanning signal lines GL (4) to GL (6). include.
- the first and second blocks are given a temporary selection order within the blocks independently of each other, and the blocks closest to the first row are selected first among the blocks.
- the provisional selection order in the first block is the order of the scanning signal line GL (1), the scanning signal line GL (3), and the scanning signal line GL (2)
- the provisional selection order in the second block is The scanning signal line GL (6), the scanning signal line GL (5), and the scanning signal line GL (4) are arranged in this order. Therefore, the final selection order is as shown in FIG. Although a simple apparatus example has been described here, in actuality, several to several hundred blocks are provided. Furthermore, a specific operation will be described with reference to FIG.
- FIG. 19 is a waveform diagram of each signal in the display device as such a simple example.
- the scanning signal line GL (1) becomes active from time t1 to t2.
- the scanning signal line GL (3) becomes active, from time t3 to t4, the scanning signal line GL (2) becomes active, and from time t4 to t5, the scanning signal line GL (6) becomes active.
- the scanning signal line GL (5) becomes active from t5 to t6, and the scanning signal line GL (4) becomes active from time t6 to t7.
- the corresponding driving video signal voltages V11 to V61 are applied to the video signal line SL (1).
- the potential change of the video signal line SL (1) is gentle and the total amount of potential change is the smallest.
- the voltage V11 greatly changes from the voltage V11 to the voltage V21 at the time t2, and the voltage V31 to the voltage at the time t4.
- the total amount of potential change of the video signal line SL becomes much larger than in the case shown in FIG.
- the scanning signal lines are selected in the order in which the total amount of potential fluctuation of the video signal lines is made smaller than in the case where the scanning signal lines are selected in the arrangement order of the scanning signal lines, the video signal lines are driven. Therefore, power consumption can be reduced.
- the plurality of blocks are sequentially selected from the block closest to the first row, one of the scanning signal lines included in the same block in the next frame is selected after one of the scanning signal lines included in the block is selected.
- the time until one is selected is almost constant, and if it is a sufficiently small block, a time of about one frame is left. Therefore, since the pixel gray scale retention time in each row is substantially equal to the time for one frame, there is no significant problem in display quality. Note that even when the number of blocks is large, for example, when the number of blocks is two, a holding time for at least 1 ⁇ 2 frame is secured, so that no major problem is caused in display quality.
- the pixel gray scale retention time in that row is approximately 2.
- the pixel gray scale retention time in that row is approximately equal to the vertical blanking period. It will be only time.
- the screen may be collapsed, which may cause a serious problem in display quality.
- the configuration of the present embodiment can avoid this problem.
- the same selection order as in the first embodiment is calculated in units of blocks. However, if calculation is performed in a certain block, the calculation proceeds to the next block. Therefore, it is not necessary to hold data for one frame, and it is sufficient to hold data for one block (or two blocks including the output buffer). Therefore, a line memory capable of holding these data can be used. Since this line memory has a small circuit scale and is inexpensive, by using the output line memory 32, the manufacturing cost of the device can be reduced and the circuit scale of the display control circuit 230 can be reduced.
- the scanning signal lines are grouped into a plurality of blocks, and the selection order in the group is calculated so that the total amount of potential fluctuation of the video signal lines is minimized.
- the power consumption can be reduced, and by fixing the selection order between the groups, a holding time of at least 1/2 frame or more can be secured. Good quality can be maintained.
- the active matrix type liquid crystal display device has been described as an example.
- the active matrix type display device is not limited to this example as long as it is an active matrix type display device, such as an organic EL (Electro-Luminescence) element.
- the present invention can be similarly applied to display devices using LEDs (Light Emitting Diodes) and other flat panel display devices.
- FIG. 20 is a circuit diagram showing an equivalent circuit of a pixel formation unit using an organic EL element.
- the pixel forming section includes an organic EL element 14 that is an electro-optical element, a power supply line electrode 17 that supplies a current from a drive power supply Vref (current supply section not shown), and a scanning signal line.
- This pixel formation portion is driven by a so-called constant voltage type control method (voltage program method). That is, the video signal voltage is applied to the video signal line electrode 16 during the period when the data voltage control TFT 11 is selected by the scanning signal applied to the scanning signal line electrode 15, so The stored voltage is held in the auxiliary capacitor 13.
- the conductivity of the current control TFT 12 is controlled in accordance with the voltage held in the auxiliary capacitor 13.
- the configuration of each of the above embodiments can be similarly applied to an organic EL display device including such a pixel circuit.
- the present invention is applied to a display device such as an active matrix liquid crystal display device, and is particularly suitable for a display device that requires low power consumption.
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Abstract
Description
前記画像を表す画像信号に基づき、前記複数の映像信号線を駆動するための映像信号線駆動回路と、
前記複数の走査信号線を選択的に駆動するための走査信号線駆動回路と、
前記複数の走査信号線が配置順で選択される場合に前記複数の映像信号線の駆動に要する電力よりも小さい電力で前記複数の映像信号線が駆動されるように、前記複数の走査信号線における選択の順番を前記画像信号に基づき決定する走査順序決定回路と
を備えることを特徴とする。
前記走査順序決定回路は、前記走査信号線駆動回路によって選択される走査信号線が切り替わる毎に生じる前記複数の映像信号線の少なくとも一部のそれぞれにおける電位変動量の絶対値を積算した値が最も小さくなるよう、前記順番の少なくとも一部を決定することを特徴とする。
前記走査順序決定回路は、次に選択されると前記電位変動量の絶対値を積算した値が最も小さくなる走査信号線を決定し、当該走査信号線が選択された後に続いて選択されると前記電位変動量の絶対値を積算した値が最も小さくなる走査信号線を決定することを特徴とする。
前記走査順序決定回路は、前記画像が表示される直前に表示された画像を表示するために最後に選択されるべき走査信号線が選択された後、前記画像を表示するために次に選択されると前記電位変動量の絶対値を積算した値が最も小さくなる走査信号線を、前記複数の走査信号線のうちの最初に選択されるべき走査信号線とすることを特徴とする。
前記走査順序決定回路は、予め定められた電位と前記複数の映像信号線における電位との差の絶対値の積算値が最も小さくなる走査信号線を、前記複数の走査信号線のうちの最初に選択されるべき走査信号線とすることを特徴とする。
前記走査順序決定回路は、前記画像の一行目を表示するために選択される走査信号線を前記複数の走査信号線のうちの最初に選択されるべき走査信号線とすることを特徴とする。
前記走査順序決定回路は、前記画像信号に含まれる階調データであって前記複数の映像信号線に与えられるべき電位を示すデジタル階調データのうち、所定数の上位ビットに基づき、前記積算値を算出することを特徴とする。
前記走査順序決定回路は、前記順番を決定した後、所定の待機時間が経過するかまたは所定の開始時点まで決定された順番を固定することを特徴とする。
前記走査順序決定回路は、前記画像の変化が検出される時点を前記開始時点とし、または前記画像が静止画像であると判定される場合に前記画像が動画像であると判定される場合よりも長い時間を前記待機時間として定めることを特徴とする。
前記走査順序決定回路は、前記複数の映像信号線を、隣接する所定数の走査信号線毎にグループ化し、当該グループ毎に前記順番を決定することを特徴とする。
前記グループの1つに含まれる複数の映像信号線に与えられるべき電位を示すデジタル階調データを記憶する大きさを有するメモリをさらに備えることを特徴とする。
前記走査順序決定回路は、前記複数の映像信号線のうち2以上の所定の整数倍毎の映像信号線のそれぞれにおける電位変動量の絶対値を積算することを特徴とする。
前記走査信号線駆動回路は、アドレスデコーダであり、
前記走査順序決定回路は、前記走査信号線駆動回路に対して、前記順序に応じたアドレスを与えることを特徴とする。
前記走査信号線駆動回路は、前記複数の走査信号線の少なくとも一方の端に信号を与えるよう、前記複数の走査信号線の両端側の位置にそれぞれ配置されることを特徴とする。
前記画像を表す画像信号に基づき、前記複数の映像信号線を駆動するための映像信号線駆動ステップと、
前記複数の走査信号線を選択的に駆動するための走査信号線駆動ステップと、
前記複数の走査信号線が配置順で選択される場合に前記複数の映像信号線の駆動に要する電力よりも小さい電力で前記複数の映像信号線が駆動されるように、前記複数の走査信号線における選択の順番を前記画像信号に基づき決定する走査順序決定ステップと
を備えることを特徴とする。
<1.1 液晶表示装置の全体構成および動作>
図1は、本発明の第1の実施形態に係るアクティブマトリクス型液晶表示装置の全体構成を示すブロック図である。この液晶表示装置は、表示制御回路200、映像信号線駆動回路(ソースドライバ)300、および走査信号線駆動回路(ゲートドライバ)400からなる駆動制御部と、表示部500とを備えている。表示部500は、複数本(M本)の映像信号線SL(1)~SL(M)と、複数本(N本)の走査信号線GL(1)~GL(N)と、それら複数本の映像信号線SL(1)~SL(M)と複数本の走査信号線GL(1)~GL(N)とに沿って設けられた複数個(M×N個)の画素形成部を含んでいる。なお以下では、走査信号線GL(n)と映像信号線SL(m)との交差点に関連づけて当該交差点近傍(図では当該交差点の右下近傍)に設けられた画素形成部を参照符号“P(m,n)”で示すものとする。図2は、本実施形態の表示部500における画素形成部P(m,n)の等価回路を示している。
図3は、本実施形態における表示制御回路200の構成を示すブロック図である。この表示制御回路200は、入力用フレームメモリ21と、出力用フレームメモリ22と、走査順序算出部23と、走査順序設定部24と、タイミング制御部25と、アドレス出力部26とを備えている。
以上のように本実施形態によれば、最初に設定された基準行からの電位変動量の総量が最も小さい行を次行として選択し、選択された当該次行を次の基準行として、次の次行を決定するために同様の処理を行う、という処理を繰り返すことにより、全て(すなわち1フレーム分)の行についての選択の順序を決定し、当該順序で走査信号線を選択する。この構成によって、走査信号線の配列順で走査信号線を選択する場合よりも、映像信号線の電位変動量の総量をより小さくする順序で走査信号線を選択すれば、映像信号線を駆動するための消費電力を低減することができる。
<1.4.1 第1の変形例>
次に本実施形態の第1の変形例について、図8および図9を参照して説明する。図8は、入力用フレームメモリおよび走査順序算出部に入力される表示データ信号を示す部分的なブロック図である。入力用フレームメモリ21は、前述したように外部から表示データ信号DATを受け取る。この表示データ信号DATは、1画素(RGBの各画素)につき6ビットの階調データを含み、マスクされるビットはない。図中では、このデータ内容を示す[5:0]という記号が表示データ信号DATに付されている。また、入力用フレームメモリ21から走査順序算出部23に与えられる表示データ信号DATmは、表示データ信号DATと同一の信号であるが、6ビットの階調データのうち下位の3ビットがマスクされている。図中では、このデータ内容を示す[5:3]という記号が表示データ信号DATmに付されている。以下では、この表示データ信号DATmのうち、マスクされていない上位の3ビットのデータを判定データと呼ぶ。
また、演算量を低減するために、映像信号線SL(1)~SL(M)全ての電位変動量の積算値を計算するのではなく、これらのうちのいくつかを間引いて(演算を行わずに)積算値の計算を行ってもよい。例えば、上式(1)に代えて次式(2)に示す電位の変動総量を、行毎に算出してもよい。
<2.1 液晶表示装置の全体構成および動作>
本実施形態に係るアクティブマトリクス型液晶表示装置は、図1に示される第1の実施形態の表示装置と表示制御回路の一部の構成を除き、同一の構成で同一の動作を行うので、同一の構成要素には同一の符号を付してその説明を省略する。
図10に示す表示切り替わり検出部28は、外部から与えられる表示データ信号DATを受け取り、表される画像の変化を検出する。例えば、壁紙など同一の静止画が連続して表示されている場合、走査順序算出部23において算出される映像信号線の電位変動量の総量をより小さくする順序は、変化しないはずである。したがって、繰り返し同一の演算を行うことは消費電力を低減する観点からも好ましくない。そこで、表示切り替わり検出部28は、フレーム毎の画像の内容(例えば画素階調値の積算値など)を監視し、その変化が検出される場合に、更新制御信号Crを走査順序算出部23に与える。
以上のように本実施形態によれば、表示切り替わり検出部28によって、画像の変化が検出される場合にのみ、走査順序算出部23による選択順序の算出が行われる。この構成によって、走査順序算出部23における演算回数を低減させることができ、演算による消費電力を低減することができる。
図11は、本発明の第2の実施形態の変形例における表示制御回路の構成を示すブロック図である。この図11に示される表示制御回路220は、図10に示される表示制御回路210と比較すればわかるように、表示切り替わり検出部28に代えて変更頻度設定部29が設けられるほかは、同一の構成で同一の動作を行うので、同一の構成要素には同一の符号を付してその説明を省略し、この変更頻度設定部29の動作について説明する。
<3.1 液晶表示装置の全体構成および動作>
本実施形態に係るアクティブマトリクス型液晶表示装置は、図1に示される第1の実施形態の表示装置と表示制御回路の一部の構成を除き、同一の構成で同一の動作を行うので、同一の構成要素には同一の符号を付してその説明を省略する。
以上のように本実施形態によれば、走査信号線を複数のブロックにグループ化し、グループ内での選択順を、映像信号線の電位変動の総量が最も小さくなるように算出するので、第1の実施形態の場合と同様に消費電力を低減することができ、かつグループ間での選択順序を固定化することにより、少なくとも1/2フレーム分以上の保持時間を確保することができるため、表示品位を良好に保つことができる。
なお上記各実施形態における表示制御回路の全部または一部の機能は、ホストコントローラに含まれてもよいし、これらとは異なる別個の駆動制御回路に含まれてもよい。またこれらの機能は、対応するプログラムを実行するマイクロコンピュータにより実現されてもよい。
21 …入力用フレームメモリ
22 …出力用フレームメモリ
23 …走査順序算出部
24 …走査順序設定部
25 …タイミング制御部
26 …アドレス出力部
32 …出力用ラインメモリ
33 …ブロック内走査順序算出部
34 …ブロック内走査順序設定部
200~230…表示制御回路
300 …映像信号線駆動回路
400 …走査信号線駆動回路
500 …表示部
DAT …表示データ信号(画像信号)
DV …デジタル画像信号
Epix …画素電極
GL(n) …走査信号線(n=1~N)
SL(m) …データ号線(m=1~M)
P(m,n) …画素形成部(n=1~N、m=1~M)
Claims (15)
- 複数の映像信号を伝達するための複数の映像信号線と、前記複数の映像信号線と交差する複数の走査信号線とに沿って配置される複数の画素形成部により画像を表示する表示装置であって、
前記画像を表す画像信号に基づき、前記複数の映像信号線を駆動するための映像信号線駆動回路と、
前記複数の走査信号線を選択的に駆動するための走査信号線駆動回路と、
前記複数の走査信号線が配置順で選択される場合に前記複数の映像信号線の駆動に要する電力よりも小さい電力で前記複数の映像信号線が駆動されるように、前記複数の走査信号線における選択の順番を前記画像信号に基づき決定する走査順序決定回路と
を備えることを特徴とする、表示装置。 - 前記走査順序決定回路は、前記走査信号線駆動回路によって選択される走査信号線が切り替わる毎に生じる前記複数の映像信号線の少なくとも一部のそれぞれにおける電位変動量の絶対値を積算した値が最も小さくなるよう、前記順番の少なくとも一部を決定することを特徴とする、請求項1に記載の表示装置。
- 前記走査順序決定回路は、次に選択されると前記電位変動量の絶対値を積算した値が最も小さくなる走査信号線を決定し、当該走査信号線が選択された後に続いて選択されると前記電位変動量の絶対値を積算した値が最も小さくなる走査信号線を決定することを特徴とする、請求項2に記載の表示装置。
- 前記走査順序決定回路は、前記画像が表示される直前に表示された画像を表示するために最後に選択されるべき走査信号線が選択された後、前記画像を表示するために次に選択されると前記電位変動量の絶対値を積算した値が最も小さくなる走査信号線を、前記複数の走査信号線のうちの最初に選択されるべき走査信号線とすることを特徴とする、請求項3に記載の表示装置。
- 前記走査順序決定回路は、予め定められた電位と前記複数の映像信号線における電位との差の絶対値の積算値が最も小さくなる走査信号線を、前記複数の走査信号線のうちの最初に選択されるべき走査信号線とすることを特徴とする、請求項3に記載の表示装置。
- 前記走査順序決定回路は、前記画像の一行目を表示するために選択される走査信号線を前記複数の走査信号線のうちの最初に選択されるべき走査信号線とすることを特徴とする、請求項3に記載の表示装置。
- 前記走査順序決定回路は、前記画像信号に含まれる階調データであって前記複数の映像信号線に与えられるべき電位を示すデジタル階調データのうち、所定数の上位ビットに基づき、前記積算値を算出することを特徴とする、請求項2に記載の表示装置。
- 前記走査順序決定回路は、前記順番を決定した後、所定の待機時間が経過するかまたは所定の開始時点まで決定された順番を固定することを特徴とする、請求項1に記載の表示装置。
- 前記走査順序決定回路は、前記画像の変化が検出される時点を前記開始時点とし、または前記画像が静止画像であると判定される場合に前記画像が動画像であると判定される場合よりも長い時間を前記待機時間として定めること を特徴とする、請求項8に記載の表示装置。
- 前記走査順序決定回路は、前記複数の映像信号線を、隣接する所定数の走査信号線毎にグループ化し、当該グループ毎に前記順番を決定することを特徴とする、請求項1に記載の表示装置。
- 前記グループの1つに含まれる複数の映像信号線に与えられるべき電位を示すデジタル階調データを記憶する大きさを有するメモリをさらに備えることを特徴とする、請求項10に記載の表示装置。
- 前記走査順序決定回路は、前記複数の映像信号線のうち2以上の所定の整数倍毎の映像信号線のそれぞれにおける電位変動量の絶対値を積算することを特徴とする、請求項2に記載の表示装置。
- 前記走査信号線駆動回路は、アドレスデコーダであり、
前記走査順序決定回路は、前記走査信号線駆動回路に対して、前記順序に応じたアドレスを与えることを特徴とする、請求項1に記載の表示装置。 - 前記走査信号線駆動回路は、前記複数の走査信号線の少なくとも一方の端に信号を与えるよう、前記複数の走査信号線の両端側の位置にそれぞれ配置されることを特徴とする、請求項1に記載の表示装置。
- 複数の映像信号を伝達するための複数の映像信号線と、前記複数の映像信号線と交差する複数の走査信号線とに沿って配置される複数の画素形成部に画像を表示する方法であって、
前記画像を表す画像信号に基づき、前記複数の映像信号線を駆動するための映像信号線駆動ステップと、
前記複数の走査信号線を選択的に駆動するための走査信号線駆動ステップと、
前記複数の走査信号線が配置順で選択される場合に前記複数の映像信号線の駆動に要する電力よりも小さい電力で前記複数の映像信号線が駆動されるように、前記複数の走査信号線における選択の順番を前記画像信号に基づき決定する走査順序決定ステップと
を備えることを特徴とする、表示方法。
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US14/375,832 US20140375622A1 (en) | 2012-02-10 | 2012-07-09 | Display device and display method |
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JP2016031431A (ja) * | 2014-07-28 | 2016-03-07 | 株式会社Joled | 画像表示装置および画像表示装置の駆動方法。 |
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KR102426668B1 (ko) * | 2015-08-26 | 2022-07-28 | 삼성전자주식회사 | 디스플레이 구동 회로 및 디스플레이 장치 |
US10896650B2 (en) * | 2016-06-01 | 2021-01-19 | Sharp Kabushiki Kaisha | Video signal line drive circuit, display device including same, and drive method for video signal line |
US10572080B2 (en) | 2016-06-13 | 2020-02-25 | Samsung Display Co., Ltd. | Optical touch film, display device including the same, and manufacturing method thereof |
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KR20210043047A (ko) | 2019-10-10 | 2021-04-21 | 삼성디스플레이 주식회사 | 표시장치 |
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