WO2013099697A1 - Active matrix substrate - Google Patents

Active matrix substrate Download PDF

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Publication number
WO2013099697A1
WO2013099697A1 PCT/JP2012/082784 JP2012082784W WO2013099697A1 WO 2013099697 A1 WO2013099697 A1 WO 2013099697A1 JP 2012082784 W JP2012082784 W JP 2012082784W WO 2013099697 A1 WO2013099697 A1 WO 2013099697A1
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Prior art keywords
layer
transparent conductive
insulating layer
active matrix
inorganic insulating
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PCT/JP2012/082784
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French (fr)
Japanese (ja)
Inventor
美崎　克紀
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シャープ株式会社
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Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to US14/368,557 priority Critical patent/US9035302B2/en
Priority to CN201280063901.4A priority patent/CN104011587B/en
Publication of WO2013099697A1 publication Critical patent/WO2013099697A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
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    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to an active matrix substrate, and more particularly to an active matrix substrate suitably used for a liquid crystal display device.
  • An active matrix liquid crystal display device generally includes an active matrix substrate (sometimes referred to as a “TFT substrate”) in which a thin film transistor (TFT) is formed as a switching element for each pixel, and a counter substrate on which a color filter or the like is formed. (Sometimes referred to as a “color filter substrate”) and a liquid crystal layer provided between the active matrix substrate and the counter substrate.
  • TFT substrate active matrix substrate
  • color filter substrate a liquid crystal layer provided between the active matrix substrate and the counter substrate.
  • the active matrix type liquid crystal display device various display modes are proposed and adopted depending on the application.
  • the display mode include a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In-Plane-Switching) mode, and an FFS (Fringe Field Switching) mode.
  • TN Transmission Nematic
  • VA Very Alignment
  • IPS In-Plane-Switching
  • FFS Frringe Field Switching
  • an active matrix substrate has two transparent conductive layers formed with an inorganic insulating layer interposed therebetween.
  • the structure of an electrode formed by two transparent conductive layers sandwiching an inorganic insulating layer is referred to as a “two-layer electrode structure”.
  • a lower transparent conductive layer is provided as a common electrode, and an upper transparent conductive layer is provided as a pixel electrode in which a plurality of slits are formed.
  • an upper transparent conductive layer is provided as a pixel electrode in which a plurality of slits are formed.
  • Patent Document 2 in the FFS mode, a configuration in which a pixel electrode is provided as a lower layer electrode and a common electrode in which a plurality of slits are formed is provided as an upper layer electrode is also known.
  • the applicant is researching and developing a liquid crystal display device having an auxiliary capacity using a two-layer electrode structure. Specifically, a configuration in which the lower transparent conductive layer is an auxiliary capacitor counter electrode (a common voltage or an auxiliary capacitor counter voltage is supplied) and the upper transparent conductive layer is a pixel electrode is being studied.
  • This liquid crystal display device is, for example, the VA mode, but can be applied to other display modes.
  • the present invention has been found that the active matrix substrate having the above two-layer electrode structure has the following problems, although details will be described later with reference to a comparative example.
  • a transparent conductive layer (generally formed from a transparent inorganic oxide represented by ITO (indium tin oxide) or IZO (indium zinc oxide))
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • An object of the present invention is to provide an active matrix substrate that solves at least a part of the above problems.
  • An active matrix substrate includes a substrate, a thin film transistor supported by the substrate and having a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, at least one of which is electrically connected to the drain electrode of the thin film transistor
  • the body includes a first inorganic insulating layer having a tensile stress, and second and third inorganic insulating layers having a compressive stress formed so as to sandwich the first inorganic insulating layer, and the stacked body includes As a whole, it has tensile stress.
  • the first inorganic insulating layer having a tensile stress does not directly contact any of the first transparent conductive layer and the second transparent conductive layer.
  • the first inorganic insulating layer is a silicon nitride layer having a refractive index of 1.804 or less.
  • the second inorganic insulating layer and the third inorganic insulating layer are silicon nitride layers having a refractive index of 1.805 or more.
  • the first transparent conductive layer is formed closer to the substrate than the second transparent conductive layer
  • the second inorganic insulating layer is closer to the substrate than the third inorganic insulating layer.
  • the laminated body further includes a fourth inorganic insulating layer between the first transparent conductive layer and the second inorganic insulating layer.
  • the fourth inorganic insulating layer is a silicon oxide layer having a refractive index of 1.4 to 1.6.
  • the laminate further includes a fifth inorganic insulating layer between the second transparent conductive layer and the third inorganic insulating layer.
  • the fifth inorganic insulating layer is a silicon oxide layer having a refractive index of 1.4 to 1.6.
  • the first transparent conductive layer and the second transparent conductive layer are ITO layers or IZO layers.
  • the semiconductor layer is an oxide semiconductor layer.
  • the oxide semiconductor layer includes, for example, an In—Ga—Zn—O-based semiconductor (IGZO-based semiconductor).
  • the first transparent conductive layer is in an electrically floating state
  • the second transparent conductive layer is a pixel electrode
  • the first transparent conductive layer is a storage capacitor counter electrode
  • the second transparent conductive layer is a pixel electrode.
  • the active matrix substrate of this embodiment is used in, for example, a vertical alignment (VA) mode liquid crystal display device.
  • VA vertical alignment
  • the first transparent conductive layer is a common electrode
  • the second transparent conductive layer is a pixel electrode having a plurality of slits.
  • the active matrix substrate of this embodiment is used for an FFS mode liquid crystal display device, for example.
  • the active matrix substrate further includes an organic insulating layer covering the thin film transistor, and a part of the organic insulating layer is in direct contact with a part of the stacked body.
  • peeling is suppressed by the laminate of inorganic insulating layers formed between two transparent conductive layers having tensile stress.
  • the first inorganic insulating layer having a tensile stress contained in the laminate does not directly contact either the first transparent conductive layer or the second transparent conductive layer. Even if the first inorganic insulating layer is formed of a silicon nitride layer, the transparent oxide (ITO, IZO) constituting the first transparent conductive layer and the second transparent conductive layer is not reduced, and light is transmitted. The rate will not drop.
  • FIG. 3 is a schematic plan view of an active matrix substrate 100A according to an embodiment of the present invention.
  • 2A and 2B are schematic cross-sectional views of an active matrix substrate 100A, in which FIG. 1A shows a cross section along the line AA ′ in FIG. 1, and FIG. 2B shows a cross section along the line BB ′ in FIG. A cross section is shown.
  • substrates 100B by embodiment of this invention, (a) and (b) has shown the cross section corresponding to Fig.2 (a) and (b), respectively.
  • (A)-(d) is typical sectional drawing for demonstrating the manufacturing method of the active matrix substrate 100B.
  • FIG. 1A shows a cross section along the line AA ′ in FIG. 1
  • FIG. 2B shows a cross section along the line BB ′ in FIG.
  • a cross section is shown.
  • FIG. 10 is a schematic plan view of still another active matrix substrate 100C according to an embodiment of the present invention.
  • 6A and 6B are schematic cross-sectional views of an active matrix substrate 100C, in which FIG. 5A shows a cross section along the line AA ′ in FIG. 5, and FIG. A cross section is shown.
  • (A)-(d) is typical sectional drawing for demonstrating the manufacturing method of 100 C of active matrix substrates. It is a typical sectional view of active matrix substrate 200A of a comparative example.
  • (A) And (b) is a schematic diagram for demonstrating the evaluation method of the internal stress of a film
  • an active matrix substrate used for a VA mode liquid crystal display device having a two-layer electrode structure will be exemplified.
  • the embodiment of the present invention is not limited to this, and can be applied to other display devices besides the active matrix substrate used in the above-described FFS mode liquid crystal display device.
  • FIG. 1 is a schematic plan view of an active matrix substrate 100A according to an embodiment of the present invention.
  • 2 is a schematic cross-sectional view of the active matrix substrate 100A.
  • FIG. 2 (a) shows a cross-section along the line AA ′ in FIG. 1
  • FIG. 2 (b) shows the cross-section in FIG. A cross section along the line BB ′ is shown.
  • the active matrix substrate 100A includes a substrate (for example, a glass substrate) 11, a thin film transistor (hereinafter referred to as TFT) 10A supported by the substrate 11, and having a semiconductor layer 14, a gate electrode 12g, a source electrode 16S, and a drain electrode 16D, and at least.
  • TFT thin film transistor
  • the laminated body 23S1 of the inorganic insulating layer is formed.
  • the first transparent conductive layer 22 is formed closer to the substrate 11 than the second transparent conductive layer 24, and the second transparent conductive layer 24 is electrically connected to the drain electrode 16D of the TFT 10A. Yes.
  • the first transparent conductive layer 22 and the second transparent conductive layer 24 are an ITO layer or an IZO layer.
  • Both the ITO layer and the IZO layer are known to have tensile stress.
  • the ITO layer has a larger tensile stress than the IZO layer and is easily peeled off.
  • the reason why the ITO layer and the IZO layer have a tensile stress is not necessarily clear, but generally has a tensile stress regardless of the film formation temperature and conditions.
  • the internal stress (tensile stress or compressive stress) of each layer will be described later with reference to FIG.
  • the laminated body 23S1 includes a first inorganic insulating layer 23a1 having tensile stress, and a second inorganic insulating layer 23b1 and a third inorganic insulating layer 23c1 which are formed so as to sandwich the first inorganic insulating layer 23a1 and have compressive stress. is doing.
  • the second inorganic insulating layer 23b1 is formed on the substrate 11 side of the first inorganic insulating layer 23a1
  • the third inorganic insulating layer 23c1 is formed on the side opposite to the substrate 11 of the first inorganic insulating layer 23a1.
  • the laminated body 23S1 has a tensile stress as a whole. Further, in the active matrix substrate 100A, the first inorganic insulating layer 23a1 having a tensile stress is not in direct contact with either the first transparent conductive layer 22 or the second transparent conductive layer 24.
  • the first inorganic insulating layer 23a1 is, for example, a silicon nitride layer having a refractive index of 1.804 or less.
  • the second inorganic insulating layer 23b1 and the third inorganic insulating layer 23c1 are, for example, silicon nitride layers having a refractive index of 1.805 or more.
  • a silicon nitride layer or a silicon oxide layer has a compressive stress.
  • a silicon nitride layer having a refractive index of 1.804 or less exceptionally has a tensile stress. Accordingly, when a silicon nitride layer having a refractive index of 1.804 or less is used as the third interlayer insulating layer 23P as in the active matrix substrate 200A of the comparative example shown in FIG. 8, peeling of the third interlayer insulating layer 23P is suppressed. Can do.
  • a silicon nitride layer having a refractive index of 1.804 or less has a strong reducing power.
  • the vicinity of the interface between the silicon nitride layer and the ITO layers 22 and 24 is obtained.
  • the ITO is reduced and metallized. If it does so, the light transmittance of ITO layers 22 and 24 will fall.
  • IZO layers are used as the first transparent conductive layer 22 and the second transparent conductive layer 24.
  • the silicon nitride layer 23a1 (having a tensile stress) having a refractive index of 1.804 or less
  • the silicon nitride layer 23b1 and the silicon nitride layer 23c1 (having a compressive stress) having a refractive index of 1.805 or more.
  • the stacked body 23S1 having a structure sandwiched between the first transparent conductive layer (ITO layer or IZO layer) 22 and the first transparent conductive layer (ITO layer or IZO layer) 22 having a refractive index of 1.804 or less having tensile stress.
  • the direct contact with any of the two transparent conductive layers (ITO layer or IZO layer) 24 is prevented.
  • the laminated body 23S1 is configured to have a tensile stress as a whole.
  • the thicknesses of the silicon nitride layers 23b1 and 23c1 having a refractive index of 1.805 or more are thb1 and thc1, respectively, and the thickness of the silicon nitride layer 23a1 having a refractive index of 1.804 or less is tha1, tha1 ⁇ thb1 + thc1. It is preferable to satisfy the relationship. At this time, it is preferable that thb1 and thc1 are independently 100 nm or less.
  • the magnitude of the stress of each layer is affected not only by the thickness of each layer but also by the structure (composition, etc.) of each film. May have tensile stress.
  • the laminated body 23S1 as a whole has a tensile stress if the above relationship is satisfied. Note that if thb1 and thc1 exceed 100 nm, there is a problem that the production efficiency is lowered. Therefore, it is preferable that thb1 and thc1 are independently 100 nm or less.
  • the active matrix substrate 100A further includes an organic insulating layer 19 that covers the TFT 10A, and a part of the organic insulating layer 19 is in direct contact with a part of the stacked body 23S1.
  • the organic insulating layer 19 is made of, for example, a transparent positive photosensitive resin.
  • the organic insulating layer 19 formed on a substrate formed of an inorganic material such as a glass substrate generally has a tensile stress. Therefore, the inorganic insulating layer having compressive stress has low adhesion to the organic insulating layer 19.
  • the adhesiveness is excellent. Therefore, since the laminate 23S1 is excellent in adhesiveness with the first transparent conductive layer 22 and the organic insulating layer 19 with which the lower surface is in contact, peeling is suppressed.
  • a part 22a of the first transparent conductive layer 22 is not connected anywhere, is in an electrically floating state, functions as a shield electrode 22a, and is a second transparent conductive layer.
  • a part 24p of the layer 24 functions as a pixel electrode. That is, the first transparent conductive layer 22 protects the potential of the pixel electrode 24p from being affected by an electric field generated by various electrodes and wirings formed on the substrate 11.
  • a part 22a of the first transparent conductive layer 22 may be used as the auxiliary capacitance counter electrode 22a.
  • the auxiliary capacitor counter electrode 22a, the pixel electrode 24p, and the stacked body 23S1 therebetween function as an auxiliary capacitor. Since the auxiliary capacitance is formed of the first transparent conductive layer 22 and the second transparent conductive layer 24, it can have a large capacitance value without reducing the pixel aperture ratio. Accordingly, it is possible to suppress an increase in feedthrough voltage due to an increase in parasitic capacitance by adopting a configuration having the source contact hole 15a and the drain contact hole 15b on the gate bus line 12 as in the TFT 10A. .
  • the semiconductor layer 14 is, for example, an oxide semiconductor layer. Since an oxide semiconductor has high mobility, an auxiliary capacitor having a relatively large capacitance value formed using a two-layer electrode structure can be charged sufficiently quickly.
  • the oxide semiconductor layer includes, for example, an In—Ga—Zn—O-based semiconductor (hereinafter abbreviated as “IGZO-based semiconductor”).
  • IGZO-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited.
  • In: Ga: Zn 2: 2: 1
  • the IGZO semiconductor may be amorphous or crystalline.
  • a crystalline IGZO-based semiconductor having a c-axis oriented substantially perpendicular to the layer surface is preferable.
  • Such a crystal structure of an IGZO-based semiconductor is disclosed in, for example, Japanese Patent Application Laid-Open No. 2012-134475.
  • the entire disclosure of Japanese Patent Application Laid-Open No. 2012-134475 is incorporated herein by reference.
  • FIG. 9A A film to be evaluated is deposited on the silicon wafer 1.
  • FIG. 9A when the silicon wafer 1 is warped upward, a compressive stress ac is generated in the film 2a. At this time, tensile stress is generated in the silicon wafer 1.
  • FIG. 9 (b) the silicon wafer 1 is warped in a convex down, the film 2b, the tensile stress a t occurs. At this time, compressive stress is generated in the silicon wafer 1.
  • the internal stress is determined from the elastic modulus and dimensions (thickness and size) of the silicon wafer 1 and the elastic modulus and dimensions (thickness and size) of the films 2a and 2b. This can be quantitatively determined.
  • a film stress meter manufactured by Tencor was used to determine whether the internal stress of each layer was a tensile stress or a compressive stress.
  • size of internal stress can be calculated
  • FIG. 3 is a schematic cross-sectional view of another active matrix substrate 100B according to an embodiment of the present invention.
  • FIGS. 3 (a) and 3 (b) show the active corresponding to FIGS. 2 (a) and 2 (b), respectively.
  • the cross section of the matrix substrate 100B is shown.
  • the planar structure of the active matrix substrate 100B is the same as that of the active matrix substrate 100A shown in FIG.
  • the structure of the stacked body 23S2 included in the active matrix substrate 100B is different from the structure of the stacked body 23S1 of the active matrix substrate 100A.
  • the laminate 23S2 includes a first inorganic insulating layer 23a2 having tensile stress, and a second inorganic insulating layer 23b2 and a third inorganic insulating layer 23c2 that are formed so as to sandwich the first inorganic insulating layer 23a2 and have compressive stress. is doing.
  • the laminated structure of this portion is the same as that of the laminated body 23S1.
  • the stacked body 23S2 further includes a fourth inorganic insulating layer 23d2 between the first transparent conductive layer 22 and the second inorganic insulating layer 23b2, that is, on the substrate 11 side of the second inorganic insulating layer 23b2, and A fifth inorganic insulating layer 23e2 is further provided between the second transparent conductive layer 24 and the third inorganic insulating layer 23c2, that is, on the side opposite to the substrate 11 of the third inorganic insulating layer 23c2.
  • the laminated body 23S2 also has a tensile stress as a whole, like the laminated body 23S1.
  • the first inorganic insulating layer 23a2 is, for example, a silicon nitride layer having a refractive index of 1.804 or less, and the second inorganic insulating layer 23b2 and the third inorganic insulating layer 23c2 have, for example, a refractive index of 1.805.
  • the fourth inorganic insulating layer 23d2 and the fifth inorganic insulating layer 23e2 are silicon oxide layers having a refractive index of 1.4 to 1.6.
  • a silicon oxide layer having a refractive index of 1.4 to 1.6 also has a compressive stress.
  • the thicknesses of the silicon nitride layers 23b2 and 23c2 having a refractive index of 1.805 or more are set to thb2 and thc2, respectively, and the thicknesses of the silicon oxide layers 23d2 and 23e2 having a refractive index of 1.4 to 1.6 are set to thd2.
  • the thickness of the silicon nitride layer 23a2 having a refractive index of 1.804 or less is tha2
  • it is preferable that the relationship of tha2 ⁇ thb2 + thc2 + thd2 + the2 is satisfied.
  • thb2, thc2, thd2, and the2 are independently 100 nm or less for the same reason as described above.
  • the magnitude of the stress of each layer is affected not only by the thickness of each layer but also by the structure (composition, etc.) of each film. May have tensile stress. According to the inventor's study, if the above relationship is satisfied, the laminate 23S2 has a tensile stress as a whole.
  • the active matrix substrate 100B further includes an organic insulating layer 19 that covers the TFT 10A, and a part of the organic insulating layer 19 is in direct contact with a part of the stacked body 23S2. Accordingly, the laminate 23S2 is excellent in adhesion to the first transparent conductive layer 22 and the organic insulating layer 19 with which the lower surface is in contact, similarly to the laminate 23S1 of the active matrix substrate 100A, and therefore, peeling is suppressed.
  • the active matrix substrate 100B having the multilayer body 23S2 has an advantage that the reduction reaction of the transparent conductive layer can be more effectively suppressed than the active matrix substrate 100A having the multilayer body 23S1.
  • 4A to 4D are schematic cross-sectional views for explaining a method of manufacturing the active matrix substrate 100B, in the vicinity of the TFT 10A in FIG. 3A and the gate terminal portion in FIG. The cross-sectional structure near 12t is also shown.
  • a substrate for example, a glass substrate
  • a gate metal film is formed on the substrate 11
  • a gate metal layer 12 is formed by patterning the gate metal film.
  • the gate metal layer 12 includes a gate electrode 12g, a gate wiring, an auxiliary capacitance bus line (CS bus line), and a gate terminal portion 12t.
  • a storage capacitor bus line (not shown) is connected to the storage capacitor counter electrode 22a and supplies a storage capacitor counter voltage.
  • the gate metal layer 12 can be formed by a known method using various known conductive films.
  • the gate metal layer 12 is formed of, for example, a MoNb film / Al film laminated film (Al film is a lower layer).
  • the thickness of the MoNb film / Al film is, for example, about 20 nm / about 50 nm to about 200 nm / about 300 nm.
  • the gate metal layer 12 may be formed of, for example, an Al film, a Cu film, a Ta film, or a TaN film.
  • a gate insulating layer 13 is formed so as to cover the gate metal layer 12.
  • the gate insulating layer 13 is formed from, for example, silicon nitride (SiN x ), silicon oxide (SiO 2 ), or a stacked film thereof having a thickness of about 100 nm to about 600 nm.
  • a semiconductor layer 14 is formed on the gate insulating layer 13.
  • the semiconductor layer 14 is, for example, an In—Ga—Zn—O based semiconductor (IGZO based semiconductor) layer having a thickness of about 20 nm to about 200 nm.
  • the semiconductor layer 14 may be an oxide semiconductor layer other than the IGZO-based semiconductor layer, or may be another known semiconductor layer such as a polycrystalline silicon layer.
  • an etch stop layer 15 is formed so as to cover the semiconductor layer 14.
  • the etch stop layer 15 has a source contact hole 15a and a drain contact hole 15b (see FIG. 1).
  • a through hole is formed in the gate insulating layer 13 by etching so that the gate terminal portion 12t is exposed.
  • the etch stop layer 15 protects the semiconductor layer 14 in an etching process for forming the source electrode 16S and the drain electrode 16D later.
  • the source metal layer 16 includes a source electrode 16S, a drain electrode 16D, a source bus line, and a source terminal portion 16t (see FIG. 1).
  • the source electrode 16S and the drain electrode 16D are each formed, for example, from a laminate of a MoN layer 16Sa / Al layer 16Sb / MoN layer 16Sc and a MoN layer 16Da / Al layer 16Db / MoN layer 16Dc.
  • the source metal layer 16 can be formed using another known conductive film. In this way, the TFT 10A having the etch stop layer 15 on the semiconductor layer 14 is obtained.
  • the first interlayer insulating layer 17 is typically an inorganic insulating layer, for example, silicon nitride (SiN x ) having a thickness of about 50 nm to about 500 nm, silicon oxide (SiO 2 ), or a laminate thereof. Formed from a film.
  • SiN x silicon nitride
  • SiO 2 silicon oxide
  • a second interlayer insulating layer 19 is formed on the first interlayer insulating layer 17.
  • the second interlayer insulating layer 19 is, for example, a transparent resin layer having a thickness of about 1000 nm to about 5000 nm.
  • the transparent resin layer 19 forms a flat surface on the substrate 11. Further, since the transparent resin layer 19 can easily form a thick film and has a low dielectric constant as compared with a general inorganic insulating layer, an electrode (for example, a pixel electrode) formed on the transparent resin layer 19. And the parasitic capacitance between the electrode and the wiring (for example, the gate bus line 12 and the source bus line 16) formed under the transparent resin layer 19 can be reduced.
  • a hole (for source) 17c is formed.
  • a contact hole for connecting the auxiliary capacitor counter electrode 22a to the auxiliary capacitor wiring is provided in the first interlayer insulating layer. 17, formed on the etch stop layer 15 and the gate insulating layer 13. In the step shown in FIG.
  • a through hole (a hole exposing the lower layer) is formed in the second interlayer insulating layer 19 at a position corresponding to the contact hole.
  • the second interlayer insulating layer 19 is formed of, for example, a positive photosensitive resin, and the through hole is formed by a photolithography process.
  • a contact hole for connecting the storage capacitor counter electrode 22a to the storage capacitor wiring is also formed as necessary.
  • the first transparent conductive layer 22 is formed on the second interlayer insulating layer 19.
  • an ITO film having a thickness of about 40 nm to about 150 nm is formed by a sputtering method (conditions: for example, Ar / O 2 : 300 sccm / 1 sccm, pressure: 0.6 Pa, DC power: 2.5 kW).
  • the first transparent conductive layer 22 including the shield electrode or auxiliary capacitance counter electrode 22a, the first contact electrode 22c, and the first transparent terminal electrode 22t is obtained.
  • a stacked body 23 ⁇ / b> S ⁇ b> 2 is formed on the first transparent conductive layer 22.
  • a silicon oxide layer 23d2 (conditions: for example, SiH 4 / N 2 O: 50 to 300/1000 to 7000 sccm, pressure: 100 to 300 Pa, RF power: 400 to 3000 W), Silicon nitride layer 23b2 (conditions: for example, SiH 4 / NH 3 / N 2 : 100 to 500/100 to 1000/1000 to 6000 sccm, pressure: 100 to 300 Pa, RF power: 400 to 4000 W), silicon nitride layer 23a2 (conditions : For example, SiH 4 / NH 3 / N 2 : 100 to 500/100 to 1000/1000 to 6000 sccm, pressure: 100 to 300 Pa, RF power: 400 to 4000 W, silicon nitride layer 23c2 (condition: SiH 4 / NH 3 / N 2: 100 ⁇ 500/ 100 ⁇ 1000/1000 ⁇ 6000sc m, the pressure: 100 ⁇ 300 Pa,
  • each film is formed on the silicon wafer 1 alone, and the result of internal stress measured using a film stress meter is also shown. Note that the magnitude of the internal stress of each layer does not depend on the film thickness.
  • the silicon oxide layers 23d2 and 23e2 have a refractive index of 1.46, a thickness of 20 nm, and a compressive stress of about 50 MPa.
  • the silicon nitride layers 23b2 and 23c2 have, for example, a refractive index of 1.85, a thickness of 20 nm, and a compressive stress of 150 MPa.
  • the silicon nitride layer 23a2 has a refractive index of 1.75, a thickness of 200 nm, and a tensile stress of 200 MPa.
  • the second transparent conductive layer 24 is formed. Similar to the first transparent conductive layer 22, for example, an ITO film having a thickness of about 40 nm to about 150 nm is formed by a sputtering method. By patterning the obtained ITO film, the second transparent conductive layer 24 including the pixel electrode 24p, the second contact electrode 24c, and the second transparent terminal electrode 24t is obtained.
  • the active matrix substrate 100B shown in FIG. 3 is obtained.
  • the active matrix substrate 100A can also be manufactured by the same method by omitting the silicon oxide layers 23d2 and 23e2.
  • FIG. 5 is a schematic plan view of still another active matrix substrate 100C according to the embodiment of the present invention.
  • 6 is a schematic cross-sectional view of the active matrix substrate 100C.
  • FIG. 6A shows a cross-section along the line AA ′ in FIG. 5
  • FIG. 6B shows the cross-section in FIG. A cross section along the line BB ′ is shown.
  • the above-described stacked body 23S2 of the active matrix substrate 100B has five inorganic insulating layers, but one of the fourth inorganic insulating layer 23d2 and the fifth inorganic insulating layer 23e2 can be omitted.
  • the stacked body 23S3 included in the active matrix substrate 100C does not include the fifth inorganic insulating layer 23e2 of the stacked body 23S2 included in the active matrix substrate 100B.
  • the laminated body 23S3 is formed so as to sandwich the first inorganic insulating layer 23a3 having tensile stress, the second inorganic insulating layer 23b3 and the third inorganic insulating layer 23c3 having compressive stress. have.
  • the laminated structure of this portion is the same as that of the laminated body 23S1.
  • the stacked body 23S3 further includes a fourth inorganic insulating layer 23d3 between the first transparent conductive layer 22 and the second inorganic insulating layer 23b3, that is, on the substrate 11 side of the second inorganic insulating layer 23b3.
  • the laminated body 23S3 also has a tensile stress as a whole, like the laminated bodies 23S1 and 23S2.
  • the first inorganic insulating layer 23a3 is, for example, a silicon nitride layer having a refractive index of 1.804 or less, and the second inorganic insulating layer 23b3 and the third inorganic insulating layer 23c3 have, for example, a refractive index of 1.805.
  • the fourth inorganic insulating layer 23d3 is a silicon oxide layer having a refractive index of 1.4 or more and 1.6 or less.
  • the thicknesses of the silicon nitride layers 23b3 and 23c3 having a refractive index of 1.805 or more are set to thb3 and thc3, respectively, and the thicknesses of the silicon oxide layers 23d3 having a refractive index of 1.4 to 1.6 are set to thd3, respectively.
  • the thickness of the silicon nitride layer 23a3 having a refractive index of 1.804 or less is tha3, it is preferable to satisfy the relationship tha3 ⁇ thb3 + thc3 + thd3.
  • thb3, thc3, and thd3 are independently 100 nm or less for the same reason as described above.
  • the magnitude of the stress of each layer is affected not only by the thickness of each layer but also by the structure (composition, etc.) of each film. May have tensile stress. According to the inventor's study, if the above relationship is satisfied, the laminate 23S3 has a tensile stress as a whole.
  • the active matrix substrate 100C also has an organic insulating layer 19 that covers the TFT 10C, and a part of the organic insulating layer 19 is in direct contact with a part of the stacked body 23S3. Accordingly, the laminated body 23S3 is excellent in adhesion to the first transparent conductive layer 22 and the organic insulating layer 19 that are in contact with the lower surface, like the laminated body 23S1 of the active matrix substrate 100A and the laminated body 23S2 of the active matrix substrate 100B. , Peeling is suppressed.
  • the active matrix substrate 100C having the stacked body 23S3 has an advantage that the reduction reaction of the transparent conductive layer can be more effectively suppressed than the active matrix substrate 100A having the stacked body 23S1.
  • the TFT 10A included in the active matrix substrates 100A and 100B is an etch stop type TFT, whereas the TFT 10C included in the active matrix substrate 100C is a channel etch type TFT.
  • FIGS. 7A to 7D are schematic cross-sectional views for explaining a method of manufacturing the active matrix substrate 100C, in the vicinity of the TFT 10C of FIG. 6A and the gate terminal portion of FIG. 6B.
  • the cross-sectional structure near 12t is also shown.
  • the material, thickness, and the like forming each component may be the same as described above with reference to FIGS.
  • a substrate 11 is prepared, a gate metal film is formed on the substrate 11, and a gate metal layer 12 is formed by patterning the gate metal film.
  • the gate metal layer 12 includes a gate electrode 12g, a gate wiring, an auxiliary capacitance bus line (CS bus line), and a gate terminal portion 12t.
  • a gate insulating layer 13 is formed so as to cover the gate metal layer 12, and a semiconductor layer 14 is formed on the gate insulating layer 13.
  • the source metal layer 16 including the source electrode 16S and the drain electrode 16D is formed.
  • the first interlayer insulating layer 17 (and the gate insulating layer 13) includes a first contact hole (for pixel electrode) 17a, a second contact hole (for gate) 17b, and a third contact hole (for source) shown in FIG. 17c is formed.
  • a contact hole for connecting the auxiliary capacitor counter electrode 22a to the auxiliary capacitor wiring (not shown) is provided in the first interlayer insulating layer. 17 and the gate insulating layer 13.
  • a through hole (a hole exposing the lower layer) is formed at a location corresponding to the contact hole in the second interlayer insulating layer 19.
  • a contact hole 17a penetrating the first interlayer insulating layer 17 and a contact hole 17b penetrating the first interlayer insulating layer 17 and the gate insulating layer 13 are formed.
  • a contact hole for connecting the storage capacitor counter electrode 22a to the storage capacitor wiring (not shown) is also formed as necessary.
  • the first transparent conductive layer 22 is formed on the second interlayer insulating layer 19.
  • the first transparent conductive layer 22 including the shield electrode or auxiliary capacitance counter electrode 22a, the first contact electrode 22c, and the first transparent terminal electrode 22t is obtained.
  • a stacked body 23 ⁇ / b> S ⁇ b> 3 is formed on the first transparent conductive layer 22.
  • the stacked body 23S3 can be formed by a similar method by omitting the silicon oxide layer 23e2 in FIG.
  • the second transparent conductive layer 24 is formed.
  • the second transparent conductive layer 24 including the pixel electrode 24p, the second contact electrode 24c, and the second transparent terminal electrode 24t is obtained. In this way, the active matrix substrate 100C shown in FIGS. 5 and 6 is obtained.
  • the active matrix substrate 100C including the channel etch type TFT is exemplified, but the active matrix substrate 100C including the channel etch type TFT can be applied to the above-described etch stop type active matrix substrate.
  • the bodies 23S1 and 23S2 can also be applied.
  • the active matrix substrate used in the VA mode liquid crystal display device having the two-layer electrode structure is exemplified.
  • the present invention is not limited to this, and the embodiment of the present invention is not limited to the liquid crystal display device in various modes. It is applied to an active matrix substrate used in the above.
  • the first transparent conductive layer 22 is a common electrode
  • the second transparent conductive layer 24 is a pixel electrode having a plurality of slits. .
  • the embodiment of the present invention is applied to an active matrix substrate, particularly an active matrix substrate suitably used for a liquid crystal display device.

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Abstract

This active matrix substrate (100A) comprises: a substrate (11); a TFT (10A) supported by the substrate and including a semiconductor layer (14), a gate electrode (12g), a source electrode (16S), and a drain electrode (16D); a first transparent electroconductive layer (22) and a second transparent electroconductive layer (24) that have tensile stress, at least one of which is electrically connected to the drain electrode of the TFT; and a laminate (23S1) of inorganic insulating layers that is formed between the first transparent electroconductive layer and the second transparent electroconductive layer. The laminate includes a first inorganic insulating layer (23a1) that has tensile stress, and second and third inorganic insulating layers (23b1, 23c1) that have compressive stress and that are formed so as to sandwich the first inorganic insulating layer. The laminate has tensile stress as a whole.

Description

アクティブマトリクス基板Active matrix substrate
　本発明は、アクティブマトリクス基板に関し、特に、液晶表示装置に好適に用いられるアクティブマトリクス基板に関する。 The present invention relates to an active matrix substrate, and more particularly to an active matrix substrate suitably used for a liquid crystal display device.
　アクティブマトリクス型の液晶表示装置は、一般に、画素ごとにスイッチング素子として薄膜トランジスタ（ＴＦＴ）が形成されたアクティブマトリクス基板（「ＴＦＴ基板」と呼ばれることもある）と、カラーフィルタなどが形成された対向基板（「カラーフィルタ基板」と呼ばれることもある）と、アクティブマトリクス基板および対向基板の間に設けられた液晶層とを備えている。薄膜トランジスタに電気的に接続された画素電極と、共通電極との電位差に応じた電界が液晶層に印加され、この電界によって液晶層中の液晶分子の配向状態が変化することにより、各画素の光透過率を制御して表示を行うことができる。 An active matrix liquid crystal display device generally includes an active matrix substrate (sometimes referred to as a “TFT substrate”) in which a thin film transistor (TFT) is formed as a switching element for each pixel, and a counter substrate on which a color filter or the like is formed. (Sometimes referred to as a “color filter substrate”) and a liquid crystal layer provided between the active matrix substrate and the counter substrate. An electric field corresponding to the potential difference between the pixel electrode electrically connected to the thin film transistor and the common electrode is applied to the liquid crystal layer, and the alignment state of the liquid crystal molecules in the liquid crystal layer is changed by this electric field, so that the light of each pixel Display can be performed by controlling the transmittance.
　アクティブマトリクス型の液晶表示装置には、その用途に応じて様々な表示モードが提案され、採用されている。表示モードとしては、ＴＮ（Ｔｗｉｓｔｅｄ　Ｎｅｍａｔｉｃ）モード、ＶＡ（Ｖｅｒｔｉｃａｌ　Ａｌｉｇｎｍｅｎｔ）モード、ＩＰＳ（Ｉｎ－Ｐｌａｎｅ－Ｓｗｉｔｃｈｉｎｇ）モード、ＦＦＳ（Ｆｒｉｎｇｅ　Ｆｉｅｌｄ　Ｓｗｉｔｃｈｉｎｇ）モードなどが挙げられる。 In the active matrix type liquid crystal display device, various display modes are proposed and adopted depending on the application. Examples of the display mode include a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In-Plane-Switching) mode, and an FFS (Fringe Field Switching) mode.
　これらの液晶表示装置の中には、アクティブマトリクス基板が無機絶縁層を間に介して形成された２つの透明導電層を有するものがある。無機絶縁層を間に挟んだ２つの透明導電層で形成される電極の構造を、簡単のために、「２層電極構造」ということにする。 In some of these liquid crystal display devices, an active matrix substrate has two transparent conductive layers formed with an inorganic insulating layer interposed therebetween. For the sake of simplicity, the structure of an electrode formed by two transparent conductive layers sandwiching an inorganic insulating layer is referred to as a “two-layer electrode structure”.
　例えば、一般的なＦＦＳモードでは、特許文献１に開示されているように、下層の透明導電層が共通電極として設けられ、上層の透明導電層が複数のスリットを形成された画素電極として設けられる。なお、特許文献２に開示されているように、ＦＦＳモードにおいて、画素電極が下層電極として設けられ、複数のスリットが形成された共通電極が上層電極として設けられる構成も知られている。 For example, in a general FFS mode, as disclosed in Patent Document 1, a lower transparent conductive layer is provided as a common electrode, and an upper transparent conductive layer is provided as a pixel electrode in which a plurality of slits are formed. . In addition, as disclosed in Patent Document 2, in the FFS mode, a configuration in which a pixel electrode is provided as a lower layer electrode and a common electrode in which a plurality of slits are formed is provided as an upper layer electrode is also known.
特開２００２－１８２２３０号公報JP 2002-182230 A 特開２０１１－５３４４３号公報JP 2011-53443 A
　また、出願人は、後述するように、２層電極構造を利用した補助容量を有する液晶表示装置を研究開発している。具体的には、下層の透明導電層を補助容量対向電極（共通電圧または補助容量対向電圧が供給される）とし、上層の透明導電層を画素電極とした構成を検討している。この液晶表示装置は、例えばＶＡモードであるが、他の表示モードにも適用できる。 Also, as will be described later, the applicant is researching and developing a liquid crystal display device having an auxiliary capacity using a two-layer electrode structure. Specifically, a configuration in which the lower transparent conductive layer is an auxiliary capacitor counter electrode (a common voltage or an auxiliary capacitor counter voltage is supplied) and the upper transparent conductive layer is a pixel electrode is being studied. This liquid crystal display device is, for example, the VA mode, but can be applied to other display modes.
　本発明は、上記の２層電極構造を有するアクティブマトリクス基板に、詳細は比較例を参照して後述するが、以下の課題があることを見出した。 The present invention has been found that the active matrix substrate having the above two-layer electrode structure has the following problems, although details will be described later with reference to a comparative example.
　まず、２層電極構造において、２つの透明導電層の間に形成された層間絶縁膜（図８に示す比較例のアクティブマトリクス基板２００Ａの第３層間絶縁層２３Ｐ）と透明導電層との密着性が低く、剥がれやすいという問題がある。 First, in the two-layer electrode structure, adhesion between an interlayer insulating film (third interlayer insulating layer 23P of the active matrix substrate 200A of the comparative example shown in FIG. 8) formed between two transparent conductive layers and the transparent conductive layer. There is a problem that it is low and easily peeled off.
　さらに、２層電極構造において、透明導電層と層間絶縁膜との密着性を改善するために、種々の無機絶縁層を検討したところ、密着性を向上させることができる無機絶縁層（例えば、引張応力を有する窒化シリコン（ＳｉＮx）層）を用いると、透明導電層（一般に、ＩＴＯ（インジウム錫酸化物）またはＩＺＯ（インジウム亜鉛酸化物）などで代表される透明無機酸化物から形成される）が窒化シリコン層によって、界面近傍の酸化物が還元され金属化される結果、透明導電層の光の透過率が低下するという問題がある。 Furthermore, in the two-layer electrode structure, various inorganic insulating layers have been studied in order to improve the adhesion between the transparent conductive layer and the interlayer insulating film. When a stressed silicon nitride (SiN x ) layer is used, a transparent conductive layer (generally formed from a transparent inorganic oxide represented by ITO (indium tin oxide) or IZO (indium zinc oxide)) However, the oxide near the interface is reduced and metallized by the silicon nitride layer, resulting in a problem that the light transmittance of the transparent conductive layer is lowered.
　本発明は、上記の問題の少なくとも一部を解決したアクティブマトリクス基板を提供することを目的とする。 An object of the present invention is to provide an active matrix substrate that solves at least a part of the above problems.
　本発明の実施形態によるアクティブマトリクス基板は、基板と、前記基板に支持され、半導体層、ゲート電極、ソース電極およびドレイン電極を有する薄膜トランジスタと、少なくとも一方が前記薄膜トランジスタの前記ドレイン電極と電気的に接続された、第１透明導電層および第２透明導電層と、前記第１透明導電層と前記第２透明導電層との間に形成された、無機絶縁層の積層体とを有し、前記積層体は、引張応力を有する第１無機絶縁層と、前記第１無機絶縁層を挟むように形成され、圧縮応力を有する第２および第３無機絶縁層とを有し、且つ、前記積層体は全体として引張応力を有する。本発明の実施形態によるアクティブマトリクス基板においては、引張応力を有する前記第１無機絶縁層が、前記第１透明導電層および前記第２透明導電層のいずれにも直接接触することがない。 An active matrix substrate according to an embodiment of the present invention includes a substrate, a thin film transistor supported by the substrate and having a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, at least one of which is electrically connected to the drain electrode of the thin film transistor The first transparent conductive layer and the second transparent conductive layer, and a laminate of inorganic insulating layers formed between the first transparent conductive layer and the second transparent conductive layer, The body includes a first inorganic insulating layer having a tensile stress, and second and third inorganic insulating layers having a compressive stress formed so as to sandwich the first inorganic insulating layer, and the stacked body includes As a whole, it has tensile stress. In the active matrix substrate according to the embodiment of the present invention, the first inorganic insulating layer having a tensile stress does not directly contact any of the first transparent conductive layer and the second transparent conductive layer.
　ある実施形態において、前記第１無機絶縁層は、屈折率が１．８０４以下の窒化シリコン層である。 In one embodiment, the first inorganic insulating layer is a silicon nitride layer having a refractive index of 1.804 or less.
　ある実施形態において、前記第２無機絶縁層および前記第３無機絶縁層は、屈折率が１．８０５以上の窒化シリコン層である。 In one embodiment, the second inorganic insulating layer and the third inorganic insulating layer are silicon nitride layers having a refractive index of 1.805 or more.
　ある実施形態において、前記第１透明導電層は前記第２透明導電層よりも前記基板の近くに形成されており、前記第２無機絶縁層は前記第３無機絶縁層よりも前記基板の近くに形成されており、前記積層体は、前記第１透明導電層と前記第２無機絶縁層との間に第４無機絶縁層をさらに有する。 In one embodiment, the first transparent conductive layer is formed closer to the substrate than the second transparent conductive layer, and the second inorganic insulating layer is closer to the substrate than the third inorganic insulating layer. The laminated body further includes a fourth inorganic insulating layer between the first transparent conductive layer and the second inorganic insulating layer.
　ある実施形態において、前記第４無機絶縁層は、屈折率が１．４以上１．６以下の酸化シリコン層である。 In one embodiment, the fourth inorganic insulating layer is a silicon oxide layer having a refractive index of 1.4 to 1.6.
　ある実施形態において、前記積層体は、前記第２透明導電層と前記第３無機絶縁層との間に第５無機絶縁層をさらに有する。 In one embodiment, the laminate further includes a fifth inorganic insulating layer between the second transparent conductive layer and the third inorganic insulating layer.
　ある実施形態において、前記第５無機絶縁層は、屈折率が１．４以上１．６以下の酸化シリコン層である。 In one embodiment, the fifth inorganic insulating layer is a silicon oxide layer having a refractive index of 1.4 to 1.6.
　ある実施形態において、前記第１透明導電層および前記第２透明導電層は、ＩＴＯ層またはＩＺＯ層である。 In one embodiment, the first transparent conductive layer and the second transparent conductive layer are ITO layers or IZO layers.
　ある実施形態において、前記半導体層は、酸化物半導体層である。前記酸化物半導体層は、例えば、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体（ＩＧＺＯ系半導体）を含む。 In one embodiment, the semiconductor layer is an oxide semiconductor layer. The oxide semiconductor layer includes, for example, an In—Ga—Zn—O-based semiconductor (IGZO-based semiconductor).
　ある実施形態において、前記第１透明導電層は、電気的にフローティング状態にあり、前記第２透明導電層は、画素電極である。 In one embodiment, the first transparent conductive layer is in an electrically floating state, and the second transparent conductive layer is a pixel electrode.
　ある実施形態において、前記第１透明導電層は、補助容量対向電極であり、前記第２透明導電層は、画素電極である。この実施形態のアクティブマトリクス基板は、例えば、垂直配向（ＶＡ）モードの液晶表示装置に用いられる。 In one embodiment, the first transparent conductive layer is a storage capacitor counter electrode, and the second transparent conductive layer is a pixel electrode. The active matrix substrate of this embodiment is used in, for example, a vertical alignment (VA) mode liquid crystal display device.
　ある実施形態において、前記第１透明導電層は、共通電極であり、前記第２透明導電層は、複数のスリットを有する画素電極である。この実施形態のアクティブマトリクス基板は、例えば、ＦＦＳモードの液晶表示装置に用いられる。 In one embodiment, the first transparent conductive layer is a common electrode, and the second transparent conductive layer is a pixel electrode having a plurality of slits. The active matrix substrate of this embodiment is used for an FFS mode liquid crystal display device, for example.
　ある実施形態において、前記アクティブマトリクス基板は、前記薄膜トランジスタを覆う有機絶縁層をさらに有し、前記有機絶縁層の一部は、前記積層体の一部と直接接触している。 In one embodiment, the active matrix substrate further includes an organic insulating layer covering the thin film transistor, and a part of the organic insulating layer is in direct contact with a part of the stacked body.
　本発明の実施形態によると、引張応力を有する２つの透明導電層の間に形成された、無機絶縁層の積層体によって、剥離が抑制される。また、本発明の実施形態によると、積層体に含まれる引張応力を有する第１無機絶縁層が、第１透明導電層および第２透明導電層のいずれにも直接接触することがないので、例えば、第１無機絶縁層を窒化シリコン層で形成しても、第１透明導電層および第２透明導電層を構成している透明酸化物（ＩＴＯ、ＩＺＯ）を還元することがなく、光の透過率の低下を招かない。 According to the embodiment of the present invention, peeling is suppressed by the laminate of inorganic insulating layers formed between two transparent conductive layers having tensile stress. Further, according to the embodiment of the present invention, the first inorganic insulating layer having a tensile stress contained in the laminate does not directly contact either the first transparent conductive layer or the second transparent conductive layer. Even if the first inorganic insulating layer is formed of a silicon nitride layer, the transparent oxide (ITO, IZO) constituting the first transparent conductive layer and the second transparent conductive layer is not reduced, and light is transmitted. The rate will not drop.
本発明の実施形態によるアクティブマトリクス基板１００Ａの模式的な平面図である。FIG. 3 is a schematic plan view of an active matrix substrate 100A according to an embodiment of the present invention. アクティブマトリクス基板１００Ａの模式的な断面図であり、（ａ）は、図１中のＡ－Ａ’線に沿った断面を示し、（ｂ）は図１中のＢ－Ｂ’線に沿った断面を示している。2A and 2B are schematic cross-sectional views of an active matrix substrate 100A, in which FIG. 1A shows a cross section along the line AA ′ in FIG. 1, and FIG. 2B shows a cross section along the line BB ′ in FIG. A cross section is shown. 本発明の実施形態による他のアクティブマトリクス基板１００Ｂの模式的な断面図であり、（ａ）および（ｂ）は、図２（ａ）および（ｂ）にそれぞれ対応する断面を示している。It is typical sectional drawing of other active matrix board | substrates 100B by embodiment of this invention, (a) and (b) has shown the cross section corresponding to Fig.2 (a) and (b), respectively. （ａ）～（ｄ）は、アクティブマトリクス基板１００Ｂの製造方法を説明するための模式的な断面図である。(A)-(d) is typical sectional drawing for demonstrating the manufacturing method of the active matrix substrate 100B. 本発明の実施形態によるさらに他のアクティブマトリクス基板１００Ｃの模式的な平面図である。FIG. 10 is a schematic plan view of still another active matrix substrate 100C according to an embodiment of the present invention. アクティブマトリクス基板１００Ｃの模式的な断面図であり、（ａ）は、図５中のＡ－Ａ’線に沿った断面を示し、（ｂ）は図５中のＢ－Ｂ’線に沿った断面を示している。6A and 6B are schematic cross-sectional views of an active matrix substrate 100C, in which FIG. 5A shows a cross section along the line AA ′ in FIG. 5, and FIG. A cross section is shown. （ａ）～（ｄ）は、アクティブマトリクス基板１００Ｃの製造方法を説明するための模式的な断面図である。(A)-(d) is typical sectional drawing for demonstrating the manufacturing method of 100 C of active matrix substrates. 比較例のアクティブマトリクス基板２００Ａの模式的な断面図である。It is a typical sectional view of active matrix substrate 200A of a comparative example. （ａ）および（ｂ）は、膜の内部応力の評価方法を説明するための模式図である。(A) And (b) is a schematic diagram for demonstrating the evaluation method of the internal stress of a film | membrane.
　以下、図面を参照して、本発明の実施形態によるアクティブマトリクス基板の構造と製造方法を説明する。以下では、２層電極構造を有するＶＡモードの液晶表示装置に用いられるアクティブマトリクス基板を例示する。しかし、本発明の実施形態はこれに限られず、上述のＦＦＳモードの液晶表示装置に用いられるアクティブマトリクス基板の他、他の表示装置にも適用できる。 Hereinafter, the structure and manufacturing method of an active matrix substrate according to an embodiment of the present invention will be described with reference to the drawings. In the following, an active matrix substrate used for a VA mode liquid crystal display device having a two-layer electrode structure will be exemplified. However, the embodiment of the present invention is not limited to this, and can be applied to other display devices besides the active matrix substrate used in the above-described FFS mode liquid crystal display device.
　まず、図１および図２を参照して、本発明の実施形態によるアクティブマトリクス基板１００Ａの構造を説明する。図１は、本発明の実施形態によるアクティブマトリクス基板１００Ａの模式的な平面図である。図２は、アクティブマトリクス基板１００Ａの模式的な断面図であり、図２（ａ）は、図１中のＡ－Ａ’線に沿った断面を示し、図２（ｂ）は図１中のＢ－Ｂ’線に沿った断面を示している。 First, the structure of an active matrix substrate 100A according to an embodiment of the present invention will be described with reference to FIG. 1 and FIG. FIG. 1 is a schematic plan view of an active matrix substrate 100A according to an embodiment of the present invention. 2 is a schematic cross-sectional view of the active matrix substrate 100A. FIG. 2 (a) shows a cross-section along the line AA ′ in FIG. 1, and FIG. 2 (b) shows the cross-section in FIG. A cross section along the line BB ′ is shown.
　アクティブマトリクス基板１００Ａは、基板（例えばガラス基板）１１と、基板１１に支持され、半導体層１４、ゲート電極１２ｇ、ソース電極１６Ｓおよびドレイン電極１６Ｄを有する薄膜トランジスタ（以下、ＴＦＴという。）１０Ａと、少なくとも一方がＴＦＴ１０Ａのドレイン電極１６Ｄと電気的に接続された、引張応力を有する第１透明導電層２２および第２透明導電層２４と、第１透明導電層２２と第２透明導電層２４との間に形成された、無機絶縁層の積層体２３Ｓ１とを有している。ここでは、第１透明導電層２２は、第２透明導電層２４よりも基板１１に近い側に形成されており、第２透明導電層２４が、ＴＦＴ１０Ａのドレイン電極１６Ｄと電気的に接続されている。 The active matrix substrate 100A includes a substrate (for example, a glass substrate) 11, a thin film transistor (hereinafter referred to as TFT) 10A supported by the substrate 11, and having a semiconductor layer 14, a gate electrode 12g, a source electrode 16S, and a drain electrode 16D, and at least. One of the first transparent conductive layer 22 and the second transparent conductive layer 24 having tensile stress, one of which is electrically connected to the drain electrode 16D of the TFT 10A, and between the first transparent conductive layer 22 and the second transparent conductive layer 24 The laminated body 23S1 of the inorganic insulating layer is formed. Here, the first transparent conductive layer 22 is formed closer to the substrate 11 than the second transparent conductive layer 24, and the second transparent conductive layer 24 is electrically connected to the drain electrode 16D of the TFT 10A. Yes.
　ここで、第１透明導電層２２および第２透明導電層２４は、ＩＴＯ層またはＩＺＯ層である。ＩＴＯ層およびＩＺＯ層は、いずれも引張応力を有することが知られている。特に、ＩＴＯ層はＩＺＯ層に比べて、引張応力が大きく、剥がれやすい。ＩＴＯ層やＩＺＯ層が引張応力を有する理由は必ずしも明らかではないが、成膜温度や条件等によらず、一般に引張応力を有する。各層の内部応力（引張応力または圧縮応力）については、図９を参照して後述する。 Here, the first transparent conductive layer 22 and the second transparent conductive layer 24 are an ITO layer or an IZO layer. Both the ITO layer and the IZO layer are known to have tensile stress. In particular, the ITO layer has a larger tensile stress than the IZO layer and is easily peeled off. The reason why the ITO layer and the IZO layer have a tensile stress is not necessarily clear, but generally has a tensile stress regardless of the film formation temperature and conditions. The internal stress (tensile stress or compressive stress) of each layer will be described later with reference to FIG.
　積層体２３Ｓ１は、引張応力を有する第１無機絶縁層２３ａ１と、第１無機絶縁層２３ａ１を挟むように形成され、圧縮応力を有する第２無機絶縁層２３ｂ１および第３無機絶縁層２３ｃ１とを有している。第２無機絶縁層２３ｂ１は、第１無機絶縁層２３ａ１の基板１１側に形成されており、第３無機絶縁層２３ｃ１は、第１無機絶縁層２３ａ１の基板１１とは反対側に形成されている。積層体２３Ｓ１は全体として引張応力を有する。また、アクティブマトリクス基板１００Ａにおいては、引張応力を有する第１無機絶縁層２３ａ１が、第１透明導電層２２および第２透明導電層２４のいずれにも直接接触することがない。 The laminated body 23S1 includes a first inorganic insulating layer 23a1 having tensile stress, and a second inorganic insulating layer 23b1 and a third inorganic insulating layer 23c1 which are formed so as to sandwich the first inorganic insulating layer 23a1 and have compressive stress. is doing. The second inorganic insulating layer 23b1 is formed on the substrate 11 side of the first inorganic insulating layer 23a1, and the third inorganic insulating layer 23c1 is formed on the side opposite to the substrate 11 of the first inorganic insulating layer 23a1. . The laminated body 23S1 has a tensile stress as a whole. Further, in the active matrix substrate 100A, the first inorganic insulating layer 23a1 having a tensile stress is not in direct contact with either the first transparent conductive layer 22 or the second transparent conductive layer 24.
　ここで、第１無機絶縁層２３ａ１は、例えば、屈折率が１．８０４以下の窒化シリコン層である。第２無機絶縁層２３ｂ１および第３無機絶縁層２３ｃ１は、例えば、屈折率が１．８０５以上の窒化シリコン層である。 Here, the first inorganic insulating layer 23a1 is, for example, a silicon nitride layer having a refractive index of 1.804 or less. The second inorganic insulating layer 23b1 and the third inorganic insulating layer 23c1 are, for example, silicon nitride layers having a refractive index of 1.805 or more.
　一般に、窒化シリコン層や酸化シリコン層は、圧縮応力を有することが知られている。ただし、屈折率が１．８０４以下の窒化シリコン層は例外的に引張応力を有する。従って、図８に示す比較例のアクティブマトリクス基板２００Ａのように、第３層間絶縁層２３Ｐとして、屈折率が１．８０４以下の窒化シリコン層を用いると、第３層間絶縁層２３Ｐの剥離を抑制することはできる。しかしながら、屈折率が１．８０４以下の窒化シリコン層は、還元力が強く、例えばＩＴＯ層２２、２４と接触した状態で、熱処理を行うと、窒化シリコン層とＩＴＯ層２２、２４との界面近傍のＩＴＯを還元し、金属化する。そうすると、ＩＴＯ層２２、２４の光透過率は低下する。第１透明導電層２２および第２透明導電層２４としてＩＺＯ層を用いる場合も同様である。 Generally, it is known that a silicon nitride layer or a silicon oxide layer has a compressive stress. However, a silicon nitride layer having a refractive index of 1.804 or less exceptionally has a tensile stress. Accordingly, when a silicon nitride layer having a refractive index of 1.804 or less is used as the third interlayer insulating layer 23P as in the active matrix substrate 200A of the comparative example shown in FIG. 8, peeling of the third interlayer insulating layer 23P is suppressed. Can do. However, a silicon nitride layer having a refractive index of 1.804 or less has a strong reducing power. For example, when heat treatment is performed in contact with the ITO layers 22 and 24, the vicinity of the interface between the silicon nitride layer and the ITO layers 22 and 24 is obtained. The ITO is reduced and metallized. If it does so, the light transmittance of ITO layers 22 and 24 will fall. The same applies to the case where IZO layers are used as the first transparent conductive layer 22 and the second transparent conductive layer 24.
　そこで、アクティブマトリクス基板１００Ａにおいては、屈折率が１．８０４以下の窒化シリコン層２３ａ１（引張応力を有する）を、屈折率が１．８０５以上の窒化シリコン層２３ｂ１と窒化シリコン層２３ｃ１（圧縮応力を有する）とで挟んだ構造を有する積層体２３Ｓ１を用いることによって、引張応力を有する屈折率が１．８０４以下の窒化シリコン層２３ａ１が、第１透明導電層（ＩＴＯ層またはＩＺＯ層）２２および第２透明導電層（ＩＴＯ層またはＩＺＯ層）２４のいずれにも直接接触することを防止している。 Therefore, in the active matrix substrate 100A, the silicon nitride layer 23a1 (having a tensile stress) having a refractive index of 1.804 or less, the silicon nitride layer 23b1 and the silicon nitride layer 23c1 (having a compressive stress) having a refractive index of 1.805 or more. By using the stacked body 23S1 having a structure sandwiched between the first transparent conductive layer (ITO layer or IZO layer) 22 and the first transparent conductive layer (ITO layer or IZO layer) 22 having a refractive index of 1.804 or less having tensile stress. The direct contact with any of the two transparent conductive layers (ITO layer or IZO layer) 24 is prevented.
　積層体２３Ｓ１は、全体として、引張応力を有するように構成されている。例えば、屈折率が１．８０５以上の窒化シリコン層２３ｂ１および２３ｃ１の厚さをそれぞれｔｈｂ１およびｔｈｃ１とし、屈折率が１．８０４以下の窒化シリコン層２３ａ１の厚さをｔｈａ１とすると、ｔｈａ１≧ｔｈｂ１＋ｔｈｃ１の関係を満足することが好ましい。このとき、ｔｈｂ１およびｔｈｃ１は、それぞれ独立に１００ｎｍ以下であることが好ましい。もちろん、厳密には、各層の応力の大きさは、各層の厚さだけでなく、各膜の構造（組成など）の影響を受けるので、上記の関係を有しない場合でも、積層体２３Ｓ１が全体として引張応力を有することがある。発明者の検討によると、上記の関係を満足すれば、積層体２３Ｓ１は、全体として、引張応力を有する。なお、ｔｈｂ１およびｔｈｃ１が１００ｎｍを超えると、生産効率の低下という問題が生じることがあるので、ｔｈｂ１およびｔｈｃ１はそれぞれ独立に１００ｎｍ以下であることが好ましい。 The laminated body 23S1 is configured to have a tensile stress as a whole. For example, assuming that the thicknesses of the silicon nitride layers 23b1 and 23c1 having a refractive index of 1.805 or more are thb1 and thc1, respectively, and the thickness of the silicon nitride layer 23a1 having a refractive index of 1.804 or less is tha1, tha1 ≧ thb1 + thc1. It is preferable to satisfy the relationship. At this time, it is preferable that thb1 and thc1 are independently 100 nm or less. Needless to say, strictly speaking, the magnitude of the stress of each layer is affected not only by the thickness of each layer but also by the structure (composition, etc.) of each film. May have tensile stress. According to the inventor's study, the laminated body 23S1 as a whole has a tensile stress if the above relationship is satisfied. Note that if thb1 and thc1 exceed 100 nm, there is a problem that the production efficiency is lowered. Therefore, it is preferable that thb1 and thc1 are independently 100 nm or less.
　アクティブマトリクス基板１００Ａは、ＴＦＴ１０Ａを覆う有機絶縁層１９をさらに有しており、有機絶縁層１９の一部は、積層体２３Ｓ１の一部と直接接触している。有機絶縁層１９は、例えば、透明のポジ型感光性樹脂で形成されている。ガラス基板などの無機材料で形成された基板上に形成された有機絶縁層１９は、一般に、引張応力を有している。従って、圧縮応力を有する無機絶縁層は、有機絶縁層１９に対する密着性が低い。これに対して、アクティブマトリクス基板１００Ａにおいては、引張応力を有する積層体２３Ｓ１の一部が有機絶縁層１９の一部と接触しているので、密着性に優れる。従って、積層体２３Ｓ１は、その下面が接する第１透明導電層２２および有機絶縁層１９との密着性に優れるので、剥離することが抑制される。 The active matrix substrate 100A further includes an organic insulating layer 19 that covers the TFT 10A, and a part of the organic insulating layer 19 is in direct contact with a part of the stacked body 23S1. The organic insulating layer 19 is made of, for example, a transparent positive photosensitive resin. The organic insulating layer 19 formed on a substrate formed of an inorganic material such as a glass substrate generally has a tensile stress. Therefore, the inorganic insulating layer having compressive stress has low adhesion to the organic insulating layer 19. On the other hand, in the active matrix substrate 100A, since a part of the laminate 23S1 having a tensile stress is in contact with a part of the organic insulating layer 19, the adhesiveness is excellent. Therefore, since the laminate 23S1 is excellent in adhesiveness with the first transparent conductive layer 22 and the organic insulating layer 19 with which the lower surface is in contact, peeling is suppressed.
　本発明の実施形態によるアクティブマトリクス基板１００Ａにおいて、第１透明導電層２２の一部２２ａはどこにも接続されておらず、電気的にフローティング状態にあり、シールド電極２２ａとして機能し、第２透明導電層２４の一部２４ｐは画素電極として機能する。すなわち、第１透明導電層２２は、画素電極２４ｐの電位が、基板１１上に形成された種々の電極や配線による電界からの影響を受けないように保護する。 In the active matrix substrate 100A according to the embodiment of the present invention, a part 22a of the first transparent conductive layer 22 is not connected anywhere, is in an electrically floating state, functions as a shield electrode 22a, and is a second transparent conductive layer. A part 24p of the layer 24 functions as a pixel electrode. That is, the first transparent conductive layer 22 protects the potential of the pixel electrode 24p from being affected by an electric field generated by various electrodes and wirings formed on the substrate 11.
　なお、第１透明導電層２２の一部２２ａを補助容量対向電極２２ａとして用いてもよい。このとき、補助容量対向電極２２ａと、画素電極２４ｐと、これらの間の積層体２３Ｓ１が補助容量として機能する。補助容量は、第１透明導電層２２および第２透明導電層２４で形成されているので、画素開口率を低下させることなく、大きな容量値を有し得る。従って、ＴＦＴ１０Ａのように、ゲートバスライン１２上にソースコンタクトホール１５ａおよびドレインコンタクトホール１５ｂを有する構成を採用することによる、寄生容量の増大に伴うフィードスルー電圧の増大を抑制することが可能となる。 A part 22a of the first transparent conductive layer 22 may be used as the auxiliary capacitance counter electrode 22a. At this time, the auxiliary capacitor counter electrode 22a, the pixel electrode 24p, and the stacked body 23S1 therebetween function as an auxiliary capacitor. Since the auxiliary capacitance is formed of the first transparent conductive layer 22 and the second transparent conductive layer 24, it can have a large capacitance value without reducing the pixel aperture ratio. Accordingly, it is possible to suppress an increase in feedthrough voltage due to an increase in parasitic capacitance by adopting a configuration having the source contact hole 15a and the drain contact hole 15b on the gate bus line 12 as in the TFT 10A. .
　半導体層１４は、例えば、酸化物半導体層である。酸化物半導体は移動度が高いので、２層電極構造を利用して形成される比較的大きな容量値の補助容量を十分に速く充電できる。酸化物半導体層は、例えばＩｎ－Ｇａ－Ｚｎ－Ｏ系の半導体（以下、「ＩＧＺＯ系半導体」と略する。）を含む。ここで、ＩＧＺＯ系半導体は、Ｉｎ（インジウム）、Ｇａ（ガリウム）、Ｚｎ（亜鉛）の三元系酸化物であって、Ｉｎ、ＧａおよびＺｎの割合（組成比）は特に限定されず、例えばＩｎ：Ｇａ：Ｚｎ＝２：２：１、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１、Ｉｎ：Ｇａ：Ｚｎ＝１：１：２等を含む。ＩＧＺＯ系半導体は、アモルファスでもよいし、結晶質でもよい。結晶質ＩＧＺＯ系半導体としては、ｃ軸が層面に概ね垂直に配向した結晶質ＩＧＺＯ系半導体が好ましい。このようなＩＧＺＯ系半導体の結晶構造は、例えば、特開２０１２－１３４４７５号公報に開示されている。参考のために、特開２０１２－１３４４７５号公報の開示内容の全てを本明細書に援用する。 The semiconductor layer 14 is, for example, an oxide semiconductor layer. Since an oxide semiconductor has high mobility, an auxiliary capacitor having a relatively large capacitance value formed using a two-layer electrode structure can be charged sufficiently quickly. The oxide semiconductor layer includes, for example, an In—Ga—Zn—O-based semiconductor (hereinafter abbreviated as “IGZO-based semiconductor”). Here, the IGZO-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited. In: Ga: Zn = 2: 2: 1, In: Ga: Zn = 1: 1: 1, In: Ga: Zn = 1: 1: 2, and the like. The IGZO semiconductor may be amorphous or crystalline. As the crystalline IGZO-based semiconductor, a crystalline IGZO-based semiconductor having a c-axis oriented substantially perpendicular to the layer surface is preferable. Such a crystal structure of an IGZO-based semiconductor is disclosed in, for example, Japanese Patent Application Laid-Open No. 2012-134475. For reference, the entire disclosure of Japanese Patent Application Laid-Open No. 2012-134475 is incorporated herein by reference.
　ここで、図９を参照して、各層（膜）の内部応力の評価方法を説明する。シリコンウエファ１の上に、評価対象の膜を堆積する。図９（ａ）に示したように、シリコンウエファ１が上に凸に反ると、膜２ａには、圧縮応力ａcが発生している。このとき、シリコンウエファ１には引張応力が発生している。逆に、図９（ｂ）に示したように、シリコンウエファ１が下に凸に反ると、膜２ｂには、引張応力ａｔが発生している。このとき、シリコンウエファ１には圧縮応力が発生している。 Here, with reference to FIG. 9, the evaluation method of the internal stress of each layer (film | membrane) is demonstrated. A film to be evaluated is deposited on the silicon wafer 1. As shown in FIG. 9A, when the silicon wafer 1 is warped upward, a compressive stress ac is generated in the film 2a. At this time, tensile stress is generated in the silicon wafer 1. Conversely, as shown in FIG. 9 (b), the silicon wafer 1 is warped in a convex down, the film 2b, the tensile stress a t occurs. At this time, compressive stress is generated in the silicon wafer 1.
　反りの大きさを測定することによって、シリコンウエファ１の弾性率およびディメンジョン（厚さ、大きさ）と、膜２ａ、２ｂの弾性率およびディメンジョン（厚さ、大きさ）とから、内部応力の大きさを定量的に求めることができる。ここでは、膜ストレス計（テンコール社製）を用いて、各層の内部応力が引張応力か圧縮応力であるかを求めた。なお、膜ストレス計を用いて、曲率半径を求めることによって、内部応力の大きさを求めることができる。 By measuring the size of the warp, the internal stress is determined from the elastic modulus and dimensions (thickness and size) of the silicon wafer 1 and the elastic modulus and dimensions (thickness and size) of the films 2a and 2b. This can be quantitatively determined. Here, a film stress meter (manufactured by Tencor) was used to determine whether the internal stress of each layer was a tensile stress or a compressive stress. In addition, the magnitude | size of internal stress can be calculated | required by calculating | requiring a curvature radius using a film | membrane stress meter.
　次に、図１および図３を参照して、本発明の実施形態による他のアクティブマトリクス基板１００Ｂの構造を説明する。図３は、本発明の実施形態による他のアクティブマトリクス基板１００Ｂの模式的な断面図であり、図３（ａ）および（ｂ）は、図２（ａ）および（ｂ）にそれぞれ対応するアクティブマトリクス基板１００Ｂの断面を示している。アクティブマトリクス基板１００Ｂの平面構造は、図１に示したアクティブマトリクス基板１００Ａと同じである。 Next, the structure of another active matrix substrate 100B according to an embodiment of the present invention will be described with reference to FIG. 1 and FIG. FIG. 3 is a schematic cross-sectional view of another active matrix substrate 100B according to an embodiment of the present invention. FIGS. 3 (a) and 3 (b) show the active corresponding to FIGS. 2 (a) and 2 (b), respectively. The cross section of the matrix substrate 100B is shown. The planar structure of the active matrix substrate 100B is the same as that of the active matrix substrate 100A shown in FIG.
　アクティブマトリクス基板１００Ｂが有する積層体２３Ｓ２の構造は、アクティブマトリクス基板１００Ａの積層体２３Ｓ１の構造と異なっている。 The structure of the stacked body 23S2 included in the active matrix substrate 100B is different from the structure of the stacked body 23S1 of the active matrix substrate 100A.
　積層体２３Ｓ２は、引張応力を有する第１無機絶縁層２３ａ２と、第１無機絶縁層２３ａ２を挟むように形成され、圧縮応力を有する第２無機絶縁層２３ｂ２および第３無機絶縁層２３ｃ２とを有している。この部分の積層構造は、積層体２３Ｓ１と同じである。積層体２３Ｓ２は、さらに、第１透明導電層２２と第２無機絶縁層２３ｂ２との間に、すなわち第２無機絶縁層２３ｂ２の基板１１側に、第４無機絶縁層２３ｄ２を有し、且つ、第２透明導電層２４と第３無機絶縁層２３ｃ２との間に、すなわち第３無機絶縁層２３ｃ２の基板１１とは反対側に、第５無機絶縁層２３ｅ２をさらに有する。積層体２３Ｓ２も、積層体２３Ｓ１と同様に、全体として引張応力を有する。 The laminate 23S2 includes a first inorganic insulating layer 23a2 having tensile stress, and a second inorganic insulating layer 23b2 and a third inorganic insulating layer 23c2 that are formed so as to sandwich the first inorganic insulating layer 23a2 and have compressive stress. is doing. The laminated structure of this portion is the same as that of the laminated body 23S1. The stacked body 23S2 further includes a fourth inorganic insulating layer 23d2 between the first transparent conductive layer 22 and the second inorganic insulating layer 23b2, that is, on the substrate 11 side of the second inorganic insulating layer 23b2, and A fifth inorganic insulating layer 23e2 is further provided between the second transparent conductive layer 24 and the third inorganic insulating layer 23c2, that is, on the side opposite to the substrate 11 of the third inorganic insulating layer 23c2. The laminated body 23S2 also has a tensile stress as a whole, like the laminated body 23S1.
　ここで、第１無機絶縁層２３ａ２は、例えば、屈折率が１．８０４以下の窒化シリコン層であり、第２無機絶縁層２３ｂ２および第３無機絶縁層２３ｃ２は、例えば、屈折率が１．８０５以上の窒化シリコン層である。また、第４無機絶縁層２３ｄ２および第５無機絶縁層２３ｅ２は、屈折率が１．４以上１．６以下の酸化シリコン層である。屈折率が１．４以上１．６以下の酸化シリコン層も圧縮応力を有する。 Here, the first inorganic insulating layer 23a2 is, for example, a silicon nitride layer having a refractive index of 1.804 or less, and the second inorganic insulating layer 23b2 and the third inorganic insulating layer 23c2 have, for example, a refractive index of 1.805. The above silicon nitride layer. The fourth inorganic insulating layer 23d2 and the fifth inorganic insulating layer 23e2 are silicon oxide layers having a refractive index of 1.4 to 1.6. A silicon oxide layer having a refractive index of 1.4 to 1.6 also has a compressive stress.
　例えば、屈折率が１．８０５以上の窒化シリコン層２３ｂ２および２３ｃ２の厚さをそれぞれｔｈｂ２およびｔｈｃ２とし、屈折率が１．４以上１．６以下の酸化シリコン層２３ｄ２および２３ｅ２の厚さをそれぞれｔｈｄ２およびｔｈｅ２とし、屈折率が１．８０４以下の窒化シリコン層２３ａ２の厚さをｔｈａ２とすると、ｔｈａ２≧ｔｈｂ２＋ｔｈｃ２＋ｔｈｄ２＋ｔｈｅ２の関係を満足することが好ましい。このとき、ｔｈｂ２、ｔｈｃ２、ｔｈｄ２およびｔｈｅ２は、上記と同じ理由から、それぞれ独立に１００ｎｍ以下であることが好ましい。もちろん、厳密には、各層の応力の大きさは、各層の厚さだけでなく、各膜の構造（組成など）の影響を受けるので、上記の関係を有しない場合でも、積層体２３Ｓ２が全体として引張応力を有することがある。発明者の検討によると、上記の関係を満足すれば、積層体２３Ｓ２は、全体として、引張応力を有する。 For example, the thicknesses of the silicon nitride layers 23b2 and 23c2 having a refractive index of 1.805 or more are set to thb2 and thc2, respectively, and the thicknesses of the silicon oxide layers 23d2 and 23e2 having a refractive index of 1.4 to 1.6 are set to thd2. When the thickness of the silicon nitride layer 23a2 having a refractive index of 1.804 or less is tha2, it is preferable that the relationship of tha2 ≧ thb2 + thc2 + thd2 + the2 is satisfied. At this time, it is preferable that thb2, thc2, thd2, and the2 are independently 100 nm or less for the same reason as described above. Of course, strictly speaking, the magnitude of the stress of each layer is affected not only by the thickness of each layer but also by the structure (composition, etc.) of each film. May have tensile stress. According to the inventor's study, if the above relationship is satisfied, the laminate 23S2 has a tensile stress as a whole.
　アクティブマトリクス基板１００Ｂも、ＴＦＴ１０Ａを覆う有機絶縁層１９をさらに有しており、有機絶縁層１９の一部は、積層体２３Ｓ２の一部と直接接触している。従って、積層体２３Ｓ２は、アクティブマトリクス基板１００Ａの積層体２３Ｓ１と同様に、その下面が接する第１透明導電層２２および有機絶縁層１９との密着性に優れるので、剥離することが抑制される。 The active matrix substrate 100B further includes an organic insulating layer 19 that covers the TFT 10A, and a part of the organic insulating layer 19 is in direct contact with a part of the stacked body 23S2. Accordingly, the laminate 23S2 is excellent in adhesion to the first transparent conductive layer 22 and the organic insulating layer 19 with which the lower surface is in contact, similarly to the laminate 23S1 of the active matrix substrate 100A, and therefore, peeling is suppressed.
　積層体２３Ｓ２を有するアクティブマトリクス基板１００Ｂは、積層体２３Ｓ１を有するアクティブマトリクス基板１００Ａに比べて、透明導電層の還元反応をより効果的に抑制できるという利点がある。 The active matrix substrate 100B having the multilayer body 23S2 has an advantage that the reduction reaction of the transparent conductive layer can be more effectively suppressed than the active matrix substrate 100A having the multilayer body 23S1.
　次に、図４（ａ）～（ｄ）を参照して、アクティブマトリクス基板１００Ｂの製造方法を説明する。図４（ａ）～（ｄ）は、アクティブマトリクス基板１００Ｂの製造方法を説明するための模式的な断面図であり、図３（ａ）のＴＦＴ１０Ａの近傍および図３（ｂ）のゲート端子部１２ｔ付近の断面構造を併せて示している。 Next, with reference to FIGS. 4A to 4D, a method for manufacturing the active matrix substrate 100B will be described. 4A to 4D are schematic cross-sectional views for explaining a method of manufacturing the active matrix substrate 100B, in the vicinity of the TFT 10A in FIG. 3A and the gate terminal portion in FIG. The cross-sectional structure near 12t is also shown.
　まず、図４（ａ）に示すように、基板（例えばガラス基板）１１を用意し、基板１１上に、ゲートメタル膜を形成し、それをパターニングすることによって、ゲートメタル層１２を形成する。ゲートメタル層１２は、ゲート電極１２ｇ、ゲート配線および補助容量バスライン（ＣＳバスライン）、ゲート端子部１２ｔを含む。補助容量バスライン（不図示）は、補助容量対向電極２２ａに接続され、補助容量対向電圧を供給する。ゲートメタル層１２は、種々の公知の導電膜を用いて公知の方法で形成され得る。ゲートメタル層１２は、例えば、ＭｏＮｂ膜／Ａｌ膜の積層膜（Ａｌ膜が下層）で形成される。ＭｏＮｂ膜／Ａｌ膜の厚さは例えば約２０ｎｍ/約５０ｎｍ～約２００ｎｍ/約３００ｎｍである。ゲートメタル層１２は、例えば、Ａｌ膜、Ｃｕ膜、Ｔａ膜またはＴａＮ膜から形成されてもよい。 First, as shown in FIG. 4A, a substrate (for example, a glass substrate) 11 is prepared, a gate metal film is formed on the substrate 11, and a gate metal layer 12 is formed by patterning the gate metal film. The gate metal layer 12 includes a gate electrode 12g, a gate wiring, an auxiliary capacitance bus line (CS bus line), and a gate terminal portion 12t. A storage capacitor bus line (not shown) is connected to the storage capacitor counter electrode 22a and supplies a storage capacitor counter voltage. The gate metal layer 12 can be formed by a known method using various known conductive films. The gate metal layer 12 is formed of, for example, a MoNb film / Al film laminated film (Al film is a lower layer). The thickness of the MoNb film / Al film is, for example, about 20 nm / about 50 nm to about 200 nm / about 300 nm. The gate metal layer 12 may be formed of, for example, an Al film, a Cu film, a Ta film, or a TaN film.
　続いて、ゲートメタル層１２を覆うように、ゲート絶縁層１３を形成する。ゲート絶縁層１３は、例えば、厚さが約１００ｎｍ～約６００ｎｍの窒化シリコン（ＳｉＮx）、酸化シリコン（ＳｉＯ2）、または、これらの積層膜から形成される。 Subsequently, a gate insulating layer 13 is formed so as to cover the gate metal layer 12. The gate insulating layer 13 is formed from, for example, silicon nitride (SiN x ), silicon oxide (SiO 2 ), or a stacked film thereof having a thickness of about 100 nm to about 600 nm.
　ゲート絶縁層１３上に、半導体層１４を形成する。半導体層１４は、例えば、厚さが約２０ｎｍ～約２００ｎｍのＩｎ－Ｇａ－Ｚｎ－Ｏ系半導体（ＩＧＺＯ系半導体）層である。半導体層１４として、ＩＧＺＯ系半導体層以外の酸化物半導体層であってもよいし、多結晶シリコン層など他の公知の半導体層であってもよい。 A semiconductor layer 14 is formed on the gate insulating layer 13. The semiconductor layer 14 is, for example, an In—Ga—Zn—O based semiconductor (IGZO based semiconductor) layer having a thickness of about 20 nm to about 200 nm. The semiconductor layer 14 may be an oxide semiconductor layer other than the IGZO-based semiconductor layer, or may be another known semiconductor layer such as a polycrystalline silicon layer.
　次に、半導体層１４を覆うようにエッチストップ層１５を形成する。エッチストップ層１５は、ソースコンタクトホール１５ａおよびドレインコンタクトホール１５ｂ（図１参照）を有している。エッチストップ層１５を形成する際に、ゲート端子部１２ｔを露出するように、エッチングによって、ゲート絶縁層１３に貫通孔を形成する。エッチストップ層１５は、後の、ソース電極１６Ｓおよびドレイン電極１６Ｄを形成するためのエッチング工程において、半導体層１４を保護する。 Next, an etch stop layer 15 is formed so as to cover the semiconductor layer 14. The etch stop layer 15 has a source contact hole 15a and a drain contact hole 15b (see FIG. 1). When the etch stop layer 15 is formed, a through hole is formed in the gate insulating layer 13 by etching so that the gate terminal portion 12t is exposed. The etch stop layer 15 protects the semiconductor layer 14 in an etching process for forming the source electrode 16S and the drain electrode 16D later.
　次に、図４（ｂ）に示すように、ソースメタル層１６を形成する。ソースメタル層１６は、ソース電極１６Ｓ、ドレイン電極１６Ｄ、ソースバスラインおよびソース端子部１６ｔ（図１参照）を含む。ソース電極１６Ｓおよびドレイン電極１６Ｄは、それぞれ、例えば、ＭｏＮ層１６Ｓａ／Ａｌ層１６Ｓｂ／ＭｏＮ層１６ＳｃおよびＭｏＮ層１６Ｄａ／Ａｌ層１６Ｄｂ／ＭｏＮ層１６Ｄｃの積層体から形成されている。もちろん、ソースメタル層１６は、他の公知の導電膜を用いて形成され得る。このようにして、半導体層１４上にエッチストップ層１５を有するＴＦＴ１０Ａが得られる。 Next, as shown in FIG. 4B, the source metal layer 16 is formed. The source metal layer 16 includes a source electrode 16S, a drain electrode 16D, a source bus line, and a source terminal portion 16t (see FIG. 1). The source electrode 16S and the drain electrode 16D are each formed, for example, from a laminate of a MoN layer 16Sa / Al layer 16Sb / MoN layer 16Sc and a MoN layer 16Da / Al layer 16Db / MoN layer 16Dc. Of course, the source metal layer 16 can be formed using another known conductive film. In this way, the TFT 10A having the etch stop layer 15 on the semiconductor layer 14 is obtained.
　次に、ＴＦＴ１０Ａを覆う第１層間絶縁層１７を形成する。第１層間絶縁層１７は、典型的には、無機絶縁層であって、例えば、厚さが約５０ｎｍ～約５００ｎｍの窒化シリコン（ＳｉＮx）、酸化シリコン（ＳｉＯ2）、または、これらの積層膜から形成される。 Next, a first interlayer insulating layer 17 covering the TFT 10A is formed. The first interlayer insulating layer 17 is typically an inorganic insulating layer, for example, silicon nitride (SiN x ) having a thickness of about 50 nm to about 500 nm, silicon oxide (SiO 2 ), or a laminate thereof. Formed from a film.
　さらに、第１層間絶縁層１７の上に、第２層間絶縁層１９を形成する。第２層間絶縁層１９は例えば、厚さが約１０００ｎｍ～約５０００ｎｍの透明樹脂層である。透明樹脂層１９は、基板１１の上に平坦な表面を形成する。また、透明樹脂層１９は、一般的な無機絶縁層に比べて、厚い膜を容易に形成でき、且つ、誘電率が低いので、透明樹脂層１９の上に形成される電極（例えば画素電極）と、透明樹脂層１９の下に形成されている電極や配線（例えば、ゲートバスライン１２やソースバスライン１６）との間の寄生容量を小さくできるという利点を有している。第１層間絶縁層１７（およびエッチストップ層１５、ゲート絶縁層１３）には、図１に示した第１コンタクトホール（画素電極用）１７ａ、第２コンタクトホール（ゲート用）１７ｂおよび第３コンタクトホール（ソース用）１７ｃが形成されている。また、第１透明導電層２２の一部２２ａを補助容量対向電極２２ａとして用いる場合には、補助容量対向電極２２ａを補助容量配線（不図示）と接続するためのコンタクトホールが第１層間絶縁層１７、エッチストップ層１５およびゲート絶縁層１３に形成されている。図４（ｂ）に示した工程では、第２層間絶縁層１９の、上記のコンタクトホールに対応する箇所に貫通孔（下層を露出させる孔）が形成される。第２層間絶縁層１９は例えばポジ型感光性樹脂で形成され、上記貫通孔はフォトリソグラフィ工程で形成される。 Further, a second interlayer insulating layer 19 is formed on the first interlayer insulating layer 17. The second interlayer insulating layer 19 is, for example, a transparent resin layer having a thickness of about 1000 nm to about 5000 nm. The transparent resin layer 19 forms a flat surface on the substrate 11. Further, since the transparent resin layer 19 can easily form a thick film and has a low dielectric constant as compared with a general inorganic insulating layer, an electrode (for example, a pixel electrode) formed on the transparent resin layer 19. And the parasitic capacitance between the electrode and the wiring (for example, the gate bus line 12 and the source bus line 16) formed under the transparent resin layer 19 can be reduced. In the first interlayer insulating layer 17 (and the etch stop layer 15 and the gate insulating layer 13), the first contact hole (for pixel electrode) 17a, the second contact hole (for gate) 17b and the third contact shown in FIG. A hole (for source) 17c is formed. When a part 22a of the first transparent conductive layer 22 is used as the auxiliary capacitor counter electrode 22a, a contact hole for connecting the auxiliary capacitor counter electrode 22a to the auxiliary capacitor wiring (not shown) is provided in the first interlayer insulating layer. 17, formed on the etch stop layer 15 and the gate insulating layer 13. In the step shown in FIG. 4B, a through hole (a hole exposing the lower layer) is formed in the second interlayer insulating layer 19 at a position corresponding to the contact hole. The second interlayer insulating layer 19 is formed of, for example, a positive photosensitive resin, and the through hole is formed by a photolithography process.
　次に、図４（ｃ）に示すように、第１層間絶縁層１７を貫通するコントタクトホール１７ａと、第１層間絶縁層１７、エッチストップ層１５およびゲート絶縁層１３を貫通するコントタクトホール１７ｂとを形成する。このときに、必要に応じて、補助容量対向電極２２ａを補助容量配線（不図示）と接続するためのコンタクトホールも形成する。 Next, as shown in FIG. 4C, a contact hole 17 a that penetrates the first interlayer insulating layer 17 and a contact hole that penetrates the first interlayer insulating layer 17, the etch stop layer 15, and the gate insulating layer 13. 17b. At this time, a contact hole for connecting the storage capacitor counter electrode 22a to the storage capacitor wiring (not shown) is also formed as necessary.
　その後、第２層間絶縁層１９上に、第１透明導電層２２を形成する。例えば、厚さが約４０ｎｍ～約１５０ｎｍのＩＴＯ膜をスパッタリング法（条件：例えば、Ａｒ／Ｏ2：３００ｓｃｃｍ／１ｓｃｃｍ、圧力：０．６Ｐａ、ＤＣ電力：２．５ｋＷ）で形成する。得られたＩＴＯ膜をパターニングすることによって、シールド電極または補助容量対向電極２２ａ、第１コンタクト電極２２ｃおよび第１透明端子電極２２ｔを含む第１透明導電層２２が得られる。 Thereafter, the first transparent conductive layer 22 is formed on the second interlayer insulating layer 19. For example, an ITO film having a thickness of about 40 nm to about 150 nm is formed by a sputtering method (conditions: for example, Ar / O 2 : 300 sccm / 1 sccm, pressure: 0.6 Pa, DC power: 2.5 kW). By patterning the obtained ITO film, the first transparent conductive layer 22 including the shield electrode or auxiliary capacitance counter electrode 22a, the first contact electrode 22c, and the first transparent terminal electrode 22t is obtained.
　次に、図４（ｄ）に示すように、第１透明導電層２２の上に、積層体２３Ｓ２を形成する。 Next, as illustrated in FIG. 4D, a stacked body 23 </ b> S <b> 2 is formed on the first transparent conductive layer 22.
　例えば、第１透明導電層２２の上に、酸化シリコン層２３ｄ２（条件：例えば、ＳｉＨ4／Ｎ2Ｏ：５０～３００／１０００～７０００ｓｃｃｍ、圧力：１００～３００Ｐａ、ＲＦ電力：４００～３０００Ｗ）、窒化シリコン層２３ｂ２（条件：例えば、ＳｉＨ4／ＮＨ3／Ｎ2：１００～５００／１００～１０００／１０００～６０００ｓｃｃｍ、圧力：１００～３００Ｐａ、ＲＦ電力：４００～４０００Ｗ）、窒化シリコン層２３ａ２（条件：例えば、ＳｉＨ4／ＮＨ3／Ｎ2：１００～５００／１００～１０００／１０００～６０００ｓｃｃｍ、圧力：１００～３００Ｐａ、ＲＦ電力：４００～４０００Ｗ）、窒化シリコン層２３ｃ２（条件：ＳｉＨ４／ＮＨ3／Ｎ2：１００～５００／１００～１０００／１０００～６０００ｓｃｃｍ、圧力：１００～３００Ｐａ、ＲＦ電力：２００～２０００Ｗ）および酸化シリコン層２３ｅ２（条件：えば、ＳｉＨ4／Ｎ2Ｏ：５０～３００／１０００～７０００ｓｃｃｍ、圧力：１００～３００Ｐａ、ＲＦ電力：４００～３０００Ｗ）をこの順で形成する。各層の屈折率および厚さは、以下の通りである。また、図９を参照して説明したように、それぞれの膜を単独でシリコンウエファ１上に形成し、膜ストレス計を用いて測定した内部応力の結果を併せて示す。なお各層の内部応力の大きさは膜厚に依存しない。 For example, on the first transparent conductive layer 22, a silicon oxide layer 23d2 (conditions: for example, SiH 4 / N 2 O: 50 to 300/1000 to 7000 sccm, pressure: 100 to 300 Pa, RF power: 400 to 3000 W), Silicon nitride layer 23b2 (conditions: for example, SiH 4 / NH 3 / N 2 : 100 to 500/100 to 1000/1000 to 6000 sccm, pressure: 100 to 300 Pa, RF power: 400 to 4000 W), silicon nitride layer 23a2 (conditions : For example, SiH 4 / NH 3 / N 2 : 100 to 500/100 to 1000/1000 to 6000 sccm, pressure: 100 to 300 Pa, RF power: 400 to 4000 W, silicon nitride layer 23c2 (condition: SiH 4 / NH 3 / N 2: 100 ~ 500/ 100 ~ 1000/1000 ~ 6000sc m, the pressure: 100 ~ 300 Pa, RF power: 200 ~ 2000 W) and a silicon oxide layer 23e2 (Conditions: In example, SiH 4 / N 2 O: 50 ~ 300/1000 ~ 7000sccm, pressure: 100 ~ 300 Pa, RF power: 400 ˜3000 W) in this order. The refractive index and thickness of each layer are as follows. Further, as described with reference to FIG. 9, each film is formed on the silicon wafer 1 alone, and the result of internal stress measured using a film stress meter is also shown. Note that the magnitude of the internal stress of each layer does not depend on the film thickness.
　酸化シリコン層２３ｄ２および２３ｅ２は、例えば、屈折率が１．４６、厚さが２０ｎｍで、圧縮応力は約５０ＭＰａである。 For example, the silicon oxide layers 23d2 and 23e2 have a refractive index of 1.46, a thickness of 20 nm, and a compressive stress of about 50 MPa.
　窒化シリコン層２３ｂ２および２３ｃ２は、例えば、屈折率が１．８５、厚さが２０ｎｍで、圧縮応力が１５０ＭＰａである。 The silicon nitride layers 23b2 and 23c2 have, for example, a refractive index of 1.85, a thickness of 20 nm, and a compressive stress of 150 MPa.
　窒化シリコン層２３ａ２は、例えば、屈折率が１．７５、厚さが２００ｎｍで、引張応力は２００ＭＰａである。 For example, the silicon nitride layer 23a2 has a refractive index of 1.75, a thickness of 200 nm, and a tensile stress of 200 MPa.
　次に、第２透明導電層２４を形成する。第１透明導電層２２と同様に、例えば、厚さが約４０ｎｍ～約１５０ｎｍのＩＴＯ膜をスパッタリング法で形成する。得られたＩＴＯ膜をパターニングすることによって、画素電極２４ｐ、第２コンタクト電極２４ｃおよび第２透明端子電極２４ｔを含む第２透明導電層２４が得られる。 Next, the second transparent conductive layer 24 is formed. Similar to the first transparent conductive layer 22, for example, an ITO film having a thickness of about 40 nm to about 150 nm is formed by a sputtering method. By patterning the obtained ITO film, the second transparent conductive layer 24 including the pixel electrode 24p, the second contact electrode 24c, and the second transparent terminal electrode 24t is obtained.
　このようにして、図３に示したアクティブマトリクス基板１００Ｂが得られる。なお、アクティブマトリクス基板１００Ａも、上記酸化シリコン層２３ｄ２および２３ｅ２を省略することによって、同様の方法で製造することができる。 In this way, the active matrix substrate 100B shown in FIG. 3 is obtained. The active matrix substrate 100A can also be manufactured by the same method by omitting the silicon oxide layers 23d2 and 23e2.
　次に、図５および図６を参照して、本発明の実施形態によるさらに他のアクティブマトリクス基板１００Ｃの構造を説明する。図５は、本発明の実施形態によるさらに他のアクティブマトリクス基板１００Ｃの模式的な平面図である。図６は、アクティブマトリクス基板１００Ｃの模式的な断面図であり、図６（ａ）は、図５中のＡ－Ａ’線に沿った断面を示し、図６（ｂ）は図５中のＢ－Ｂ’線に沿った断面を示している。 Next, the structure of still another active matrix substrate 100C according to an embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a schematic plan view of still another active matrix substrate 100C according to the embodiment of the present invention. 6 is a schematic cross-sectional view of the active matrix substrate 100C. FIG. 6A shows a cross-section along the line AA ′ in FIG. 5, and FIG. 6B shows the cross-section in FIG. A cross section along the line BB ′ is shown.
　上述したアクティブマトリクス基板１００Ｂの積層体２３Ｓ２は、５つの無機絶縁層を有しているが、第４無機絶縁層２３ｄ２および第５無機絶縁層２３ｅ２のいずれか一方を省略することができる。アクティブマトリクス基板１００Ｃが有する積層体２３Ｓ３は、アクティブマトリクス基板１００Ｂが有する積層体２３Ｓ２の第５無機絶縁層２３ｅ２を有しない。 The above-described stacked body 23S2 of the active matrix substrate 100B has five inorganic insulating layers, but one of the fourth inorganic insulating layer 23d2 and the fifth inorganic insulating layer 23e2 can be omitted. The stacked body 23S3 included in the active matrix substrate 100C does not include the fifth inorganic insulating layer 23e2 of the stacked body 23S2 included in the active matrix substrate 100B.
　すなわち、積層体２３Ｓ３は、引張応力を有する第１無機絶縁層２３ａ３と、第１無機絶縁層２３ａ３を挟むように形成され、圧縮応力を有する第２無機絶縁層２３ｂ３および第３無機絶縁層２３ｃ３とを有している。この部分の積層構造は、積層体２３Ｓ１と同じである。積層体２３Ｓ３は、さらに、第１透明導電層２２と第２無機絶縁層２３ｂ３との間に、すなわち第２無機絶縁層２３ｂ３の基板１１側に、第４無機絶縁層２３ｄ３を有している。積層体２３Ｓ３も、積層体２３Ｓ１および２３Ｓ２と同様に、全体として引張応力を有する。 That is, the laminated body 23S3 is formed so as to sandwich the first inorganic insulating layer 23a3 having tensile stress, the second inorganic insulating layer 23b3 and the third inorganic insulating layer 23c3 having compressive stress. have. The laminated structure of this portion is the same as that of the laminated body 23S1. The stacked body 23S3 further includes a fourth inorganic insulating layer 23d3 between the first transparent conductive layer 22 and the second inorganic insulating layer 23b3, that is, on the substrate 11 side of the second inorganic insulating layer 23b3. The laminated body 23S3 also has a tensile stress as a whole, like the laminated bodies 23S1 and 23S2.
　ここで、第１無機絶縁層２３ａ３は、例えば、屈折率が１．８０４以下の窒化シリコン層であり、第２無機絶縁層２３ｂ３および第３無機絶縁層２３ｃ３は、例えば、屈折率が１．８０５以上の窒化シリコン層である。また、第４無機絶縁層２３ｄ３は、屈折率が１．４以上１．６以下の酸化シリコン層である。 Here, the first inorganic insulating layer 23a3 is, for example, a silicon nitride layer having a refractive index of 1.804 or less, and the second inorganic insulating layer 23b3 and the third inorganic insulating layer 23c3 have, for example, a refractive index of 1.805. The above silicon nitride layer. The fourth inorganic insulating layer 23d3 is a silicon oxide layer having a refractive index of 1.4 or more and 1.6 or less.
　例えば、屈折率が１．８０５以上の窒化シリコン層２３ｂ３および２３ｃ３の厚さをそれぞれｔｈｂ３およびｔｈｃ３とし、屈折率が１．４以上１．６以下の酸化シリコン層２３ｄ３の厚さをそれぞれｔｈｄ３とし、屈折率が１．８０４以下の窒化シリコン層２３ａ３の厚さをｔｈａ３とすると、ｔｈａ３≧ｔｈｂ３＋ｔｈｃ３＋ｔｈｄ３の関係を満足することが好ましい。このとき、ｔｈｂ３、ｔｈｃ３、およびｔｈｄ３は、上記と同じ理由から、それぞれ独立に１００ｎｍ以下であることが好ましい。もちろん、厳密には、各層の応力の大きさは、各層の厚さだけでなく、各膜の構造（組成など）の影響を受けるので、上記の関係を有しない場合でも、積層体２３Ｓ３が全体として引張応力を有することがある。発明者の検討によると、上記の関係を満足すれば、積層体２３Ｓ３は、全体として、引張応力を有する。 For example, the thicknesses of the silicon nitride layers 23b3 and 23c3 having a refractive index of 1.805 or more are set to thb3 and thc3, respectively, and the thicknesses of the silicon oxide layers 23d3 having a refractive index of 1.4 to 1.6 are set to thd3, respectively. When the thickness of the silicon nitride layer 23a3 having a refractive index of 1.804 or less is tha3, it is preferable to satisfy the relationship tha3 ≧ thb3 + thc3 + thd3. At this time, it is preferable that thb3, thc3, and thd3 are independently 100 nm or less for the same reason as described above. Of course, strictly speaking, the magnitude of the stress of each layer is affected not only by the thickness of each layer but also by the structure (composition, etc.) of each film. May have tensile stress. According to the inventor's study, if the above relationship is satisfied, the laminate 23S3 has a tensile stress as a whole.
　アクティブマトリクス基板１００Ｃも、ＴＦＴ１０Ｃを覆う有機絶縁層１９をさらに有しており、有機絶縁層１９の一部は、積層体２３Ｓ３の一部と直接接触している。従って、積層体２３Ｓ３は、アクティブマトリクス基板１００Ａの積層体２３Ｓ１およびアクティブマトリクス基板１００Ｂの積層体２３Ｓ２と同様に、その下面が接する第１透明導電層２２および有機絶縁層１９との密着性に優れるので、剥離することが抑制される。 The active matrix substrate 100C also has an organic insulating layer 19 that covers the TFT 10C, and a part of the organic insulating layer 19 is in direct contact with a part of the stacked body 23S3. Accordingly, the laminated body 23S3 is excellent in adhesion to the first transparent conductive layer 22 and the organic insulating layer 19 that are in contact with the lower surface, like the laminated body 23S1 of the active matrix substrate 100A and the laminated body 23S2 of the active matrix substrate 100B. , Peeling is suppressed.
　積層体２３Ｓ３を有するアクティブマトリクス基板１００Ｃは、積層体２３Ｓ１を有するアクティブマトリクス基板１００Ａに比べて、透明導電層の還元反応をより効果的に抑制できるという利点がある。 The active matrix substrate 100C having the stacked body 23S3 has an advantage that the reduction reaction of the transparent conductive layer can be more effectively suppressed than the active matrix substrate 100A having the stacked body 23S1.
　上記のアクティブマトリクス基板１００Ａおよび１００Ｂが有するＴＦＴ１０Ａは、エッチストップ型のＴＦＴであるのに対し、アクティブマトリクス基板１００Ｃが有するＴＦＴ１０Ｃは、チャネルエッチ型のＴＦＴである。 The TFT 10A included in the active matrix substrates 100A and 100B is an etch stop type TFT, whereas the TFT 10C included in the active matrix substrate 100C is a channel etch type TFT.
　次に、図７（ａ）～（ｄ）を参照して、アクティブマトリクス基板１００Ｃの製造方法を説明する。図７（ａ）～（ｄ）は、アクティブマトリクス基板１００Ｃの製造方法を説明するための模式的な断面図であり、図６（ａ）のＴＦＴ１０Ｃの近傍および図６（ｂ）のゲート端子部１２ｔ付近の断面構造を併せて示している。以下の説明では、各構成要素を形成する材料や厚さ等は、図４（ａ）～（ｄ）を参照して先に説明したのと同じあってよいので、省略する。 Next, a method for manufacturing the active matrix substrate 100C will be described with reference to FIGS. 7 (a) to (d). FIGS. 7A to 7D are schematic cross-sectional views for explaining a method of manufacturing the active matrix substrate 100C, in the vicinity of the TFT 10C of FIG. 6A and the gate terminal portion of FIG. 6B. The cross-sectional structure near 12t is also shown. In the following description, the material, thickness, and the like forming each component may be the same as described above with reference to FIGS.
　まず、図７（ａ）に示すように、基板１１を用意し、基板１１上に、ゲートメタル膜を形成し、それをパターニングすることによって、ゲートメタル層１２を形成する。ゲートメタル層１２は、ゲート電極１２ｇ、ゲート配線および補助容量バスライン（ＣＳバスライン）、ゲート端子部１２ｔを含む。 First, as shown in FIG. 7A, a substrate 11 is prepared, a gate metal film is formed on the substrate 11, and a gate metal layer 12 is formed by patterning the gate metal film. The gate metal layer 12 includes a gate electrode 12g, a gate wiring, an auxiliary capacitance bus line (CS bus line), and a gate terminal portion 12t.
　続いて、ゲートメタル層１２を覆うように、ゲート絶縁層１３を形成し、ゲート絶縁層１３上に、半導体層１４を形成する。 Subsequently, a gate insulating layer 13 is formed so as to cover the gate metal layer 12, and a semiconductor layer 14 is formed on the gate insulating layer 13.
　次に、ソース電極１６Ｓおよびドレイン電極１６Ｄを含むソースメタル層１６を形成する。 Next, the source metal layer 16 including the source electrode 16S and the drain electrode 16D is formed.
　次に、ＴＦＴ１０Ｃを覆う第１層間絶縁層１７を形成する。第１層間絶縁層１７（およびゲート絶縁層１３）には、図５に示した第１コンタクトホール（画素電極用）１７ａ、第２コンタクトホール（ゲート用）１７ｂおよび第３コンタクトホール（ソース用）１７ｃが形成されている。また、第１透明導電層２２の一部２２ａを補助容量対向電極２２ａとして用いる場合には、補助容量対向電極２２ａを補助容量配線（不図示）と接続するためのコンタクトホールが第１層間絶縁層１７およびゲート絶縁層１３に形成されている。図７（ｂ）に示した工程では、第２層間絶縁層１９の、上記のコンタクトホールに対応する箇所に貫通孔（下層を露出させる孔）が形成される。 Next, a first interlayer insulating layer 17 covering the TFT 10C is formed. The first interlayer insulating layer 17 (and the gate insulating layer 13) includes a first contact hole (for pixel electrode) 17a, a second contact hole (for gate) 17b, and a third contact hole (for source) shown in FIG. 17c is formed. When a part 22a of the first transparent conductive layer 22 is used as the auxiliary capacitor counter electrode 22a, a contact hole for connecting the auxiliary capacitor counter electrode 22a to the auxiliary capacitor wiring (not shown) is provided in the first interlayer insulating layer. 17 and the gate insulating layer 13. In the step shown in FIG. 7B, a through hole (a hole exposing the lower layer) is formed at a location corresponding to the contact hole in the second interlayer insulating layer 19.
　次に、図７（ｃ）に示すように、第１層間絶縁層１７を貫通するコントタクトホール１７ａおよび第１層間絶縁層１７およびゲート絶縁層１３を貫通するコントタクトホール１７ｂを形成する。このときに、必要に応じて、補助容量対向電極２２ａを補助容量配線（不図示）と接続するためのコンタクトホールも形成する。 Next, as shown in FIG. 7C, a contact hole 17a penetrating the first interlayer insulating layer 17 and a contact hole 17b penetrating the first interlayer insulating layer 17 and the gate insulating layer 13 are formed. At this time, a contact hole for connecting the storage capacitor counter electrode 22a to the storage capacitor wiring (not shown) is also formed as necessary.
　その後、第２層間絶縁層１９上に、第１透明導電層２２を形成する。ＩＴＯ膜をパターニングすることによって、シールド電極または補助容量対向電極２２ａ、第１コンタクト電極２２ｃおよび第１透明端子電極２２ｔを含む第１透明導電層２２が得られる。 Thereafter, the first transparent conductive layer 22 is formed on the second interlayer insulating layer 19. By patterning the ITO film, the first transparent conductive layer 22 including the shield electrode or auxiliary capacitance counter electrode 22a, the first contact electrode 22c, and the first transparent terminal electrode 22t is obtained.
　次に、図７（ｄ）に示すように、第１透明導電層２２の上に、積層体２３Ｓ３を形成する。積層体２３Ｓ３は、図４（ｄ）において、上記酸化シリコン層２３ｅ２を省略することによって、同様の方法で形成することができる。その後、第２透明導電層２４を形成する。ＩＴＯ膜をパターニングすることによって、画素電極２４ｐ、第２コンタクト電極２４ｃおよび第２透明端子電極２４ｔを含む第２透明導電層２４が得られる。このようにして、図５および図６に示したアクティブマトリクス基板１００Ｃが得られる。 Next, as illustrated in FIG. 7D, a stacked body 23 </ b> S <b> 3 is formed on the first transparent conductive layer 22. The stacked body 23S3 can be formed by a similar method by omitting the silicon oxide layer 23e2 in FIG. Thereafter, the second transparent conductive layer 24 is formed. By patterning the ITO film, the second transparent conductive layer 24 including the pixel electrode 24p, the second contact electrode 24c, and the second transparent terminal electrode 24t is obtained. In this way, the active matrix substrate 100C shown in FIGS. 5 and 6 is obtained.
　ここでは、チャネルエッチ型ＴＦＴを備えるアクティブマトリクス基板１００Ｃを例示したが、上述のエッチストップ型アクティブマトリクス基板に適用することもできるし、逆に、チャネルエッチ型ＴＦＴを備えるアクティブマトリクス基板に上述の積層体２３Ｓ１、２３Ｓ２を適用することもできる。 Here, the active matrix substrate 100C including the channel etch type TFT is exemplified, but the active matrix substrate 100C including the channel etch type TFT can be applied to the above-described etch stop type active matrix substrate. The bodies 23S1 and 23S2 can also be applied.
　また、上記の実施形態では、２層電極構造を有するＶＡモードの液晶表示装置に用いられるアクティブマトリクス基板を例示したが、これに限られず、本発明の実施形態は、種々のモードの液晶表示装置に用いられるアクティブマトリクス基板に適用される。例えば、上述のＦＦＳモードの液晶表示装置に用いられるアクティブマトリクス基板に適用する場合、第１透明導電層２２は共通電極であり、第２透明導電層２４は、複数のスリットを有する画素電極である。 In the above embodiment, the active matrix substrate used in the VA mode liquid crystal display device having the two-layer electrode structure is exemplified. However, the present invention is not limited to this, and the embodiment of the present invention is not limited to the liquid crystal display device in various modes. It is applied to an active matrix substrate used in the above. For example, when applied to an active matrix substrate used in the above-described FFS mode liquid crystal display device, the first transparent conductive layer 22 is a common electrode, and the second transparent conductive layer 24 is a pixel electrode having a plurality of slits. .
　本発明の実施形態は、アクティブマトリクス基板、特に、液晶表示装置に好適に用いられるアクティブマトリクス基板に適用される。 The embodiment of the present invention is applied to an active matrix substrate, particularly an active matrix substrate suitably used for a liquid crystal display device.
　１０Ａ、１０Ｃ　薄膜トランジスタ（ＴＦＴ）
　１１　　　基板
　１２　　　ゲートメタル層（ゲートバスライン）
　１２ｇ　　ゲート電極
　１２ｔ　　ゲート端子部
　１３　　　ゲート絶縁層
　１４　　　半導体層
　１５　　　エッチストップ層
　１５ａ、１５ｂ　コンタクトホール（ソース、ドレイン用）
　１６　　　ソースメタル層（ソースバスライン）
　１６Ｓ　　ソース電極
　１６Ｄ　　ドレイン電極
　１６ｔ　　ソース端子部
　１７　　　第１層間絶縁層（無機絶縁層）
　１７ａ　　第１コンタクトホール（画素電極用）
　１７ｂ　　第２コンタクトホール（ゲート用）
　１７ｃ　　第３コンタクトホール（ソース用）
　１９　　　第２層間絶縁層（透明樹脂層）
　２２　　　第１透明導電層
　２２ａ　　シールド電極または補助容量対向電極
　２２ｃ　　第１コンタクト電極
　２２ｔ　　第１透明端子電極
　２３Ｐ　　第３層間絶縁層
　２３Ｓ１、２３Ｓ２、２３Ｓ３　無機絶縁層積層体
　２３ａ１、２３ｂ１、２３ｃ１　無機絶縁層
　２３ａ２、２３ｂ２、２３ｃ２、２３ｄ２、２３ｅ２　無機絶縁層
　２３ａ３、２３ｂ３、２３ｃ３、２３ｄ３　無機絶縁層
　２４　　　第２透明導電層
　２４ｃ　　第２コンタクト電極
　２４ｐ　　画素電極
　２４ｔ　　第２透明端子電極
　１００、１００Ａ、１００Ｂ、１００Ｃ　アクティブマトリクス基板 10A, 10C Thin film transistor (TFT)
11 Substrate 12 Gate metal layer (gate bus line)
12g Gate electrode 12t Gate terminal part 13 Gate insulating layer 14 Semiconductor layer 15 Etch stop layer 15a, 15b Contact hole (for source and drain)
16 Source metal layer (source bus line)
16S source electrode 16D drain electrode 16t source terminal portion 17 first interlayer insulating layer (inorganic insulating layer)
17a First contact hole (for pixel electrode)
17b Second contact hole (for gate)
17c Third contact hole (for source)
19 Second interlayer insulating layer (transparent resin layer)
22 1st transparent conductive layer 22a Shield electrode or auxiliary capacity counter electrode 22c 1st contact electrode 22t 1st transparent terminal electrode 23P 3rd interlayer insulation layer 23S1, 23S2, 23S3 Inorganic insulation layer laminated body 23a1, 23b1, 23c1 Inorganic insulation layer 23a2 , 23b2, 23c2, 23d2, 23e2 Inorganic insulating layer 23a3, 23b3, 23c3, 23d3 Inorganic insulating layer 24 Second transparent conductive layer 24c Second contact electrode 24p Pixel electrode 24t Second transparent terminal electrode 100, 100A, 100B, 100C Active matrix substrate

Claims (13)

  1. 　基板と、
    　前記基板に支持され、半導体層、ゲート電極、ソース電極およびドレイン電極を有する薄膜トランジスタと、
    　少なくとも一方が前記薄膜トランジスタの前記ドレイン電極と電気的に接続された、第１透明導電層および第２透明導電層と、
    　前記第１透明導電層と前記第２透明導電層との間に形成された、無機絶縁層の積層体とを有し、
    　前記積層体は、引張応力を有する第１無機絶縁層と、前記第１無機絶縁層を挟むように形成され、圧縮応力を有する第２および第３無機絶縁層とを有し、且つ、前記積層体は全体として引張応力を有する、アクティブマトリクス基板。     A substrate,
    A thin film transistor supported by the substrate and having a semiconductor layer, a gate electrode, a source electrode and a drain electrode;
    A first transparent conductive layer and a second transparent conductive layer, at least one of which is electrically connected to the drain electrode of the thin film transistor;
    A laminate of inorganic insulating layers formed between the first transparent conductive layer and the second transparent conductive layer;
    The laminate includes a first inorganic insulating layer having a tensile stress, and second and third inorganic insulating layers having a compressive stress formed so as to sandwich the first inorganic insulating layer. An active matrix substrate whose body has tensile stress as a whole.
  2. 　前記第１無機絶縁層は、屈折率が１．８０４以下の窒化シリコン層である、請求項１に記載のアクティブマトリクス基板。 The active matrix substrate according to claim 1, wherein the first inorganic insulating layer is a silicon nitride layer having a refractive index of 1.804 or less.
  3. 　前記第２無機絶縁層および前記第３無機絶縁層は、屈折率が１．８０５以上の窒化シリコン層である、請求項１または２に記載のアクティブマトリクス基板。 The active matrix substrate according to claim 1 or 2, wherein the second inorganic insulating layer and the third inorganic insulating layer are silicon nitride layers having a refractive index of 1.805 or more.
  4. 　前記第１透明導電層は前記第２透明導電層よりも前記基板の近くに形成されており、前記第２無機絶縁層は前記第３無機絶縁層よりも前記基板の近くに形成されており、
    　前記積層体は、前記第１透明導電層と前記第２無機絶縁層との間に第４無機絶縁層をさらに有する、請求項１から３のいずれかに記載のアクティブマトリクス基板。     The first transparent conductive layer is formed closer to the substrate than the second transparent conductive layer, and the second inorganic insulating layer is formed closer to the substrate than the third inorganic insulating layer;
    4. The active matrix substrate according to claim 1, wherein the stacked body further includes a fourth inorganic insulating layer between the first transparent conductive layer and the second inorganic insulating layer. 5.
  5. 　前記第４無機絶縁層は、屈折率が１．４以上１．６以下の酸化シリコン層である、請求項４に記載のアクティブマトリクス基板。 The active matrix substrate according to claim 4, wherein the fourth inorganic insulating layer is a silicon oxide layer having a refractive index of 1.4 to 1.6.
  6. 　前記積層体は、前記第２透明導電層と前記第３無機絶縁層との間に第５無機絶縁層をさらに有する、請求項４または５に記載のアクティブマトリクス基板。 6. The active matrix substrate according to claim 4, wherein the laminate further includes a fifth inorganic insulating layer between the second transparent conductive layer and the third inorganic insulating layer.
  7. 　前記第５無機絶縁層は、屈折率が１．４以上１．６以下の酸化シリコン層である、請求項６に記載のアクティブマトリクス基板。 The active matrix substrate according to claim 6, wherein the fifth inorganic insulating layer is a silicon oxide layer having a refractive index of 1.4 to 1.6.
  8. 　前記第１透明導電層および前記第２透明導電層は、ＩＴＯ層またはＩＺＯ層である、請求項１から７のいずれかに記載のアクティブマトリクス基板。 The active matrix substrate according to any one of claims 1 to 7, wherein the first transparent conductive layer and the second transparent conductive layer are ITO layers or IZO layers.
  9. 　前記半導体層は、酸化物半導体層である、請求項１から８のいずれかに記載のアクティブマトリクス基板。 The active matrix substrate according to any one of claims 1 to 8, wherein the semiconductor layer is an oxide semiconductor layer.
  10. 　前記第１透明導電層は、電気的にフローティング状態にあり、前記第２透明導電層は、画素電極である、請求項１から９のいずれかに記載のアクティブマトリクス基板。 The active matrix substrate according to any one of claims 1 to 9, wherein the first transparent conductive layer is in an electrically floating state, and the second transparent conductive layer is a pixel electrode.
  11. 　前記第１透明導電層は、補助容量対向電極であり、前記第２透明導電層は、画素電極である、請求項１から９のいずれかに記載のアクティブマトリクス基板。 10. The active matrix substrate according to claim 1, wherein the first transparent conductive layer is a storage capacitor counter electrode, and the second transparent conductive layer is a pixel electrode.
  12. 　前記第１透明導電層は、共通電極であり、前記第２透明導電層は、複数のスリットを有する画素電極である、請求項１から９のいずれかに記載のアクティブマトリクス基板。 10. The active matrix substrate according to claim 1, wherein the first transparent conductive layer is a common electrode, and the second transparent conductive layer is a pixel electrode having a plurality of slits.
  13. 　前記薄膜トランジスタを覆う有機絶縁層を有し、前記有機絶縁層の一部は、前記積層体の一部と直接接触している、請求項１から１２のいずれかに記載のアクティブマトリクス基板。 The active matrix substrate according to any one of claims 1 to 12, further comprising an organic insulating layer covering the thin film transistor, wherein a part of the organic insulating layer is in direct contact with a part of the stacked body.
PCT/JP2012/082784 2011-12-28 2012-12-18 Active matrix substrate WO2013099697A1 (en)

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TWI519876B (en) 2016-02-01

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