WO2013090472A1 - Procédé de recuit et dispositifs fabriqués ainsi - Google Patents

Procédé de recuit et dispositifs fabriqués ainsi Download PDF

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Publication number
WO2013090472A1
WO2013090472A1 PCT/US2012/069314 US2012069314W WO2013090472A1 WO 2013090472 A1 WO2013090472 A1 WO 2013090472A1 US 2012069314 W US2012069314 W US 2012069314W WO 2013090472 A1 WO2013090472 A1 WO 2013090472A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor material
high pressure
defects
gan
semiconductor
Prior art date
Application number
PCT/US2012/069314
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English (en)
Inventor
Chien-Min Sung
Original Assignee
Ritedia Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Publication of WO2013090472A1 publication Critical patent/WO2013090472A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3245—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering of AIIIBV compounds

Definitions

  • One problem that has been difficult to overcome for many types of semiconductor device relates to dislocations and other lattice defects that arise in a semiconductor during the manufacturing process. Such defects can hinder the performance of many
  • LEDs are made via a heteroepitaxial process of forming a GaN material on a single crystal AI2O3 substrate (sapphire).
  • Sapphire wafers are difficult and expensive to process due to their hardness and high melting temperature.
  • Si wafers are much easier and less costly to work with, however such wafers are not used for many LEDs due to the large crystal lattice mismatch between GaN and Si.
  • GaN deposited by metal organic chemical vapor deposition (MOCVD) on sapphire contains substantial defects, on the order of one billion per square centimeter in some cases.
  • the defect separation across such a material is about 1-2 um.
  • the wavelength of the blue light is approximately 0.4 - 0.47 ⁇ (400 to 470 nm).
  • the blue light can move through the GaN layer with a fairly low chance of collision with the defects, so in some cases the emission efficacy of the LED can still be high.
  • Defects such as dislocation can move upon heating, however, as the LED is subject to high temperature degradation. In some cases it is estimated that light emission can decay by about 18% in 6000 hours. While this rate of decay may be acceptable for some general purposes, it may not be acceptable for purposes that require a more stable illuminating brightness or color temperature (warmness).
  • a method of decreasing defects in a semiconductor material can include placing a semiconductor material into a high pressure device, applying high presser to the semiconductor material via the high pressure device, and heating the semiconductor material to a temperature that is below a thermal stability limit of the semiconductor material lattice. The high pressure and temperature are maintained for a time sufficient to decrease crystal lattice defects in the semiconductor material as compared to the semiconductor material prior to high pressure treatment.
  • the semiconductor material is a semiconductor layer epitaxially grown on a support substrate.
  • the high pressure is a uniformly distributed pressure. In another aspect, the uniformly distributed pressure is by hot isostatic pressing. In yet another aspect, the high pressure is from about 0.1 GPa to about 6 GPa. In a further aspect, the high pressure is from about 1 GPa to about 5 GPa. Additionally, in one aspect the temperature is at least 100° C below the thermal stability limit of the semiconductor material lattice.
  • the defects in the semiconductor material lattice are reduced by at least 50% as compared to the semiconductor material prior to high pressure treatment. In another aspect, the defects in the semiconductor material lattice are reduced by at least 90% as compared to the semiconductor material prior to high pressure treatment.
  • any semiconductor material that can be improved by high pressure processing is considered to be within the present scope.
  • Non-limiting examples of such materials include GaN, A1N, Si, GaP, GaAs, and the like, including and combinations thereof.
  • the semiconductor material is GaN.
  • the semiconductor material is GaN formed by MOCVD.
  • the semiconductor material is formed by MOCVD.
  • the semiconductor material is formed by a liquid crystallization process.
  • a semiconductor device can include a semiconductor material having been processed by high temperature heat treatment as is disclosed herein, wherein the semiconductor material has decreased crystal lattice defects as compared to the semiconductor material prior to high pressure treatment.
  • FIG. 1 is an image of a GaN on sapphire semiconductor in accordance with one embodiment of the present invention.
  • FIG. 2 is a cross-section view of the uniform distribution of high pressure across a semiconductor material in accordance with one embodiment of the present invention.
  • FIG. 3 is an image of untreated GaN on sapphire (A) and hot pressed GaN on sapphire (B) after etching in accordance with one embodiment of the present invention.
  • FIG. 4 shows x-ray diffraction data from untreated GaN on sapphire (A) and hot pressed GaN on sapphire (B) in accordance with one embodiment of the present invention.
  • vapor deposited refers to materials which are formed using vapor deposition techniques.
  • Vapor deposition refers to a process of forming or depositing materials on a substrate through the vapor phase. Vapor deposition processes can include any process such as, but not limited to, chemical vapor deposition (CVD) and physical vapor deposition (PVD). A wide variety of variations of each vapor deposition method can be performed by those skilled in the art.
  • vapor deposition methods include hot filament CVD, rf-CVD, laser CVD (LCVD), laser ablation, conformal diamond coating processes, metal-organic CVD (MOCVD), sputtering, thermal evaporation PVD, ionized metal PVD (IMPVD), electron beam PVD (EBPVD), reactive PVD, and the like.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • thermal stability limit refers to the temperature limit at which a semiconductor material begins to lose structural stability.
  • the thermal stability limit of a material is that material's melting point.
  • the term “substantially” refers to the complete or nearly complete extent or degree of an action, characteristic, property, state, structure, item, or result.
  • an object that is “substantially” enclosed would mean that the object is either completely enclosed or nearly completely enclosed.
  • the exact allowable degree of deviation from absolute completeness may in some cases depend on the specific context. However, generally speaking the nearness of completion will be so as to have the same overall result as if absolute and total completion were obtained.
  • the use of “substantially” is equally applicable when used in a negative connotation to refer to the complete or near complete lack of an action, characteristic, property, state, structure, item, or result.
  • compositions that is "substantially free of particles would either completely lack particles, or so nearly completely lack particles that the effect would be the same as if it completely lacked particles.
  • a composition that is "substantially free of" an ingredient or element may still actually contain such item as long as there is no measurable effect thereof.
  • the term "about” is used to provide flexibility to a numerical range endpoint by providing that a given value may be “a little above” or “a little below” the endpoint.
  • rate of decay of light emission can be greatly reduced. Additionally, such a reduction in defects can allow the LED to be operated at much higher operating temperatures, thus generating more intense light emissions for longer durations. For example, one industry standard is 350 mA for a 1 W LED. If the defect density of such an LED were reduced by on order of magnitude, with all else being equivalent, such an LED can be driven by 1 A to generate a light emission equivalent to a 3 W brightness.
  • crystal lattice dislocations and other defects can be particularly unstable under high pressure.
  • applying a high pressure to the semiconductor material can cause a mending of at least a portion of the dislocations or defects in the crystal lattice, thus reducing the dislocation density of the material.
  • heat can be applied to the semiconductor material along with the pressure to further facilitate the process.
  • the high pressure can be a uniformly distributed pressure.
  • the uniformly distributed pressure can be a pressure that is uniformly distributed across the entire or substantially the entire surface of the semiconductor surface being high pressure treated.
  • applying heat to the semiconductor material under such high pressure conditions can further facilitate the movement of dislocations from the lattice.
  • the dislocations may move from the lattice as a result of the pressure-induced reduction of the semiconductor material volume.
  • a dislocation is a perturbation in the crystal lattice and thus requires a higher material volume, compressing the volume with high pressure forces the dislocations to move, thus allowing correction of the defects.
  • FIG. lb shows a GaN 12 on sapphire 14 material wherein the GaN 12 has a thickness of 2.2 ⁇ . Following high pressure treatment (FIG. la), the thickness of the GaN layer has been compressed to 1.5 ⁇ .
  • GaN layer is due to the applied pressure moving the dislocations therefrom and more effectively orienting the atoms in the material as the lattice compresses. Additionally, in some cases such high pressure can facilitate the stabilization of the semiconductor lattice. As one example, GaN materials tend to sublimate at high temperatures, so the introduction of high pressure can limit the formation of vapors that cause disintegration of the lattice.
  • any type of pressure delivered to the semiconductor material that does not result in significant damage (e.g. cracking or breaking) to the material is considered to be within the present scope.
  • an evenly distributed or uniform stress across the semiconductor material may not cause significant damage as compared to a non-uniform or uneven pressure distribution.
  • Such stress can be defined as stress that is distributed across the surface of the semiconductor material in such a way as to minimize unequal forces that would crack or otherwise damage the semiconductor material.
  • pressure applied via a gas or a liquid medium will generally result in a uniform distribution of pressure across the surface of the semiconductor material.
  • the high pressure can be applied by hot isostatic pressing (HIP) using a liquid and or gas medium.
  • HIP hot isostatic pressing
  • a gas medium will exclusively be used as many liquids will boil at the temperatures utilized.
  • the high pressure can be applied by a uniaxial pressing technique. It is noted that HIP can be limited as to reaching very high pressures (e.g. 1 Kb) that is well below ultrahigh pressure (e.g. 5 GPa or 50Kb), and as such the temperature can be reduced to avoid disintegration of the semiconductor lattice.
  • Solid medium pressing may stress the semiconductor material in an uneven distribution, thus leading to damage. This may not be the case with certain solid media such as certain powders, however. Powders may allow for a more uniform pressure distribution in a high pressure system.
  • Non-limiting examples can include graphite powder, hexagonal boron nitride powder, molybdenum disulfide powder, talc powder, pyrophyllite powder, lime powder, dolomite powder, salt or the like.
  • the pressure treatment techniques disclosed herein can be utilized to decrease defects in semiconductor materials made from any known process, all of which are considered to be within the present scope.
  • Non-limiting examples include liquid crystallization, chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • atoms that are deposited at mismatched locations tend to generate lattice defects. Such defects can be repaired following deposition of the layer by the high pressure treatment techniques of the present disclosure.
  • a method of decreasing the incidence of defects in a semiconductor material can include placing a semiconductor material into a high pressure device, applying high presser to the semiconductor material via the high pressure device, and heating the semiconductor material to a temperature that is below a thermal stability limit of the semiconductor material lattice. The method further includes maintaining the high pressure and temperature for a time sufficient to decrease crystal lattice defects in the semiconductor material as compared to the semiconductor material prior to high pressure treatment.
  • the high pressure can be a high pressure that is uniformly distributed around the high pressure
  • FIG. 2 An example of the uniform distribution of high pressure is shown in FIG. 2. A
  • semiconductor material 12 is shown positioned in a support material 14 in a device that generates high pressure (not shown).
  • the high pressure is uniformly distributed 16 across the surface of the semiconductor material 12.
  • the high pressure can be by hot isostatic pressing.
  • multiple semiconductor material layers can be stacked with appropriate pressure generating material there between so that more than one semiconductor material can be simultaneously processed.
  • the stacks can be prepared such that pressure applied to the stack is uniformly applied to all semiconductor material layers located therein. Pressure from the surrounding stack will thus provide uniform pressure to a given semiconductor material to minimize cracking or damage.
  • semiconductor material layers will facilitate uniform pressing.
  • the pressure exerted on the semiconductor material can vary depending on the material, the type of pressing, the degree of lattice defects, the temperature used, and the like.
  • the high pressure is from about 0.1 GPa to about 6 GPa.
  • the high pressure is from about 1 GPa to about 5 GPa.
  • the high pressure is from about 2 GPa to about 5 GPa.
  • the high pressure is from about 0.01 GPa to about 5 GPa.
  • the semiconductor material can be heated to any temperature below the thermal stability of the material that allows the defect density to be decreased.
  • the thermal stability of a semiconductor material need only be noted or calculated, and a temperature that is less than this value can be utilized.
  • the temperature can be at least 50° C below the thermal stability limit of the semiconductor material lattice.
  • the temperature can be at least 100° C below the thermal stability limit of the semiconductor material lattice.
  • the temperature applied can be a result of the temperature increase due to the high pressure.
  • heat can be provided to the interior of the high pressure apparatus in order to increase the temperature therein.
  • the temperature can be from about 950°C to about 1500°C.
  • the thermal stability of a semiconductor material need only be noted or calculated, and a temperature that is less than this value can be utilized.
  • the temperature can be at least 50° C below the thermal stability limit of the semiconductor material lattice.
  • the temperature can be at least 100° C below the thermal stability limit of the semiconductor material lattice.
  • the temperature applied can
  • temperature can be from about 1000°C to about 1300°C.
  • the degree of reduction of defects in the semiconductor material can vary, depending at least in part on the nature of the semiconductor material, the configuration of the pressure apparatus and the amount of pressure utilized, the applied temperature, and the like. In one aspect, however, the defects in the semiconductor material lattice are reduced by at least 50% as compared to the semiconductor material prior to high pressure treatment. In another aspect, the defects in the semiconductor material lattice are reduced by at least 90% as compared to the semiconductor material prior to high pressure treatment. In yet another aspect, the defects in the semiconductor material lattice are reduced from between about 10 8 /cm 2 and 10 9 /cm 2 prior to high pressure treating, to between about 10 4 /cm 2 andl0 6 /cm 2 following high pressure treating.
  • the high pressure and/or temperature can be cycled or otherwise varied over time.
  • multi-stage heating and/or pressure variation can be performed. Heating and/or pressure can be ramped up or stepped from one stage to the next.
  • time durations of various stages can be the same or different, depending on the desire results of the annealing process.
  • the semiconductor material can be vibrated while being subjected to high pressure and high temperature.
  • This vibration can be applied to the pressing device, applied by rapidly varying the pressure within the pressing device, or applied by any other useful technique.
  • the vibration source can be a vibrator coupled to the high temperature furnace. The amplitude and frequency of the vibration source can be selected according to material characteristics of the
  • the amplitude of the vibration source can be between about lOum and about 30um, with a frequency of between about 20 kHz and about 40kHz. With the aid of vibration, movement of defects in the semiconductor material can be accelerated, thus decreasing the time period to achieve a lower defect density.
  • FIG. 3 shows a comparison of hot pressed and non-hot pressed materials.
  • FIG. 3A shows a GaN on sapphire material that has been acid etched with an acid. Etching pits initiate at crystal dislocations and other defects in the GaN material, and thus are further etched to expose the underlying sapphire material.
  • FIG. 3B shows a material of GaN on sapphire that has been hot pressed at about 5 GPa at 1300°C in a cubic press, followed by etching with the acid. As can be seen in FIG. 3B, the GaN material did not have sufficient defects or dislocations to allow etching by the acid.
  • FIG. 4 shows x-ray diffraction peaks of the untreated (FIG. 4A) and the hot pressed (FIG. 4B) materials. Note that the hot pressed material shows a much higher peak intensity, indicating that crystallinity is improved compared to the non-hot pressed material.
  • the semiconductor material can be a wafer.
  • the semiconductor material can be a semiconductor layer that is epitaxially grown on a substrate.
  • combinations of semiconductor materials are contemplated.
  • multiple semiconductor layers can be high pressure treated to reduce defects. This can be accomplished simultaneously following the deposition of one or more layers on a substrate, or the high pressure treatment can be performed sequentially following the deposition of each layer.
  • a wafer can be high pressure treated to reduce defects in the wafer, following which an epitaxial layer can be deposited thereon.
  • the wafer and epitaxial layer can subsequently be high pressure treated to reduce defects in the epitaxial layer.
  • an epitaxial layer and/or a wafer can have additional layers or features deposited thereon prior to high pressure treatment.
  • Non-limiting examples can include reflective layers, passivation layers, circuitry features, and the like.
  • the specific semiconductor material can include any material having undesirable defects that can be reduced due to the application of high pressures thereto.
  • Many semiconductors are based on silicon, gallium, indium, and germanium.
  • suitable materials for the semiconductor layer can include, without limitation, silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, germanium, zinc sulfide, gallium phosphide, gallium
  • the semiconductor layer can include silicon, silicon carbide, gallium arsenide, gallium nitride, gallium phosphide, aluminum nitride, indium nitride, indium gallium nitride, aluminum gallium nitride, or composites of these materials.
  • the semiconductor material can include gallium nitride, aluminum nitride, silicon, gallium phosphide, gallium arsenide, indium gallium nitride, indium nitride, or a combination thereof.
  • the semiconductor material can include gallium nitride, aluminum nitride, silicon, gallium phosphide, gallium arsenide, or a combination thereof.
  • the semiconductor material is gallium nitride.
  • the semiconductor material can include a gallium nitride layer on a silicon wafer. As has been described, the atomic mismatch in such a case results in a gallium nitride layer having substantial numbers of defects.
  • the semiconductor material is aluminum nitride. It should be noted that the semiconductor material can be doped as is well known in the art
  • semiconductor materials may be of any structural configuration known, for example, without limitation, cubic (zincblende or sphalerite), wurtzitic, rhombohedral, graphitic, turbostratic, pyrolytic, hexagonal, amorphous, or combinations thereof.
  • the semiconductor material can be formed by any method known to one of ordinary skill in the art Various known methods of vapor deposition, physical deposition, liquid crystallization, and the like, can be utilized to form such layers.
  • a deposition process can be MOCVD.
  • materials having a cubic crystal lattice can be created via hot pressing according to the present aspects.
  • cubic GaN having a low to zero dislocation density can be created.
  • GaN can be deposited onto the 100 face of a Si substrate. The 100 face of Si thus is used as a template to deposit the GaN as cubic GaN. The size disparity of the crystalline structure between Si and GaN will produce a number of crystal dislocations and defects in the cubic GaN.
  • the crystal dislocations can be reduced or eliminated, resulting in a high quality low-lo-no defect cubic GaN on Si.
  • Exemplary devices can include optoelectronic devices such as LEDs, solar cells, laser diodes, and the like, CPUs, graphics ICs, memory ICs, filters such as SAW, B AW, and the like, as well as any other known semiconductor device or device configuration.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

L'invention concerne des procédés de diminution des défauts dans un matériau semi-conducteur, y compris des dispositifs associés. Selon un aspect de l'invention, par exemple, un procédé de diminution des défauts dans un matériau semi-conducteur peut comprendre la mise en place d'un matériau semi-conducteur dans un dispositif à haute pression, l'application d'une haute pression sur le matériau semi-conducteur par le dispositif à haute pression, et le chauffage du matériau semi-conducteur à une température qui est inférieure à une limite de stabilité thermique du réseau cristallin du matériau semi-conducteur. La haute pression et la température sont maintenues pendant une durée suffisante pour diminuer les défauts de réseau cristallin dans le matériau semi-conducteur par comparaison au matériau semi-conducteur avant le traitement à haute pression.
PCT/US2012/069314 2011-12-12 2012-12-12 Procédé de recuit et dispositifs fabriqués ainsi WO2013090472A1 (fr)

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US201161569682P 2011-12-12 2011-12-12
US201161569666P 2011-12-12 2011-12-12
US61/569,666 2011-12-12
US61/569,682 2011-12-12

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010006852A1 (en) * 1998-12-23 2001-07-05 Yong Chen Method for relieving lattice mismatch stress in semiconductor devices
US6447600B1 (en) * 1998-09-30 2002-09-10 Mitsubishi Materials Silicon Corporation Method of removing defects of single crystal material and single crystal material from which defects are removed by the method
EP1715086A1 (fr) * 2002-06-27 2006-10-25 General Electric Company Méthode por réduire des défaults à l'intérieur de cristaux
JP2010070398A (ja) * 2008-09-16 2010-04-02 Stanley Electric Co Ltd 酸化亜鉛単結晶層の成長方法
JP4633962B2 (ja) * 2001-05-18 2011-02-16 日亜化学工業株式会社 窒化物半導体基板の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6447600B1 (en) * 1998-09-30 2002-09-10 Mitsubishi Materials Silicon Corporation Method of removing defects of single crystal material and single crystal material from which defects are removed by the method
US20010006852A1 (en) * 1998-12-23 2001-07-05 Yong Chen Method for relieving lattice mismatch stress in semiconductor devices
JP4633962B2 (ja) * 2001-05-18 2011-02-16 日亜化学工業株式会社 窒化物半導体基板の製造方法
EP1715086A1 (fr) * 2002-06-27 2006-10-25 General Electric Company Méthode por réduire des défaults à l'intérieur de cristaux
JP2010070398A (ja) * 2008-09-16 2010-04-02 Stanley Electric Co Ltd 酸化亜鉛単結晶層の成長方法

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