WO2013077619A1 - Diode électroluminescente et son procédé de fabrication - Google Patents

Diode électroluminescente et son procédé de fabrication Download PDF

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WO2013077619A1
WO2013077619A1 PCT/KR2012/009849 KR2012009849W WO2013077619A1 WO 2013077619 A1 WO2013077619 A1 WO 2013077619A1 KR 2012009849 W KR2012009849 W KR 2012009849W WO 2013077619 A1 WO2013077619 A1 WO 2013077619A1
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Prior art keywords
layer
pattern
micro
semiconductor
gallium nitride
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PCT/KR2012/009849
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English (en)
Korean (ko)
Inventor
김다혜
김창연
정재혜
이준희
유종균
이미희
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서울옵토디바이스주식회사
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Priority claimed from KR1020110121713A external-priority patent/KR20130055999A/ko
Priority claimed from KR1020110133833A external-priority patent/KR20130067014A/ko
Priority claimed from KR1020120020539A external-priority patent/KR20130098760A/ko
Application filed by 서울옵토디바이스주식회사 filed Critical 서울옵토디바이스주식회사
Publication of WO2013077619A1 publication Critical patent/WO2013077619A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/387—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

Definitions

  • the present invention relates to a light emitting diode and a method of manufacturing the same, and more particularly to a high efficiency light emitting diode and a method of manufacturing the same.
  • nitrides of group III elements such as gallium nitride (GaN) and aluminum nitride (AlN) have excellent thermal stability and have a direct transition type energy band structure. It is attracting much attention as a substance.
  • GaN gallium nitride
  • AlN aluminum nitride
  • blue and green light emitting devices using indium gallium nitride (InGaN) have been used in various applications such as large-scale color flat panel display devices, traffic lights, indoor lighting, high density light sources, high resolution output systems, and optical communications.
  • Such a nitride semiconductor layer of Group III elements is difficult to fabricate homogeneous substrates capable of growing them, and therefore, such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), etc., on heterogeneous substrates having a similar crystal structure. It has been grown through the process of.
  • a hetero substrate a sapphire substrate having a hexagonal structure is mainly used.
  • epitaxial layers such as nitride semiconductor layers are grown on dissimilar substrates such as sapphire, bonding supporting substrates to the epitaxial layers, and then dissociating dissimilar substrates using a laser lift-off technique. Techniques for manufacturing light emitting diodes have been developed. Since a heterogeneous substrate such as sapphire and an epitaxial layer grown thereon have different physical properties, the growth substrate can be easily separated by using an interface between them.
  • epitaxial layers grown on dissimilar substrates have a relatively high dislocation density due to lattice mismatch with the growth substrate and differences in coefficient of thermal expansion.
  • Epilayers grown on sapphire substrates are generally known to have dislocation densities of at least 1E8 / cm 2.
  • the epitaxial layer having such a high dislocation density has a limit in improving the luminous efficiency of the light emitting diode.
  • the total thickness of the epi layer is very thin, for example, compared to the light emitting area of 350 ⁇ m ⁇ 350 ⁇ m, or 1 mm 2, there are many difficulties in current dispersion. Moreover, when operating the light emitting diode at high current, the potential Since the current is concentrated through the droop phenomenon, the internal quantum efficiency decreases more severely than when operating at low current.
  • the epitaxial layer which is separated and exposed to the growth substrate is mainly an n-type doped epi layer, it is difficult to increase its roughness only by wet etching.
  • An object of the present invention is to provide a high efficiency light emitting diode having a vertical structure.
  • Another object of the present invention is to provide a high efficiency light emitting diode that can alleviate droop.
  • Another problem to be solved by the present invention is to provide a high efficiency light emitting diode with improved current dispersion performance.
  • Another object of the present invention is to provide a high efficiency light emitting diode with improved light extraction efficiency.
  • the present invention provides a high efficiency light emitting diode and a method of manufacturing the same.
  • a light emitting diode according to an aspect of the present invention the support substrate;
  • a reflective layer positioned between the support substrate and the semiconductor stacked structure.
  • the semiconductor laminate includes a main pattern having protrusions and recesses and a roughened surface formed on the protrusions and recesses of the main pattern, wherein the semiconductor laminate is formed to have a dislocation density of 5 ⁇ 10 6 / cm 2 or less. do.
  • the semiconductor stack structure may be formed of semiconductor layers grown on a gallium nitride substrate.
  • the semiconductor laminate structure may have a plurality of protrusions.
  • the semiconductor stack structure may have a plurality of recesses.
  • the average height of the protrusion (s) is greater than 3um, and the surface roughness of the roughened surface may be in the range of 0.1um to 1um.
  • a light emitting diode manufacturing method wherein a pattern of a sacrificial material is formed on a gallium nitride substrate, and a gallium nitride-based n-type semiconductor layer and gallium nitride are formed on a gallium nitride substrate on which the pattern of the sacrificial material is formed.
  • the semiconductor layers including the active layer and the gallium nitride-based p-type semiconductor layer are grown to form a semiconductor stack structure, a support substrate is formed on the semiconductor stack structure, and the gallium nitride substrate is removed to remove the sacrificial material. Exposing the pattern and removing the pattern of the sacrificial material.
  • the pattern of the sacrificial material is formed of a material having an etching selectivity with respect to the gallium nitride-based semiconductor layer, for example, may be formed of a silicon oxide film or a silicon nitride film.
  • the light emitting diode manufacturing method may further include forming a roughened surface by wet etching the surface of the semiconductor laminate structure after the pattern of the sacrificial material is removed. Further, the wet etching may be performed using a boiling solution of KOH or NaOH.
  • a light emitting diode manufacturing method comprising growing a semiconductor layer including a gallium nitride based n-type semiconductor layer, a gallium nitride based active layer, and a gallium nitride based p-type semiconductor layer on a gallium nitride substrate.
  • a semiconductor laminate is formed, a support substrate is formed on the semiconductor laminate, the gallium nitride substrate is removed to expose the semiconductor laminate, and the semiconductor laminate is patterned to form a main pattern having protrusions and recesses. And wet etching the surface of the semiconductor laminate structure on which the main pattern is formed to form a roughened surface of the protrusion and the recess.
  • Forming the main pattern may be performed by dry etching.
  • the wet etching may be performed using a boiling solution of KOH or NaOH.
  • removing the gallium nitride substrate may include grinding a gallium nitride substrate to remove a part of the gallium nitride substrate, and removing a portion of the gallium nitride substrate remaining on the semiconductor laminate structure by using inductively coupled plasma reactive ion etching ( Removal using ICP-RIE) techniques.
  • ICP-RIE inductively coupled plasma reactive ion etching
  • Removing the gallium nitride substrate may further include polishing the gallium nitride substrate after polishing the gallium nitride substrate.
  • the polishing includes, for example, chemical polishing.
  • an inspection may be performed to confirm whether the surface of the semiconductor laminate structure is exposed.
  • the inspection may be performed by measuring the sheet resistance of the surface.
  • the protrusion may have a circular top surface, and the bottom surface may include a plurality of micro cones.
  • the roughened surface may include at least one sub-microcone formed on the upper surface of the microcone.
  • any one of the microcones may be surrounded by six other microcones.
  • one or two sub-microcones may be formed between the one microcone and one of the six microcones.
  • the microcones may have an average diameter of 3 ⁇ m on an upper surface thereof, an average separation distance between any one of the microcones and a center point of another neighboring microcone may be 6 ⁇ m, and the average height of the microcones may be 3 ⁇ m. .
  • the at least one sub-microcone may have an average height of 0.5 ⁇ m or less.
  • the recess may include a plurality of micro-cone grooves.
  • the roughened surface may include at least one sub-micro cone.
  • At least one of the micro cone grooves may include at least one sub micro cone on a bottom surface thereof.
  • At least one of the micro-cone-shaped grooves may have a bottom surface six crystal surfaces.
  • the micro-cone grooves may be formed in a regular arrangement on the light extraction surface, and the distance between one of the micro-cone grooves and another neighboring micro-cone groove may be less than 10 ⁇ m.
  • the protruding portion includes at least one microcone
  • forming a main pattern having the protruding portion and the concave portion comprises forming a photoresist pattern on the semiconductor laminate structure.
  • forming a metal material layer on the semiconductor laminate structure on which the photoresist pattern is formed and then forming a metal pattern by a lift-off method, and partially etching the semiconductor laminate structure by dry etching using the metal pattern as a mask.
  • Etching may include forming at least one microcone.
  • wet etching may be photoelectrochemical (PEC) etching, and the roughened surface may include sub-micro cones.
  • PEC photoelectrochemical
  • One or two microcones may be formed between an upper surface of the microcones or one of the microcones and one of the six microcones.
  • the metal pattern is made of a Ti layer / Ni layer, the Ti layer is formed of a thickness of 500 kW, the Ni layer is formed of a thickness of 5000 kW.
  • the recess includes at least one micro-cone groove
  • forming a main pattern having the protrusion and the recess may include a mask pattern on the semiconductor laminate. And forming a portion of the semiconductor stacked structure layer by dry etching using the mask pattern as a mask to form at least one microcone groove.
  • wet etching may be photoelectrochemical (PEC) etching, and the roughened surface may include sub-micro cones.
  • PEC photoelectrochemical
  • the mask pattern may be a photoresist pattern.
  • the forming of the mask pattern may include forming a photoresist pattern on the semiconductor laminate, forming a metal material layer on the semiconductor laminate having the photoresist pattern, and forming the photoresist pattern and the photoresist pattern. It may include forming a mask pattern made of a metal material by removing the metal material layer formed on the.
  • the metal material layer may be formed of a single layer or multiple layers including at least one of nickel (Ni), platinum (Pt), palladium (Pd), tungsten (W), titanium (Ti), or chromium (Cr).
  • the forming of the mask pattern may include forming an insulating film pattern forming layer on the semiconductor laminate, forming a photoresist pattern on the insulating film pattern forming layer, and etching the insulating film pattern forming layer using the photoresist pattern as a mask. This may include forming an insulating film pattern to form a mask pattern including a photoresist pattern and an insulating film pattern.
  • the insulating layer pattern forming layer may include silicon oxide.
  • a semiconductor laminate structure having a low dislocation density can be formed by growing semiconductor layers using a gallium nitride substrate as a growth substrate, thereby reducing the droop phenomenon of the light emitting diode. Furthermore, a high efficiency light emitting diode can be provided by removing a gallium nitride substrate from the semiconductor laminate to manufacture a light emitting diode having a vertical structure.
  • the semiconductor layers grown on the gallium nitride substrate have a very low dislocation density, it is difficult to improve the light extraction efficiency due to the limitation in providing a rough surface by conventional photochemical etching, but according to the present invention, protrusions are formed. The light extraction efficiency of the semiconductor laminated structure with low dislocation density can be improved by this.
  • FIG. 1 is a schematic layout diagram illustrating a light emitting diode according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along the line A-A of FIG. 1 to illustrate a light emitting diode according to an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view taken along the line B-B of FIG. 1 to illustrate a light emitting diode according to an embodiment of the present invention.
  • FIG. 4 is a cross-sectional view taken along the line C-C of FIG. 1 to illustrate a light emitting diode according to an embodiment of the present invention.
  • FIG. 5 is a cross-sectional view for describing a light emitting diode according to another exemplary embodiment of the present invention.
  • 6 to 11 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention, each of which corresponds to a cut line A-A of FIG. 1.
  • FIG. 12 is a cross-sectional view for describing a light emitting diode according to another embodiment of the present invention.
  • FIG. 13 is a graph for explaining a droop of a semiconductor laminate structure grown on a sapphire substrate and a semiconductor laminate structure grown on a gallium nitride substrate.
  • FIG. 14 is a cross-sectional view for describing a light emitting diode according to another embodiment of the present invention.
  • 15A and 15B are photographs illustrating a light extraction surface of a light emitting diode according to another embodiment of the present invention.
  • 16 is a graph comparing the power of a light emitting diode according to another embodiment of the present invention and a conventional light emitting diode.
  • 17 to 23 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention.
  • FIG. 24 is a cross-sectional view for describing a light emitting diode according to another embodiment of the present invention.
  • 25 and 26 are photographs illustrating a light extraction surface of a light emitting diode according to another embodiment of the present invention.
  • FIG. 27 is a graph showing power versus spacing between micro-conical grooves of a light emitting diode according to another embodiment of the present invention.
  • Vf vs. power of a light emitting diode and a conventional light emitting diode is a graph showing Vf vs. power of a light emitting diode and a conventional light emitting diode according to another embodiment of the present invention.
  • 29 is a graph showing wavelength versus power of a light emitting diode and a conventional light emitting diode according to another embodiment of the present invention.
  • 30 to 35 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to still another embodiment of the present invention.
  • FIG. 1 is a schematic layout diagram illustrating a light emitting diode according to an embodiment of the present invention
  • FIGS. 2 to 4 are cross-sectional views taken along the cutting lines A-A, B-B, and C-C of FIG. 1, respectively.
  • the reflective metal layer 31 and the intermediate insulating layer 33 positioned under the semiconductor stacked structure 30 are indicated by dotted lines.
  • the light emitting diode includes a support substrate 41, a semiconductor stacked structure 30, a reflective metal layer 31, an intermediate insulating layer 33, a barrier metal layer 35, and an upper insulating layer 47. ), an n-electrode pad 51 and an electrode extension 51a.
  • the light emitting diode may include a bonding metal 43.
  • the support substrate 41 is distinguished from a growth substrate for growing the compound semiconductor layers, and is a secondary substrate attached to the compound semiconductor layers that have already been grown.
  • the support substrate 41 may be a conductive substrate, such as a metal substrate or a semiconductor substrate.
  • the semiconductor stacked structure 30 is disposed on the support substrate 41 and includes a p-type semiconductor layer 29, an active layer 27, and an n-type semiconductor layer 25.
  • the p-type semiconductor layer 29 is located closer to the support substrate 41 side than the n-type semiconductor layer 25 in the semiconductor laminate structure 30.
  • the semiconductor stacked structure 30 may be located on a portion of the support substrate 41. That is, the support substrate 41 has a relatively large area compared to the semiconductor laminate structure 30, and the semiconductor laminate structure 30 is located in an area surrounded by an edge of the support substrate 41.
  • the n-type semiconductor layer 25, the active layer 27, and the p-type semiconductor layer 29 may be formed of a III-N series compound semiconductor, such as (Al, Ga, In) N semiconductor.
  • the n-type semiconductor layer 25 and the p-type semiconductor layer 29 may be a single layer or multiple layers, respectively.
  • the n-type semiconductor layer 25 and / or p-type semiconductor layer 29 may include a contact layer and a cladding layer, and may also include a superlattice layer.
  • the active layer 27 may have a single quantum well structure or a multiple quantum well structure.
  • the semiconductor stacked structure 30 may be formed to have a dislocation density of 5 ⁇ 10 6 / cm 2 or less.
  • Semiconductor layers grown on sapphire substrates generally have a high dislocation density of 1 ⁇ 10 8 / cm 2 or more.
  • the semiconductor stacked structure 30 according to the present invention uses a semiconductor layer 25, 27, 29 grown by using a gallium nitride substrate as a growth substrate, and thus has a low dislocation density of 5 ⁇ 10 6 / cm 2 or less. It can be formed to have.
  • the lower limit of the dislocation density is not particularly limited, but may be 1 ⁇ 10 4 / cm 2 or more or 1 ⁇ 10 6 / cm 2 or more.
  • the p-electrode is positioned between the p-type semiconductor layer 29 and the support substrate 41 and may include a reflective metal layer 31 and a barrier metal layer 35.
  • the reflective metal layer 31 may be in ohmic contact with the p-type semiconductor layer 29 between the semiconductor stacked structure 30 and the support substrate 41.
  • the reflective metal layer 31 may include a reflective layer, for example Ag.
  • the reflective metal layer 31 is located below the semiconductor stacked structure 30. As shown in FIG. 1, the reflective metal layer 31 may be formed of a plurality of plates, and grooves are formed between the plurality of plates. The semiconductor stacked structure 30 is exposed through the groove.
  • An intermediate insulating layer 33 covers the reflective metal layer 31 between the reflective metal layer 31 and the support substrate 41.
  • the intermediate insulating layer 33 covers the side and edges of the reflective metal layer 31, for example, the plurality of plates, and has openings that expose the reflective metal layer 31.
  • the intermediate insulating layer 33 may be formed of a single layer or multiple layers of a silicon oxide film or a silicon nitride film, and may also be a distributed Bragg reflector in which insulating layers having different refractive indices, such as SiO 2 / TiO 2 or SiO 2 / Nb 2 O 5, are repeatedly stacked. have.
  • the side surface of the reflective metal layer 31 may be prevented from being exposed to the outside by the intermediate insulating layer 33.
  • the intermediate insulating layer 33 may also be located below the side surface of the semiconductor laminate 30, thus preventing leakage current through the side of the semiconductor laminate 30.
  • the barrier metal layer 35 covers the intermediate insulating layer 33 under the intermediate insulating layer 33 and is connected to the reflective metal layer 31 through the opening of the intermediate insulating layer 33.
  • the barrier metal layer 35 protects the reflective metal layer 31 by preventing diffusion of a metal material, such as Ag, of the reflective metal layer 31.
  • the barrier metal layer 35 may include, for example, a Ni layer.
  • the barrier metal layer 35 may be located on the front surface of the support substrate 41.
  • the support substrate 41 may be bonded to the barrier metal layer 35 through a bonding metal 43.
  • Bonding metal 43 may be formed using eutectic bonding, for example, with Au—Sn.
  • the support substrate 41 may be formed on the barrier metal layer 35 using, for example, a plating technique.
  • the support substrate 41 is a conductive substrate, it may function as a p-electrode pad.
  • a p-electrode pad may be formed on the barrier metal layer 35 positioned on the support substrate 41.
  • the upper surface of the semiconductor laminated structure 30, that is, the surface of the n-type semiconductor layer 25 has a main pattern having protrusions 25a and recesses 25b, and protrusions 25a and recesses 25b of the main patterns. May have a roughened surface 25r.
  • the semiconductor laminate 30 may have a flat surface on a portion of an upper surface thereof. As shown in FIGS. 2-4, the n-electrode pad 51 and the electrode extension 51a may be located on a flat surface. As shown in the drawing, the n-electrode pad 51 and the electrode extension 51a may be defined and positioned on a flat surface, and may have a narrow width compared to the width of the flat surface. Therefore, peeling of an electrode pad or an electrode extension part by generation
  • the main pattern may have a plurality of protrusions 25a and a recess 25b may be located between the protrusions 25a.
  • the present invention is not limited thereto.
  • the main pattern may have a mesh-shaped protrusion 25a and may have a plurality of recesses 25b separated from each other by the protrusion 25a.
  • the plurality of protrusions 25a or the plurality of recesses 25b may be arranged in various shapes, and in particular, may be arranged in a honeycomb shape.
  • the average height of the protrusion 25a may be 2.5um or more.
  • the protrusion 25a is formed in the n-type semiconductor layer 25 and smaller than the thickness of the n-type semiconductor layer 25.
  • the n-type semiconductor layer 25 may have a thickness of about 6um, and the average height of the protrusion 25a may be in a range of 2.5 to 5um.
  • the side surface of the protrusion 25a may have an inclination angle of 85 to 90 degrees with respect to the surface of the support substrate 41. That is, the protrusion 25a has a shape substantially perpendicular to the support substrate 41.
  • the roughened surface 25r is formed on the top surface of the protrusion 25a and the bottom surface of the recess 25b, and may also be formed on the side surface of the protrusion 25a.
  • the surface roughness Ra of the roughened surface 25r is smaller than the average height of the protrusion 25a and may be, for example, in a range of 0.1 to 1 um.
  • the roughened surface 25r may be made of fine cones, but is not limited thereto.
  • the light extraction efficiency may be improved by the main patterns of the protrusions 25a and the recesses 25b and the roughened surface 25r.
  • the n-electrode pad 51 is located on the semiconductor stacked structure 30, and the electrode extension 51a extends from the n-electrode pad 51.
  • a plurality of n-electrode pads 51 may be positioned on the semiconductor stacked structure 30, and electrode extensions 51a may extend from the n-electrode pads 51, respectively.
  • the electrode extensions 51a may be electrically connected to the semiconductor stacked structure 30 and may directly contact the n-type semiconductor layer 25.
  • the n-electrode pad 51 may also be located above the groove region of the reflective metal layer 31. That is, under the n-electrode pad 51, there is no reflective metal layer 31 in ohmic contact with the p-type semiconductor layer 29. Instead, the intermediate insulating layer 33 is positioned.
  • the electrode extension part 51a is also positioned above the groove area of the reflective metal layer 31. As shown in FIG. 1, an electrode extension part 51a may be positioned on an area between the plates in the reflective metal layer 31 including a plurality of plates.
  • the width of the groove region of the reflective metal layer 31, for example, the region between the plurality of plates is wider than the width of the electrode extension 51a. Accordingly, it is possible to prevent the current from flowing intensively directly below the electrode extension part 51a.
  • an upper insulating layer 47 is interposed between the n-electrode pad 51 and the semiconductor stacked structure 30.
  • the upper insulating layer 47 prevents current from flowing directly from the n-electrode pad 51 to the semiconductor stacked structure 30, and in particular, prevents current from concentrating directly under the n-electrode pad 51. Can be.
  • the upper insulating layer 47 covers the protrusion 25a and the recess 25b. In this case, if the upper insulating layer 47 may have a convex shape along the protrusion 25a, the total internal reflection generated at the upper surface of the upper insulating layer 47 may be reduced.
  • the upper insulating layer 47 may also cover side surfaces of the semiconductor stack 30 to protect the semiconductor stack 30 from an external environment.
  • the upper insulating layer 47 may have an opening exposing the semiconductor stack 30, and the electrode extension 51a may be located in the opening to contact the semiconductor stack 30.
  • FIG. 5 is a cross-sectional view for describing a light emitting diode according to another exemplary embodiment of the present invention.
  • the light emitting diode is generally similar to that described with reference to FIGS. 1 to 4, but there is a difference in that the support substrate 60 has a laminated structure of specific materials.
  • the support substrate 60 includes a first metal layer 64 positioned in the center of the support substrate 60 and second metal layers 62 and 66 symmetrically disposed above and below the first metal layer 64. do.
  • the first metal layer 64 may include, for example, at least one of tungsten (W) or molybdenum (Mo).
  • the second metal layers 62 and 66 are materials having a higher coefficient of thermal expansion than the first metal layer 64 and may include, for example, copper (Cu).
  • Bonding layers 63 and 65 are formed between the first metal layer 64 and the second metal layers 62 and 66.
  • the bonding layer 61 is also formed between the bonding metal 43 and the second metal layer 62.
  • These bonding layers 61, 63, 65 may comprise at least one of Ni, Ti, Cr, and Pt.
  • a lower bonding metal 68 may be formed on the bottom surface of the second metal layer 66 disposed below the first metal layer 64 through the bonding layer 67.
  • the lower bonding metal 68 is a structure symmetrical to the bonding metal 43 interposed between the supporting substrate 60 and the semiconductor stack 30, and may be made of the same material as the bonding metal 43, for example, Au or Au-Sn (80 / 20wt%).
  • the lower bonding metal 68 may be used to attach the support substrate 60 to an electronic circuit or a PCB substrate.
  • the support substrate 60 has a structure including the first metal layer 64 and the second metal layers 62 and 66 symmetrically formed on the upper and lower surfaces of the first metal layer 64.
  • tungsten (W) or molybdenum (Mo) constituting the first metal layer 64 has a relatively low coefficient of thermal expansion and relatively high strength as compared to, for example, copper (Cu) constituting the second metal layers 62, 66.
  • Cu copper
  • forming the second metal layers 62 and 66 on the upper and lower surfaces of the first metal layer 64 may be performed in a step rather than having the opposite structure (the structure in which the first metal layer is formed on the upper and lower surfaces of the second metal layer). Even more preferred.
  • the thickness of the first metal layer 64 and the thickness of the second metal layers 62, 66 are appropriate. Can be adjusted.
  • the support substrate 60 may be manufactured separately from the semiconductor stack structure 30 and then bonded to the barrier metal layer 35 through the bonding metal 43.
  • the bonding metal 43 may be formed using eutectic bonding, for example, with Au or Au—Sn (80/20 wt%).
  • the support substrate 60 may be formed by plating or depositing the barrier metal layer 35.
  • the support substrate 60 may be plated by an electrolytic plating method for depositing a metal using a rectifier, an electroless plating method for depositing a metal using a reducing agent, and thermal deposition, electron beam deposition, sputtering, and chemical vapor deposition. Or the like.
  • FIG. 6 to 11 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.
  • the cross-sectional views correspond to the cross-sectional views taken along the cut line A-A of FIG. 1.
  • a pattern 23 of sacrificial material is formed on the gallium nitride substrate 21.
  • the sacrificial material pattern 23 may be formed of a material having an etch selectivity with respect to the gallium nitride-based semiconductor layer (eg, the n-type semiconductor layer 25), and may be formed of, for example, a silicon oxide film or a silicon nitride film.
  • the pattern 23 of the sacrificial material may be formed in a stripe pattern, a mesh pattern or an island pattern. Such a pattern has a shape corresponding to the recess 25b of the light emitting diode described with reference to FIGS. 1 to 4.
  • the semiconductor stacked structure 30 including the n-type semiconductor layer 25, the active layer 27, and the p-type semiconductor layer 29 is formed on the gallium nitride substrate 21 on which the pattern 23 of the sacrificial material is formed. .
  • the n-type and p-type semiconductor layers 25 and 29 may be formed in a single layer or multiple layers, respectively.
  • the active layer 27 may be formed in a single quantum well structure or a multiple quantum well structure.
  • the semiconductor layers 25, 27, and 29 may be formed to have a dislocation density of about 5 ⁇ 10 6 / cm 2 or less.
  • the compound semiconductor layers may be formed of a gallium nitride-based compound semiconductor, such as (Al, Ga, In) N, and may be formed by a process such as metal organic chemical vapor deposition (MOCVD) or molecular beam deposition (MBE). May be grown on the substrate 21.
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam deposition
  • a reflective metal layer 31 is formed on the semiconductor stacked structure 30.
  • the reflective metal layer 31 has a groove exposing the semiconductor stacked structure 30.
  • the reflective metal layer 31 may be formed of a plurality of plates, and grooves may be formed between the plurality of plates (see FIG. 1).
  • an intermediate insulating layer 33 covering the reflective metal layer 31 is formed.
  • the intermediate insulating layer 33 fills the groove in the reflective metal layer and covers the side and edge of the reflective metal layer.
  • the intermediate insulating layer 33 has openings that expose the reflective metal layer 31.
  • the intermediate insulating layer 33 may be formed of a silicon oxide film or a silicon nitride film, or may be formed of a distributed Bragg reflector by repeatedly stacking insulating layers having different refractive indices.
  • the barrier metal layer 35 is formed on the intermediate insulating layer 33.
  • the barrier metal layer 35 may be connected to the reflective metal layer 31 by filling an opening formed in the intermediate insulating layer 33.
  • a support substrate 41 is attached on the barrier metal layer 35.
  • the support substrate 41 may be manufactured separately from the semiconductor stack structure 30 and then bonded to the barrier metal layer 35 through the bonding metal 43.
  • the support substrate 41 may be formed by plating on the barrier metal layer 35.
  • gallium nitride substrate 21 is removed to expose the n-type semiconductor layer 25 surface of the semiconductor laminate 30.
  • the sapphire substrate When the conventional sapphire substrate is used as a growth substrate, since the sapphire substrate has different physical properties from those of the semiconductor layers 25, 27, and 29 grown thereon, the sapphire substrate can be easily separated using the interface between the substrate and the semiconductor layers. Can be. However, when the gallium nitride substrate 21 is used as a growth substrate, since the gallium nitride substrate 21 and the semiconductor layers 25, 27, 29 grown thereon are the same material, the substrate 21 and the semiconductor layers It is difficult to separate the substrate 21 using the interface between the 25, 27, and 29.
  • the gallium nitride substrate 21 can be removed by grinding. Further, in addition to the polishing, polishing such as chemical mechanical polishing (CMP) can be performed, and can also be precisely removed using inductively coupled plasma reactive ion etching (ICP-RIE) technology.
  • CMP chemical mechanical polishing
  • ICP-RIE inductively coupled plasma reactive ion etching
  • the pattern 23 of the sacrificial material is positioned between the gallium nitride substrate 21 and the semiconductor layers 25, 27, and 29, the exposure of the pattern 23 of the sacrificial material is confirmed. It can be easily confirmed that the gallium nitride substrate 21 is removed.
  • the pattern 23 of the sacrificial material is removed to form main patterns of the protrusions 25a and the recesses 25b.
  • the pattern 23 of the sacrificial material may be removed by wet etching or dry etching using an etching selectivity.
  • the lateral shape of the protrusion 25a may be modified by an etching process.
  • a mask pattern 45 is formed.
  • the mask pattern 45 covers a region where n-electrode pads and electrode extensions will be formed in the future.
  • the surface of the n-type semiconductor layer 25 is wet etched to form a surface 25r roughened on the protrusion 25a and the recess 25b.
  • the wet etching may be performed using a boiling solution of KOH or NaOH, and thus, a roughened surface having a surface roughness Ra of about 0.1 to 1 um may be formed.
  • cones are formed by etching the N-face using photochemical (PEC) etching techniques.
  • PEC photochemical
  • it is difficult to form cones using PEC technology because semiconductor layers grown on gallium nitride substrates have very few crystal defects such as dislocations.
  • KOH or NaOH a boiling solution of KOH or NaOH, it is possible to form cones or roughened surfaces of at least 1 ⁇ m or less.
  • the mask pattern 45 is removed, and the n-type semiconductor layer 25 surface on which the mask pattern 45 is located maintains a flat surface.
  • the semiconductor stacked structure 30 is patterned to form a chip segment, and the intermediate insulating layer 33 is exposed.
  • the chip segment may be formed before or after forming the roughened surface 25r.
  • the upper insulating layer 47 is formed on the n-type semiconductor layer 25 on which the main pattern including the protrusions 25a and the recesses 25b and the roughened surface 25r are formed.
  • the upper insulating layer 47 is formed along the protrusion 25a to have a convex surface.
  • the upper insulating layer 47 covers the flat surface on which the n-electrode pad 51 is to be formed.
  • the upper insulating layer 47 may also cover side surfaces of the semiconductor stacked structure 30 exposed to the chip division region. However, the upper insulating layer 47 has an opening 47a exposing a flat surface of the region where the electrode extension 51a is to be formed.
  • an n-electrode pad 51 is formed on the upper insulating layer 47, and an electrode extension part is formed in the opening 47a.
  • the electrode extension extends from the n-electrode pad 51 and is electrically connected to the semiconductor laminate 30.
  • the light emitting diode is completed by dividing into individual chips along the chip division region (see Fig. 2).
  • FIG. 12 is a cross-sectional view for describing a method of manufacturing the light emitting diode of FIG. 5.
  • the light emitting diode manufacturing method according to the present embodiment is similar to the light emitting diode manufacturing method described with reference to FIGS. 6 to 11, but there is a difference in forming a support substrate 60 of a specific material and structure. .
  • the sacrificial material pattern 23 is formed on the gallium nitride substrate 21, and the n-type semiconductor layer 25, the active layer 27, and the p-type semiconductor layer 29 are formed.
  • a semiconductor laminate structure 30 is formed including. Thereafter, as described with reference to FIG. 7, the reflective metal layer 31, the intermediate insulating layer 33, and the barrier metal layer 35 are formed on the semiconductor laminate structure 30.
  • a support substrate 60 is attached onto the barrier metal layer 35.
  • the support substrate 60 may be manufactured separately from the semiconductor stack structure 30 and then bonded to the barrier metal layer 35 through the bonding metal 43.
  • the support substrate 60 may include a first metal layer 64 positioned in the center of the support substrate 60 and a second metal layer symmetrically disposed below the first metal layer 64. (62, 66).
  • the first metal layer 64 may include, for example, at least one of tungsten (W) or molybdenum (Mo).
  • the second metal layers 62 and 66 are materials having a higher thermal expansion coefficient than the first metal layer 64 and may include, for example, copper (Cu). Bonding layers 63 and 65 are formed between the first metal layer 64 and the second metal layers 62 and 66.
  • a bonding layer 61 is formed between the bonding metal 43 and the second metal layer 62.
  • These bonding layers 61, 63, 65 may comprise at least one of Ni, Ti, Cr, and Pt.
  • a lower bonding metal 68 may be formed on the bottom surface of the second metal layer 66 through the bonding layer 67. The lower bonding metal 68 may be used to attach the support substrate 60 to an electronic circuit or a PCB substrate.
  • the support substrate 60 has a structure including the first metal layer 64 and the second metal layers 62 and 66 symmetrically formed on the upper and lower surfaces of the first metal layer 64.
  • tungsten (W) or molybdenum (Mo) constituting the first metal layer 64 has a relatively low coefficient of thermal expansion and relatively high strength as compared to, for example, copper (Cu) constituting the second metal layers 62, 66.
  • Cu copper
  • has The thickness of the first metal layer 64 is formed thicker than the thickness of the second metal layers 62 and 66.
  • the thickness of the first metal layer 64 and the thickness of the second metal layers 62, 66 are appropriate. Can be adjusted.
  • the coefficient of thermal expansion between the gallium nitride substrate 21, the semiconductor stacked structure 30, and the support substrate 60 during or after the thermal process according to the bonding of the support substrate 60 is achieved.
  • the stress due to the difference can be effectively alleviated, so that damage and warpage of the compound semiconductor layer can be suppressed.
  • a high temperature atmosphere is required, and pressure may be applied to facilitate the bonding.
  • This pressure can be applied only during the joining process using a pressure applying plate placed on top of the hot chamber, after which the pressure can be removed.
  • the pressure may be applied by a holder for fixing the support substrate 60 and the growth substrate 21 on both sides, and thus the pressure may be applied separately from the chamber in a high temperature atmosphere. Accordingly, after bonding the support substrate 60, the pressure can be maintained even at room temperature.
  • the support substrate 60 may be formed on the barrier metal layer 35 using, for example, a plating technique.
  • the gallium nitride substrate 21 is removed to expose the surface of the n-type semiconductor layer 25 of the semiconductor laminate 30. 9 to 11, the pattern 23 of the sacrificial material is removed and a roughened surface 25r is formed, and the upper insulating layer 47, the n-electrode pad 51, and the electrode extend.
  • the portion 51a is formed and divided into individual chips to complete the light emitting diode of FIG. 5.
  • a pattern 23 of the sacrificial material is formed on the gallium nitride substrate 21 to form a main pattern including the protrusions 25a and the recesses 25b.
  • the gallium nitride based semiconductor layer can be grown by using a horizontal growth technique, and thus the dislocation density in the semiconductor laminate can be further lowered.
  • the present invention is not limited to forming the main pattern by using the pattern 23 of the sacrificial material, and may also form the main pattern by using photo and etching techniques.
  • the semiconductor layered structure 30 is formed by growing the semiconductor layers 25, 27, and 29 directly on the gallium nitride substrate 21 without forming the sacrificial material pattern 23. Thereafter, after attaching the support substrate 41 onto the semiconductor laminate 30, the gallium nitride substrate 21 is removed to expose the semiconductor laminate 30. Subsequently, the exposed semiconductor stacked structure 30 may be patterned using photo and etching techniques to form a main pattern having protrusions 25a and recesses 25b. Thereafter, individual light emitting diodes may be completed through a process as described with reference to FIGS. 10 and 11.
  • the gallium nitride substrate 21 is the same type as the semiconductor layers 25 27 and 29, a conventional sapphire substrate removing technique cannot be used. Accordingly, the gallium nitride substrate 21 is first removed by grinding and then precisely removed using inductively coupled plasma reactive ion etching (ICP-RIE). In addition, polishing, such as chemical mechanical polishing (CMP), may be performed in addition to the polishing, and then the gallium nitride substrate 21 may be removed using reactive ion etching techniques.
  • ICP-RIE inductively coupled plasma reactive ion etching
  • CMP chemical mechanical polishing
  • a test for checking whether the n-type semiconductor layer 25 is exposed may be separately performed.
  • the surface resistance of the exposed surface may be measured after polishing, after polishing, or after reactive ion etching, and the surface resistance measurement may determine whether the n-type semiconductor layer 25 is exposed. Based on the inspection result, the removal process of the gallium nitride substrate 21 can be performed precisely.
  • FIG. 13 is a graph illustrating a droop of a semiconductor laminate structure grown on a conventional sapphire substrate and a semiconductor laminate structure grown on a gallium nitride substrate.
  • a light emitting diode with a size of 350 ⁇ m ⁇ 350 ⁇ m was fabricated and the light output according to the current was measured. The current was applied in the form of a pulse to measure the light output at each current.
  • the droop is represented by the value of the reduced external quantum efficiency relative to the maximum external quantum efficiency.
  • the semiconductor stack structure grown on the sapphire substrate or the semiconductor stack structure grown on the gallium nitride substrate did not show a significant difference in the light output while the current increased to about 40 mA, but exceeded 40 mA at the light output. The difference increased.
  • the semiconductor stacked structure grown on the sapphire substrate exhibited about 27% (-0.27) of droop, whereas the semiconductor stacked structure grown on the gallium nitride substrate had about 17% (-0.17) of droop. Indicated.
  • a light emitting diode having a droop of less than 20% may be provided by fabricating a light emitting diode having a vertical structure using a semiconductor laminate structure grown on a gallium nitride substrate.
  • FIG. 14 is a cross-sectional view for describing a light emitting diode according to another embodiment of the present invention.
  • 15A and 15B are photographs illustrating a light extraction surface of a light emitting diode according to another embodiment of the present invention.
  • 16 is a graph comparing power of a light emitting diode according to another embodiment of the present invention and a conventional light emitting diode.
  • a light emitting diode may include a support substrate 41, a bonding metal layer 120, an intermediate insulating layer 33, a reflective metal layer 31, and a semiconductor laminate structure 30. , A main pattern including protrusions and recesses, a rough surface, an upper insulating layer 47, and an n-electrode pad 51.
  • the semiconductor stacked structure 30 may include a p-type semiconductor layer 29, an active layer 27, and an n-type semiconductor layer 25.
  • the support substrate 41 serves to support the semiconductor laminate 30.
  • the support substrate 41 may serve to supply power to the light emitting diode, in particular, the semiconductor stack 30, that is, may serve as an electrode of the light emitting diode. Therefore, the support substrate 41 may be a conductive substrate.
  • the support substrate 41 when the support substrate 41 does not operate as an electrode, the support substrate 41 may be an insulating substrate such as a ceramic substrate.
  • the bonding metal layer 120 may include a bonding metal and a barrier metal layer. Therefore, the bonding metal layer 120 is interposed between the supporting substrate 41 and the intermediate insulating layer 33 or the semiconductor stacked structure 30 positioned on the supporting substrate 41 to serve to couple them. Can be. In addition, the bonding metal layer 120 may serve to maintain the reflectivity of the reflective metal layer 31 by preventing metal elements from being diffused from the support substrate 41 to the reflective metal layer 31.
  • the intermediate insulating layer 33 is provided between the bonding metal layer 120 and the semiconductor stacked structure 30.
  • the intermediate insulating layer 33 informs an end point of etching of the plurality of semiconductor layers for forming the semiconductor stacked structure 30 during the process of manufacturing the light emitting diode.
  • the intermediate insulating layer 33 may be made of a material different from that of the semiconductor laminate structure 30, and may be preferably made of a silicon oxide film or a silicon nitride film.
  • a schottky barrier metal layer (not shown) may be further included between the bonding metal layer 120 and the intermediate insulating layer 33.
  • the reflective metal layer 31 is provided between the bonding metal layer 120 and the semiconductor stacked structure 30.
  • the intermediate insulating layer 33 may have an open area, and the reflective metal layer 31 may be filled in the open area of the intermediate insulating layer 33. That is, the intermediate insulating layer 33 and the reflective metal layer 31 may be provided as one layer.
  • the reflective metal layer 31 may include a material in ohmic contact with the n-type semiconductor layer 25.
  • the reflective metal layer 31 is nickel (Ni), platinum (Pt), palladium (Pd), rhodium (Rh), tungsten (W), titanium It may be formed of a material containing (Ti), silver (Ag) or gold (Au).
  • the semiconductor stacked structure 30 may include a p-type semiconductor layer 29, an active layer 27, and an n-type semiconductor layer 25, and the p-type semiconductor layer 29 on the reflective metal layer 31.
  • the active layer 27 may be positioned on the p-type semiconductor layer 29, and the n-type semiconductor layer 25 may be positioned on the active layer 27.
  • the semiconductor laminate 30 may further include a superlattice layer (not shown) or an electron breaking layer (not shown). In this case, the semiconductor stack 30 may be omitted except for the active layer 27.
  • the n-type semiconductor layer 25 may be a III-N-based compound semiconductor doped with a first-type impurity, for example, an N-type impurity, such as an (Al, Ga, In) N-based Group III nitride semiconductor layer.
  • the n-type semiconductor layer 25 may be a GaN layer doped with N-type impurities, that is, an N-GaN layer.
  • the n-type semiconductor layer 25 may be formed in a super lattice structure when a single layer or multiple layers, for example, the n-type semiconductor layer 25 is formed of multiple layers.
  • the active layer 27 may be formed of a III-N series compound semiconductor, for example, an (Al, Ga, In) N semiconductor layer, and the active layer 27 may be formed of a single layer or a plurality of layers, It can emit light.
  • the active layer 27 may have a single quantum well structure including one well layer (not shown), or a multi quantum well having a structure in which a well layer (not shown) and a barrier layer (not shown) are alternately stacked. It may be provided in a structure.
  • the well layer (not shown) or the barrier layer (not shown) may be formed of a superlattice structure, respectively or both.
  • the p-type semiconductor layer 29 may be a III-N-based compound semiconductor doped with a second-type impurity, for example, a P-type impurity, such as (Al, In, Ga) N-based Group III nitride semiconductor.
  • the p-type semiconductor layer 29 may be a GaN layer doped with P-type impurities, that is, a P-GaN layer.
  • the p-type semiconductor layer 29 may be formed of a single layer or multiple layers.
  • the p-type semiconductor layer 29 may have a superlattice structure.
  • the superlattice layer (not shown) may be provided between the n-type semiconductor layer 25 and the active layer 27, a plurality of III-N-based compound semiconductor, for example (Al, Ga, In) N semiconductor layer A layer stacked in layers, for example, an InN layer and an InGaN layer, may be repeatedly stacked.
  • the superlattice layer (not shown) may be formed before forming the active layer 27 to the active layer 27. It is possible to prevent dislocations or defects from being transmitted and to mitigate the formation of dislocations or defects in the active layer 27 and to improve crystallinity of the active layer 27. .
  • the electron breaking layer may be provided between the active layer 27 and the p-type semiconductor layer 29, and may be provided to increase recombination efficiency of electrons and holes, and have a relatively wide band gap. It may be provided as.
  • the electron breaking layer may be formed of a (Al, In, Ga) N-based group III nitride semiconductor, and may be formed of a P-AlGaN layer doped with Mg.
  • the protrusion may include a micro cone 161.
  • the light emitting diode including the micro cone 161 will be described below.
  • the microcones 161 may be provided in plural on the light extraction surface, which is one surface of the semiconductor laminate structure 30. That is, the micro cone 161 may be provided on one surface of the n-type semiconductor layer 25 or the p-type semiconductor layer 29 of the semiconductor stacked structure 30. In an embodiment of the present invention, the microcone 161 is illustrated on the surface of the n-type semiconductor layer 25 and described with reference to the same.
  • the microcones 161 may not be provided in some regions of the n-type semiconductor layer 25. That is, the microcones 161 may be formed on a surface of a region of the n-type semiconductor layer 25 in contact with the n-electrode pad 51, preferably in contact with the n-electrode pad 51. It may not be provided. However, the present invention is not limited thereto.
  • the micro cone 161 may have a circular upper body 161a having a circular shape, and the lower surface 161b having a hexagonal shape.
  • the micro cone 161 may include a pillar surface 161c connecting the upper surface 161a and the lower surface 161b, and the pillar surface 161c may be provided in an inclined shape thereof.
  • microcones 161 are provided in plural on one surface of the semiconductor stack 30, and any one of the microcones 161 is surrounded by six microcones 161. It may be provided in the form.
  • the micro cones 161 may have an average diameter of the upper surface (161a) of 3 ⁇ m.
  • an average separation distance between any one of the microcones 161 and a center point of the neighboring microcones 161 may be 6 ⁇ m, and the average height of the microcons 161 may be 3 ⁇ m.
  • the roughened surface may include a sub micro cone 164.
  • a light emitting diode including the sub micro cone 164 will be described.
  • the sub-micro cones 164 may be provided in plural on the top surface 161a of the micro cones 161. In addition, one or two sub-micro cones 164 may be provided between the micro cones 161.
  • At least one, preferably a plurality of sub-micro cones 164 are provided on the upper surface 161 a of the micro cones 161, and between the micro cones 161. That is, one or two may be provided between one micro cone 161 and six micro cones 161 surrounding the one micro cone 161.
  • the average height of the sub-micro cone 164 may be 0.5 ⁇ m or less.
  • the upper insulating layer 47 may be provided on one surface of the support substrate 41 having the semiconductor stacked structure 30. In this case, the upper insulating layer 47 covers not only one surface of the semiconductor stack 30 but also a side surface thereof to protect the semiconductor stack 30 by preventing the semiconductor stack 30 from being exposed to the outside. can do.
  • the upper insulating layer 47 may be formed of an insulating film such as a silicon oxide film or a silicon nitride film.
  • the upper insulating layer 47 may include an opening 172 that exposes a predetermined region of the n-type semiconductor layer 25.
  • the micro cone 161 or the sub micro cone 164 may not be provided in a predetermined region of the first type semiconductor stacked structure 30 exposed by the upper insulating layer 47.
  • the n-electrode pad 51 may be provided in contact with the n-type semiconductor layer 25 through the opening 172.
  • the n-electrode pad 51 may be connected to a wire (not shown) or a wire (not shown) to supply external power.
  • a light emitting diode has a surface in which light emitted from the active layer 27 of the semiconductor laminate structure 30 is extracted from any one surface of the semiconductor laminate structure 30, That is, the upper surface 161a has a circular shape and the lower surface 161b has a plurality of hexagonal micro cones 161 on the light extraction surface (one surface of the n-type semiconductor layer 25 in this embodiment).
  • the micro-cones 161 are provided in a form of enclosing any one of the micro-cones 161 in six micro-cones 161, the micro-cones (164), the micro-cones ( The upper surface 161a of the 161 is provided with a plurality of sub-micro cones 164, and one or two subs between any one of the micro-cones 161 and the six micro-cones 161 provided to surround the micro-cones 161. Micro Cone 164 is provided.
  • Such a light emitting diode according to an embodiment of the present invention can be seen that the light extraction efficiency is higher than the light emitting diode according to the prior art as shown in FIG.
  • the light emitting diodes according to the prior art show a power Po of an average of 460 mW
  • the light emitting diodes according to an embodiment of the present invention appear to exhibit an average power of 520 mW. It can be seen that they exhibit a high power of about 60 mW compared to the prior art.
  • the light emitting diodes according to the related art are light emitting diodes in which the micro cone 161 and the sub micro cone 164 are not provided as compared with the light emitting diodes according to the exemplary embodiment of the present invention.
  • the light emitting diode according to an embodiment of the present invention has a higher light extraction efficiency than the light emitting diode according to the prior art, which is described above with the micro cone 161 and the sub micro cone (e. 164). This is because the micro cones 161 and the sub micro cones 164 serve to easily extract light reaching the light extraction surface to the outside.
  • 17 to 23 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.
  • a light emitting diode first includes an n-type semiconductor layer 25, an active layer 27, and a semiconductor layer structure 30 for forming a semiconductor stacked structure 30 on a growth substrate 22.
  • a plurality of semiconductor layers including the p-type semiconductor layer 29 are formed.
  • the growth substrate 22 may be a sapphire substrate, a glass substrate, a silicon carbide (SiC) substrate, a silicon (Si) substrate, or the like.
  • the growth substrate 22 may be a gallium nitride substrate.
  • the plurality of semiconductor layers may include a buffer layer (not shown), a superlattice layer (not shown), or an electron breaking layer (not shown).
  • an intermediate insulating layer 33 and a reflective metal layer 31 may be formed on the plurality of semiconductor layers, preferably the p-type semiconductor layer 29.
  • the intermediate insulating layer 33 is formed on a predetermined region on the p-type semiconductor layer 29, and the n-type semiconductor layer 25 is etched by etching the plurality of semiconductor layers including the p-type semiconductor layer 29. ), In forming the semiconductor stacked structure 30 including the active layer 27 and the p-type semiconductor layer 29, serves to inform an end point of etching of the plurality of semiconductor layers. Can be formed of other materials, such as silicon oxide.
  • the intermediate insulating layer 33 may have an open area, and the reflective metal layer 31 may be formed in the open area.
  • the reflective metal layer 31 may be formed by filling an open region of the intermediate insulating layer 33 with a material that is ohmicly coupled to the p-type semiconductor layer 29.
  • a supporting substrate 41 is prepared, and the supporting substrate 41 is formed on one surface of the growth substrate 22 on which the intermediate insulating layer 33 and the reflective metal layer 31 are formed.
  • the support substrate 41 is formed by the support substrate 41 and the reflective metal layer 31 being electrically connected to the support substrate 41 to the intermediate insulating layer 33 or the reflective metal layer 31. Bonding may be performed by a bonding metal layer 120 including a material that may be physically fastened.
  • the growth substrate 110 may be bonded.
  • the semiconductor layer is separated from a plurality of semiconductor layers including the n-type semiconductor layer 25.
  • a buffer layer (not shown) is formed between the growth substrate 110 and the n-type semiconductor layer 25, the growth substrate 110 is separated from the buffer layer (not shown). do.
  • the step of exposing one surface of the n-type semiconductor layer 25 is not only a process for removing the buffer layer (not shown) on the one surface of the n-type semiconductor layer 25, but also the n If the roughness of one surface of the type semiconductor layer 25 is rough, it may include a step of planarization.
  • a photoresist pattern 310 is formed on one surface of the n-type semiconductor layer 25.
  • the photoresist pattern 310 may be provided in a pattern having a circular open area. Since the open area of the photoresist pattern 310 corresponds to the top surface 161a of the micro cone 161 formed thereafter, the open area of the photoresist pattern 310 is formed in a circular shape, and the diameter of the photoresist pattern 310 is also circular. It is preferably formed to correspond to the diameter of the upper surface (161a) of (161).
  • a metal material layer 320 is formed on the n-type semiconductor layer 25 on which the photoresist pattern 310 is formed.
  • the metal material layer 320 may be formed of a single layer or multiple layers including a metal material, preferably, a metal material including a Ti layer / Ni layer.
  • the Ti layer may be formed to a thickness of 500 kPa
  • the Ni layer may be formed to a thickness of 5000 kPa.
  • the photoresist pattern 310 is lifted off.
  • the metal material layer 320 is removed to form the metal pattern 330.
  • the metal pattern 330 removes the photoresist pattern 310 and the metal material layer 330 formed on the photoresist pattern 310 by the lift-off method, and the photoresist pattern 310.
  • the metal material layer 310 formed in the open region 312 may be formed by leaving. Therefore, the metal pattern 330 may be formed in a circular pattern having a predetermined straight line.
  • the n-type semiconductor layer 25 is dry-etched using the metal pattern 330 as a mask, and the upper surface 161a is circular, and the lower surface 161b is a hexagonal pillar-shaped micro cone ( 161 is formed.
  • the micro-cone 161 is formed by dry etching the n-type semiconductor layer 25 with the mask pattern 330. As the etching depth is increased, the etching width is narrowed, and as shown in FIG.
  • the pillar surfaces 161c of the microcones 161 may be provided to meet each other.
  • the metal pattern 330 may be etched together with the etching of the n-type semiconductor layer 25 to form a residual metal pattern 350 having a thin thickness, and by adjusting the thickness of the metal pattern 330.
  • the residual metal pattern 350 may not be left, and the residual metal pattern 350 may be left in a thick thickness.
  • the residual metal pattern 350 is removed.
  • a process of wet etching one surface of the n-type semiconductor layer 25 on which the micro cone 161 is formed may be performed to form the sub micro cone 164.
  • the wet etching may be photoelectrochemical (PEC) etching.
  • the upper surface 161a of the micro cone 161 has a diameter of 3 ⁇ m, and a plurality of sub micro cones 164 having an average height of 0.5 ⁇ m may be formed, while between the micro cones 161. This may be because the spacing of the microcones 161 is densely formed such that one or two submicrocones 164 are formed.
  • a protective pattern (not shown) is formed to protect a predetermined region of the n-type semiconductor layer 25 in which the micro-cone 161 is not formed. Afterwards, the sub-micro cones 164 may be formed.
  • the n-type semiconductor layer 25, the active layer 27, and the p-type semiconductor layer 29 may be included.
  • a plurality of semiconductor layers are etched to form the semiconductor stacked structure 30.
  • the semiconductor stacked structure 30 may be formed by etching the plurality of semiconductor layers until the etch stop pattern layer 140 disposed under the p-type semiconductor layer 29 is exposed. That is, in forming the semiconductor laminate structure 30 by etching the plurality of semiconductor layers, the exposure of the etch stop pattern layer 140 may be used as an etch stop point.
  • an upper insulating layer 47 that protects the semiconductor laminate 30 is formed on the support substrate 41 on which the semiconductor laminate 30 is formed.
  • the upper insulating layer 47 may include an opening 172 exposing a portion of the n-type semiconductor layer 25.
  • an n-electrode pad 51 may be formed to be electrically connected to the n-type semiconductor layer 25 through the opening 152.
  • the microcone 161 and the sub microcone 164 are formed first, and then the semiconductor layers are etched to etch the semiconductor stacked structure 30. ), But before the micro-cones 161 and the sub-micro cones 164 are formed, the process of forming the semiconductor laminate structure 30 by etching the plurality of semiconductor layers is performed first.
  • the microcone 161 and the submicrocone 164 may be formed on one surface of the n-type semiconductor layer 25 of the semiconductor laminate 30.
  • 24 is a cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.
  • 25 and 26 are photographs illustrating a light extraction surface of a light emitting diode according to another embodiment of the present invention.
  • FIG. 27 is a graph showing power versus spacing between micro-conical grooves of a light emitting diode according to another embodiment of the present invention.
  • a light emitting diode may include a support substrate 41, a bonding metal layer 120, an intermediate insulation layer 33, a reflective metal layer 31, and a semiconductor laminate structure 30. , A main pattern including protrusions and recesses, a rough surface, an upper insulating layer 47, and an n-electrode pad 51.
  • the semiconductor stacked structure 30 may include an n-type semiconductor layer 25, an active layer 27, and a p-type semiconductor layer 29.
  • the support substrate 41 serves to support the semiconductor laminate 30.
  • the support substrate 41 may serve to supply power to the light emitting diode, in particular, the semiconductor stack 30, that is, may serve as an electrode of the light emitting diode. Therefore, the support substrate 41 may be a conductive substrate.
  • the support substrate 41 when the support substrate 41 does not operate as an electrode, the support substrate 41 may be an insulating substrate such as a ceramic substrate.
  • the bonding metal layer 120 may include a bonding metal and a barrier metal layer. Therefore, the bonding metal layer 120 is interposed between the supporting substrate 41 and the intermediate insulating layer 33 or the semiconductor stacked structure 30 positioned on the supporting substrate 41 to serve to couple them. Can be. In addition, the bonding metal layer 120 may serve to maintain the reflectivity of the reflective metal layer 31 by preventing metal elements from being diffused from the support substrate 41 to the reflective metal layer 31.
  • the intermediate insulating layer 33 is provided between the bonding metal layer 120 and the semiconductor stacked structure 30.
  • the intermediate insulating layer 33 serves to inform an end point of etching of the plurality of semiconductor layers for forming the semiconductor stacked structure 30 during the process of manufacturing the light emitting diode.
  • the intermediate insulating layer 33 may be formed of a material different from that of the semiconductor stacked structure 30, and may preferably include a silicon oxide film or a silicon nitride film.
  • a schottky barrier metal layer (not shown) may be further included between the bonding metal layer 120 and the intermediate insulating layer 33.
  • the reflective metal layer 31 is provided between the bonding metal layer 120 and the semiconductor stacked structure 30.
  • the intermediate insulating layer 33 may have an open area, and the reflective metal layer 31 may be filled in the open area of the intermediate insulating layer 33. That is, the intermediate insulating layer 33 and the reflective metal layer 31 may be provided as one layer.
  • the reflective metal layer 31 may include a material in ohmic contact with the p-type semiconductor layer 29.
  • the reflective metal layer 31 is nickel (Ni), platinum (Pt), palladium (Pd), rhodium (Rh), tungsten (W), titanium It may be formed of a material containing (Ti), silver (Ag) or gold (Au).
  • the semiconductor stacked structure 30 may include an n-type semiconductor layer 25, an active layer 27, and a p-type semiconductor layer 29, and the p-type semiconductor layer 29 may be disposed on the reflective metal layer 31. May be provided, the active layer 27 may be provided on the p-type semiconductor layer 29, and the n-type semiconductor layer 25 may be provided on the active layer 27.
  • the semiconductor laminate 30 may further include a superlattice layer (not shown) or an electron breaking layer (not shown). In this case, the semiconductor stack 30 may be omitted except for the active layer 27.
  • the n-type semiconductor layer 25 may be a III-N-based compound semiconductor doped with a first-type impurity, for example, an N-type impurity, such as an (Al, Ga, In) N-based Group III nitride semiconductor layer.
  • the n-type semiconductor layer 25 may be a GaN layer doped with N-type impurities, that is, an N-GaN layer.
  • the n-type semiconductor layer 25 may include a super lattice structure when a single layer or multiple layers, for example, the n-type semiconductor layer 25 is formed of multiple layers.
  • the active layer 27 may be formed of a III-N series compound semiconductor, for example, an (Al, Ga, In) N semiconductor layer, and the active layer 27 may be formed of a single layer or a plurality of layers, It can emit light.
  • the active layer 27 may have a single quantum well structure including one well layer (not shown), or a multi quantum well having a structure in which a well layer (not shown) and a barrier layer (not shown) are alternately stacked. It may be provided in a structure.
  • the well layer (not shown) or the barrier layer (not shown) may each or both include a superlattice structure.
  • the p-type semiconductor layer 29 may be a III-N-based compound semiconductor doped with a second-type impurity, for example, a P-type impurity, such as (Al, In, Ga) N-based Group III nitride semiconductor.
  • the p-type semiconductor layer 29 may be a GaN layer doped with P-type impurities, that is, a P-GaN layer.
  • the p-type semiconductor layer 29 may be formed of a single layer or multiple layers.
  • the p-type semiconductor layer 29 may include a superlattice structure.
  • the superlattice layer (not shown) may be provided between the n-type semiconductor layer 25 and the active layer 27, a plurality of III-N-based compound semiconductor, for example (Al, Ga, In) N semiconductor layer A stacked layer, for example, an InN layer and an InGaN layer, may be repeatedly stacked.
  • the superlattice layer (not shown) may be formed before forming the active layer 27 to the active layer 27. It is possible to prevent dislocations or defects from being transmitted and to mitigate the formation of dislocations or defects in the active layer 27 and to improve crystallinity of the active layer 27. .
  • the electron breaking layer may be provided between the active layer 27 and the p-type semiconductor layer 29, and may be provided to increase recombination efficiency of electrons and holes, and have a relatively wide band gap. It may be provided as.
  • the electron breaking layer may be formed of a (Al, In, Ga) N-based group III nitride semiconductor, and may be formed of a P-AlGaN layer doped with Mg.
  • the recess may include a micro cone groove 162.
  • the light emitting diode including the micro cone groove 162 will be described below.
  • the micro-cone groove 162 may be provided in plural on the light extraction surface 160, which is one surface of the semiconductor stacked structure 30. That is, the micro cone groove 162 may be provided on one surface of the n-type semiconductor layer 25 or the p-type semiconductor layer 29 of the semiconductor laminate 30. In an embodiment of the present invention, the micro-cone groove 162 is illustrated on the surface of the n-type semiconductor layer 25 and described with reference to the same.
  • the micro-cone grooves 162 may not be provided in some regions of the n-type semiconductor layer 25.
  • the micro-cone grooves 162 may have a surface corresponding to the n-electrode pad 51, preferably a surface of the n-type semiconductor layer 25 in contact with the n-electrode pad 51. It may not be provided.
  • the micro-conical groove 162 is shown in FIGS. 25 and 26, the inlet of which is polygonal (e.g., the planar shape of the inlet may be hexagonal), the deeper its depth, the smaller its diameter, and the horizontal cross section. May be provided in the form of a polygonal cone formed of a polygon. This may be formed when the n-type semiconductor layer 25 is etched by dry etching.
  • the micro-cone groove 162 may have a diameter of 1 to 10 ⁇ m, preferably 3 ⁇ m, and a depth of 3 to 5 ⁇ m.
  • the micro-cone groove 162 may be provided in plural on the surface of the n-type semiconductor layer 25, and may be provided in a regularly arranged form.
  • the micro-cone grooves 162 are close to the neighboring micro-cone grooves 162, and the micro-cone grooves 162 are preferably provided at a distance of less than 10 ⁇ m.
  • the degree of power improvement of the light emitting diode according to the exemplary embodiment of the present invention decreases.
  • the separation distance between the micro cone grooves 162 is 10 ⁇ m or more, it can be seen that the power is improved by 0.97% compared to the conventional light emitting diode.
  • the power is improved to 0.97%, that is, less than 1% may fall within the process deviation during manufacturing of the light emitting diode, it may be determined that the power is not improved.
  • the micro-cone grooves 162 are preferably formed at a separation distance of at least 10 ⁇ m, since the micro cone-shaped grooves 162 should be provided at a separation distance of less than 10 ⁇ m, thereby improving the power by the micro-cone grooves 162. to be.
  • At least one of the micro-cone grooves 162 is formed by exposing a plurality of crystal planes on the bottom surface 166 of the micro-cone groove 162, preferably six crystal planes. It may be provided in the form.
  • the bottom surface 166 of the micro-cone groove 162 may be a flat surface as shown in FIG. 24, etc., but as shown in FIG. The center portion may be provided in a deeper form than other portions.
  • the roughened surface may include a sub micro cone 164.
  • a light emitting diode including the sub micro cone 164 will be described.
  • the sub-micro cones 164 may be provided in plural on the surface of the n-type semiconductor layer 25 where the micro-cone grooves 162 are not provided. In addition, at least one sub-micro cone 164 may be provided on the bottom surface 166 of the micro cone-shaped groove 162.
  • the sub-micro cones 164 are provided on at least one, preferably plural, surfaces of the n-type semiconductor layer 25. At least one may be provided on the bottom surface 166.
  • the sub-micro cone 164 may have an average diameter of 3 ⁇ m or less, and its height may be 3 ⁇ m on average, preferably 0.5 ⁇ m or less.
  • the upper insulating layer 47 may be provided on one surface of the support substrate 41 having the semiconductor stacked structure 30. In this case, the upper insulating layer 47 covers not only one surface of the semiconductor stack 30 but also a side surface thereof to protect the semiconductor stack 30 by preventing the semiconductor stack 30 from being exposed to the outside. can do.
  • the upper insulating layer 47 may be formed of an insulating film such as a silicon oxide film or a silicon nitride film.
  • the upper insulating layer 47 may include an opening 172 that exposes a predetermined region of the n-type semiconductor layer 25.
  • the micro cone groove 162 or the sub micro cone 164 may not be provided in a predetermined region of the first type semiconductor stacked structure 30 exposed by the upper insulating layer 47.
  • the n-electrode pad 51 may be provided in contact with the n-type semiconductor layer 25 through the opening 172.
  • the n-electrode pad 51 may be connected to a wire (not shown) or a wire (not shown) to supply external power.
  • a light emitting diode has a surface in which light emitted from the active layer 27 of the semiconductor laminate structure 30 is extracted from any one surface of the semiconductor laminate structure 30, That is, a plurality of micro cone grooves 162 are provided on the light extraction surface 160 (one surface of the n-type semiconductor layer 25 in this embodiment), and in addition, the micro cone grooves 162 are not formed.
  • a sub micro cone 164 is provided on the light extraction surface 160 of the region or the bottom surface 166 of the micro cone groove 162.
  • Vf vs. power of a light emitting diode and a conventional light emitting diode is a graph showing Vf vs. power of a light emitting diode and a conventional light emitting diode according to an embodiment of the present invention.
  • 29 is a graph showing wavelength versus power of a light emitting diode and a conventional light emitting diode according to an embodiment of the present invention.
  • Such a light emitting diode according to an embodiment of the present invention can be seen that the light extraction efficiency is higher than the light emitting diode according to the prior art as shown in FIG.
  • the light emitting diodes according to the prior art exhibit an average power of 420.7 mW
  • the light emitting diodes according to the embodiment of the present invention appear to exhibit an average power of 452.3 mW. It can be seen that the light emitting diodes exhibit a higher power of about 30 mW compared to the prior art.
  • the light emitting diodes according to the related art are light emitting diodes without the micro cone groove 162 and the sub micro cone 164 compared to the light emitting diodes according to the exemplary embodiment of the present invention.
  • the light emitting diode according to the exemplary embodiment of the present invention shows that the power is higher than the light emitting diode according to the prior art in the same wavelength band as a whole. Can be.
  • the light emitting diode according to an embodiment of the present invention has a higher light extraction efficiency than the light emitting diode according to the prior art, which is the micro cone groove 162 and the sub micro cone provided on the light extraction surface as described above.
  • the micro cone groove 162 and the sub micro cone 164 serve to easily extract light reaching the light extraction surface to the outside.
  • 30 to 35 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.
  • a light emitting diode first includes an n-type semiconductor layer 25, an active layer 27, and a semiconductor layer structure 30 for forming a semiconductor stacked structure 30 on a growth substrate 22.
  • a plurality of semiconductor layers including the p-type semiconductor layer 29 are formed.
  • the growth substrate 22 may be a sapphire substrate, a glass substrate, a silicon carbide (SiC) substrate, a silicon (Si) substrate, or the like.
  • the growth substrate 22 may be a gallium nitride substrate.
  • the plurality of semiconductor layers may include a buffer layer (not shown), a superlattice layer (not shown), or an electron breaking layer (not shown).
  • an intermediate insulating layer 33 and a reflective metal layer 31 may be formed on the plurality of semiconductor layers, preferably the p-type semiconductor layer 29.
  • the intermediate insulating layer 33 is formed on a predetermined region on the p-type semiconductor layer 29, and the n-type semiconductor layer 25 is etched by etching the plurality of semiconductor layers including the p-type semiconductor layer 29. ), In forming the semiconductor stacked structure 30 including the active layer 27 and the p-type semiconductor layer 29, serves to inform an end point of etching of the plurality of semiconductor layers. May comprise other materials, such as silicon oxide.
  • the intermediate insulating layer 33 may have an open area, and the reflective metal layer 31 may be formed in the open area.
  • the reflective metal layer 31 may be formed by filling an open region of the intermediate insulating layer 33 with a material that is ohmicly coupled to the p-type semiconductor layer 29.
  • the support substrate 41 is prepared, and the support substrate 41 is formed on one surface of the growth substrate 110 on which the intermediate insulating layer 33 and the reflective metal layer 31 are formed.
  • the support substrate 41 is formed by the support substrate 41 and the reflective metal layer 31 being electrically connected to the support substrate 41 to the intermediate insulating layer 33 or the reflective metal layer 31. Bonding may be performed by a bonding metal layer 120 including a material that may be physically fastened.
  • the growth substrate 110 may be bonded.
  • the semiconductor layer is separated from a plurality of semiconductor layers including the n-type semiconductor layer 25.
  • a buffer layer (not shown) is formed between the growth substrate 110 and the n-type semiconductor layer 25, the growth substrate 110 is separated from the buffer layer (not shown). do.
  • the step of exposing one surface of the n-type semiconductor layer 25 is not only a process for removing the buffer layer (not shown) on the one surface of the n-type semiconductor layer 25, but also the n If the roughness of one surface of the type semiconductor layer 25 is rough, it may include a step of planarization.
  • a photoresist pattern (not shown) is formed on one surface of the n-type semiconductor layer 25.
  • the photoresist pattern (not shown) includes an open area and a masking area.
  • the masking area may be formed in a circular shape.
  • An open area of the photoresist pattern (not shown) corresponds to a mask pattern 210 formed thereafter, and the photoresist pattern (not shown) is in the form of the microcone groove 162, in particular, the microcone shape. Forming an appropriate shape by controlling the shape of the inlet of the groove 162.
  • a metal material layer (not shown) is formed on the n-type semiconductor layer 25 on which the photoresist pattern (not shown) is formed.
  • the metal material layer may be formed of a single layer or multiple layers including a metal material, and the metal material may be nickel (Ni), platinum (Pt), palladium (Pd), tungsten (W), or titanium ( Ti) or chromium (Cr).
  • the metal material layer may include a Ti layer / Ni layer, wherein the Ti layer is formed to a thickness of 100 to 600 kPa, preferably 500 kPa, and the Ni layer of 4000 to 8000 kPa. Thickness, preferably 5000 mm.
  • the photoresist pattern (not shown) is removed by a lift-off method to form the metal material layer (not shown) as a mask pattern 210.
  • the mask pattern 210 removes the photoresist pattern (not shown) and the metal material layer (not shown) formed on the photoresist pattern (not shown) by the lift-off method, and the photoresist pattern ( The metal material layer (not shown) formed in the open area of the not shown may be formed by leaving. Accordingly, the mask pattern 210 may be formed in a form in which a region corresponding to the micro cone groove 162 is formed as an open region. In addition, the mask pattern 210 has a surface corresponding to the n-electrode pad 51, preferably a surface of a predetermined region of the n-type semiconductor layer 25 in contact with the n-electrode pad 51. It may be provided in a covering form.
  • the mask pattern 210 may use the photoresist pattern as a mask pattern.
  • the mask pattern 210 is formed on the first semiconductor layer 210 to form an insulating film pattern forming layer (not shown) formed of an insulating material such as silicon oxide or silicon nitride, After the photoresist pattern (not shown) is formed on the insulating film pattern forming layer (not shown), the insulating film pattern forming layer (not shown) is etched using the photoresist pattern (not shown) as a mask, and thus the insulating film pattern ( A mask pattern formed of the photoresist pattern (not shown) and the insulating film pattern (not shown) may be formed to be used.
  • an insulating film pattern forming layer formed of an insulating material such as silicon oxide or silicon nitride
  • the mask pattern 210 may be a pattern made of a photoresist, a pattern including an insulating film and a photoresist, or may be a pattern including a metal material.
  • a description will be made based on a pattern including a metal material, but may be changed to a pattern including the photoresist and a pattern including an insulating film and a photoresist.
  • the n-type semiconductor layer 25 is dry-etched using the mask pattern 210 as a mask to form the micro-cone groove 162.
  • the micro-cone groove 162 may be formed by dry etching the n-type semiconductor layer 25 with the mask pattern 210.
  • the mask pattern 210 may be etched together with the etching of the n-type semiconductor layer 25 to form a residual mask pattern 220 having a thin thickness, and by adjusting the thickness of the mask pattern 210.
  • the residual mask pattern 220 may not be left, and the residual mask pattern 220 may be left to a thick thickness.
  • the residual mask pattern 220 is removed.
  • a process of wet etching one surface of the n-type semiconductor layer 25 having the micro-cone groove 162 to form the sub-micro cone 164 may be performed.
  • the wet etching may be photoelectrochemical (PEC) etching.
  • At least one sub micro cone 164 may be formed on the surface of the n-type semiconductor layer 25 where the micro cone groove 162 is not formed or on the bottom surface 166 of the micro cone groove 162. Plural number is formed.
  • a protection pattern (not shown) is formed to protect a predetermined region of the n-type semiconductor layer 25 in which the micro-cone-shaped groove 162 is not formed. After that, the sub-micro cones 164 may be formed.
  • the n-type semiconductor layer 25, the active layer 27, and the p-type semiconductor layer 29 are included.
  • a plurality of semiconductor layers are etched to form the semiconductor stacked structure 30.
  • the semiconductor stacked structure 30 may be formed by etching the plurality of semiconductor layers until the etch stop pattern 140 disposed under the p-type semiconductor layer 29 is exposed. That is, in forming the semiconductor laminate structure 30 by etching the plurality of semiconductor layers, the exposure of the etch stop pattern 140 may be used as an etch stop point.
  • an upper insulating layer 47 that protects the semiconductor laminate 30 is formed on the support substrate 41 on which the semiconductor laminate 30 is formed.
  • the upper insulating layer 47 may include an opening 172 exposing a portion of the n-type semiconductor layer 25.
  • an n-electrode pad 51 may be formed to be electrically connected to the n-type semiconductor layer 25 through the opening 152.
  • the micro-cone groove 162 and the sub-micro cone 164 are first formed, and then the semiconductor layers are etched to form the semiconductor laminate structure ( 30 is formed, but before forming the micro cone groove 162 and the sub micro cone 164, the process of etching the plurality of semiconductor layers to form the semiconductor stacked structure 30 is performed first. Thereafter, the process of forming the micro cone groove 162 and the sub micro cone 164 on one surface of the n-type semiconductor layer 25 of the semiconductor laminate 30 may be performed.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

La présente invention concerne une diode électroluminescente hautement efficace et un procédé de fabrication de celle-ci. La diode électroluminescente comprend : une structure empilée semi-conductrice disposée sur un substrat de support et comprenant une couche semi-conductrice de type p à base de nitrure de gallium, une couche active à base de nitrure de gallium et une couche semi-conductrice de type n à base de nitrure de gallium ; et une couche réfléchissante disposée entre le substrat de support et la structure empilée semi-conductrice. En outre, la couche empilée semi-conductrice comprend un motif principal ayant une partie en saillie et une partie en creux, et une surface rugueuse formée sur la partie en saillie et la partie en creux du motif principal, et présente une densité des dislocations de 5 × 106/cm2. De plus, la partie en saillie peut comprendre un micro-cône et la partie en creux peut comprendre un trou en forme de micro-cône. En conséquence, il est possible d'obtenir une diode électroluminescente ayant une faible densité des dislocations, tout en ayant une efficacité d'extraction améliorée de la lumière.
PCT/KR2012/009849 2011-11-21 2012-11-21 Diode électroluminescente et son procédé de fabrication WO2013077619A1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
KR10-2011-0121713 2011-11-21
KR1020110121713A KR20130055999A (ko) 2011-11-21 2011-11-21 발광 다이오드 및 그 제조 방법
KR10-2011-0133833 2011-12-13
KR1020110133833A KR20130067014A (ko) 2011-12-13 2011-12-13 발광 다이오드
KR10-2012-0020539 2012-02-28
KR1020120020539A KR20130098760A (ko) 2012-02-28 2012-02-28 고효율 발광 다이오드 및 그것을 제조하는 방법

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TWI686962B (zh) * 2019-04-30 2020-03-01 錼創顯示科技股份有限公司 微型發光元件、結構及其顯示裝置
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