WO2013062397A1

WO2013062397A1 - Design for a support for mounting a microelectronic chip for a 5x3.2 mm half-etched dfn housing with a ground pin

Info

Publication number: WO2013062397A1
Application number: PCT/MA2012/000025
Authority: WO
Inventors: Ouadi SAIDI; Brahim LAKSSIR; Jihad KIWAN; Rachid BENNANI
Original assignee: MOROCCAN FOUNDATION FOR ADVANCED SCIENCE, INNOVATION & RESEARCH (MASclR)
Priority date: 2011-10-26
Filing date: 2012-10-25
Publication date: 2013-05-02
Also published as: MA34203B1; WO2013062397A4

Abstract

The present invention generally relates to lead-frame semiconductor devices designed for housings of the Dual Flat Non-leaded (DFN) family, linked to the process of assembling so-called chip on paddle (COP) chips. Progress made: in a standard production process, semiconductor chips are usually assembled in a DFN housing according to two processes: COP or Chip on Lead (COL). The COP is fitted with a chip centred and 0.2 mm away from the paddle, said paddle being 0.2 mm from the lead, i.e. a total of 0.4 mm. With COL, the centered die can be fitted directly on the leads via a layer of insulating epoxy, provided that the bond pads (the wirebond stacks on the die) are not floating. Depending on the application and environment used, DFN housings designed for the assembly of chips require a limited chip size. In the case of the latest existing 5x3.2 mm² DFN's, the maximum chip size is of the order of 1x0.9 mm².

Description

DESCRIPTION

Microelectronic chip mounting bracket design for a 5x3.2mm DFN housing with a grounding pin

2. Technical field:

Packaging - Microelectronics

3. Previous state:

The existing 5x3.2mm ² DFN Packages, including half-etching technology (semi-engraved lead or paddle extension at mid-height), can mount a maximum size die of 1x0.9mm ²

4. The invention:

The integration of chips larger than the standard in equivalent boxes is difficult or almost impossible.

In the case of a DFN 5x3.2 ² mm package with a PCB footprint (pin placement on the PCB) frozen (see Fig.l):

- Under COP, we can only integrate a die of size 0.54x0.41mm ² ,

- Under COL, it is possible to mount a die in half-etching technology of maximum size 1x0.9mm ² , with a disadvantage of some floating bond-pads.

The proposed solution is a DFN 5x3.2mm ² housing including a semi-etched paddle and connected to the lead connected to the ground, thus allowing the mounting of a larger size off-center chip, ie 1.55x1.05mm ² .

Thanks to this invention and for high-volume manufacturing (HVM), it is possible to provide: ■ S A reduction in manufacturing costs, in view of the replacement of ceramic packages in plastic housings,

The possibility of integrating more boxes on the same printed circuits (PCB), as well as the miniaturization of new products,

Reliability and better electrical performance,

A simplicity of the flow method of assembly process.

5. embodiment:

This invention is based on the design of a lead-frame which serves as a support in the assembly of semiconductor chips, attached via an industrial glue, and connected via wire (wirebond) connecting the off-center chip to ends of the grid. This grid is connected to one of the four pins (paddle) configured to be soldered to a printed circuit board (PCB), thus allowing to have a larger contact area compared to a standard configuration where the chip is centered in the box ( See Fig.3).

The matrix composed of several lead-frame unit (singular connection grid), comprises a dam-bar structure coupling each of the four lead pins that will be exposed and cut during a manufacturing step.

6. Industrial application: The present invention is related to the process of assembly of semiconductor chips called COP, chip deposited on a paddle having precise dimensions respecting certain rules of standard designs in accordance with international standards.

7. Brief description of the drawings: (See Fig. 1, Fig. 2 and Fig. 3)

• Fig.l, presents the two possible configurations of integration of a die under a box DFN (on the right COP and on the left COL),

• Fig.2, presents the simplified solution of a DFN box comprising a semi-etched paddle and connected to the lead connected to the ground, thus allowing the assembly of an off-center chip,

• Fig.3, presents the final solution of the case DFN 5x3.2mm ² including a paddle semi-engraved and connected to the lead connected to the mass, thus allowing the assembly of a decentered chip of size 1.55x1.05mm ² .

Claims

1. A large chip integration device under the COP process in a DFN 5x3.2mm ² package comprising an off-center chip, a semi-etched connection grid and electrically coupled with a pin to the ground, 4 pins that allow to establish the connections of the chip to the PCB and a coating material which covers the chip and the grid of connection.

2. The device of claim 1 wherein the lead frame comprises two faces opposite and symmetrical with respect to this gate.

The device of claim 1 wherein the grid is fully semi-etched except for the four pins, which are the flat portions of the exposed connections at the bottom surface of the package.

4. The device of claim 1 wherein the gate is connected to one of the four pins to allow to have a larger contact area than a standard configuration or the chip is centered in the housing.

5. The device of claim 1 wherein the grid which serves as a support of the die, covers all of the bond-pads and none of them is floating.

6. The device of claim 1 wherein the grid is attached via a die industrial glue, which is in turn connected via wire (wirebond) connecting the off-center chip to the ends of the grid.

7. The device of claim 1 wherein the singular leadframe is basically a matrix composed of several lead-frame units, and comprises a dam-bar structure coupling each of the four lead pins that will be exposed. and cut during a manufacturing step.