MA34203B1 - DESIGN OF A MICROELECTRONIC CHIP MOUNTING BRACKET FOR A 5X3.2 MM SEMI-GRAVE DFN HOUSING WITH A GROUND PIN. - Google Patents
DESIGN OF A MICROELECTRONIC CHIP MOUNTING BRACKET FOR A 5X3.2 MM SEMI-GRAVE DFN HOUSING WITH A GROUND PIN.Info
- Publication number
- MA34203B1 MA34203B1 MA34303A MA34303A MA34203B1 MA 34203 B1 MA34203 B1 MA 34203B1 MA 34303 A MA34303 A MA 34303A MA 34303 A MA34303 A MA 34303A MA 34203 B1 MA34203 B1 MA 34203B1
- Authority
- MA
- Morocco
- Prior art keywords
- chip
- dfn
- cop
- assembly
- grave
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
L'usage de l'invention:la présente invention concerne en général les dispositifs semi-conducteurs de types leadframe conçus pour les boitiers de famille (dfn) dual flat non leaded, lié au processus d'assemblage des puces appelés chip on pad (cop).Les progrès qui ont été faits :dans un processus de fabrication standard, l'assemblage des puces semi-conducteurs dans un boitier dfn se fait habituellement selon deux processus: cop ou chip on lead(col),- le cop est monté avec une puce centrée et éloignée de o.2mm du paddle, qui est à son tour éloignée de o.2mm du lead, soit o.4mm en tout.- avec col, il est possible de monter la die centrée directement sur les leads par l'intermédiaire d'une couche d'époxy isolante, à condition que les bond-pads (les superpositions des wirebonds sur la die) ne soient pas flottants.Selon l'application et l'environnement utilisé, les boitiers dfn conçu pour l'assemblage des puces, exigent une taille de puce limitée en termes de dimensions. Dans le cas des derniers dnf 5x3.2 mm2 existant, la taille de puce est de l'ordre de lxo.9mm2 max.Use of the invention: the present invention generally relates to leadframe type semiconductor devices designed for dual flat non-leaded (dfn) family packages, linked to the chip assembly process called chip on pad (cop ).The progress that has been made: in a standard manufacturing process, the assembly of semiconductor chips in a dfn package is usually done according to two processes: cop or chip on lead (col), - the cop is mounted with a chip centered and o.2mm away from the paddle, which in turn is o.2mm away from the lead, i.e. o.4mm in all.- with collar, it is possible to mount the die centered directly on the leads by l intermediate layer of insulating epoxy, provided that the bond-pads (the superimpositions of the wirebonds on the die) are not floating. Depending on the application and the environment used, the dfn boxes designed for the assembly chips, require a limited chip size in terms of dimensions. In the case of the last existing dnf 5x3.2 mm2, the chip size is of the order of lxo.9mm2 max.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
MA34303A MA34203B1 (en) | 2011-10-26 | 2011-10-26 | DESIGN OF A MICROELECTRONIC CHIP MOUNTING BRACKET FOR A 5X3.2 MM SEMI-GRAVE DFN HOUSING WITH A GROUND PIN. |
PCT/MA2012/000025 WO2013062397A1 (en) | 2011-10-26 | 2012-10-25 | Design for a support for mounting a microelectronic chip for a 5x3.2 mm half-etched dfn housing with a ground pin |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
MA34303A MA34203B1 (en) | 2011-10-26 | 2011-10-26 | DESIGN OF A MICROELECTRONIC CHIP MOUNTING BRACKET FOR A 5X3.2 MM SEMI-GRAVE DFN HOUSING WITH A GROUND PIN. |
Publications (1)
Publication Number | Publication Date |
---|---|
MA34203B1 true MA34203B1 (en) | 2013-05-02 |
Family
ID=47631682
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MA34303A MA34203B1 (en) | 2011-10-26 | 2011-10-26 | DESIGN OF A MICROELECTRONIC CHIP MOUNTING BRACKET FOR A 5X3.2 MM SEMI-GRAVE DFN HOUSING WITH A GROUND PIN. |
Country Status (2)
Country | Link |
---|---|
MA (1) | MA34203B1 (en) |
WO (1) | WO2013062397A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103413801A (en) * | 2013-07-12 | 2013-11-27 | 无锡红光微电子有限公司 | DFN package lead frame |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003086750A (en) * | 2001-09-11 | 2003-03-20 | Rohm Co Ltd | Method for manufacturing electronic device |
US7951651B2 (en) * | 2005-01-05 | 2011-05-31 | Alpha And Omega Semiconductor Incorporated | Dual flat non-leaded semiconductor package |
-
2011
- 2011-10-26 MA MA34303A patent/MA34203B1/en unknown
-
2012
- 2012-10-25 WO PCT/MA2012/000025 patent/WO2013062397A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2013062397A4 (en) | 2013-07-11 |
WO2013062397A1 (en) | 2013-05-02 |
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