KR101458755B1 - wafer level package with the heat spreader and the manufacturing method thereof - Google Patents

wafer level package with the heat spreader and the manufacturing method thereof Download PDF

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KR101458755B1
KR101458755B1 KR20130067623A KR20130067623A KR101458755B1 KR 101458755 B1 KR101458755 B1 KR 101458755B1 KR 20130067623 A KR20130067623 A KR 20130067623A KR 20130067623 A KR20130067623 A KR 20130067623A KR 101458755 B1 KR101458755 B1 KR 101458755B1
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heat spreader
wafer level
semiconductor chip
level package
manufacturing
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KR20130067623A
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Korean (ko)
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김동규
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에스티에스반도체통신 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H01L2023/4037—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink
    • H01L2023/4068—Heatconductors between device and heatsink, e.g. compliant heat-spreaders, heat-conducting bands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The present invention relates to a manufacturing method of a wafer level package with a heat spreader and, more specifically, to a wafer level package with a heat spreader and a manufacturing method thereof. The wafer level package can improve the heat radiating effects of an existing embedded wafer level package (eWLP) and can improve heat radiating effects by forming a thermal via which emits heat by touching the heat spreader with a redistribution substrate.

Description

히트 스프레더를 구비한 웨이퍼 레벨 패키지의 제조방법{wafer level package with the heat spreader and the manufacturing method thereof}BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a wafer level package having a heat spreader,

본 발명은 히트 스프레더를 구비한 웨이퍼 레벨 패키지의 제조방법에 관한 것으로, 더욱 상세하게는 종래 eWLP(embedded wafer level package) 패키지의 낮은 방열 효율을 개선할 수 있으며, 재배선 기판에 히트 스프레더와 접촉하여 열을 방출하는 써멀 비아를 형성함으로써 방열 효율을 높일 수 있는 히트 스프레더를 구비한 웨이퍼 레벨 패키지 및 그 제조방법에 관한 것이다.
The present invention relates to a method of manufacturing a wafer level package having a heat spreader, and more particularly, to a method of manufacturing a wafer level package having a heat spreader, which can improve the low heat dissipation efficiency of a conventional eWLP (embedded wafer level package) The present invention relates to a wafer level package having a heat spreader capable of enhancing heat radiation efficiency by forming a thermal via for emitting heat, and a manufacturing method thereof.

일반적으로 반도체 패키지가 가져야 할 가장 중요한 특성 중의 하나는 반도체 칩에서 발생하는 열의 방출(Thermal dissipation)에 있다.In general, one of the most important characteristics of a semiconductor package is the thermal dissipation of the semiconductor chip.

도 3a는 종래 eWLP(embedded wafer level package) 패키지의 구조를 도시하는 단면도이고, 도 3b는 종래 eWLP(embedded wafer level package) 패키지의 제조방법의 각 공정을 도시하는 단면도이며, 도 3c는 종래 eWLP(embedded wafer level package) 패키지의 제조방법의 각 공정을 도시하는 플로우 차트이다.FIG. 3A is a cross-sectional view illustrating a structure of a conventional eWLP (embedded wafer level package) package, FIG. 3B is a cross-sectional view showing each process of a conventional method of manufacturing an embedded wafer level package (eWLP) embedded wafer level package) package according to the present invention.

도 3a 내지 도 3c를 참조하면, 종래 eWLP(embedded wafer level package) 패키지는 재배선 기판 상에 반도체 칩이 탑재되고, 재배선 기판 및 반도체 칩을 밀봉하는 몰딩부로 이루어진다.3A to 3C, a conventional eWLP (embedded wafer level package) package includes a re-wiring board on which a semiconductor chip is mounted, and a molding part for sealing the re-wiring board and the semiconductor chip.

종래 eWLP(embedded wafer level package) 패키지의 제조방법을 살펴보면, 먼저 일면에 폴리머(polymer material)가 도포된 실리콘 캐리어를 마련하고, 상기 폴리머 상에 반도체 칩을 고정시킨다.Conventionally, a manufacturing method of an embedded wafer level package (eWLP) package is described. First, a silicon carrier coated with a polymer material is provided on one side, and a semiconductor chip is fixed on the polymer.

다음으로, 반도체 칩을 고정시킬 수 있도록 EMC(epoxy molding compound)로 몰딩부를 형성한다.Next, a molding part is formed of an epoxy molding compound (EMC) to fix the semiconductor chip.

그 다음으로, 상기 실리콘 캐리어를 제거한 상태에서 미리 준비한 재배선 기판을 상기 반도체 칩과 전기적으로 접속하고 고정시키게 된다.Next, the rewiring substrate prepared in advance with the silicon carrier removed is electrically connected and fixed to the semiconductor chip.

다만, 이러한 종래 eWLP(embedded wafer level package) 패키지는 열전도성이 낮은 EMC(epoxy molding compound)로 이루어지고, 상기 재배선 기판도 절연체로 이루어지며, 반도체 칩의 상면을 모두 밀봉하기 때문에 열 방출이 원활하게 이루어지지 않는 문제가 있다. 즉 BGA(ball grid array) 패키지와 같이 몰딩부(봉지재) 및 절연체를 활용하기 때문에 열 방출이 원활하지 않은 문제가 있다.
However, the conventional eWLP (embedded wafer level package) package is made of an epoxy molding compound having low thermal conductivity, and the rewiring board is also made of an insulator. Since the upper surface of the semiconductor chip is sealed, There is a problem that can not be achieved. That is, since a molding part (encapsulant) and an insulator are used as in a ball grid array (BGA) package, there is a problem that heat is not smoothly discharged.

공개특허 제10-2005-0077866호 열방출형 반도체 패키지 및 그 제조방법(공개일 : 2005. 08. 04.)Published Japanese Patent Application No. 10-2005-0077866 Thermal Discharge Semiconductor Package and Manufacturing Method Thereof (Published: 2005. 08. 04.)

이에 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 본 발명의 목적은 종래 eWLP(embedded wafer level package) 패키지의 낮은 방열 효율을 개선할 수 있는 히트 스프레더를 구비한 웨이퍼 레벨 패키지 및 그 제조방법을 제공하는 것이다.SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a wafer level package having a heat spreader capable of improving low heat dissipation efficiency of a conventional eWLP (package of an embedded wafer level package) Method.

또한, 본 발명의 목적은 일면은 반도체 칩과 접하고 타면은 외부로 노출된 구조의 히트 스프레더를 구비한 웨이퍼 레벨 패키지 및 그 제조방법을 제공하는 것이다.Another object of the present invention is to provide a wafer level package having a heat spreader having a structure in which one surface is in contact with a semiconductor chip and the other surface is exposed to the outside, and a manufacturing method thereof.

또한, 본 발명의 목적은 재배선 기판에 히트 스프레더와 접촉하여 열을 방출하는 써멀 비아를 형성함으로써 방열 효율을 높일 수 있는 히트 스프레더를 구비한 웨이퍼 레벨 패키지 및 그 제조방법을 제공하는 것이다.
It is also an object of the present invention to provide a wafer level package having a heat spreader capable of increasing heat radiation efficiency by forming a thermal via which is in contact with a heat spreader and discharging heat to a rewiring board, and a manufacturing method thereof.

이를 위해 본 발명에 따른 히트 스프레더를 구비한 웨이퍼 레벨 패키지는 재배선 기판과; 상기 재배선 기판 상에 탑재되는 반도체 칩과; 상기 반도체 칩을 수용하도록 상기 재배선 기판 상에 탑재되는 히트 스프레더(heat spreader)와; 상기 반도체 칩 및 히트 스프레더를 밀봉하는 몰딩부;를 포함하는 것을 특징으로 한다.To this end, a wafer level package having a heat spreader according to the present invention includes a rewiring board; A semiconductor chip mounted on the rewiring board; A heat spreader mounted on the reordering board to receive the semiconductor chip; And a molding part sealing the semiconductor chip and the heat spreader.

또한, 본 발명에 따른 히트 스프레더를 구비한 웨이퍼 레벨 패키지의 히트 스프레더는 상기 반도체 칩의 상면에 부착되는 것을 특징으로 한다.The heat spreader of the wafer level package having the heat spreader according to the present invention is attached to the upper surface of the semiconductor chip.

또한, 본 발명에 따른 히트 스프레더를 구비한 웨이퍼 레벨 패키지의 히트 스프레더는 상기 반도체 칩의 상부에 위치하는 중앙부와, 상기 중앙부에서 연장되어 상기 재배선 기판에 부착되는 테두리부를 포함하는 것을 특징으로 한다.The heat spreader of the wafer level package having the heat spreader according to the present invention includes a center portion located on the semiconductor chip and a rim extending from the center portion and attached to the rewiring board.

또한, 본 발명에 따른 히트 스프레더를 구비한 웨이퍼 레벨 패키지의 히트 스프레더의 중앙부는 상면이 외부에 노출되고, 하면은 상기 반도체 칩에 접촉되는 것을 특징으로 한다.The center portion of the heat spreader of the wafer level package having the heat spreader according to the present invention is characterized in that the upper surface is exposed to the outside and the lower surface is contacted to the semiconductor chip.

또한, 본 발명에 따른 히트 스프레더를 구비한 웨이퍼 레벨 패키지의 히트 스프레더의 테두리부는 몰딩부의 외측으로 노출되는 것을 특징으로 한다.The edge of the heat spreader of the wafer level package having the heat spreader according to the present invention is exposed to the outside of the molding part.

또한, 본 발명에 따른 히트 스프레더를 구비한 웨이퍼 레벨 패키지의 재배선 기판은 상기 히트 스프레더의 테두리부와 접속되는 써멀 비아(thermal via)가 형성되는 것을 특징으로 한다.The rewiring board of the wafer level package having the heat spreader according to the present invention is characterized in that a thermal via connected to the rim of the heat spreader is formed.

또한, 본 발명에 따른 스프레더를 구비한 웨이퍼 레벨 패키지의 제조방법은 히트 스프레더 및 캐리어(carrier)를 마련하는 S1단계와; 상기 히트 스프레더의 일면에는 반도체 칩을 부착하고, 타면에는 상기 캐리어를 부착하는 S2단계와; 상기 히트 스프레더 및 반도체 칩을 밀봉하도록 몰딩부를 형성하는 S3단계와; 상기 캐리어를 제거하는 S4단계와; 재배선 기판을 마련하여 상기 히트 스프레더 및 반도체 칩에 부착시키는 S5단계;를 포함하는 것을 특징으로 한다.A method of manufacturing a wafer level package having a spreader according to the present invention includes: a step S1 of providing a heat spreader and a carrier; A step S2 of attaching a semiconductor chip to one surface of the heat spreader and attaching the carrier to the other surface; Forming a molding part to seal the heat spreader and the semiconductor chip; Removing the carrier; And a step S5 of providing a rewiring substrate and attaching the rewiring substrate to the heat spreader and the semiconductor chip.

또한, 본 발명에 따른 스프레더를 구비한 웨이퍼 레벨 패키지의 제조방법의 히트 스프레더는 상기 반도체 칩의 상부에 위치하는 중앙부와, 상기 중앙부에서 연장되어 상기 재배선 기판에 부착되는 테두리부를 포함하는 것을 특징으로 한다.The heat spreader in the method of manufacturing a wafer level package having a spreader according to the present invention includes a central portion located on the semiconductor chip and a rim extending from the central portion to be attached to the re- do.

또한, 본 발명에 따른 스프레더를 구비한 웨이퍼 레벨 패키지의 제조방법의 S2단계는 상기 반도체 칩은 점착부재를 이용하여 상기 히트 스프레더에 부착되는 것을 특징으로 한다.In the step S2 of the method for manufacturing a wafer level package having a spreader according to the present invention, the semiconductor chip is attached to the heat spreader using an adhesive member.

또한, 본 발명에 따른 스프레더를 구비한 웨이퍼 레벨 패키지의 제조방법의 S3단계의 몰딩부는 상기 중앙부의 상면이 노출되도록 형성되는 것을 특징으로 한다.The molding part of step S3 of the method of manufacturing a wafer level package having a spreader according to the present invention is characterized in that an upper surface of the center part is exposed.

또한, 본 발명에 따른 스프레더를 구비한 웨이퍼 레벨 패키지의 제조방법의 재배선 기판은 상기 히트 스프레더의 테두리부와 접속되는 써멀 비아(thermal via)가 형성되는 것을 특징으로 한다.
The rewiring board of the method of manufacturing a wafer level package having a spreader according to the present invention is characterized in that a thermal via connected to the rim of the heat spreader is formed.

이상과 같은 구성의 본 발명에 따른 히트 스프레더를 구비한 웨이퍼 레벨 패키지 및 그 제조방법은 종래 eWLP(embedded wafer level package) 패키지의 낮은 방열 효율을 개선 할 수 있는 효과가 있다.The wafer-level package including the heat spreader according to the present invention having the above-described structure and the manufacturing method thereof have the effect of improving the low heat dissipation efficiency of the conventional eWLP (embedded wafer level package) package.

또한, 본 발명에 따른 히트 스프레더를 구비한 웨이퍼 레벨 패키지 및 그 제조방법은 일면은 반도체 칩과 접하고 타면은 외부로 노출되어 열방출이 용이한 구조로 이루어진다.A wafer level package having a heat spreader and a method of manufacturing the same according to the present invention has a structure in which one surface is in contact with a semiconductor chip and the other surface is exposed to the outside to facilitate heat dissipation.

또한, 본 발명에 따른 히트 스프레더를 구비한 웨이퍼 레벨 패키지 및 그 제조방법은 재배선 기판에 히트 스프레더와 접촉하여 열을 방출하는 써멀 비아를 형성함으로써 방열 효율을 더욱 높일 수 있다.
In addition, the wafer level package including the heat spreader according to the present invention and the method of manufacturing the same can further improve the heat radiation efficiency by forming a thermal via which is in contact with the heat spreader to heat the rewiring board.

도 1은 본 발명에 따른 히트 스프레더를 구비한 웨이퍼 레벨 패키지의 일실시예를 도시하는 단면도이다.
도 2a 내지 도 2f는 본 발명에 따른 스프레더를 구비한 웨이퍼 레벨 패키지의 제조방법의 각 공정을 도시하는 단면도이다.
도 3a는 종래 eWLP(embedded wafer level package) 패키지의 구조를 도시하는 단면도이고, 도 3b는 종래 eWLP(embedded wafer level package) 패키지의 제조방법의 각 공정을 도시하는 단면도이며, 도 3c는 종래 eWLP(embedded wafer level package) 패키지의 제조방법의 각 공정을 도시하는 플로우 차트이다.1 is a cross-sectional view showing an embodiment of a wafer level package having a heat spreader according to the present invention.
2A to 2F are cross-sectional views showing respective steps of a method of manufacturing a wafer level package having a spreader according to the present invention.
FIG. 3A is a cross-sectional view illustrating a structure of a conventional eWLP (embedded wafer level package) package, FIG. 3B is a cross-sectional view showing each process of a conventional method of manufacturing an embedded wafer level package (eWLP) embedded wafer level package) package according to the present invention.

이하, 첨부 도면을 참조하여 본 발명의 실시 예를 상세히 설명하면 다음과 같다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명을 설명함에 있어서, 관련된 공지기능 혹은 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우 그 상세한 설명은 생략한다. 또한, 후술되는 용어들은 본 발명에서의 기능을 고려하여 정의된 용어들로서 이는 사용자, 운용자의 의도 또는 판례 등에 따라 달라질 수 있다. 그러므로 그 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다.
In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the terms described below are defined in consideration of the functions of the present invention, and these may vary depending on the intention of the user, the operator, or the precedent. Therefore, the definition should be based on the contents throughout this specification.

도 1은 본 발명에 따른 히트 스프레더를 구비한 웨이퍼 레벨 패키지의 일실시예를 도시하는 단면도이다.1 is a cross-sectional view showing an embodiment of a wafer level package having a heat spreader according to the present invention.

도 1을 참조하면, 본 발명에 따른 히트 스프레더를 구비한 웨이퍼 레벨 패키지(100)는 팬 아웃(fan out) 구조의 eWLP(embedded wafer level package)에 적용되는 것이 특징이다.Referring to FIG. 1, a wafer level package 100 having a heat spreader according to the present invention is applied to an embedded wafer level package (eWLP) having a fan-out structure.

본 발명의 히트 스프레더를 구비한 웨이퍼 레벨 패키지(100)는 크게 재배선 기판(120)과, 반도체 칩(110)과, 히트 스프레더(130)(heat spreader)와, 몰딩부(150)를 포함할 수 있다.The wafer level package 100 having the heat spreader of the present invention includes the rewiring board 120, the semiconductor chip 110, the heat spreader 130, and the molding part 150 .

구체적으로, 본 발명의 히트 스프레더를 구비한 웨이퍼 레벨 패키지(100)는 재배선 기판(120)과, 상기 재배선 기판(120) 상에 탑재되는 반도체 칩(110)과, 상기 반도체 칩(110)을 수용하도록 상기 재배선 기판(120) 상에 탑재되는 히트 스프레더(130)(heat spreader)와, 상기 반도체 칩(110) 및 히트 스프레더(130)를 밀봉하는 몰딩부(150)를 포함할 수 있다.The semiconductor chip 110 is mounted on the rewiring board 120. The semiconductor chip 110 is mounted on the rewiring board 120. The semiconductor chip 110 is mounted on the rewiring board 120, A heat spreader 130 mounted on the reordering board 120 to receive the semiconductor chip 110 and a molding unit 150 sealing the semiconductor chip 110 and the heat spreader 130 .

상기 재배선 기판(120)은 절연물질로 이루어지는 기판부(121)와, 상기 기판부(121)에 형성되는 재배선 패턴부(123)(RDL:redistributed layer)와, 상기 재배선 패턴부(123)와 전기적으로 접속하는 솔더범프(125a)를 포함할 수 있다.The redistribution substrate 120 includes a substrate portion 121 formed of an insulating material, a redistribution layer 123 formed on the substrate portion 121, and a redistribution layer 123 formed on the redistribution pattern portion 123 And a solder bump 125a electrically connected to the solder bump 125a.

상기 반도체 칩(110)은 상기 재배선 기판(120)에 탑재되고, 일면에 접속패드(111)가 형성되어 상기 재배선 패턴부(123)와 전기적으로 접속된다.The semiconductor chip 110 is mounted on the redistribution board 120 and a connection pad 111 is formed on one side of the redistribution board 120 to be electrically connected to the redistribution pattern part 123.

상기 히트 스프레더(130)는 상기 반도체 칩(110)에서 발생된 열을 외부로 방출시키는 역할을 하는 것이다. 따라서, 상기 히트 스프레더(130)는 상기 반도체 칩(110)의 상면에 부착되는 것이 바람직하다.The heat spreader 130 serves to discharge heat generated from the semiconductor chip 110 to the outside. Accordingly, it is preferable that the heat spreader 130 is attached to the upper surface of the semiconductor chip 110.

다만, 상기 반도체 칩(110)과 히트 스프레더(130)는 TIM(113)(Thermal Interface Material)으로 밀접하게 접촉된다.However, the semiconductor chip 110 and the heat spreader 130 are closely contacted by the TIM 113 (Thermal Interface Material).

상기 히트 스프레더(130)는 중앙부(131)와, 테두리부(133)를 포함할 수 있다.The heat spreader 130 may include a central portion 131 and a rim portion 133.

구체적으로, 상기 히트 스프레더(130)는 상기 반도체 칩(110)의 상부에 위치하는 중앙부(131)와, 상기 재배선 기판(120)에 부착되는 테두리부(133)와, 일단은 상기 중앙부(131)에서 하측으로 절곡되고 타단은 상기 테두리부(133)에 연결되는 연결부(132)를 포함할 수 있다.Specifically, the heat spreader 130 includes a central portion 131 located on the upper side of the semiconductor chip 110, a rim 133 attached to the re-wiring board 120, And the other end of which is connected to the rim 133. The connection part 132 may be formed of a metal such as copper or stainless steel.

상기 중앙부(131)는 상면이 외부에 노출되고, 하면은 상기 반도체 칩(110)에 접촉되도록 구성하여 열 방출 효율을 높이는 것이 바람직하다.It is preferable that the center portion 131 is exposed to the outside and the bottom surface is brought into contact with the semiconductor chip 110 to increase heat dissipation efficiency.

마찬가지로, 상기 히트 스프레더(130)의 테두리부(133)는 몰딩부(150)의 외측으로 노출되도록 구성하는 것이 바람직하다.Similarly, it is preferable that the rim portion 133 of the heat spreader 130 is exposed to the outside of the molding portion 150.

한편, 상기 재배선 기판(120)에는 써멀 비아(127)(thermal via)를 형성할 수 있다. 상기 써멀 비아(127)는 상기 기판부(121)를 관통하고 일단은 솔더범프(125)와 접촉되고 타단은 상기 히트 스프레더(130)의 테두리부(133)와 접촉되도록 구성하는 것이 바람직하다.Meanwhile, a thermal via 127 may be formed on the rewiring board 120. The thermal via 127 may be formed so as to penetrate through the substrate 121 and be in contact with the solder bump 125 at one end and be in contact with the rim 133 of the heat spreader 130 at the other end.

상기 반도체 칩(110)에서 발생한 열의 일부는 노출된 상기 중앙부(131)를 통해 방출되고, 나머지 일부는 상기 테두리부(133)로 전달되어 테두리부(133)의 노출된 단부와 상기 써멀 비아(127)를 통해 방출된다.A part of the heat generated in the semiconductor chip 110 is discharged through the exposed central portion 131 and the remaining portion is transmitted to the rim portion 133 and the exposed end of the rim portion 133 and the thermal via 127 Lt; / RTI >

이와 같이, 종래 eWLP(embedded wafer level package) 패키지는 반도체 칩을 밀봉하는 EMC(epoxy molding compound) 몰딩부의 낮은 열전도율로 인해 열 방출 효율이 낮았으나, 본 발명에 따른 히트 스프레더를 구비한 웨이퍼 레벨 패키지는 히트 스프레더를 설치함으로써, 열 방출을 효율적으로 할 수 있는 장점이 있다.
As described above, the conventional eWLP (embedded wafer level package) package has low heat dissipation efficiency due to the low thermal conductivity of the epoxy molding compound part (EMC) which encapsulates the semiconductor chip. However, the wafer level package with the heat spreader according to the present invention By providing a heat spreader, there is an advantage that heat can be efficiently discharged.

이하에서는 본 발명에 따른 스프레더를 구비한 웨이퍼 레벨 패키지의 제조방법를 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a wafer level package having a spreader according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2f는 본 발명에 따른 스프레더를 구비한 웨이퍼 레벨 패키지의 제조방법의 각 공정을 도시하는 단면도로서, S1단계 내지 S5단계로 이루어질 수 있다.FIGS. 2A to 2F are cross-sectional views illustrating respective steps of a method of manufacturing a wafer level package having a spreader according to the present invention, and may include steps S1 to S5.

도 2a를 참조하면, S1단계는 히트 스프레더(130) 및 캐리어(170)(carrier)를 마련하는 단계이다.Referring to FIG. 2A, in step S1, a heat spreader 130 and a carrier 170 are provided.

상기 히트 스프레더(130)는 반도체 칩(110)을 수용하는 중앙부(131)와, 상기 중앙부(131)에서 연장되어 상기 재배선 기판(120)에 부착되는 테두리부(133)를 포함할 수 있다.The heat spreader 130 may include a central portion 131 for receiving the semiconductor chip 110 and a rim 133 extending from the central portion 131 and attached to the re-wiring board 120.

상기 중앙부(131)와 테두리부(133)에는 단차가 형성되고, 상기 단차는 상기 반도체 칩의 두께와 대응되도록 구성한다.A step is formed in the central part 131 and the rim 133, and the step corresponds to the thickness of the semiconductor chip.

상기 중앙부(131)의 일면에는 TIM(113)(Thermal Interface Material)이 부착되고, 상기 TIM(113)에는 반도체 칩(110)의 상면이 부착된다.A thermal interface material (TIM) 113 is attached to one surface of the central portion 131 and an upper surface of the semiconductor chip 110 is attached to the TIM 113.

상기 캐리어(170)는 실리콘으로 이루어질 수 있으며 일면에는 접착 및 탈착이 용이한 점착부재(171)가 부착된다.The carrier 170 may be made of silicon, and an adhesive member 171 is attached to one side of the carrier 170 to facilitate adhesion and detachment.

도 2b를 참조하면, S2단계는 상기 히트 스프레더(130)의 일면에는 반도체 칩(110)을 부착하고, 타면에는 상기 캐리어(170)를 부착하는 단계이다.Referring to FIG. 2B, step S2 is a step of attaching the semiconductor chip 110 to one surface of the heat spreader 130 and attaching the carrier 170 to the other surface.

즉, 상기 반도체 칩(110)을 상기 중앙부(131)의 일면에 부착된 TIM(113)을 통해 고정한 후, 상기 캐리어(170)를 일면에 부착된 점착부재(171)로 상기 반도체 칩(110) 및 히트 스프레더(130)에 각각 부착한다.That is, after the semiconductor chip 110 is fixed through the TIM 113 attached to one side of the central portion 131, the semiconductor chip 110 is bonded to the carrier 170 with the adhesive member 171 attached to one side, And the heat spreader 130, respectively.

도 2c를 참조하면, S3단계는 상기 히트 스프레더 및 반도체 칩을 밀봉하도록 몰딩부를 형성하는 단계이다.Referring to FIG. 2C, step S3 is a step of forming the molding part to seal the heat spreader and the semiconductor chip.

상기 몰딩부(150)는 EMC(epoxy molding compound)로 밀봉하여 반도체 칩을 보호하는 역할을 한다.The molding part 150 is sealed with an epoxy molding compound (EMC) to protect the semiconductor chip.

이때, 상기 몰딩부(150)는 히트 스프레더(130)의 상면, 구체적으로 중앙부 상면이 외부로 노출되도록 형성되는 것이 바람직하다.At this time, the molding part 150 is preferably formed to expose the upper surface of the heat spreader 130, specifically, the upper surface of the central part.

도 2d를 참조하면, S4단계는 상기 캐리어(170)를 제거하는 단계로서, 상기 캐리어(170)가 점착부재(171)에 부착되기 때문에 간단하게 제거할 수 있다.Referring to FIG. 2D, the step S4 is a step of removing the carrier 170, which can be simply removed because the carrier 170 is attached to the adhesive member 171. FIG.

도 2e를 참조하면, S5단계는 재배선 기판(120)을 마련하여 상기 히트 스프레더(130) 및 반도체 칩(110)에 부착하는 단계이다.Referring to FIG. 2E, step S5 is a step of providing a rewiring board 120 and attaching the rewiring board 120 to the heat spreader 130 and the semiconductor chip 110.

상기 재배선 기판(120)은 상술한 바와 같이, 절연물질로 이루어지는 기판부(121)와, 상기 기판부(121)에 형성되는 재배선 패턴부(123)(RDL:redistributed layer)와, 상기 재배선 패턴부(123)와 전기적으로 접속하는 솔더범프(125)를 포함할 수 있다. 그리고, 상기 기판부(121)에는 일단은 솔더범프(125)와 접촉되고 타단은 상기 히트 스프레더(130)의 테두리부(133)와 접촉되는 써멀 비아(127)(thermal via)가 형성될 수 있다.The redistribution substrate 120 includes a substrate 121 made of an insulating material, a redistributed layer 123 formed on the substrate 121, And a solder bump 125 electrically connected to the line pattern portion 123. A thermal via 127 may be formed on the substrate 121 so that one end thereof is in contact with the solder bump 125 and the other end is in contact with the rim 133 of the heat spreader 130 .

이때, 상기 재배선 패턴부(123)는 일측은 상기 반도체 칩(110)의 접속패드(111)와 접속되고, 타측은 솔더범프(125)와 접속된다.At this time, one side of the rewiring pattern part 123 is connected to the connection pad 111 of the semiconductor chip 110, and the other side is connected to the solder bump 125.

도 2f를 참조하면, S5단계 이후 개개의 패키지로 절단함으로써, 웨이퍼 레벨 패키지의 제조가 완료된다.
Referring to FIG. 2F, after step S5, the individual packages are cut to complete the manufacture of the wafer level package.

한편, 본 발명의 상세한 설명 및 첨부도면에서는 구체적인 실시예에 관해 설명하였으나, 본 발명은 개시된 실시예에 한정되지 않고 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다. 따라서, 본 발명의 범위는 설명된 실시예에 국한되어 정해져서는 안되며 후술하는 특허청구범위뿐만 아니라 이 특허청구범위와 균등한 것들을 포함하는 것으로 해석되어야 할 것이다.
While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and similarities. Accordingly, the scope of the present invention should be construed as being limited to the embodiments described, and it is intended that the scope of the present invention encompasses not only the following claims, but also equivalents thereto.

100 : 웨이퍼 레벨 패키지 110 : 반도체 칩
111 : 접속패드 113 : TIM
120 : 재배선 기판 121 : 기판부
123 : 재배선 패턴부 125 : 솔더범프
127 : 써멀 비아 130 : 히트 스프레더
131 : 중앙부 133 : 테두리부
150 : 몰딩부 170 : 캐리어
171 : 점착부재100: wafer level package 110: semiconductor chip
111: connection pad 113: TIM
120: rewiring board 121: substrate portion
123: rewiring pattern part 125: solder bump
127: thermal via 130: heat spreader
131: central portion 133:
150: molding part 170: carrier
171: Adhesive member

Claims (11)

삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 히트 스프레더 및 캐리어(carrier)를 마련하는 S1단계와;
상기 히트 스프레더의 일면에는 반도체 칩을 부착하고, 타면에는 상기 캐리어를 부착하는 S2단계와;
상기 히트 스프레더 및 반도체 칩을 밀봉하도록 몰딩부를 형성하는 S3단계와;
상기 캐리어를 제거하는 S4단계와;
재배선 기판을 마련하여 상기 히트 스프레더 및 반도체 칩에 부착시키는 S5단계;를 포함하되,
상기 히트 스프레더는 상기 반도체 칩의 상부에 위치하는 중앙부와, 상기 재배선 기판에 부착되는 테두리부와, 일단은 상기 중앙부에서 하측으로 절곡되고 타단은 상기 테두리부에 연결되는 연결부를 포함하며,
상기 S3단계의 몰딩부는 상기 중앙부의 상면이 노출되고,
상기 S5단계에서 테두리부는 상기 재배선 기판에 형성되는 써멀 비아(thermal via)에 접속되는 것을 특징으로 하는 스프레더를 구비한 웨이퍼 레벨 패키지의 제조방법.A step S1 of providing a heat spreader and a carrier;
A step S2 of attaching a semiconductor chip to one surface of the heat spreader and attaching the carrier to the other surface;
Forming a molding part to seal the heat spreader and the semiconductor chip;
Removing the carrier;
And a step S5 of providing a rewiring substrate and attaching the rewiring substrate to the heat spreader and the semiconductor chip,
Wherein the heat spreader includes a central portion located on an upper portion of the semiconductor chip, a rim portion attached to the rewiring board, and a connection portion having one end bent downward from the central portion and the other end connected to the rim portion,
The molding part of step S3 exposes the upper surface of the central part,
Wherein the rim is connected to a thermal via formed on the reordering board in the step S5. 삭제delete 제7항에 있어서,
상기 S2단계는 상기 반도체 칩은 점착부재를 이용하여 상기 히트 스프레더에 부착되는 것을 특징으로 하는 스프레더를 구비한 웨이퍼 레벨 패키지의 제조방법.

8. The method of claim 7,
Wherein the semiconductor chip is attached to the heat spreader using an adhesive member in step S2.

삭제delete 삭제delete
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KR101162503B1 (en) * 2010-09-08 2012-07-05 앰코 테크놀로지 코리아 주식회사 Heat slug and semiconductor package using the same

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Publication number Priority date Publication date Assignee Title
US20110278705A1 (en) * 2009-08-14 2011-11-17 Stats Chippac, Ltd. Semiconductor Device and Method of Mounting Semiconductor Die to Heat Spreader on Temporary Carrier and Forming Polymer Layer and Conductive Layer Over the Die
KR101162503B1 (en) * 2010-09-08 2012-07-05 앰코 테크놀로지 코리아 주식회사 Heat slug and semiconductor package using the same

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Publication number Priority date Publication date Assignee Title
CN116169113A (en) * 2023-04-21 2023-05-26 江苏芯德半导体科技有限公司 QFN packaging structure capable of reducing heat conduction to PCB and preparation method thereof
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