WO2013051344A1 - Dispositif à semi-conducteurs en carbure de silicium et son procédé de fabrication - Google Patents

Dispositif à semi-conducteurs en carbure de silicium et son procédé de fabrication Download PDF

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WO2013051344A1
WO2013051344A1 PCT/JP2012/070740 JP2012070740W WO2013051344A1 WO 2013051344 A1 WO2013051344 A1 WO 2013051344A1 JP 2012070740 W JP2012070740 W JP 2012070740W WO 2013051344 A1 WO2013051344 A1 WO 2013051344A1
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layer
region
silicon carbide
semiconductor device
conductivity type
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Japanese (ja)
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林　秀樹
増田　健良
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住友電気工業株式会社
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1058—Channel region of field-effect devices of field-effect transistors with PN junction gate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the present invention relates to a silicon carbide semiconductor device and a manufacturing method thereof, and more specifically to a silicon carbide semiconductor device which is a lateral junction field effect transistor and a manufacturing method thereof.
  • RESURF-JFET Reduced SURface Field-Junction Field Effect Transistor: surface field relaxation junction field effect transistor
  • SiC silicon carbide
  • the gate region is formed by ion implantation.
  • the variation in the thickness of the channel layer immediately below the gate region and the variation in the impurity concentration in the boundary region between the gate region and the channel layer become large. Therefore, the threshold voltage varies greatly.
  • the present invention has been made to solve the above-described problems, and is to provide a silicon carbide semiconductor device capable of reducing variations in threshold voltage and a method for manufacturing the same.
  • a silicon carbide semiconductor device includes a substrate, a silicon carbide layer provided on the substrate and having a main surface and a thickness direction intersecting the main surface.
  • the silicon carbide layer includes a channel layer having the first conductivity type, a source region having the first conductivity type and extending from the main surface into the channel layer along the thickness direction, and the first conductivity type
  • a drain region that extends from the main surface along the thickness direction into the channel layer and sandwiches the channel layer between the source region in the opposite direction intersecting the thickness direction, and the source region and the drain And a gate region extending from the main surface into the channel layer along the thickness direction.
  • the gate region is epitaxially grown with respect to the channel layer so as to have a second conductivity type different from the first conductivity type.
  • “provided on the substrate” may be either directly provided on the substrate or provided on the substrate via another layer.
  • the gate region is formed by ion implantation, it is difficult to control the depth of ion implantation. Therefore, variations in the thickness of the channel layer immediately below the gate region and variations in the impurity concentration in the boundary region between the gate region and the channel layer occur. growing. Therefore, the threshold voltage of the semiconductor device varies.
  • the gate region is formed not by ion implantation but by an epitaxial film. Therefore, since variations due to ion implantation do not occur, variations in threshold voltage can be reduced.
  • the first conductivity type is preferably n-type.
  • the conductivity type of the channel layer becomes n-type. Therefore, electrons having a higher mobility than holes can be used as main carriers flowing in the channel layer. Therefore, the on-resistance is reduced.
  • the above silicon carbide semiconductor device further includes an epitaxial layer connecting the source region and the drain region along the opposing direction on the channel layer provided with the gate region and having the second conductivity type.
  • the RESURF structure is provided on the channel layer by the epitaxial layer, the breakdown voltage is higher than that in the case where there is no RESURF structure. Therefore, the impurity concentration of the channel layer can be made relatively high. Thereby, the on-resistance can be further reduced.
  • the channel layer is provided on the first layer with the first impurity concentration, penetrated by the gate region, and has the second impurity concentration. And a second layer.
  • the second impurity concentration is higher than the first impurity concentration.
  • the threshold voltage is mainly determined by the first impurity concentration of the first layer
  • the first impurity concentration is determined by the required threshold voltage.
  • the second impurity concentration of the second layer has a smaller influence on the threshold voltage than the first impurity concentration of the first layer. Therefore, by making the second impurity concentration higher than the first impurity concentration, the on-resistance can be lowered without significantly affecting the threshold voltage.
  • the dimension along the facing direction of the gate region decreases as the distance from the main surface increases.
  • the method for manufacturing a silicon carbide semiconductor device includes the following steps.
  • a first layer having the first conductivity type is epitaxially formed on the substrate.
  • a gate layer having a second conductivity type different from the first conductivity type is epitaxially formed on the first layer.
  • By patterning the gate layer a gate region is formed on a portion of the first layer.
  • a second layer having the first conductivity type is epitaxially formed on the first layer provided with the gate region.
  • a channel layer having the first and second layers and a gate region penetrating the second layer are formed on the substrate.
  • a silicon carbide layer having a surface and a thickness direction intersecting with the main surface is formed.
  • a source region and a drain region are provided in the silicon carbide layer.
  • the step of providing the source region and the drain region is performed such that each of the source region and the drain region has the first conductivity type and extends from the main surface along the thickness direction into the channel layer, and the source region
  • the drain region is formed so as to sandwich a gate region extending so as to protrude into the channel layer between the source region and the drain region in the opposite direction intersecting the thickness direction.
  • “on the substrate” may be either directly on the substrate or via another layer on the substrate.
  • the gate region is formed by ion implantation, it is difficult to control the depth of ion implantation. Therefore, variations in the thickness of the channel layer immediately below the gate region and variations in the impurity concentration in the boundary region between the gate region and the channel layer occur. growing. Therefore, the threshold voltage of the semiconductor device varies.
  • the gate region is formed not by ion implantation but by an epitaxial film. Therefore, since variations due to ion implantation do not occur, variations in threshold voltage can be reduced.
  • the first conductivity type is n-type.
  • an epitaxial layer having the second conductivity type is preferably formed on the silicon carbide layer.
  • the step of providing the source region and the drain region is performed so that each of the source region and the drain region penetrates the epitaxial layer.
  • the RESURF structure is provided on the channel layer by the epitaxial layer, the breakdown voltage is higher than that in the case where there is no RESURF structure. Therefore, the impurity concentration of the channel layer can be made relatively high. Thereby, the on-resistance can be further reduced.
  • each of the first and second layers has a first impurity concentration and a second impurity concentration.
  • the second impurity concentration is higher than the first impurity concentration.
  • the threshold voltage is mainly determined by the first impurity concentration of the first layer
  • the first impurity concentration is determined by the required threshold voltage.
  • the second impurity concentration of the second layer has a smaller influence on the threshold voltage than the first impurity concentration of the first layer. Therefore, by making the second impurity concentration higher than the first impurity concentration, the on-resistance can be lowered without significantly affecting the threshold voltage.
  • the step of forming the gate region is such that the dimension along the facing direction of the gate region decreases as the distance from the main surface increases in a cross-sectional view including the thickness direction and the facing direction. To be done.
  • variations in threshold voltage can be reduced by forming the gate region with an epitaxial film.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1. It is a cross-sectional schematic diagram which shows Embodiment 2 of the silicon carbide semiconductor device according to this invention.
  • FIG. 16 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 15.
  • the silicon carbide semiconductor device in the present embodiment is an n-type JFET (Junction Field Effect Transistor) 10.
  • JFET 10 mainly includes substrate 11, p-type layers 2 and 12, and silicon carbide layer 4.
  • the substrate 11 has an upper surface 11A, is made of silicon carbide, and has an n-type (first conductivity type).
  • Silicon carbide layer 4 is provided on upper surface 11A of substrate 11 through p-type layers 2 and 12, and has a main surface 13A and a thickness direction (vertical direction in the figure) intersecting main surface 13A. is doing.
  • the p-type layer 2 is an electric field relaxation layer.
  • the p-type layer 12 is a breakdown voltage holding layer formed on the p-type layer 2.
  • the p-type layers 2 and 12 are made of p-type SiC.
  • the thicknesses of p-type layer 2 and p-type layer 12 are, for example, 0.5 ⁇ m and 10 ⁇ m, respectively.
  • the impurity concentrations of the p-type layer 2 and the p-type layer 12 are, for example, 5 ⁇ 10 16 and 1 ⁇ 10 16 atoms / cm 3 , respectively.
  • the p-type layer 12 may be formed directly on the upper surface 11A of the n-type substrate 11.
  • Silicon carbide layer 4 has channel layer 7, gate region 16 ⁇ / b> R, source region 15, and drain region 17.
  • the channel layer 7 includes a first layer 6 that is an n-type layer and a second layer 13 that is an n-type layer.
  • the impurity concentration (second impurity concentration) of the second layer 13 is higher than the impurity concentration (first impurity concentration) of the first layer 6.
  • the impurity concentrations of the first layer 6 and the second layer 13 are 1 ⁇ 10 17 atoms / cm 3 and 2 ⁇ 10 17 atoms / cm 3 , respectively.
  • the film thicknesses of the first layer 6 and the second layer 13 are, for example, 0.1 ⁇ m and 0.2 ⁇ m.
  • Each of the source region 15 and the drain region 17 extends into the channel layer 7 along the thickness direction from the main surface 13A. A part of the channel layer 7 is sandwiched between the source region 15 and the drain region 17 in the opposing direction (lateral direction in the figure) intersecting the thickness direction.
  • Gate region 16R extends between source region 15 and drain region 17 so as to protrude from main surface 13A into channel layer 7 along the thickness direction. In the present embodiment, the gate region 16R extends through the second layer 13 and onto the first layer 6. Gate region 16R is epitaxially grown with respect to channel layer 7 so as to have a p-type (second conductivity type). The thickness of the gate region 16R is, for example, 0.4 ⁇ m. The impurity concentration of the gate region 16R is, for example, 1 ⁇ 10 18 atoms / cm 3 .
  • An epitaxial layer 14 having p type (second conductivity type) is formed on silicon carbide layer 4.
  • the epitaxial layer 14 is connected between the source region 15 and the drain region 17 along the horizontal direction in the drawing on the channel layer 7.
  • the thickness of the epitaxial layer 14 is, for example, 0.2 ⁇ m.
  • the impurity concentration of the epitaxial layer 14 is, for example, 1 ⁇ 10 17 atoms / cm 3 .
  • a source region 15 and a drain region 17 containing impurities having an n conductivity type (n-type impurity) at a higher concentration than the channel layer 7 are formed.
  • a gate region 16 ⁇ / b> R containing impurities having a p-type conductivity (p-type impurity) at a higher concentration than the p-type layer 12 and the epitaxial layer 14 is formed so as to be sandwiched between the drain regions 17. That is, the source region 15, the gate region 16R, and the drain region 17 are formed so as to penetrate the epitaxial layer 14 and reach the channel layer 7, respectively.
  • the bottoms of the source region 15, the gate region 16 ⁇ / b> R, and the drain region 17 are spaced from the upper surface of the p-type layer 12 (the boundary between the p-type layer 12 and the channel layer 7) inside the channel layer 7. Has been placed.
  • the epitaxial layer 14 penetrates the epitaxial layer 14 from the upper surface of the epitaxial layer 14 (the main surface opposite to the channel layer 7 side) to the channel layer 7.
  • the groove part 31 is formed so that it may reach. That is, the bottom wall of the groove 31 is located inside the channel layer 7 with a gap from the interface between the p-type layer 12 and the channel layer 7. Further, a potential holding region 23 containing a p-type impurity having a higher concentration than the p-type layer 12 and the epitaxial layer 14 is formed so as to penetrate the channel layer 7 from the bottom wall of the trench 31 and reach the p-type layer 12. Yes.
  • the bottom of the potential holding region 23 is spaced apart from the upper surface of the n-type substrate 11 (the boundary between the n-type substrate 11 and the p-type layer 2) (more specifically, the p-type layer 2 and the p-type layer).
  • the p-type layer 12 is disposed at a distance from the boundary with the layer 12.
  • contact electrodes 19 are formed so as to be in contact with the upper surfaces of the source region 15, the gate region 16 R, the drain region 17 and the potential holding region 23.
  • the contact electrode 19 is made of a material that can make ohmic contact with the source region 15, the gate region 16R, the drain region 17, and the potential holding region 23, for example, NiSi (nickel silicide).
  • An oxide film 18 is formed between adjacent contact electrodes 19. More specifically, an oxide film 18 as an insulating layer is formed on the upper surface of the epitaxial layer 14 and the bottom wall and side wall of the groove 31 so as to cover the entire region other than the region where the contact electrode 19 is formed. ing. As a result, the adjacent contact electrodes 19 are insulated from each other.
  • a source electrode 25, a gate electrode 26, and a drain electrode 27 are formed so as to be in contact with the upper surfaces of the contact electrodes 19 on the source region 15, the gate region 16R, and the drain region 17, respectively.
  • the source electrode 25, the gate electrode 26, and the drain electrode 27 are electrically connected to the source region 15, the gate region 16R, and the drain region 17 through the contact electrode 19, respectively.
  • the source electrode 25 is also in contact with the upper surface of the contact electrode 19 on the potential holding region 23 and is also electrically connected to the potential holding region 23 through the contact electrode 19. That is, the source electrode 25 is formed to extend from the upper surface of the contact electrode 19 on the source region 15 to the upper surface of the contact electrode 19 on the potential holding region 23.
  • the contact electrode 19 on the potential holding region 23 is held at the same potential as the contact electrode 19 on the source region 15.
  • the source electrode 25, the gate electrode 26, and the drain electrode 27 are made of a conductor such as aluminum (Al).
  • an insulating protective film 28 made of an insulator is formed so as to cover the oxide film 18 and the gate electrode 26 and to fill a region between the source electrode 25 and the drain electrode 27. ing.
  • openings 33 and 34 are formed in a region on the source region 15 and the potential holding region 23 and a region on the drain region 17, respectively.
  • the source electrode 25 and the drain electrode 27 are disposed inside the openings 33 and 34.
  • the upper surfaces of the source electrode 25 and the drain electrode 27 are located above the upper surface of the insulating protective film 28 (that is, the upper portions of the source electrode 25 and the drain electrode 27 protrude from the upper surface of the insulating protective film 28, respectively. ing).
  • the JFET 10 in the present embodiment is a RESURF type JFET in which an epitaxial layer 14 (resurf layer) is formed so as to be in contact with the channel layer 7. Therefore, in the off state, the depletion layer extends in the vertical direction (thickness direction) from the interface between the channel layer 7 and the epitaxial layer 14. As a result, the electric field distribution in the drift region becomes uniform, the electric field concentration near the gate region 16R is relaxed, and the breakdown voltage is improved.
  • JFET 10 which is the silicon carbide semiconductor device in the first embodiment will be described.
  • a substrate preparation step is performed as a step (S10).
  • an n-type substrate 11 is used.
  • a 1st layer formation process is implemented as process (S20).
  • the p-type layer 2 and the p-type layer 12 made of SiC are formed sequentially on the upper surface 11A of the n-type substrate 11 by vapor phase epitaxial growth.
  • silane (SiH 4 ) gas and propane (C 3 H 8 ) gas can be used as a material gas
  • hydrogen (H 2 ) gas can be used as a carrier gas.
  • a p-type impurity source for forming the p-type layer for example, diborane (B 2 H 6 ) or trimethylaluminum (TMA) can be employed.
  • n-type impurity for forming the first layer 6 for example, nitrogen (N 2 ) can be employed.
  • gate layer 16 made of SiC is formed on first layer 6 by vapor phase epitaxial growth, for example.
  • silane (SiH 4 ) gas and propane (C 3 H 8 ) gas can be used as a material gas
  • hydrogen (H 2 ) gas can be used as a carrier gas.
  • a p-type impurity source for forming the p-type layer for example, diborane (B 2 H 6 ) or trimethylaluminum (TMA) can be employed.
  • a gate region forming step is performed as a step (S35).
  • mask 5 is formed at a position where gate region 16R (FIG. 1) on gate layer 16 is to be formed.
  • the mask 5 is made of a resist, for example.
  • the gate region 16R is formed on a part of the first layer 6 by patterning the gate layer 16.
  • gate region 16 ⁇ / b> R is formed by dry etching using mask 5. Dry etching can be performed using, for example, SF 6 .
  • over-etching may be performed as shown by a broken line in FIG. That is, a part of the surface of the first layer 6 may be removed.
  • a second layer forming step is performed as a step (S40).
  • the second layer 13 having n-type (first conductivity type) is epitaxially formed on the first layer 6 provided with the gate region 16R.
  • an n-type layer (second layer 13) made of SiC, for example is formed by vapor phase epitaxial growth so as to cover gate region 16R.
  • the second layer 13 is formed so as to cover the upper surface and side surfaces of the gate region 16R.
  • the second layer 13 is also formed on the upper surface of the first layer 6.
  • a silicon carbide layer forming step is performed as a step (S45). Specifically, as shown in FIG. 7, the second layer 13 located on the gate region 16R is removed, and the upper portion of the gate region 16R is exposed. At this time, a part of the second layer 13 other than the upper part of the gate region 16R may be removed at the same time. The removal of the second layer 13 can be performed by, for example, etch back. As described above, silicon carbide layer 4 having gate region 16R penetrating second layer 13 between main surface 13A and first layer 6 is formed.
  • epitaxial layer 14 having p-type is formed on silicon carbide layer 4. Specifically, the epitaxial layer 14 is formed on the gate region 16R and the second layer 13.
  • a groove part formation process is implemented as process (S50). Specifically, as shown in FIG. 9, the groove 31 is formed so as to penetrate from the upper surface 14 ⁇ / b> A of the epitaxial layer 14 to the channel layer 7 through the epitaxial layer 14.
  • the formation of the groove 31 can be performed by, for example, dry etching using SF 6 gas, for example, after forming a mask layer having an opening at a position where the desired groove 31 is formed on the upper surface of the epitaxial layer 14.
  • a first ion implantation step is performed.
  • a potential holding region (base contact region) that is a region containing a high concentration p-type impurity is formed.
  • a resist is applied on the upper surface of epitaxial layer 14 and the inner wall of groove portion 31, and then exposure and development are performed to obtain desired gate region 16R and potential holding region.
  • a resist film (not shown) having an opening in a region corresponding to the planar shape of 23 is formed.
  • p-type impurities such as Al (aluminum) and B (boron) are introduced into the channel layer 7 and the p-type layer 12 by ion implantation. Thereby, the potential holding region 23 is formed.
  • a second ion implantation step is performed.
  • a source region 15 and a drain region 17 that are regions containing high-concentration n-type impurities are formed.
  • a resist film (not shown) having openings in regions corresponding to the planar shape of desired source region 15 and drain region 17 in the same procedure as in step (S60). ) Is formed.
  • n-type impurities such as P (phosphorus) and N (nitrogen) are introduced into the epitaxial layer 14 and the channel layer 7 by ion implantation. Thereby, the source region 15 and the drain region 17 are formed.
  • the source region 15 and the drain region 17 are formed in contact with the epitaxial layer 14.
  • the epitaxial layer 14 is formed on the channel layer 7 so as to connect between the source region 15 and the drain region 17 along the horizontal direction in the drawing.
  • an activation annealing step is performed as a step (S80).
  • the epitaxial layer 14, the channel layer 7 and the p-type layer 12 in which the ion implantation is performed in the step (S60) and the step (S70) are heated.
  • activation annealing which is a heat treatment for activating the impurities introduced by the ion implantation, is performed.
  • the activation annealing can be performed, for example, by performing a heat treatment that is held at a temperature of about 1700 ° C. for about 30 minutes in an argon gas atmosphere.
  • an oxide film forming step is performed.
  • steps (S10) to (S80) are performed, and epitaxial layer 14 including desired ion implantation layer, channel layer 7, p-type layer 12, and p-type
  • the n-type substrate 11 on which the layer 2 is formed is thermally oxidized.
  • an oxide film 18 made of silicon dioxide (SiO 2 ) is formed so as to cover the upper surface 14 A of the epitaxial layer 14 and the inner wall of the groove 31.
  • a contact electrode forming step is performed as a step (S100).
  • contact electrode 19 made of, for example, NiSi is formed so as to be in contact with the upper surfaces of source region 15, gate region 16R, drain region 17, and potential holding region 23, respectively.
  • a resist film (not shown) having an opening in a region corresponding to the planar shape of the desired contact electrode 19 is formed by the same procedure as in the step (S60).
  • oxide film 18 on source region 15, gate region 16R, drain region 17, and potential holding region 23 is removed by, for example, RIE (Reactive Ion Etching). .
  • Ni nickel
  • the nickel layer on the resist film is removed (lifted off), and the nickel is formed on the source region 15, the gate region 16 R, the drain region 17, and the potential holding region 23 exposed from the oxide film 18.
  • the nickel layer is silicided by performing a heat treatment to be heated to a predetermined temperature (for example, 950 ° C.) in a temperature range of, for example, 900 ° to 1000 ° C.
  • a contact electrode 19 which is an ohmic electrode made of NiSi capable of making ohmic contact with the source region 15, the gate region 16R, the drain region 17 and the potential holding region 23 is formed.
  • an electrode formation process is implemented as a process (S110).
  • a gate electrode 26 is formed in contact with the upper surface of contact electrode 19 on gate region 16R.
  • a resist film (not shown) having an opening in a desired region where the gate electrode 26 is to be formed and depositing Al
  • Al on the resist film is removed together with the resist film (lift-off).
  • an insulating protective film 28 made of an insulator such as SiO 2 is formed so as to cover gate electrode 26, contact electrode 19 and oxide film 18. Specifically, for example, by CVD (Chemical Vapor Deposition), contact electrode 19 disposed on gate electrode 26, source region 15, drain region 17, and potential holding region 23, and oxide film, respectively.
  • An insulating protective film 28 (see FIG. 14) made of a SiO 2 film covering 18 is formed.
  • source electrode 25 that contacts the upper surface of contact electrode 19 on source region 15 and potential holding region 23, and drain that contacts the upper surface of contact electrode 19 on drain region 17. Electrode 27 is formed.
  • openings 33 and 34 are formed in the insulating protective film 28 in regions located on the source region 15, the drain region 17, and the potential holding region 23 by using a photolithography method.
  • a method of forming the openings 33 and 34 for example, a resist film (not shown) having an opening similar to the planar shape of the openings 33 and 34 is formed on the main surface of the insulating protective film 28, and this resist film As a mask, a part of the insulating protective film 28 is removed by etching or the like. In this way, the openings 33 and 34 are formed in the insulating protective film 28 as shown in FIG.
  • the resist film (not shown) is removed by any conventionally known method.
  • the source electrode 25 and the drain electrode 27 are formed.
  • a resist film (not shown) having openings in desired regions (regions where the openings 33 and 34 are formed) where the source electrode 25 and the drain electrode 27 are to be formed, and depositing Al, Al on the resist film is removed together with the resist film (lift-off).
  • the resist film used for forming the source electrode 25 and the drain electrode 27 may be used as the resist film used for forming the source electrode 25 and the drain electrode 27, the resist film used for forming the openings 33 and 34 may be used. That is, after forming the openings 33 and 34 by etching using the resist film as a mask as described above, the conductor film constituting the electrode such as Al is formed as described above without removing the resist film. Then, the source electrode 25 and the drain electrode 27 may be formed inside the openings 33 and 34 by lift-off.
  • the JFET 10 in the present embodiment is completed through the above steps. Next, the effect of this Embodiment is demonstrated.
  • the gate region 16R is formed by ion implantation, it is difficult to control the depth of ion implantation. The variation in impurity concentration becomes large. Therefore, the threshold voltage varies greatly.
  • the gate region 16R is formed not by ion implantation but by an epitaxial film. Therefore, the above variation due to ion implantation does not occur. Therefore, variation in threshold voltage can be reduced. Thus, it is possible to manufacture a transistor that does not flow current when the gate voltage is 0, that is, a so-called normally-off transistor.
  • the gate region 16R is fabricated by ion implantation, the impurity concentration in the boundary region between the gate region 16R and the channel layer 7 changes gradually.
  • the gate region 16R is formed of an epitaxial film, the change in the impurity concentration in the boundary region between the gate region 16R and the channel layer 7 can be made steep.
  • the channel layer 7 has an n-type. Therefore, electrons having a higher mobility than holes can be used as main carriers flowing in the channel layer. Therefore, the on-resistance is reduced.
  • the source region 15 and the drain region 17 are connected by the epitaxial layer 14 along the facing direction (lateral direction in the figure).
  • the impurity concentration (second impurity concentration) of the second layer 13 is higher than the impurity concentration (first impurity concentration) of the first layer 6. Since the threshold voltage is mainly determined by the impurity concentration of the first layer 6 (first impurity concentration), the first impurity concentration is determined by the required threshold voltage. On the other hand, the impurity concentration of the second layer 13 has a smaller influence on the threshold voltage than the first impurity concentration. Therefore, by making the second impurity concentration higher than the first impurity concentration, the on-resistance can be lowered without significantly affecting the threshold voltage.
  • the JFET 20 according to the second embodiment of the present invention has substantially the same structure as that of JFET 10 (FIG. 1), but has an inverted trapezoidal gate instead of the rectangular gate region 16R (FIG. 1). It has area
  • the width of the gate region 16S decreases from the main surface 13A of the channel layer 7 toward the substrate 11, and the gate region 16S has a finite width on the side closest to the substrate 11 of the gate region 16S. It is that.
  • the shape of the gate region 16S is such that the dimension along the opposing direction (lateral direction in the drawing) of the gate region 16S in the cross-sectional view including the thickness direction and the opposing direction (field of view in FIG. 15) is from the main surface 13A. What is necessary is just to be formed so that it may become small as it leaves
  • the shape of the gate region 16S on the substrate 11 side may be rounded.
  • JFET 20 is almost the same as the manufacturing method shown in FIGS. 2 to 14 (Embodiment 1).
  • the difference from the manufacturing method of the first embodiment is that an inverted trapezoidal gate region 16S is formed as shown in FIG. 16 instead of the step of FIG.
  • Such a shape can be formed by, for example, ion milling.
  • the dimension along the facing direction (lateral direction in the drawing) of the gate region 16S decreases as the distance from the main surface 13A increases. Thereby, the resistance of the channel portion in the vicinity of the gate region 16S is reduced, so that the on-resistance can be lowered.
  • n-type and the p-type in each of the above embodiments are interchanged may be used.
  • a p-type JFET is configured instead of the n-type JFET.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

L'invention concerne un dispositif à semi-conducteurs (10) en carbure de silicium, lequel comporte un substrat (11) ainsi qu'une couche de carbure de silicium (4) située sur le substrat (11) et possédant une surface principale (13A) et une direction d'épaisseur croisant cette surface principale (13A). La couche de carbure de silicium (4) comporte une couche canal (7), une région source (15), une région drain (17) et une région grille (16R) située entre la région source (15) et la région drain (17). On fait croître par épitaxie la région grille (16) pour qu'elle possède un deuxième type de conductivité différent d'un premier type de conductivité qui est celui de la couche canal (7). Ainsi, on obtient un dispositif à semi-conducteurs en carbure de silicium permettant de réduire les disparités de potentiel seuil.
PCT/JP2012/070740 2011-10-03 2012-08-15 Dispositif à semi-conducteurs en carbure de silicium et son procédé de fabrication WO2013051344A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010131571A1 (fr) * 2009-05-11 2010-11-18 住友電気工業株式会社 Dispositif à semi-conducteurs
JP2011134968A (ja) * 2009-12-25 2011-07-07 Denso Corp 炭化珪素半導体装置およびその製造方法
JP2011134971A (ja) * 2009-12-25 2011-07-07 Denso Corp 半導体装置およびその製造方法
JP2011159714A (ja) * 2010-01-29 2011-08-18 Denso Corp 炭化珪素半導体装置およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010131571A1 (fr) * 2009-05-11 2010-11-18 住友電気工業株式会社 Dispositif à semi-conducteurs
JP2011134968A (ja) * 2009-12-25 2011-07-07 Denso Corp 炭化珪素半導体装置およびその製造方法
JP2011134971A (ja) * 2009-12-25 2011-07-07 Denso Corp 半導体装置およびその製造方法
JP2011159714A (ja) * 2010-01-29 2011-08-18 Denso Corp 炭化珪素半導体装置およびその製造方法

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