WO2013050766A1

WO2013050766A1 - Integrated circuit

Info

Publication number: WO2013050766A1
Application number: PCT/GB2012/052458
Authority: WO
Inventors: Paul Darlington
Original assignee: Soundchip Sa
Priority date: 2011-10-05
Filing date: 2012-10-04
Publication date: 2013-04-11
Also published as: GB201117167D0; GB201405479D0; GB2512212A; GB2512212B

Abstract

An integrated circuit comprising: a plurality of resistors (R); associated with each resistor a plurality n of trimming resistances (Rtriml, Rtrim2); and a switch operative to connect a number p, where 0 < p < n, of the associated trimming resistances (Rtriml, Rtrim2) in series with each resistor (R), whereby the sum of the resistances of the resistor and the trimming resistances form a total resistance value.

Description

TITLE: INTEGRATED CIRCUIT

DESCRIPTION

The present invention relates to integrated circuits and methods of manufacturing them, and particularly but not exclusively to integrated circuits that include resistive elements fabricated in silicon and methods of manufacturing them.

The silicon fabrication process used in the construction of an integrated circuit is such that the absolute value of these resistors formed within the silicon can differ from a target nominal value by a considerable error. However, all resistors on a fabricated wafer are typically scaled from their target value by the same multiplicative error, such that, for example, resistors are n% away from their target value. This can cause problems where an application requires a resistance value to be within a tight tolerance band. For example, a specification may require resistance values to be within 10% of their nominal values, but their present production techniques cannot better 15.6%.

The underlying reason for this error is that the fabrication process yields rather poor control of the "thickness" dimension of a resistor and there is some variation in resistivity of the material due to doping. These two variables are comparatively constant throughout any given wafer. In practice, these variables may be is substantially constant over a whole manufacturing "lot" (i.e., over a group of wafers made at the same time at the same plant). That is, within a wafer or manufacturing lot, as the case may be, every resistor is approximately scaled by a common factor. The extent to which these variables are substantially constant is dependent upon the particular manufacturing technique being used.

The present applicant has identified the need to improve upon the tolerance with which resistive components can be fabricated.

In accordance with a first aspect of the present invention, there is provided an integrated circuit comprising: a plurality of resistors (e.g. formed on a substrate (e.g. wafer) during the same fabrication process); associated with each resistor a plurality n of trimming resistances; and a switch (e.g. switching means) operative to connect a number p, where 0 <p < n, of the associated trimming resistances in series with each resistor, whereby the sum of the resistances of the resistor and the trimming resistances form a total resistance value.

In this way, an integrated circuit is provided in which the resistance can be trimmed after formation of the resistors to improve tolerance values associated with the resistors.

Such an improved integrated circuit is believed to be of use in a variety of fields including but certainly not exclusive to circuitry for handling audio signals.

In one embodiment, the number p of the associated trimming resistances connected in series with each resistor is chosen such that the total resistance value most closely approximates a design resistance value.

In one embodiment, the value of p is the same for each resistor in the integrated circuit, The value of p can be the same for all of the resistors because they are all subject to substantially the same manufacturing process, and will therefore deviate from the design resistance value by an error that is proportional to the design resistance value. This greatly simplifies construction of the integrated circuit since every instance of the switch is similarly configured.

Although embodiments are possible where n = 1, advantageously, n > 2.

In one embodiment, n = 2. In this way, an effective way of controlling resistor tolerance may be provided at minimal cost.

The values of all of the trimming resistances associated with a particular resistor may be the same. This is most particularly the case where the range of the values of the resistors follows a symmetrical distribution about a mean value. In such cases, the value of each trimming resistance is advantageously approximately 6σ/(η + 1), where σ is the standard deviation of the resistance values about the mean. For example, for n = 1 the value of the trimming resistance may be approximately 3σ. In the advantageous case of n = 2, the values of each trimming resistance may be approximately 2σ (i.e. giving a total trimming resistance of 4σ where p = 2).

Typically, an integrated circuit must implement a range of different design resistance values. In such cases, the values of all of the trimming resistances may be of an approximately equal proportion to the value to their associated resistor.

In one embodiment, The switch is typically configured to be programmable once on manufacture of the integrated circuit (e.g. to permanently set the connection of the selected p trimming resistances during manufacture) . For example, the switch may include one or more fusible links that can be selectively ruptured to connect the required number of trimming resistances to the resistor.

In one embodiment, the integrated circuit is one of a plurality of integrated circuits on a single substrate each as previously defined, and the switch of each integrated circuit is configured to be activated centrally by a central switch (e.g. by forming a connection from the central switch to each individual switch during manufacture of the integrated circuits.).

In accordance with a second aspect of the present invention, there is provided a method of manufacturing an integrated circuit comprising: forming on a substrate (e.g. wafer) a plurality of resistors; forming a plurality n of trimming resistances associated with each resistor; forming a switch that can be caused to connect one or more of the associated trimming resistances in series with each resistor; choosing a value p, where 0<p<n, such that the sum of the resistance of the resistor and p trimming resistances form a total resistance value that most closely approximates a design resistance value; and causing the switch to connect each resistor in series with p of the trimming resistances.

In one embodiment, the value of p is the same for each resistor in the integrated circuit.

The value p may be chosen by measuring the actual value of a resistor after it has been formed, and setting p to be the number of trimming resistances that, when added to the resistance of the resistor, most closely approximates the design resistance value.

In one embodiment, n > 2. For example, in one embodiment, n = 2.

In one embodiment, the values of all of the trimming resistances associated with a particular resistor are the same.

In one embodiment, the value of the trimming resistance is approximately 6σ/(η + 1), where σ is the standard deviation of the values of the resistors values about their mean. In the advantageous case of « = 2, the values of each trimming resistance may be approximately 2σ (i.e. giving a total trimming resistance of 4σ where p = 2).

In the case that the formed integrated circuit implements a plurality of different design resistance values, the values of all of the trimming resistances may be of an approximately equal proportion to the value to their associated resistor.

In one embodiment, the step of causing the switch to connect each resistor in series with p of the trimming resistances involves permanently connecting each resistor with the p trimming resistances. For example, the step of causing the switch to connect each resistor in series with p of the trimming resistances may comprise rupture of one or more fusible links.

In one embodiment, the integrated circuit is one of a plurality of integrated circuits on a single substrate each formed as previously defined and the switch of each integrated circuit is caused to connect each resistor in series with p of the trimming resistances by activating a central switch (e.g. by forming a connection from the central switch to each individual switch during manufacture.)

An embodiment of the invention will now be described by way of example with reference to the accompanying drawings in which:

Figure 1 shows diagrammatically a resistor and a series-connected trimming resistance;

Figure 2 shows diagrammatically a resistor and a switchable series-connected trimming resistance;

Figure 3 is a graph comparing the distribution of resistance values that are obtained in the conventional production of integrated circuits with the distribution of resistance values that are obtained using an arrangement similar to that shown in Figure 2;

Figure 4 shows diagrammatically a resistor and two switchable series-connected trimming resistances;

Figure 5 is a graph comparing the distribution of resistance values that are obtained in the conventional production of integrated circuits with the distribution of resistance values that are obtained using an arrangement similar to that shown in Figure 4;

Figure 6 shows diagrammatically a resistor and an arbitrarily large number of switchable series-connected trimming resistances;

Figure 7 is a graph comparing the distribution of resistance values that are obtained in the conventional production of integrated circuits with the distribution of resistance values that are obtained using an arrangement similar to that shown in Figure 6;

Figure 8 is a graph comparing the distribution of resistance values that are obtained in the conventional production of integrated circuits with the distribution of resistance values that are obtained using an arrangement similar to that shown in Figure 6 when variation in the values of trimming resistances is taken into account;

Figure 9 shows diagrammatically a resistor ladder where each step in the ladder includes a resistor and two switchable series-connected trimming resistances;

Figure 10 shows the statistics of 1000 embodiments of response characteristics in an integrated circuit with all resistors subject to a Gaussian distribution at 3σ = 15.6% tolerance; and

Figure 1 1 shows the statistics of 1000 embodiments of response characteristics in an integrated circuit with all resistors subject to a Gaussian distribution at ±5.2% tolerance.

With reference first to Figure 1, consider a resistor R implemented in silicon as part of an integrated circuit. The resistor R is connected in series with a trimming resistance Rtrim. The total resistance of these two resistors is denoted RT. This is the resistance that will affect operation of the circuit, and should as closely as possible approach a nominal, design value.

When many such circuits are produced, the actual value of this RT in the many integrated circuits will vary with a Gaussian distribution about a mean impedance corresponding to the nominal value. The aim is to use series trimming resistance, Rtrim to reduce the width of the distribution of RT.

In practice, the trimmer resistor Rtrim will of course have a range of values that following some distribution, which may be correlated with R in silicon implementations. However, by way of explanation consideration will first be given to the case when the trimmer has known, fixed resistance.

Suppose it is possible to specify two values for the trimmer resistance: Rtrim=0 and Rtrim=3o, where σ is the standard deviation of the distribution of R. This arrangement is shown in Figure 2. Now select between these two trimmer resistances on the basis of the measured value of R and the mean μ:

RT=R ^>μ

RT=R+Rtrim ^<μ Given the assumed Gaussian distribution of R, the distribution of RT is found by experiment (for example, leading to the particular values of μ=933, σ=48). The results presented in Figure 3 are estimates of the probability density function (pdf) of the original distribution of a simulated population of 107 "target" resistors with μTarget=1000, oTarget=52 and the pdf of the distribution of RT.

The thin vertical lines in the left-hand plot of Figure 3 show the ±3σ points for the original Gaussian distribution (in a normal distribution approximately 99.7% of the populations lie within the 3σ limits, so in practical terms these limits define the range of resistances expected from the manufacturing process); the corresponding lines in the right- hand plot of Figure 3 show that the ±3σ points in the distribution of RT are about half this width (the new mean value for RT, μ' = μ + 1.5σ, with this offset being accounted for in the design processor by designing the original resistors to have a lower means value than the target; the lines in the right-hand plot are approximately ±1.5σ from μ'). Note that, whilst the overall distribution width has reduced (to a tolerance of less than ±10%), the distribution of the total resistance is now bi-modal, which is undesirable, and tends to increase the apparent distribution width.

A significantly improved result can be obtained using two trimming resistances Rtrim, l, Rtrim,2, as shown in Figure 4, as before, selection between trimming resistances being made on the basis of the measured value of R. In this case, the two trimming resistances are of equal value.

RT=R ^>μ+σ

RT=R+Rtrim, l |μ-σ<Κ<μ+σ

RT=R+Rtrim, l + Rtrim,2 ^<μ-σ

Given the assumed Gaussian distribution of R, the distribution of RT is found by experiment (for example, with the particular values of μ=910, σ=47, Rtrim, l= Rtrim,2=94.6). The results presented in Figure 5 are estimates of the pdf of the original distribution of a simulated population of 106 target resistors with μTarget=1000, oTarget=52 and the pdf of the distribution of RT.

With this arrangement, it will be seen from the right-hand plot of Figure 5 that the bounds of the distribution of RT have reduced to effectively 1/3 of the 3σ points of the original distribution (the new mean value for RT, μ' = μ + 2σ, with this offset being accounted for in the design processor by designing the original resistors to have a lower means value than the target; the lines in the right-hand plot are approximately ± 1 σ from μ'), and the distribution of RT is flat-topped, as is preferred. As the smallest value of n which does not give a bi-modal distribution, the case n = 2 is the preferred practical embodiment.

This progression can be extended by using more trimming resistances, as shown in

Figure 8, choosing their value based upon the measured resistance of R. For example, using ten equal trimming resistors with the particular values of μ=877, σ=45.6, Rtrim, l=Rtrim,n=24.9) produces the results shown in the right-hand plot of Figure 7, as compared with the distribution without trimming resistances shown in the left-hand plot of Figure 7.

A general trend can be established: using n (ri>\) trimming resistances produces a total resistance distributed according to a rectangular distribution of total width 3σ/(«+1). The rules for the general case of an arbitrary number of trimming resistors are now presented, in which the width of the native distribution of the resistors is assumed to be 6σ:

It will be recalled that all of the above analysis assumes that the value of the trimming resistances are known. However, in fact, these will be subject to variation in much the same way as the resistance of the resistor R. For the case of resistors implemented on-chip, the tolerances discussed in the above apply across the whole of a wafer or even manufacturing lots of wafers, with all the resistors on one wafer subject to the same overall scaling error from their nominal value. This includes any on-chip trimmers, which means that Rtrim °= R throughout the range of variation. Simulating the two-resistor arrangement described above (that is, the value for Rtrim is selected from one of three possible alternatives) with the value of the trimmer resistors proportional to R (itself normally distributed) gives, as seen in Figure 8, only a slightly poorer result than presented in Figure 7.

The resistors in an integrated circuit will typically assume a range of different values. For example, a circuit might implement a tapped resistor ladder. Each of these individual values requires trimming to bring their values within the required tolerance range. Despite the absolute values of the resistors being different, the same relative trim amount is required for all resistors for which the proportionality relationship discussed above holds true (that is, all in a wafer or a manufacturing lot). In terms of the scalar examples presented above, this means that the selection of a particular number p (0<p<n) of the n trim resistor values will be identical for each resistor.

When addressing a multi-valued vector problem, the required number of resistances quickly expands. However, for the minimum acceptable case of n=2 (two resistors selecting a one- of-three trim value), a general solution can be modelled as a cascade of three tapped resistor ladders, as shown in Figure 9.

Figure 9 shows the tapped resistor ladders as linked potentiometers - that is, each resistor in the ladder corresponds to a specific setting of the potentiometers. The existing resistor ladder [R] is at the left hand end of the ladder as shown in Figure 9. Also shown are the two additional trimmers [Rtrim,l], [Rtrim,2]. If the original is an m-step ladder, each of the trimmers must also be m-step so that there are separate trimmer resistors for each step in the ladder. These trimmers have step sizes equal to twice the standard deviation in the variation that is expected in the absolute values of each of the steps of [R]. That means they are of order 10% of the magnitude of [R] to where the manufacturing tolerances are as described above. All the taps are set by logic contained within the integrated circuit to ensure that the active section of the resistor ladder [R] is trimmed by the appropriate sections of Rtrim, l and Rtrim,2. The one-of-three selection at the right-hand end of Figure 9 is controlled by a common wafer-wide setting, reflecting the actual value of resistance scaling on that wafer. A wafer that carries multiple circuits that each includes multiple resistor ladders can be corrected by a single setting. Such as setting could be implemented using fusible links or alternative one-time programmable setting means.

Once a wafer has been manufactured, the actual value of the resistance R can be measured directly, the appropriate number of trimmer resistances can be selected to bring the value of the corresponding RT as close as possible to the nominal value. The wafer is then configured such that for every resistor, the correct number of trimming resistances are connected in series. This can be done as a one-time irreversible programming step, implemented, for example, by the provision of fusible links within the wafer. By this arrangement, a wafer that includes resistors with quoted 3σ tolerance of 15.6% (Gaussian) can be improved to a flat-top distribution of approximately 5% tolerance. The consequence of such a distribution on the resulting control filters is considered below. (Of course, a corresponding improvement will be obtained when the quoted tolerance is greater than or lesser than 15.6%.)

The effects of the modification of the statistical distribution of resistor values using the techniques discussed above in a control law network of an integrated circuit will be discussed with reference to Figures 10 and 11.

Figure 10 shows the statistics of 1000 embodiments of response characteristics of an integrated circuit with best-case capacitors and with all resistors subject to Gaussian distribution at 3σ = 15.6% tolerance, which is the unimproved N-Poly silicon process limit. Figure 1 1 shows the corresponding statistics when the variation in the resistors is reduced to a ±5.2% tolerance using the arrangement of two trimming resistances described with reference to Figures 8 and 9. It can be seen that there is a significant reduction in the spread shown in Figure 1 1 as compared with Figure 10.

Claims

Claims:

1. An integrated circuit comprising:

a plurality of resistors;

associated with each resistor a plurality n of trimming resistances; and

a switch operative to connect a number p, where 0 <p < n, of the associated trimming resistances in series with each resistor, whereby the sum of the resistances of the resistor and the trimming resistances form a total resistance value.

2. An integrated circuit according to claim 1, wherein the value of p is the same for each resistor in the integrated circuit.

3. An integrated circuit according to claim 1 or claim 2, wherein n > 2.

4. An integrated circuit according to any of claims 1-3, wherein the values of all of the trimming resistances associated with a particular resistor are the same.

5. An integrated circuit according to any preceding claim, wherein the value of the trimming resistance is approximately 6σ/(η + 1), where σ is the standard deviation of the values of the resistors values about their mean.

6. An integrated circuit according to any preceding claim that implements a plurality of different design resistance values, wherein the values of all of the trimming resistances are of an approximately equal proportion to the value to their associated resistor.

7. An integrated circuit according to any preceding claim, wherein the switch is configured to be programmable once on manufacture of the integrated circuit.

8. An integrated circuit according to claim 7, wherein the switch includes one or more fusible links that can be selectively ruptured to connect the required number of trimming resistances to the resistor.

9. An integrated circuit according to any of the preceding claims, wherein the integrated circuit is one of a plurality of integrated circuits on a single substrate each as previously defined, and the switch of each integrated circuit is configured to be activated centrally by a central switch.

5

10. A method of manufacturing an integrated circuit comprising:

forming a plurality of resistors on a substrate;

forming a plurality n of trimming resistances associated with each resistor; forming a switch that can be caused to connect one or more of the associated 10 trimming resistances in series with each resistor;

choosing a value p, where 0 <p < n, such that the sum of the resistance of the resistor and p trimming resistances form a total resistance value that most closely approximates a design resistance value; and

causing the switch to connect each resistor in series with p of the trimming 15 resistances.

11. A method of manufacturing an integrated circuit according to claim 10, wherein the value of p is the same for each resistor in the integrated circuit.

20 12. A method of manufacturing an integrated circuit according to claim 10 or claim 1 1, wherein the value p is chosen by measuring the actual value of a resistor after it has been formed, and setting p to be the number of trimming resistances that, when added to the resistance of the resistor, most closely approximates the design resistance value.

25 13. A method of manufacturing an integrated circuit according to any of claims 10-12, wherein n > 2.

14. A method of manufacturing an integrated circuit according to any of claims 10-13, wherein the values of all of the trimming resistances associated with a particular resistor are 30 the same.

15. A method of manufacturing an integrated circuit according to any of claims 10-14, wherein the value of the trimming resistance is approximately 6σ/(η + 1), where σ is the standard deviation of the values of the resistors values about their mean.

16. A method of manufacturing an integrated circuit according to any of claims 10-15 that implements a plurality of different design resistance values, wherein the values of all of the trimming resistances are of an approximately equal proportion to the value to their associated resistor.

17. A method of manufacturing an integrated circuit according to any of claims 10-16, wherein the step of causing the switch to connect each resistor in series with p of the trimming resistances involves permanently connecting each resistor with the p trimming resistances.

18. A method of manufacturing an integrated circuit according to claim 17, wherein the step of causing the switch to connect each resistor in series with p of the trimming resistances involves rupture of one or more fusible links.

19. A method of manufacturing an integrated circuit according to any of claims 10-18, wherein the integrated circuits is one of a plurality of integrated circuits on a single substrate each formed as previously defined, and the switch of each integrated circuit is caused to connect each resistor in series with p of the trimming resistances by activating a central switch.