WO2013049333A1 - Système et procédé de distribution d'horloge retardée dans des architectures a/n parallèles en colonne utilisées dans des capteurs d'image cmos - Google Patents

Système et procédé de distribution d'horloge retardée dans des architectures a/n parallèles en colonne utilisées dans des capteurs d'image cmos Download PDF

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Publication number
WO2013049333A1
WO2013049333A1 PCT/US2012/057534 US2012057534W WO2013049333A1 WO 2013049333 A1 WO2013049333 A1 WO 2013049333A1 US 2012057534 W US2012057534 W US 2012057534W WO 2013049333 A1 WO2013049333 A1 WO 2013049333A1
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WO
WIPO (PCT)
Prior art keywords
clock signal
output
latches
complement
propagated
Prior art date
Application number
PCT/US2012/057534
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English (en)
Inventor
Thomas Poonnen
Jeffrey Zarnowski
Michael Eugene Joyner
Ketan Vrajlal Karia
Original Assignee
Panavision Imaging
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panavision Imaging filed Critical Panavision Imaging
Publication of WO2013049333A1 publication Critical patent/WO2013049333A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present invention relates to CMOS image sensors using column-parallel A/D architectures, as discussed by way of non-limiting example by Gowda et al. in U.S. Pat. No. 5,877,715 and by Zarnowski et al. in U.S. Pat. No. 7,903,159. More specifically, the present invention relates to duty-cycle skew resistant delayed clock distribution to arrayed digitization and readout structures, in particular, to column- parallel A/D architectures used in CMOS image sensors, and methods for reducing the frequency of the clocks distributed to such arrayed digitization and readout stuctures without compromising digitization resolution or readout rate.
  • FIG. 1 A conventional column-parallel A/D architecture 100 used in a CMOS image sensor is shown in Fig. 1.
  • This type of architecture employs a single-rate readout scheme with B-bit positive-edge triggered shift registers 102 under control of clock signals from inverting buffers 106 and count signals from B-bit positive-edge triggered up-counters 104; the count signals are generated relative to the output of pixels and control commands via logic gates 108 and comparators 110. Only six columns are shown, but the dashed lines of components within the interior columns represents that there may be any number of columns as appropriate.
  • the frequency fo of the digitization clock determines the digitization resolution (maximum number of counts that can be incremented and/or decremented in a given time) and the frequency f R of the readout clock determines the readout rate (maximum number of shifts that be accomplished in a given time).
  • the frequency f R of the readout clock determines the readout rate (maximum number of shifts that be accomplished in a given time).
  • Embodiments herein are directed to a delayed clock distribution scheme, where the duty-cycle skew is substantially independent of the number of stages in the chain. Embodiments herein are also directed to methods for reducing the frequency of clocks that are distributed using the delayed clock distribution scheme to a column-parallel A/D architecture used in a CMOS image sensor without compromising digitization resolution or readout rate.
  • a method of distributing a clock comprises: receiving a clock signal; generating a complement of the clock signal; feeding both the received clock signal and the generated complement of the clock signal to a first of a plurality of latches connected in series; propagating the received clock signal and the generated complement of the clock signal through the plurality of latches connected in series; and tapping, at a plurality of locations along the plurality of latches, an output to drive a load, the output being either the clock signal as propagated or the complement of the clock signal as propagated.
  • the method may have various features.
  • the latches may be set-reset
  • the tapping may occur at every latch, or every other latch.
  • the output may be the clock signal as propagated or the complement of the clock signal as propagated.
  • Another clock signal may be received, and the method may generate, from the another clock signal, the clock signal, the clock signal having a lower frequency than the another clock signal.
  • the frequency of each output may be multiplied before passing the output to a load.
  • a method of distributing a clock includes: receiving a clock signal; generating a complement of the clock signal; feeding both the received clocks signal and the generated complement of the clock signal to a first of a plurality of latches connected in series; propagating the received clock signal and the generated complement of the clock signal through the plurality of latches connected in series; tapping, at a plurality of locations along the plurality of latches, an output, the output being either the clock signal as propagated or the complement of the clock signal as propagated; and driving, by each output, a shift register.
  • the above embodiment may have various features.
  • the latches may be set-reset (SR) latches.
  • the tapping may occur at every latch, or every other latch.
  • the output may be the clock signal as propagated or the complement of the clock signal as propagated. Another clock signal may be received, and the method may generate, from the another clock signal, the clock signal, the clock signal having a lower frequency than the another clock signal. The frequency of each output may be multiplied before passing the output to a load.
  • the shift register may be part of an image sensor.
  • the shift register may be one of a plurality of shift registers connected in series, each shift register having a readout line, the method further comprising reading out the shift registers via a multiplexer.
  • the shift register may be one of a plurality of shift registers connected in series, the method further comprising reading out the shift registers via a single readout line.
  • a method of distributing clock includes: receiving a clock signal;
  • the above embodiment may have various features.
  • the latches may be set-reset (SR) latches.
  • the tapping may occur at every latch, or every other latch.
  • the output may be the clock signal as propagated or the complement of the clock signal as propagated. Another clock signal may be received, and the method may generate, from the another clock signal, the clock signal, the clock signal having a lower frequency than the another clock signal.
  • the frequency of each output may be multiplied before passing the output to a load.
  • the counter may be part of an image sensor. The counter may increment at either only the positive edges of the output or only the negative edges of the output, or at both the positive edges of the output and the negative edges of the output.
  • Fig. 1 is a layout of a prior art column-parallel A/D architecture used in a CMOS image sensor.
  • Fig. 2 is a layout of a prior art delayed clock distribution scheme using inverting buffers.
  • Fig. 3 is a layout of a delayed clock distribution scheme according to an embodiment of the invention.
  • Figs. 4A-4G are other layouts of the delayed clock distribution scheme according to embodiments of the invention.
  • Fig. 5 is a column-parallel A/D architecture used in a CMOS image sensor incorporating the embodiment of Fig. 3.
  • Fig. 6 is a column-parallel A/D architecture used in a CMOS image sensor incorporating a dual-edge triggered counter according to an embodiment of the invention.
  • Fig. 7 is a timing diagram of an input clock as converted to counts by a positive-edge triggered counter in the prior art.
  • Fig. 8 is a timing diagram of an input clock as converted to counts by a dual-edge triggered counter according to an embodiment of the invention.
  • Fig. 9 is a timing diagram of an input clock relative to the output of a frequency divider according to an embodiment of the invention.
  • Fig. 10 is a timing diagram of an input clock relative to the output of a frequency multiplier according to an embodiment of the invention.
  • Fig. 11 is a column-parallel A/D architecture used in a CMOS image sensor incorporating a frequency divider, a frequency multiplier, a dual-edge triggered counter and a multi-rate readout scheme according to embodiments of the invention.
  • Fig. 12 is a timing diagram of a readout of shift registers relative to a clock in the prior art.
  • Fig. 13 is a timing diagram of a readout of shift registers relative to a clock according to an embodiment of the invention.
  • Fig. 14 is a column-parallel A/D architecture used in a CMOS image sensor according to embodiments of the invention. DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
  • An embodiment of the invention is directed to addressing drawbacks from the use of inverting buffers 106 for distributing clocks in a column-parallel A/D architecture 100 of Fig. 1 used in a CMOS image sensor.
  • Such inverting buffers 106 are each made of a pFET and a nFET.
  • the pFETs and nFETs have different drive capabilities that can only be matched to the extent allowable by technology and design limitations.
  • a mismatch between the pull-up time of the pFET and the pulldown time of the nFET degrades the duty-cycle of the clock as it propagates through each inverting buffer.
  • Fig. 2 an example of conventional delayed clock distribution scheme 200 and 202 of inverting buffers 106 such as used in the column- parallel A/D architecture 100 of Fig. 1 is shown.
  • the duty-cycle skew induced by each inverting buffer 106 is cumulative, such that resulting overall duty-cycle skew is proportional to the number of stages in the chain.
  • Non-uniformity in wiring and/or loading can further augment this mismatch along the chain. This effect becomes more prominent as the number of stages in the chain increases.
  • a delayed clock distribution scheme 300 is shown.
  • a clock 302 is fed to a two- phase clock generator 304 that generates complementary versions of the clock.
  • the complementary versions of the clock are fed into a chain of SR latches 306, which may be symmetrically cross-coupled identical logic gates.
  • the SR latches 306 may be of any known design. By way of non-limiting example, it could be a pair of cross- coupled NAND logic gates or cross-coupled NOR logic gates.
  • each SR latch 306 As the complementary versions of the clock propagate through the latches 306, they traverse through paths with alternating duty-cycle skew polarities, the overall effect being that the effective duty-cycle skew across each SR latch 306 becomes insignificant. Due to this resistance offered by each SR latch 306 to clock duty-cycle skew, the overall duty- cycle skew of the chain of SR latches 306 is substantially independent of the number of stages in the chain.
  • the underlying circuitry such as by way of non-limiting example cross-coupled NAND logic gates or cross-coupled NOR logic gates, may be gated to control the clock distribution.
  • the invention is not limited to any particular architecture of the SR latch. Alternatively, other latches with similar characteristics could also be used.
  • Fig. 3 is a non-limiting example of a chain 300 with a particular load to latches 306 relationship and particularly with the loads connecting to the QN output of every other latch 306.
  • the invention is not so limited, and the loads can be located wherever desired.
  • Figs. 4A-4G illustrate a variety of non-limiting examples of other chains of latches 306 with different load relationships.
  • FIG. 5 an embodiment of a column-parallel A/D architecture 500 is shown.
  • the architecture 500 is the same as Fig. 1 (and uses like numerals) save that the inverting buffers 106 have been replaced with chain 300 of Fig. 3. Due to the inherent resistance of chain 300 to clock duty-cycle skew, the architecture 500 is less vulnerable to the difficulties of distributing higher frequency clock signals as compared to the circuit of Fig. 1.
  • FIG. 6 another embodiment of a column-parallel A/D architecture 600 is shown.
  • the positive-edge triggered up- counters 104 in Fig. 1 are replaced with dual-edge triggered up-counters 604.
  • the circuitry of Fig. 6 also shows the substitution of the inverting buffers 106 from Fig. 1 with the latches 306 as discussed above, but this need not be the case with respect to the design of architecture 600 of Fig. 6.
  • Using a dual-edge triggered counter 604 reduces the frequency of the clock that needs to be distributed to the column-parallel A/D architecture 600 in a CMOS image sensor for achieving a desired digitization resolution. In addition to alleviating the complexities involved in distributing clocks that are required for stable digitization, this also results in lower power consumption for distributing such clocks as well as lower power consumption for digitization primarily due to the lesser number of transitions involved.
  • a conventional single-edge triggered counter 104 increments or decrements the count 702 at only the positive (rising) edge or negative (falling) edge of the digitization clock 700, but not both.
  • a dual-edge triggered counter 604 increments or decrements the count 802 at both the positive (rising) edge and the negative (falling) edge of a digitization clock 800.
  • This methodology counts at the rate of the single- edge triggered counter 104 using half the clock frequency fo/2.
  • the resulting count 802 is the same as count 702 of Fig. 7, but the frequency of the applied clock 800 is smaller than that of clock 700 in Fig. 7.
  • a frequency divider 606 as shown in Fig. 6, which operates by way of non-limiting example as shown in Fig. 9. Note that during one cycle of the output clock 902 there may be multiple cycles of the input clock 904 (e.g., via a divisor y, where y>l), such that the frequency can be still further reduced.
  • a frequency multiplier 608 as shown in Fig. 11, which operates by way of non-limiting example as shown in Fig. 10. Note that there may be multiple cycles of the output clock 1002 during one cycle of the input clock 1004 (e.g., via a multiplier x, where x>l), such that the frequency can be still further increased.
  • the circuitry of Fig. 11 includes another embodiment of the invention directed to a multi-rate readout scheme.
  • a single-rate readout scheme of the prior art such as Fig. 1 operates as shown in Fig. 12, where data 1202 is read out using positive-edge triggered shift registers 102 at a desired rate by shifting n shift registers connected in series at a clock 1204 frequency fR.
  • a multi-rate readout scheme reads out data at the same rate by multiplexing, at frequency fR, data from m>l parallel readout lines 1104, 1106 of shift registers 1102. For n total shift registers in the row, each readout line 1104, 1006 connects with n/m shift registers 1102 in series.
  • shift registers 1102 are shifted at a clock frequency fo/m via the influence of the frequency divider 606 and/or frequency multiplier 608 in proximity to the shift registers, thereby reducing the frequency of the readout clock to be distributed across the column-parallel A/D architecture without compromising readout rate.
  • this also results in lower power consumption for distributing such clocks as well as lower power consumption for readout primarily due to the lesser number of transitions involved.
  • the multi-rate readout scheme in the column-parallel A/D architecture in a CMOS image sensor, shift registers 1102 in all columns are concurrently loaded with data from corresponding dual-edge triggered counters 604, and the stored data is read out during the next digitization session(s) for achieving high frame rate.
  • This design essentially incorporated several of the embodiments disclosed herein. However, the invention is not so limited, and not all embodiments need be present.
  • the circuit 1400 of Fig. 14 does not utilize a frequency multiplier 608 as in Fig.11.

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  • Engineering & Computer Science (AREA)
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Abstract

L'invention porte sur un système et un procédé de distribution d'horloge. Le procédé consiste à : recevoir un signal d'horloge; générer un complément du signal d'horloge; appliquer le signal d'horloge reçu et le complément généré du signal d'horloge à un premier verrou d'une pluralité de verrous connectés en série; propager le signal d'horloge reçu et le complément généré du signal d'horloge à travers la pluralité de verrous connectés en série; et prélever, au niveau d'une pluralité d'emplacements le long de la pluralité de verrous, une sortie afin d'attaquer une charge, la sortie étant soit le signal d'horloge propagé soit le complément du signal d'horloge propagé.
PCT/US2012/057534 2011-09-28 2012-09-27 Système et procédé de distribution d'horloge retardée dans des architectures a/n parallèles en colonne utilisées dans des capteurs d'image cmos WO2013049333A1 (fr)

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US201161540024P 2011-09-28 2011-09-28
US61/540,024 2011-09-28

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111294531A (zh) * 2020-03-12 2020-06-16 西安微电子技术研究所 一种高帧频cmos图像传感器及其实现方法

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US6121816A (en) * 1999-04-23 2000-09-19 Semtech Corporation Slave clock generation system and method for synchronous telecommunications networks
US6507247B2 (en) * 2001-02-27 2003-01-14 Corrent Corporation Circuit and method for generating a variable frequency clock signal
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US6757018B1 (en) * 1998-12-18 2004-06-29 Agilent Technologies, Inc. CMOS image sensor with pixel level gain control
US20070069810A1 (en) * 2005-09-23 2007-03-29 Korea Advanced Institute Of Science And Technology. SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit thereof
US7236057B2 (en) * 2003-08-26 2007-06-26 Toshiba America Electronic Components, Inc. Spread spectrum clock generator
US20080024639A1 (en) * 2001-03-13 2008-01-31 Ecchandes Inc. Visual device, interlocking counter, and image sensor

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Publication number Priority date Publication date Assignee Title
US4648105A (en) * 1985-06-06 1987-03-03 Motorola, Inc. Register circuit for transmitting and receiving serial data
US6757018B1 (en) * 1998-12-18 2004-06-29 Agilent Technologies, Inc. CMOS image sensor with pixel level gain control
US6121816A (en) * 1999-04-23 2000-09-19 Semtech Corporation Slave clock generation system and method for synchronous telecommunications networks
US6507247B2 (en) * 2001-02-27 2003-01-14 Corrent Corporation Circuit and method for generating a variable frequency clock signal
US20080024639A1 (en) * 2001-03-13 2008-01-31 Ecchandes Inc. Visual device, interlocking counter, and image sensor
US20030011413A1 (en) * 2001-06-29 2003-01-16 Masleid Robert P. Low latency clock distribution
US7236057B2 (en) * 2003-08-26 2007-06-26 Toshiba America Electronic Components, Inc. Spread spectrum clock generator
US20070069810A1 (en) * 2005-09-23 2007-03-29 Korea Advanced Institute Of Science And Technology. SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111294531A (zh) * 2020-03-12 2020-06-16 西安微电子技术研究所 一种高帧频cmos图像传感器及其实现方法
CN111294531B (zh) * 2020-03-12 2021-11-05 西安微电子技术研究所 一种高帧频cmos图像传感器及其实现方法

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