WO2013046464A1 - 不揮発半導体記憶媒体を有するストレージシステム - Google Patents
不揮発半導体記憶媒体を有するストレージシステム Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
Definitions
- the present invention relates to storage control of a storage system having a nonvolatile semiconductor storage medium.
- the storage system generally provides a logical volume created based on a RAID (Redundant Array of Independent Disks) group composed of a plurality of storage media to a higher-level device (for example, a host computer).
- RAID Redundant Array of Independent Disks
- flash storage using NAND flash memory has been adopted as a storage medium in addition to or in place of HDD (Hard Disk Drive).
- the NAND flash memory is a non-volatile semiconductor memory, and is read in units called pages. Similarly, writing is performed in units of pages, but it is necessary to erase the target area in advance when writing. Erasing is performed in units called blocks composed of a plurality of pages.
- the following control is effective.
- the erased area is created asynchronously with the I / O processing from the host device.
- Write target data from the host device is stored in an erased area prepared in advance.
- an update data storage area used as a buffer is required.
- the “update data storage area” referred to here is an empty storage area indicated by a physical address that is not assigned to any logical address (for example, valid data (the latest data for the logical address) in an erased block). Page not stored).
- Patent Document 1 describes a method of using a specific area in a block as an update data storage area.
- the size of the update data storage area greatly affects performance and life. Since the update data storage area is an area that cannot be directly used by the host device, it is generally not included in the user capacity (the storage capacity represented by the logical address space provided to the host device). Therefore, in a system that uses 55% of the physical mounting capacity compared to a system that uses 10% of the physical mounting capacity (total storage capacity of one or more flash storages) as the update data storage area, Even if the installed capacity is the same, the user capacity is halved. On the other hand, generally, the larger the update data storage area, the better the write performance and lifetime.
- the application program used (and / or used) It depends on the area and address. For example, for an area used by an application program that does not require high write performance, it is desirable to reduce the size of the update data storage area. Conversely, for an area that requires high write performance, the size of the update data storage area It is desirable to increase.
- An object of the present invention is to appropriately set the size of the update data storage area in the nonvolatile semiconductor storage medium.
- a storage system is connected to a nonvolatile semiconductor storage medium, a storage unit that stores logical-physical conversion information that is information representing a correspondence relationship between a logical address and a physical storage area of the nonvolatile semiconductor storage medium, and the storage unit and the nonvolatile semiconductor storage medium And a media controller which is a designated controller.
- the logical-physical conversion information includes information indicating the correspondence between a plurality of logical pages and a plurality of logical chunks constituting the logical address space of the nonvolatile semiconductor storage medium, and the correspondence between the plurality of logical chunks and the plurality of physical storage areas. Information to represent.
- Each logical page is a logical storage area according to a logical address range.
- Each logical chunk is assigned to two or more logical pages of the plurality of logical pages. Two or more physical storage areas among a plurality of physical storage areas are allocated to each logical chunk. Based on the logical-physical conversion information, the media controller identifies the physical storage area assigned to the logical chunk to which the logical page to which the logical address of the data write destination belongs is assigned, and stores the physical storage area in the identified physical storage area. , Configured to write the data. The media controller adjusts the number of physical storage areas to be allocated for each logical chunk.
- This storage system may be a single storage device having a non-volatile storage medium and a medium controller, or one or more such storage devices and a host controller that is a controller connected to the one or more storage devices. Or a storage device group obtained by combining a plurality of such storage devices.
- the host device may be a host device connected to a storage device or a storage device group, or the above-described host controller connected to a storage device.
- the size of the update data storage area in the nonvolatile semiconductor storage medium can be set appropriately.
- 1 shows an example of the overall configuration of a computer system including a storage system according to an embodiment.
- 2 shows an example of an internal configuration of a flash storage according to an embodiment.
- An example of the information stored in the memory in the flash storage according to the embodiment is shown.
- summary of the logical physical conversion process which concerns on an Example is shown. It is the flowchart which showed the 1st example of the flow of the write process which concerns on an Example.
- FIG. 4 shows a configuration example of logical chunk-physical chunk conversion information according to an embodiment.
- the structural example of the physical chunk structure information which concerns on an Example is shown.
- the structural example of the page information in a physical chunk based on an Example is shown.
- the structural example of the pool structure information which concerns on an Example is shown.
- the structural example of the capacity allocation information which concerns on an Example is shown.
- achieving the logical-physical conversion based on an Example is shown.
- the 1st example of the hierarchical structure regarding the logical physical conversion which concerns on an Example is shown.
- region correspondence correspondence between a logical chunk, a physical chunk, and a pool which concerns on an Example is shown.
- FIG. 6 shows an example of an address space correspondence relationship (relation between an address space used by a user and a logical address space on a flash storage device) according to the embodiment.
- xxx table various types of information may be described using the expression “xxx table”, but the various types of information may be expressed using a data structure other than a table. In order to show that it does not depend on the data structure, the “xxx table” can be called “xxx information”.
- identification information including a number is used to specify an element (for example, a page, a chunk, or a flash memory chip (FM chip)), but information that does not include a number is used as the identification information. May be.
- a combination of an element name and identification information may be used instead of a combination of an element name and a reference code.
- a page with identification information identification number “0” may be referred to as “page # 0”.
- the process may be described using “program” as the subject, but the program is executed by a processor (for example, a CPU (Central Processing Unit)) included in the controller, so that a predetermined process is performed.
- a processor for example, a CPU (Central Processing Unit) included in the controller, so that a predetermined process is performed.
- the subject of processing may be a controller or a processor.
- the processing described with the program as the subject may be processing performed by a flash storage device, flash storage, flash controller, RAID controller, or storage system, which will be described later.
- the controller may include a hardware circuit that performs a part or all of the processing performed by the processor instead of or in addition to the processor.
- the computer program may be installed in a later-described flash controller or RAID controller from a program source.
- the program source may be, for example, a program distribution server or a computer-readable storage medium.
- a set of one or more computers that manage a computer system may be called a management system.
- the management system displays the display information
- the computer is the management system.
- a combination of a computer and a display device is also a management system.
- processing equivalent to that of the management system may be realized with a plurality of computers.
- the plurality of computers if the display device performs display, display is performed).
- Management system has an input / output device. Examples of the input / output device include a display, a keyboard, and a pointing device.
- a touch panel display instead of a display, a keyboard, and a pointing device
- Apparatus may be employed.
- a serial interface or an Ethernet interface (Ethernet is a registered trademark) is used as an input / output device, and a display device having a display, a keyboard, or a pointer device is connected to the interface, and display information is displayed.
- the input and display on the input / output device may be replaced by displaying on the display device or receiving input by transmitting to the display device or receiving input information from the display device.
- an interface device may be abbreviated as “I / F”.
- the flash memory is a type of flash memory that is erased in units of blocks and accessed in units of pages, typically a NAND flash memory.
- the flash memory may be another type of flash memory (for example, NOR type) instead of the NAND type.
- other types of nonvolatile semiconductor storage media for example, phase change memory may be adopted.
- the nonvolatile semiconductor storage medium is a NAND flash memory.
- page and block are used.
- a certain logical page (referred to as “target logical page” in this paragraph) is a write destination, and a physical page (referred to as “first physical page” in this paragraph) has already been assigned to the target logical page. If the data is stored in the first physical page, the target logical page has an empty physical page (referred to as “second physical page” in this paragraph) instead of the first physical page. Allocate and write data to the second physical page. The data written in the second physical page is the latest data for the target logical page, and the data stored in the first physical page is old data for the target logical page.
- valid data the latest data
- invalid data the old data
- invalid physical page a physical page storing valid data
- invalid physical page a physical page storing invalid data
- FIG. 1 shows an example of the overall configuration of a computer system including a storage system according to the embodiment.
- the computer system includes a storage system 101, a host computer (hereinafter, host) 102, and a management system 103.
- the host 102 has a communication port for connecting to the storage system 101.
- the host 102 is connected to the storage system 101 through the host connection path 104 via this port.
- the management system 103 is connected to the storage system 101 through the management connection path 105.
- FIG. 1 shows a configuration in which the host 102 and the storage system 101 are directly connected
- the host connection path 104 may be a network called SAN (Storage Area Network), and includes many hosts, management systems, and storages. The structure which can respond to is sufficient.
- a protocol such as Fiber Channel or iSCSI can be used as the SAN.
- the management connection path 105 may be the same connection path as the host connection path 104 or a different connection path.
- the host connection path 104 may be a SAN
- the management connection path 105 may be a LAN (Local Area Network).
- At least one of the connection paths 104 and 105 may be a communication network other than the SAN or the LAN described above.
- the storage system 101 includes a RAID controller 111, a flash storage device 141, and a disk device 142.
- a flash storage device 141 and a disk device 142 are connected to the RAID controller 111 via the internal bus 112.
- the storage system 101 is a system that implements a redundant configuration using RAID, and therefore includes a RAID controller 111.
- the present invention is not limited to adopting a RAID configuration.
- the flash storage device 141 has an I / F switch 121 and a flash storage 131.
- the RAID controller 111 is connected to the I / F switch 121 via the internal bus 112, and the flash storage 131 is connected to the I / F switch 121 via the disk connection path 122.
- a storage medium that actually stores data is the flash storage 131.
- the flash storage 131 is, for example, an SSD (Solid State Drive).
- the disk device 142 includes a disk-type storage medium, for example, an HDD (Hard Disk Drive).
- the I / F of the HDD may be, for example, FC (Fibre Channel), SAS (Serial Attached SCSI), or ATA.
- the disk-type storage medium may be another type of medium instead of the HDD, for example, a DVD (Digital Versatile Disk) drive.
- another type of storage medium for example, a tape device having a tape may be used.
- the flash storage device 141 and the disk device 142 are described separately, but the flash storage 131 and other disk devices can be mixed by making these devices physically and logically compatible. It is.
- an SSD having a SAS protocol disk I / F and a SAS HDD can be stored and used in the same apparatus.
- FIG. 2 shows an example of the internal configuration of the flash storage 131.
- the flash storage 131 has a flash controller and a flash memory connected to the flash controller.
- the flash controller has an upper I / F, a storage unit, a buffer memory 213, a lower I / F, and a control unit connected to them.
- the host I / F is, for example, the host input / output control unit 201.
- the storage unit includes a memory 211, for example.
- the lower I / F is, for example, the flash input / output control unit 203.
- the control unit includes, for example, a data transfer control unit 202 and a CPU 212.
- the components 201, 202, 203, 213, 211 and 212 are connected by an internal bus 222.
- the flash memory has a plurality of FM (flash memory) chips 1451.
- the plurality of FM chips 1451 are connected to the flash input / output control unit 203 via the FM bus 223.
- the flash memory may be an example of an auxiliary storage device.
- the host I / O control unit 201 is connected to the I / F switch 121 through the disk connection path 122 and controls data input / output with the host device.
- the data transfer control unit 202 controls data transfer in the flash storage 131.
- the flash input / output control unit 203 controls data input / output to / from the FM chip 1451 through the FM bus 223.
- the CPU 212 is connected to the data transfer control unit 202 via the internal bus 222, executes various arithmetic processes according to programs stored in the memory 211, and controls the entire flash storage 131.
- the buffer memory 213 temporarily stores data exchanged with the host input / output control unit 201 and the flash memory input / output control unit 203.
- At least one of the components shown in FIG. 2 may not be in the flash storage 131.
- a configuration using a chip in which the control units such as the CPU 212 are integrated, or a configuration using a chip that integrates only a part thereof may be employed.
- a configuration in which the memory 211 and the buffer memory 213 are physically the same memory may be employed.
- FIG. 3 shows an example of information stored in the memory 211.
- the memory 211 may be an example of a main storage device.
- the memory 211 stores, for example, an operating system 301, a flash storage control program 302, a data transfer control unit control program 303, an input / output control unit control program 304, a logical physical conversion program 311 and logical physical conversion information 312.
- Programs 301 to 304 and 311 are programs executed by the CPU 212.
- the operating system 301 is a program that performs basic processing such as scheduling when the CPU 212 executes each program.
- the flash storage control program 302 is a program used for control for the flash storage 131 to operate as a storage device, such as management of a volume provided by the flash storage 131 to a host device and management of a buffer memory.
- the data transfer control unit control program 303 is a program used for control of the data transfer control unit 202.
- the input / output control unit control program 304 is a program used for controlling the host input / output control unit 201 and the flash input / output control unit 203.
- the logical-physical conversion program 311 is a physical address in which a logical address that is an input / output request (I / O request) issued from a higher-level device (in this embodiment, the RAID controller 111 or the host 102) is a physical location on the flash memory. This is a program that converts and determines which part of the file corresponds to.
- the “logical address” referred to in the present embodiment may be, for example, an LBA (Logical Block Address).
- the logical / physical conversion information 312 is information for conversion used when the logical / physical conversion program 311 operates.
- the memory 211 may store information for controlling the host device input / output control unit 201 and the flash input / output control unit 203.
- FIG. 4 shows an example of an outline of logical-physical conversion processing.
- the logical address layer 1401 is an address that represents the position on the volume that the flash storage 131 provides to the host device (in the embodiment, the RAID controller 111 or the host 102).
- the logical space is divided into a plurality of logical pages 1411, and the size of the logical page 1411 is the same as the size of the physical page of the FM chip 1451.
- the size of the logical page 1411 is assumed to be 8 volume blocks.
- the “volume block” referred to here is an individual storage area constituting a logical volume provided to the host 102.
- the logical / physical conversion program 311 associates the logical address layer area with the physical area in the physical layer 1405.
- the physical layer 1405 is a layer composed of a plurality of FM chips 1451.
- Each FM chip 1451 includes a plurality of physical blocks 1452 which are erase units of the NAND flash memory.
- Each physical block 1452 includes a plurality of physical pages 1453 that are read / write units.
- the logical page 1411 is associated with the physical page 1453.
- the area from LBA 0x00 to 0x07 is allocated to physical page # 0 of physical block # 0 of FM chip # 0.
- the flash controller receives the read request and follows the read request. Based on the above allocation information (logical / physical conversion information 312), data is read from physical page # 0 of physical block # 0 of FM chip # 0, and the result (including the read data) is returned to the host device. It becomes.
- the logical page size and the physical page size are the same, but they are not necessarily the same.
- the storage position can be determined for each smaller range of the logical space. That is, four volume blocks from logical addresses 0x00 to 0x03 and four volume blocks from 0x04 to 0x07 can be stored in separate physical pages.
- the logical page size is larger than the physical page size, it is desirable to place some restrictions on the physical page arrangement. For example, the range from logical address 0x00 to 0x0F will be associated with two physical pages, but these physical pages are automatically based on certain rules, such as consecutive physical pages in the same physical block. It is desirable that the page group be determined by In this case, it is equivalent to virtually expanding and using the physical page, and management information can be reduced.
- FIG. 5 is a flowchart showing an example of the flow of write processing.
- the write process is started.
- the write process is typically started when the flash controller receives a write request from a host device.
- the flash controller determines whether there are enough free physical pages for writing (for example, whether the total size of free physical pages appropriate as a data write destination is equal to or larger than the size of the data to be written). (S502). This is because the NAND flash memory cannot be overwritten, and it is necessary to erase in advance when writing. In step S502, it is determined whether there is a writable erased physical page.
- the flash controller writes the data to be written to the free physical page (S503), and ends the processing (S504).
- the flash controller selects a free physical page creation target block from a plurality of erase candidate physical blocks (S511).
- the “erase candidate physical block” is, for example, a physical block in which data is written up to the last physical page. In particular, a physical block with few physical pages (physical pages storing valid data) associated with a logical address is desirable as an erasure candidate for page saving processing described later.
- the flash controller saves the valid data in the selected physical block to another free physical block (S512).
- the valid data is data existing in the physical page actually allocated to the logical page at the time of this processing according to the above-described definition. Since valid data is data that must not be erased, it must be saved to another physical block.
- the valid data saving process is a process of copying valid data in a valid physical page to a physical block different from the physical block having the valid physical page, and updating the allocation relationship.
- the copy source data changes from valid data to invalid data (unnecessary data), so the copy source physical page changes from a valid physical page to an invalid physical page.
- the free physical page creation target block (copy source physical block) is configured only with non-valid physical pages, that is, invalid physical pages or empty physical pages that originally do not contain data. Become.
- the flash controller performs an erasing process on the free physical page creation target block (the physical block selected in S511) (S513).
- the free physical page creation process (S511 to S513) is performed in the write process, but this is asynchronous with the write process (that is, not the process included in the write process but the write process). May be performed as a separate process).
- FIG. 6 shows the states of a plurality of physical blocks and physical pages at the first time point in the first viewpoint of page state transition.
- the logical / physical conversion information 312 includes a logical / physical conversion table T601 corresponding to the hierarchical structure of FIG.
- the table T601 is a simplified table of logical-physical conversion tables, and is a block page table having information on physical blocks and physical pages.
- the number of physical pages in the physical block is 4, and the area usable by the user is 75% of the total physical capacity. That is, among the four physical pages in the physical block, on average, three physical pages are in a valid state (valid physical page).
- valid data is stored in the physical pages # 0, # 1, and # 2 in the physical block # 10, and the physical page in the physical block # 10.
- # 3 is empty.
- Physical block # 22 is in a state immediately after the erasure process (all physical pages are free physical pages).
- FIG. 7 shows a block page table T601 at a time point (second time point) after a write occurs after the time point in FIG.
- the data at the address # 101 is stored in the physical page # 3 of the physical block # 10, which is an empty physical page at the first time point.
- the physical page # 1 of the physical block # 10 that has stored the data of the address # 101 at the first time point is an invalid physical page because unnecessary data has already been stored.
- the table T601 at the second time point corresponds to the state after the execution of S503 in FIG.
- FIG. 8 shows the block page table T601 at the time (third time point) after the effective data saving process is performed from the time point of FIG.
- the valid data in the valid physical pages # 0, # 2 and # 3 of the physical block # 10 at the second time point are the physical pages # 0 and # 1 of the physical block # 22. And physical pages # 0, # 2 and # 3 as copy sources are all invalid physical pages.
- the table T601 at the third time point corresponds to the state after the execution of S511 in FIG.
- FIG. 9 shows a block page at the time point (fourth time point) after the erasure process is performed on the physical block # 10 that has become all invalid physical pages (invalid physical pages or empty physical pages) from the time point of FIG. Table T601 is shown.
- the size of the write according to the write request issued from the higher-level device is equal to or smaller than the size of one page (physical page # 3 of physical block # 10).
- the write performed to the flash memory also includes a copy of the valid physical page, four pages (physical page # 3 of physical block # 10, physical page # 0 of physical block # 22, physical block # 22) Physical page # 1 and physical page # 2 of physical block # 22).
- FIG. 10 shows the block page table T601 at the first time point in the second viewpoint of the page state transition.
- the area usable by the user is 50% of the total physical capacity. That is, of the four physical pages in the physical block, two physical pages are valid on average.
- FIG. 11 shows a block page table T601 at a time point (second time point) after a write occurs from the time point of FIG.
- the data of the addresses # 101 and # 100 are stored in the physical pages # 2 and # 3 of the physical block # 10, which are free physical pages at the first time point, respectively. Thereby, the physical pages # 0 and # 1 of the physical block # 10 are invalid physical pages, respectively.
- the table T601 at the second time point corresponds to the state after the execution of S503 in FIG.
- FIG. 12 shows the block page table T601 at the time (third time point) after the effective data saving process is performed from the time point of FIG.
- the data of the valid physical pages # 2 and # 3 included in the physical block # 10 at the second time point are transferred to the physical pages # 0 and # 1 of the physical block # 22.
- the copied physical pages # 2 and # 3 are all invalid physical pages.
- the table T601 at the third time point corresponds to the state after the execution of S511 in FIG.
- FIG. 13 shows a block page table T601 at the time point (fourth time point) after the erasure process is performed on the block 10 that has become all invalid physical pages (invalid physical pages) from the time point of FIG.
- FIG. 10 when FIG. 10 is compared with FIG. 13, the number of physical pages is the same for each attribute (valid, invalid, empty), although the data storage positions are different, as in the relationship between FIG. 6 and FIG. 9. I understand.
- two pages (physical pages # 2 and # 3 of physical block # 10) are written in accordance with the write request issued from the host device.
- the write performed on the flash memory since the write performed on the flash memory also includes a copy of the valid physical page, it corresponds to four pages (physical pages # 2 and # 3 of physical block 10 #, physical pages # 0 and # 3 of physical block # 22). 1).
- FIGS. 6 and 9 and FIG. 10 and FIG. 13 have different ratios (capacity ratios) of user-usable capacity to physical capacity as preconditions, and this difference is a free physical page for writing (update data storage area). ) Affects the difference in amount.
- FIGS. 6 to 9 and FIGS. 10 to 13 four pages are written to the flash memory. However, according to the write request from the host device, one page and two pages are written respectively. There is a difference in the amount of writing (the number of pages to which data is written).
- the performance deteriorates because the resources required for flash memory access by the write or copy process are used,
- the lifetime is shortened by increasing the number of writes to the flash memory. That is, it is shown that the performance and life can be improved by increasing the update capacity.
- FIG. 25 shows a first example of a hierarchical structure for realizing logical-physical conversion according to the embodiment.
- the highest layer is a logical address layer 1401, which is a layer for the RAID controller 111 and the host 102, which are higher-level devices, to recognize.
- the logical address layer 1401 is managed by a logical page 1411 having the same size as the physical page 1453.
- a logical chunk layer 1402 is provided as a first intermediate layer between the logical address layer 1401 and the physical layer 1405.
- the logical chunk layer 1402 is composed of a plurality of logical chunks 1421.
- Each logical chunk 1421 is composed of a plurality of LC pages 1422.
- a page in the logical chunk 1421 may be referred to as an “LC page”.
- the logical page (logical address range) 1411 is mapped as the LC page 1422. Further, the LC page 1422 is mapped to the physical page 1453 in the physical layer 1405.
- the logical page 1411 is allocated to the physical page 1453 via the logical chunk 1421 (LC page 1422), and the actual data storage location is determined. For example, LBA0x00 is mapped as LC page # 00, and LC page # 00 is mapped to physical page # F001. For this reason, data with LBA0x00 as the write destination is stored in the physical page # F001.
- the logical chunk 1421 is mapped to the FM chip 1451. That is, logical chunk # 0 is mapped to FM chip # F0, and logical chunk # 1 is mapped to FM chip # F1. This means that the LC page 1422 in the logical chunk # 0 is associated only with any physical page of the FM chip # F0.
- the size of the logical-physical conversion information 312 can be reduced. For example, if there is no or only one logical chunk 1421 and the number of pages to be mapped is, for example, 2 16, information of 2 bytes per page is required as information included in the logical-physical conversion information 312. Become.
- the number of pages to be mapped in the logical chunk 1421 is, for example, 2 8, and the information included in the logical physical conversion information 312 is For example, 1 byte may be used per page.
- the size of the logical-physical conversion information 312 can be reduced.
- FIG. 14 shows a second example of a hierarchical structure for realizing logical-physical conversion according to this embodiment.
- the number of intermediate layers existing between the logical address layer 1401 and the physical layer 1405 is larger than that in the first example shown in FIG.
- the highest layer is the logical address layer 1401 and the logical chunk layer 1402 described above is below the logical address layer 1401.
- the physical chunk layer 1402 is further below the physical chunk layer 1402.
- a chunk layer 1403 is provided, and a pool layer 1404 is provided below the physical chunk layer 1403.
- a lower layer of the pool layer 1404 is a physical layer 1405. Either one of the physical chunk layer 1403 and the pool layer 1404 may be omitted.
- the physical chunk layer 1403 is composed of a plurality of physical chunks 1431.
- Each physical chunk 1431 is composed of a plurality of blocks 1431.
- Each block 1431 includes a plurality of pages 1433.
- a block in the physical chunk 1431 may be referred to as a “PC block”
- a page in the physical chunk 1431 may be referred to as a “PC page”.
- the pool layer 1404 includes a plurality of pools 1441.
- Each pool 1441 includes a plurality of blocks 1442.
- Each block 1442 is composed of a plurality of pages 1443.
- Each pool 1441 may be the same size.
- a block in the pool 1441 may be referred to as a “pool block”, and a page in the pool 1441 may be referred to as a “pool page”.
- the plurality of FM chips 1451 may constitute a plurality of FM chip groups, and the pool may be based on one or more FM chip groups.
- the FM chip group may be a circuit board having a plurality of FM chips constituting the FM chip group, for example, a DIMM (Dual Inline Memory Module).
- the chip enable lines of two or more FM chips 1451 may be common. Further, the chip enable lines of the plurality of FM chips 1451 may be common across two or more FM chip groups. In this case, if one chip enable line is activated, data can be written in parallel to a plurality of FM buses 223 sharing the chip enable line. Therefore, as described later, it is desirable to perform mapping such that physical pages of a plurality of different FM chips on the FM bus 223 are allocated to adjacent logical pages 1411.
- the PC page 1433 and the pool page 1443 are substantially the same as the physical page 1453.
- the PC block 1432 and the pool block 1442 are substantially the same as the physical block 1452.
- the logical chunk 1421 is mapped to the physical chunk 1431 on a one-to-one basis, for example.
- the PC block 1432 is mapped to the pool block 1442 on a one-to-one basis, for example.
- the pool block 1442 is mapped to the physical block 1452 on a one-to-one basis, for example.
- LBA0x00 is mapped to LC page # 00.
- the LC page # 00 is mapped to the PC page # C010 in the physical chunk # C0 to which the logical chunk # 0 is mapped.
- the PC page # C010 is mapped to the pool page # P010 in the pool block # P01 to which the PC block # C01 is mapped.
- Pool page # P010 is mapped to physical page # F010 in physical block # F01 to which pool block # P01 is mapped.
- Appropriate performance, lifetime, and logical-physical conversion information size can be obtained by giving restrictions or degrees of freedom in mapping in each of these layers.
- striping is performed in the conversion from the logical address layer 1401 to the logical chunk layer 14012, and adjacent logical address ranges (logical pages 1411) are not the same logical chunk 1421 but different logical addresses.
- adjacent logical address ranges (logical pages 1411) are allocated to different physical resources and can be processed in parallel. As will be described later, this assignment is performed in this embodiment.
- the logical chunk 1421 and the physical chunk 1431 have a one-to-one correspondence.
- logical chunk # 0 is fixedly assigned to physical chunk # C0.
- the assignment of pages 1422/1433 in logical / physical chunks 1421/1431 can be freely changed. For example, in FIG.
- the LC page # 00 of the logical chunk # 0 is mapped to the PC page # C010 of the PC block # C01 of the physical chunk # C0, but at this location in the logical space (LBA0x00)
- the data is written to another PC page on the physical chunk # C0, and there is no particular restriction on the position. For this reason, the data to be written can be arranged at a free position on the physical chunk 1431.
- pages with similar tendencies for example, data with similar access frequency
- Increasing the degree of freedom with respect to the physical position makes it possible to collect pages having a similar tendency and reduce the copy amount.
- the disadvantage is that the size of the logical physical conversion information 312 increases.
- a mapping table indicating the correspondence between the LC page 1422 and the PC page 1433 is displayed as a logical physical. It is necessary to include it in the conversion information 312.
- a plurality of physical chunks 1403 use the resources of one pool 1441 in the conversion between the physical chunk layer 1403 and the pool layer 1404.
- the unit of resources given from the pool 1441 to the physical chunk 1403 is a block 1442, and the block 1432 in the physical chunk 1403 is mapped to the block 1442 in the pool 1441 on a one-to-one basis.
- this correspondence is changed dynamically.
- block # C01 of physical chunk C # 0 is assigned to block # P01 of pool # P0
- block # C10 of physical chunk # C1 is mapped to block # P02 of pool # P0. Yes.
- the page unit mapping is not performed, and is determined by the relative position in the block.
- page # C010 which is the first page of block # C01
- page # C011 is allocated to page # P011, and these are automatically determined when the allocation relationship (C01 and P01) between blocks is determined. The allocation between blocks will be described later.
- the relationship between the pool layer 1404 and the physical layer 1405 is determined by mapping between the blocks 1442 and 1452. It is assumed that the mapping (correspondence relationship) between the blocks 1442 and 1452 is fixed in this embodiment. For example, block # P01 in pool # P0 is allocated to block # F01 of FM chip # F0.
- the mapping between the pages 1443 and 1453 is uniquely determined by the relative position in the blocks 1442 and 1452, similarly to the page 1433 in the block 1432 in the physical chunk 1403 and the page 1443 in the block 1442 in the pool 1441.
- the above-described parallel processing can be easily performed by appropriately determining the physical resource mapping.
- adjacent logical address ranges are mapped to different adjacent logical chunks 1421, and adjacent logical chunks 1421 are mapped to adjacent physical chunks 1431.
- the FM bus 223 is preferably different. Since the block 1432 used in the physical chunk 1431 changes dynamically, the block 1402 cannot be fixedly mapped.
- the pool 1441 to be used is mapped to each physical chunk 1431. That is, the adjacent pool 1441 is mapped to the adjacent physical chunk 1431, and further, different FM chips (preferably, FM chips having different buses 223) 1451 are mapped to the adjacent pool 1441. To do.
- adjacent logical address ranges (logical pages) 1411 are mapped to different FM chips (preferably, FM chips with different FM bus 223) 1451.
- FM chips preferably, FM chips with different FM bus 223
- a plurality of FM chips 1451 can be accessed in parallel (that is, parallel processing is performed) at the time of access to large-size data or sequential access.
- all of the above are implemented by fixed mapping and parallel processing is realized, and there is no need to be aware of the FM chip 1451 which is a physical position in dynamic physical block mapping. For this reason, the restriction of the physical position can be realized by a prior configuration, and an arithmetic process for restricting the physical position is not necessary during the IO process.
- the page 1411 to which LBA0x00 belongs and the page 1411 to which LBA0x08 belongs are assigned to logical chunks # 0 and # 1, respectively.
- Logical chunks # 0 and # 1 are assigned to physical chunks # C0 and # C # 1, respectively.
- Physical chunks # C0 and # C # 1 are assigned to pools # P0 and # P1, respectively.
- Pools # P0 and # P1 are assigned to FM chips # F0 and # F1, respectively. Therefore, both FM chips # F0 and # F1 are operated in a case where adjacent logical pages 1411 (page 1411 to which LBA0x00 belongs and page 1411 to which LBA0x08 belongs) are accessed simultaneously or successively.
- the pool block # P02 is assigned to the physical chunk # C1, but as described above, these correspondences are dynamically changed.
- the pool block 1442 assigned to a certain physical chunk 1431 not only the position of the pool block 1442 is changed, but also the number of pool blocks 1442 assigned to the physical chunk 1431 can be changed.
- the number of LC pages 1422 included in a certain logical chunk 1421 is fixed, and the number of PC blocks 1432 included in the physical chunk 1431 can be increased or decreased.
- the physical resource amount allocated to a certain logical space that is, the actual number of physical pages that can be used for a certain number of logical pages is increased or decreased, and the performance and lifetime can be adjusted. Details of this method will be described later with reference to FIGS.
- the above adjustment is realized by fixing the number of pages 1422 in the logical chunk 1421 and changing the number of blocks 1432 in the physical chunk 1431.
- other methods are used. May be.
- the number of LC pages 1422 included in the logical chunk 1421 may be increased or decreased.
- the correspondence relationship between the logical chunk 1421 and the physical chunk 1431 is one-to-one, but may be one-to-many or many-to-one.
- the size of all pages from the logical address layer 1401 to the pool layer 1404 is the same as the size of the physical page 1453 of the physical layer 1405.
- the size of a page (hereinafter sometimes referred to as “upper page”) in at least one layer may be different from the size of the physical page 1453. For example, one of the following: (1) By realizing the size of the upper page smaller than the size of the physical page 1453, the performance and life for smaller size accesses are improved. (2) The size of the logical physical conversion information 312 is reduced by making the size of the upper page larger than the size of the physical page 1453. (3) Parallel processing is realized by assigning one logical page 1411 in the logical address layer 1401 to a plurality of physical pages 1453 of different FM chips 1451 (preferably FM chips 1451 having different FM buses 223). May be adopted.
- the resource considered in the physical layer 1405 may not be limited to the FM chip 1451 itself.
- the dies may be considered as resources.
- the FM bus 1223 connected to the chip enable which is a kind of control line of the FM chip 1451 and / or a plurality of FM chips 1451 is connected to the physical layer 1405 is aware of parallel processing. May be considered as a resource.
- FIG. 15 shows an example of a correspondence relationship between the logical chunk 1421, the physical chunk 1431, and the pool 1441.
- All the LC pages 1422 belonging to the logical chunk 1421 are allocated to the PC page 1433 in the physical chunk 1431. Basically, one of the PC pages 1433 is assigned to the LC page 1422 corresponding to the logical page 1411 that is the write destination. Also, blocks # 0, # 1 and # 2 belonging to physical chunk # 0 are blocks # 1, # 0 and # 2 belonging to pool # 0, which are used by physical chunk # 0 Is in a state of being. Block # 3 of pool # 0 is not assigned to physical chunk # 0. In the example of FIG. 15, there are eight LC pages 1422 included in the logical chunk # 0, and twelve PC pages 1433 included in the physical chunk # 0 allocated thereto.
- FIG. 16 shows a state in which pool block # 3 is further assigned to physical chunk # 0 from the state of FIG.
- FIG. 26 shows a situation where logical page mapping is organized from the state of FIG.
- the state where the logical page 1411 (LC page 1422) is not allocated to the block # 3 of the physical chunk # 0 is created by the valid data saving process of S512 in FIG.
- the state in which block # 3 of physical chunk # 0 is released from the state of FIG. 26 is equivalent to FIG. At this time, there are 8 pages 1422 included in the logical chunk # 0 and 12 pages 1433 included in the physical chunk # 0.
- the block # 3 of the pool # 0 that has been allocated to the block # 3 of the physical chunk # 0 is in a state in which the allocation state is released and does not belong to any physical chunk 1431. is there. Therefore, as performed in FIGS. 15 to 16, the block # 3 of the pool # 0 may be newly allocated to the physical chunk # 0 and the physical chunk 1431 using the other pool # 0.
- FIG. 28 shows an example of a flow in which the process of acquiring the block 1442 from the pool 1441 is added to the write process (FIG. 5).
- FIG. 5 shows an example of a flow in which the process of acquiring the block 1442 from the pool 1441 is added to the write process (FIG. 5).
- the flash controller determines whether there are enough blocks in the write-destination physical chunk (S2802).
- the write destination physical chunk is a physical chunk mapped to a logical chunk including a page corresponding to the logical address range (page 1411) to which the write destination logical address belongs.
- the details of the determination in S2802 will be described later.
- the determination in S2802 is a determination as to whether or not the number of blocks in the physical chunk is greater than or equal to the expected value.
- the expected value of the number of blocks in the physical chunk can be found, for example, based on “target” of “capacity allocation state” in table T2301 shown in FIG.
- the flash controller obtains blocks from the pool (S2812).
- the pool from which the block is acquired may be any pool, but may be selected based on a given policy (for example, capacity or performance). For example, a flash controller accesses adjacent logical address ranges if performance is important (for example, if multiple FM chips operate in parallel when access occurs in a continuous logical address range).
- the pool may be selected so that a different pool (FM chip) is accessed in the event of occurrence.
- the flash controller When there are enough blocks, the flash controller needs to generate an empty block from the already allocated block in the write destination physical chunk, and therefore performs an empty block generation process (S2813) for the write destination physical chunk. After performing block acquisition (S2812) and free block generation processing (S2813), the flash controller returns to the determination of the number of free physical pages for writing (S2802) and continues the write processing.
- S2811, S2812, and S2813 a series of processes (S2811, S2812, and S2813) for generating a free physical page are performed in synchronization with the write process, but these are the same as the free physical page generating process in FIG.
- the write process may be performed asynchronously.
- FIG. 29 shows an example of the flow of empty block generation processing (S2813).
- the flash controller When the free block generation process is started (S2901), the flash controller first selects a free physical page generation target block (S2902). Next, the flash controller saves the valid data in the selected block to another block (S2903), and thereafter, since the block is composed only of non-valid physical pages, the flash controller erases the block. (S2904).
- the processing up to S2904 is equivalent to the empty block generation processing (S511, S512, S513) in FIG. 5, and an empty block is thereby generated.
- the flash controller determines whether the number of blocks in the physical chunk being processed is greater than or equal to the expected value (S2905).
- the flash controller ends the empty block generation process as it is (S2906).
- the flash controller returns the generated free block to the pool (S2911).
- the return destination Boolean may be a pool based on the FM chip 1451 having an empty block.
- S2911 corresponds to a process for releasing a block allocated to a physical chunk, and is a process for allocating an appropriate amount of blocks to each physical chunk.
- the empty block generation process is executed in synchronization with the write process. However, as with the empty physical page generation process, the empty block generation process may be executed asynchronously with the write process. .
- FIG. 17 shows an example of an information group included in the logical-physical conversion information 312.
- Logical physical conversion information 312 includes logical chunk configuration information 1701, logical chunk-physical chunk conversion information 1702, physical chunk configuration information 1703, physical chunk page information 1704, pool configuration information 1705, and capacity allocation information 1706. including. Hereinafter, these pieces of information will be described.
- FIG. 18 shows a configuration example of the logical chunk configuration information 1701.
- This information 1701 includes a logical chunk configuration information table T1801.
- the table T1801 indicates to which logical chunk and LC page each logical page 1411 of the logical address layer 1401 is assigned in the logical chunk layer 1402.
- a simple allocation method between the logical address layer and the logical chunk layer is also effective. For example, when the LC page number in a logical chunk increases in ascending order of LBA (logical address) and the LC page number reaches a number according to the upper limit of the number of pages of the logical chunk, the LBA is assigned to the next logical chunk.
- a method is conceivable.
- table T1801 in FIG. 18 a method in which logical chunk numbers are added in the ascending order of LBA without changing the page number in the logical chunk.
- FIG. 19 shows a configuration example of logical chunk-physical chunk conversion information 1702.
- This information 1702 includes a logical chunk-physical chunk conversion information table T1901.
- the table T1901 indicates to which physical chunk 1431 and PC page 1433 of the physical chunk layer 1403 the page 1422 in the logical chunk 1421 is assigned.
- page unit mapping is performed between the logical chunk layer 1402 and the physical chunk layer 1403.
- FIG. 20 shows a configuration example of the physical chunk configuration information 1703.
- This information 1703 includes a logical chunk configuration information table T2001.
- Table T2001 indicates where the physical chunk 1431 uses the pool, how many blocks it currently owns, and what the number of those blocks is.
- the blocks in use with respect to the physical chunk 1431 are arranged in order. Thereby, the corresponding physical block number and the position of the page in the physical block are specified from the number of the page in the physical chunk 1431 in the table T1901. That is, the position in page units is specified.
- FIG. 21 shows a configuration example of the physical chunk page information 1704.
- the information 1704 includes a physical chunk page information table T2101.
- the table T2101 shows the status of each block belonging to each physical chunk and the page in the block (whether it is assigned to which LC page, whether it is not assigned and invalid data is stored, or is a free physical page) ).
- This table T2101 is not necessarily only information essential for IO processing.
- the block number is specified from the used block number in this table T2101, and the page numbers need not be registered in the table T2101 by arranging them in order.
- the page number in the logical chunk may be unnecessary because there is a method for examining the physical position from the logical position in the reverse direction.
- this information is useful when it is necessary to investigate the logical position from the physical position. In such a case, for example, a failure occurs in the FM chip 1451 or a part thereof, and it becomes necessary to specify the logical position from the physical position (FM chip, block, or page) where the failure occurs and to save the data. Cases are possible.
- FIG. 22 shows a configuration example of the pool configuration information 1705.
- This information 1705 includes a pool configuration information table T2201.
- the table T2201 indicates the state of FM chips and physical blocks that are the basis of each pool (for example, which physical chunk currently belongs to, unaffiliated, or free).
- information about resources to be managed by the physical layer 1405 such as the FM bus 223 may be described.
- FIG. 23 shows a configuration example of the capacity allocation information 1706.
- This information 1706 includes a capacity allocation table T2301.
- This table T2301 indicates what attributes and states each storage area has and how it should be changed.
- the storage area is indicated by a logical address.
- attributes of each storage area for example, attributes determined from the usage method of the host device such as RAID5 parity, attributes determined from statistical information during operation such as high-frequency write, capacity specification, etc. There are attributes that are determined by instructions from the manager.
- the information finally obtained from this table T2301 is preferably the capacity (number of blocks) to be allocated to each physical chunk. . Therefore, in the capacity allocation table T2301, conversion from the storage area to the physical chunk number is performed.
- a configuration is adopted in which a certain continuous storage area is composed of a plurality of physical chunks, and a certain physical chunk does not span a plurality of storage areas. It is desirable to employ when the storage area size is large, the logical chunk size is small, and the striping size and number are small.
- one physical chunk extends over a plurality of storage areas, making management in the format shown in FIG. 23 difficult.
- the current allocated capacity and the target capacity are managed for each physical chunk.
- the target allocation capacity is the same for the physical chunks having the same attribute.
- physical chunk blocks are secured and released.
- the physical chunk # 0 associated with the storage area # 1 is currently 4 MB with respect to the target 4 MB, and therefore, block reservation / release processing is not particularly performed.
- the physical chunk # 10 associated with the storage area # 1 is currently 6 MB in relation to the target 8 MB, and the number of allocated blocks is too small. Therefore, a block will be added to the physical chunk # 10.
- a specific physical chunk allocation target size is determined from the attributes of the storage area, and resources may be allocated from the pool 1441 in accordance with the target.
- resources may be allocated from the pool 1441 in accordance with the target.
- the storage area represented by the capacity allocation table T2301 is indicated by a logical address, and as described above, there are items determined by instructions from the administrator in the attributes of each storage area. However, it is difficult to specify the logical address on the flash storage device 141 from the host 102 and the management system 103 that use the storage system 101.
- FIG. 30 shows an example of the relationship between the address space used by the user of the host 102 (and / or the management system 103) and the logical address space on the flash storage device 141.
- the user address space 3001 used by the user is usually determined by an LU (Logical Unit) number and its logical address (LBA).
- LBA logical address
- FIG. 30 there are a plurality of LUs 3001 and a plurality of logical blocks 3021 exist therein.
- the LU 3011 in the user address space 3001 is assigned to an LU 3012 configured across a plurality of flash storage logical spaces 3002.
- the logical block 3021 in the user address space 3001 is also assigned to the volume block 3022 in the flash storage logical space (logical address space) 1401.
- FIG. 30 shows an example of allocation.
- This allocation method is based on a configuration method for upper data for providing redundancy called RAID level, data storage arrangement, and a unit of data distribution called striping.
- RAID level a configuration method for upper data for providing redundancy
- data storage arrangement a configuration method for data for providing redundancy
- striping a unit of data distribution called striping.
- the LU may be a pool LU including a segment assigned to a virtual LU (TP-LU) area according to Thin Provisioning.
- the pool LU is an LU constituting a capacity pool, and is divided into a plurality of segments and managed.
- a segment is assigned to the TP-LU area. In this case, the segment may be composed of one or more logical blocks 3021.
- FIG. 24 shows an example of a management screen for setting a capacity allocation policy.
- the “management screen” referred to here is a screen displayed on the display of the management system.
- the management screen 2401 displays a capacity allocation policy setting status 2411 and a capacity allocation policy setting part 2412.
- the capacity allocation policy setting status 2411 includes a policy setting status table 2421 that indicates the current policy of each LU.
- Normal set for LU # 1 means that the capacity of the amount normally used in the flash storage device 141 is allocated. In other words, the physical chunk capacity that can be allocated to logical chunks on average in the flash storage device 141 is assigned to the logical chunks used by LU # 1.
- “Performance / lifetime priority” set for LU # 2 means that a larger physical chunk capacity is allocated to the logical chunk used by LU # 2 so as to be advantageous in terms of performance / lifetime.
- Capacity priority set for LU # 3 means that a smaller physical chunk capacity is allocated to the logical chunk used by LU # 3.
- “Large write amount” set for LU # 4 is not in the form of designation of allocation amount, but is designated by the user in the form of IO characteristics for the LU concerned. Since the write amount is large, in order to operate the LU efficiently, the same setting as the performance / lifetime priority is performed. That is, a larger physical chunk capacity is allocated to the logical chunk used by LU # 4.
- Update capacity 20% set for LU # 5 takes the form of a specific capacity ratio specification. In this case, a physical chunk capacity of 120% of the capacity is allocated to the logical chunk used by LU # 5.
- the capacity allocation policy setting part 2412 includes a setting part 2431, an execution button 2432, and a cancel button 2433.
- a target LU and a policy to be set are selected, and an execution button 2432 is pressed to reflect a combination of LU and policy.
- the policy is set in units of LUs, but may be set in other types of units that can be specified by the user. For example, when performing the most detailed setting, it is the same as the storage area in the capacity allocation table T2301, which is a logical chunk unit in this embodiment.
- LU is desirable as a unit by which the user can recognize the IO characteristics and the target performance in order to prevent the user from making settings in consideration of the flash storage.
- a file system unit or a file unit when a file server is used as the host device may be useful as these setting units.
- the settings on this management screen are settings for the storage system 101.
- the LU unit setting is converted into a flash storage logical space and registered in the capacity allocation information 1706 in the flash storage device 141.
- FIG. 27 shows an example of a processing flow for changing the capacity allocation information 1706.
- This flow is started by setting the capacity allocation policy shown in FIG. 24, changing the configuration information, and regularly updating it.
- the capacity allocation policy in this embodiment is set in units of LUs. Therefore, the policy set and changed in FIG. 24 is changed to the setting of the logical address unit of the flash storage device 141 and reaches the flash storage device 141.
- the RAID controller 111 designates the flash storage device 141 corresponding to LU1 and its logical address, and issues the same setting change instruction. Do. This flow is also executed by changing the configuration information.
- the capacity allocation information 1706 includes statistical information such as the write frequency, and this flow is also executed periodically in order to update this periodically.
- the change process is started at the timing as described above (S3101).
- the flash controller checks whether there is an unreflected setting change area (S3102).
- An area is an area in the capacity allocation information 1706.
- the flash controller changes the attribute for the corresponding area (S3103).
- the attribute to be changed here is based on a user instruction. For example, in FIG. 24, when changing LU1 that has been normally designated to capacity priority, the area in which LU1 is stored is changed from normal designation to capacity priority designation.
- the flash controller reflects the statistical information for each area in the attribute (S3111). This is attribute information such as the write frequency for each area, and is an item determined irrespective of the user instruction.
- the flash controller determines a target allocated capacity in consideration of these (S3112). At this time, it is desirable to set the numerical value in consideration of the overall average of the allocation targets except for the capacity designation area. For example, if the capacity of the entire physical chunk is twice the capacity of the entire logical chunk, all areas are set with priority on performance, and the physical chunk capacity target for each area is set to 3 times the logical chunk capacity. Depending on the situation, the current allocated capacity for all areas may be less than the target, and there will always be a situation in which blocks are always reserved in physical chunks. This is because there is a possibility of being lost.
- the capacity allocation information 1706 is all updated to the latest information, and the flash storage ends the process (S3121). Thereafter, according to the new capacity allocation information 1706, the flash storage performs block allocation processing (S2812).
- storage area attributes are set in units of storage areas (for example, LU units).
- the attributes of the storage area include, for example, an attribute (for example, RAID level) indicated by a usage method by the host device of the storage area, and an attribute (for example, access frequency, last access time) indicated by statistical information acquired during operation of the storage area. ) And an attribute (for example, y% of a target value (expected value) (for example, y is a value greater than 0 and equal to or less than 100) according to an instruction from the administrator for the storage area).
- the flash controller or RAID controller or management system determines a target value (expected value) of the capacity of the physical chunk belonging to the storage area. For example, the target value may be calculated by multiplying a predetermined reference value by a coefficient according to the attribute of the storage area.
- the attributes of the storage area may be determined according to the policy entered for the storage area unit.
- the RAID controller 111 may have information (logical-physical conversion information 312) that the flash storage 131 has. Further, the RAID controller 111 may perform at least a part of the processing performed by the flash controller.
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Abstract
Description
(1)上位ページのサイズを物理ページ1453のサイズよりも小さくすることにより、より小さなサイズのアクセスに対する性能及び寿命の向上を実現する、
(2)上位ページのサイズを物理ページ1453のサイズよりも大きくすることにより、論理物理変換情報312のサイズを低減する、
(3)論理アドレス層1401における1つの論理ページ1411を異なるFMチップ1451(好ましくはFMバス223が異なるFMチップ1451)の複数の物理ページ1453に割り当てることにより、並列処理を実現する、
が採用されて良い。
Claims (15)
- 不揮発半導体記憶媒体と、
前記不揮発半導体記憶媒体の論理アドレスと物理記憶領域との対応関係を表す情報である論理物理変換情報を記憶する記憶部と、
前記記憶部及び前記不揮発半導体記憶媒体に接続されたコントローラである媒体コントローラと
を有し、
前記論理物理変換情報が、
(A)前記不揮発半導体記憶媒体の論理アドレス空間を構成する複数の論理ページと複数の論理チャンクとの対応関係を表す情報と、
(B)前記複数の論理チャンクと複数の物理記憶領域との対応関係を表す情報と
を含み、
各論理ページは、論理アドレス範囲に従う論理記憶領域であり、
各論理チャンクが、前記複数の論理ページのうちの2以上の論理ページに割り当てられ、
各論理チャンクに、前記複数の物理記憶領域のうちの2以上の物理記憶領域が割り当てられ、
前記媒体コントローラは、前記論理物理変換情報を基に、データのライト先の論理アドレスが属する論理ページが割り当てられている論理チャンクに割り当てられている物理記憶領域を特定し、その特定された物理記憶領域に、前記データを書き込むよう構成されており、
前記媒体コントローラは、各論理チャンクについて、割り当てる物理記憶領域の数を調整する、
ストレージシステム。 - 請求項1記載のストレージシステムであって、
前記(B)の情報は、下記(b1)の情報、
(b1)複数の論理チャンクと複数の物理チャンクとの対応関係を表す情報、
を含み、
前記物理チャンクに、前記複数の物理記憶領域のうちの2以上の物理記憶領域が割り当てられている、
ストレージシステム。 - 請求項2記載のストレージシステムであって、
前記(B)の情報は、更に、下記(b2)の情報、
(b2)複数の物理チャンクと複数のプールとの対応関係を表す情報、
を含み、
前記プールに、前記複数の物理記憶領域のうちの2以上の物理記憶領域が割り当てられており、
(X)前記媒体コントローラが、前記物理チャンクが割り当てられているプールからその物理チャンクに物理記憶領域を割り当て、
(Y)前記媒体コントローラが、前記物理チャンクに割り当てられている物理記憶領域をその物理チャンクに戻す、
ストレージシステム。 - 請求項3記載のストレージシステムであって、
隣り合う論理ページに異なる論理チャンクのページが割り当てられ、
異なる論理チャンクのページに異なる物理チャンクの領域が割り当てられ、
異なる物理チャンクの領域に、異なる物理リソースの物理記憶領域が割り当てられた、プールの異なる領域、が割り当てられる、
ストレージシステム。 - 請求項4記載のストレージシステムであって、
前記不揮発記憶媒体は、ブロック単位でデータが消去されページ単位でアクセスされるタイプのフラッシュメモリであり、
前記フラッシュメモリは、異なる複数のフラッシュメモリバスに接続された複数のメモリチップを含み、
各メモリチップは、複数の物理ブロックを有し、
各物理ブロックは、複数の物理ページを有し、
前記物理記憶領域は、前記物理ページであり、
前記物理チャンクの領域は、前記物理チャンクを構成する複数のブロックのうちのいずれかのブロックであり、
前記プールの領域は、前記プールを構成する複数のブロックのうちのいずれかのブロックであり、
前記複数の物理チャンクの複数のブロックに、前記複数のプールの複数のブロックが割り当てられており、
前記複数のプールの複数のブロックに、前記複数のメモリチップにおける複数の物理ブロックが割り当てられており、
前記異なる物理リソースは、異なるフラッシュメモリバスである、
ストレージシステム。 - 請求項5記載のストレージシステムであって、
前記媒体コントローラは、ライト先の論理ページ群に対応した物理ブロックにライト対象のデータのサイズ以上の空きの物理ページが無ければ、前記ライト先の各論理ページが割り当てられた各論理チャンクについて、その論理チャンクに対応した物理チャンクに割り当てられているブロックの数が、その物理チャンクについての期待値以上か否かを判断し、その判断の結果が否定的の場合に、前記(X)として、前記物理チャンクが割り当てられているプールからその物理チャンクにブロックを追加する、
ストレージシステム。 - 請求項6記載のストレージシステムであって、
前記物理チャンクに割り当てられるブロックの目標値は、その物理チャンクの属性によって異なり得る、
ストレージシステム。 - 請求項7記載のストレージシステムであって、
前記物理チャンクの属性は、その物理チャンクが属する記憶領域単位で指定されたポリシーに従って決定される、
ストレージシステム。 - 請求項8記載のストレージシステムであって、
複数の不揮発記憶デバイスと、
前記複数の不揮発記憶デバイスとホスト装置とに接続された上位のコントローラと
を有し、
各不揮発記憶デバイスが、前記不揮発記憶媒体と前記記憶部と前記媒体コントローラとを有し、
前記複数の不揮発記憶デバイスに基づく論理的な記憶領域である論理ユニットが前記ホスト装置に提供され、
前記論理ユニットの論理アドレスが、その論理ユニットに基づく複数の不揮発記憶デバイスのそれぞれの論理アドレスに対応している、
ストレージシステム。 - 請求項1記載のストレージシステムであって、
隣り合う論理ページに異なる論理チャンクのページが割り当てられ、
異なる論理チャンクのページに、異なる物理リソースの物理記憶領域が割り当てられる、
ストレージシステム。 - 請求項10記載のストレージシステムであって、
前記異なる物理リソースは、前記媒体コントローラから物理記憶領域に書き込まれるデータが経由する異なるバスであり、
前記媒体コントローラは、連続した複数の論理ページがライト先の場合、複数の異なるバスを介して複数の異なる物理記憶領域にデータを並行して書き込む、
ストレージシステム。 - 請求項10記載のストレージシステムであって、
2以上の異なる回路基板に複数の物理記憶領域が配置されており、
前記異なる物理リソースは、異なる前記回路基板である、
ストレージシステム。 - 請求項1記載のストレージシステムであって、
前記不揮発記憶媒体は、ブロック単位でデータが消去されページ単位でアクセスされるタイプのフラッシュメモリであり、
前記フラッシュメモリは、異なる複数のフラッシュメモリバスに接続された複数のメモリチップを含み、
各メモリチップは、複数の物理ブロックを有し、
各物理ブロックは、複数の物理ページを有し、
前記物理記憶領域は、前記物理ページであり、
前記(B)の情報は、下記(b1)の情報、
(b1)複数の論理チャンクと複数の物理チャンクとの対応関係を表す情報、
を含む、
ストレージシステム。 - 請求項13記載のストレージシステムであって、
前記(B)の情報は、更に、下記(b2)の情報、
(b2)複数の物理チャンクと複数のプールとの対応関係を表す情報、
を含み、
前記プールを構成する複数のブロックに、前記複数の物理チャンクの複数のブロックが割り当てられており、
前記媒体コントローラが、ライト先の論理ページ群に対応した物理ブロックにライト対象のデータのサイズ以上の空きの物理ページが無ければ、前記ライト先の各論理ページが割り当てられた各論理チャンクについて、その論理チャンクに対応した物理チャンクに割り当てられているブロックの数が、その物理チャンクについての期待値以上か否かを判断し、その判断の結果が否定的の場合に、前記物理チャンクが割り当てられているプールからその物理チャンクにブロックを追加する、
ストレージシステム。 - 不揮発半導体記憶媒体の論理アドレスと物理記憶領域との対応関係を表す情報である論理物理変換情報を基に記憶制御を行うストレージシステムの記憶制御方法であって、
前記論理物理変換情報として、
(A)前記不揮発半導体記憶媒体の論理アドレス空間を構成する複数の論理ページと複数の論理チャンクとの対応関係を表す情報と、
(B)前記複数の論理チャンクと複数の物理記憶領域との対応関係を表す情報と
を含み、
各論理チャンクについて、割り当てる物理記憶領域の数を調整する、
記憶制御方法。
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WO2015052811A1 (ja) * | 2013-10-10 | 2015-04-16 | 株式会社日立製作所 | ストレージシステムおよびデータ記憶方法 |
WO2015136619A1 (ja) * | 2014-03-11 | 2015-09-17 | 株式会社日立製作所 | ストレージ装置 |
JP2022111153A (ja) * | 2015-11-13 | 2022-07-29 | 三星電子株式会社 | 格納媒体を多重モードで動作させる管理システム、それを含む格納システム、及びそれを利用して格納媒体を管理する方法 |
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US9678832B2 (en) * | 2014-09-18 | 2017-06-13 | Sandisk Technologies Llc | Storage module and method for on-chip copy gather |
US9483413B2 (en) * | 2014-10-24 | 2016-11-01 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices and methods of controlling the same |
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WO2016194199A1 (ja) * | 2015-06-04 | 2016-12-08 | 株式会社日立製作所 | ストレージ装置 |
US20180321874A1 (en) * | 2017-05-03 | 2018-11-08 | Alibaba Group Holding Limited | Flash management optimization for data update with small block sizes for write amplification mitigation and fault tolerance enhancement |
JP2019194780A (ja) * | 2018-05-01 | 2019-11-07 | 富士通株式会社 | 情報処理装置、データ管理プログラム及びデータ管理方法 |
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